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2001-03-05 Dave Brolley <brolley
[thirdparty/binutils-gdb.git] / sim / m32r / model.c
CommitLineData
c906108c
SS		 1/* Simulator model support for m32rbf.
2
3THIS FILE IS MACHINE GENERATED WITH CGEN.
4
55552082 5Copyright (C) 1996, 1997, 1998, 1999, 2000 Free Software Foundation, Inc.
c906108c
SS		 6
7This file is part of the GNU Simulators.
8
9This program is free software; you can redistribute it and/or modify
10it under the terms of the GNU General Public License as published by
11the Free Software Foundation; either version 2, or (at your option)
12any later version.
13
14This program is distributed in the hope that it will be useful,
15but WITHOUT ANY WARRANTY; without even the implied warranty of
16MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17GNU General Public License for more details.
18
19You should have received a copy of the GNU General Public License along
20with this program; if not, write to the Free Software Foundation, Inc.,
2159 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
22
23*/
24
25#define WANT_CPU m32rbf
26#define WANT_CPU_M32RBF
27
28#include "sim-main.h"
29
30/* The profiling data is recorded here, but is accessed via the profiling
31 mechanism. After all, this is information for profiling. */
32
33#if WITH_PROFILE_MODEL_P
34
35/* Model handlers for each insn. */
36
37static int
38model_m32r_d_add (SIM_CPU *current_cpu, void *sem_arg)
39{
96baa820 40#define FLD(f) abuf->fields.sfmt_add.f
c906108c
SS		 41 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
42 const IDESC * UNUSED idesc = abuf->idesc;
43 int cycles = 0;
44 {
45 int referenced = 0;
46 int UNUSED insn_referenced = abuf->written;
47 INT in_sr = -1;
48 INT in_dr = -1;
49 INT out_dr = -1;
50 in_sr = FLD (in_sr);
51 in_dr = FLD (in_dr);
52 out_dr = FLD (out_dr);
53 referenced |= 1 << 0;
54 referenced |= 1 << 1;
55 referenced |= 1 << 2;
56 cycles += m32rbf_model_m32r_d_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
57 }
58 return cycles;
59#undef FLD
60}
61
62static int
63model_m32r_d_add3 (SIM_CPU *current_cpu, void *sem_arg)
64{
96baa820 65#define FLD(f) abuf->fields.sfmt_add3.f
c906108c
SS		 66 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
67 const IDESC * UNUSED idesc = abuf->idesc;
68 int cycles = 0;
69 {
70 int referenced = 0;
71 int UNUSED insn_referenced = abuf->written;
72 INT in_sr = -1;
73 INT in_dr = -1;
74 INT out_dr = -1;
75 in_sr = FLD (in_sr);
76 out_dr = FLD (out_dr);
77 referenced |= 1 << 0;
78 referenced |= 1 << 2;
79 cycles += m32rbf_model_m32r_d_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
80 }
81 return cycles;
82#undef FLD
83}
84
85static int
86model_m32r_d_and (SIM_CPU *current_cpu, void *sem_arg)
87{
96baa820 88#define FLD(f) abuf->fields.sfmt_add.f
c906108c
SS		 89 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
90 const IDESC * UNUSED idesc = abuf->idesc;
91 int cycles = 0;
92 {
93 int referenced = 0;
94 int UNUSED insn_referenced = abuf->written;
95 INT in_sr = -1;
96 INT in_dr = -1;
97 INT out_dr = -1;
98 in_sr = FLD (in_sr);
99 in_dr = FLD (in_dr);
100 out_dr = FLD (out_dr);
101 referenced |= 1 << 0;
102 referenced |= 1 << 1;
103 referenced |= 1 << 2;
104 cycles += m32rbf_model_m32r_d_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
105 }
106 return cycles;
107#undef FLD
108}
109
110static int
111model_m32r_d_and3 (SIM_CPU *current_cpu, void *sem_arg)
112{
96baa820 113#define FLD(f) abuf->fields.sfmt_and3.f
c906108c
SS		 114 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
115 const IDESC * UNUSED idesc = abuf->idesc;
116 int cycles = 0;
117 {
118 int referenced = 0;
119 int UNUSED insn_referenced = abuf->written;
120 INT in_sr = -1;
121 INT in_dr = -1;
122 INT out_dr = -1;
123 in_sr = FLD (in_sr);
124 out_dr = FLD (out_dr);
125 referenced |= 1 << 0;
126 referenced |= 1 << 2;
127 cycles += m32rbf_model_m32r_d_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
128 }
129 return cycles;
130#undef FLD
131}
132
133static int
134model_m32r_d_or (SIM_CPU *current_cpu, void *sem_arg)
135{
96baa820 136#define FLD(f) abuf->fields.sfmt_add.f
c906108c
SS		 137 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
138 const IDESC * UNUSED idesc = abuf->idesc;
139 int cycles = 0;
140 {
141 int referenced = 0;
142 int UNUSED insn_referenced = abuf->written;
143 INT in_sr = -1;
144 INT in_dr = -1;
145 INT out_dr = -1;
146 in_sr = FLD (in_sr);
147 in_dr = FLD (in_dr);
148 out_dr = FLD (out_dr);
149 referenced |= 1 << 0;
150 referenced |= 1 << 1;
151 referenced |= 1 << 2;
152 cycles += m32rbf_model_m32r_d_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
153 }
154 return cycles;
155#undef FLD
156}
157
158static int
159model_m32r_d_or3 (SIM_CPU *current_cpu, void *sem_arg)
160{
96baa820 161#define FLD(f) abuf->fields.sfmt_and3.f
c906108c
SS		 162 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
163 const IDESC * UNUSED idesc = abuf->idesc;
164 int cycles = 0;
165 {
166 int referenced = 0;
167 int UNUSED insn_referenced = abuf->written;
168 INT in_sr = -1;
169 INT in_dr = -1;
170 INT out_dr = -1;
171 in_sr = FLD (in_sr);
172 out_dr = FLD (out_dr);
173 referenced |= 1 << 0;
174 referenced |= 1 << 2;
175 cycles += m32rbf_model_m32r_d_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
176 }
177 return cycles;
178#undef FLD
179}
180
181static int
182model_m32r_d_xor (SIM_CPU *current_cpu, void *sem_arg)
183{
96baa820 184#define FLD(f) abuf->fields.sfmt_add.f
c906108c
SS		 185 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
186 const IDESC * UNUSED idesc = abuf->idesc;
187 int cycles = 0;
188 {
189 int referenced = 0;
190 int UNUSED insn_referenced = abuf->written;
191 INT in_sr = -1;
192 INT in_dr = -1;
193 INT out_dr = -1;
194 in_sr = FLD (in_sr);
195 in_dr = FLD (in_dr);
196 out_dr = FLD (out_dr);
197 referenced |= 1 << 0;
198 referenced |= 1 << 1;
199 referenced |= 1 << 2;
200 cycles += m32rbf_model_m32r_d_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
201 }
202 return cycles;
203#undef FLD
204}
205
206static int
207model_m32r_d_xor3 (SIM_CPU *current_cpu, void *sem_arg)
208{
96baa820 209#define FLD(f) abuf->fields.sfmt_and3.f
c906108c
SS		 210 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
211 const IDESC * UNUSED idesc = abuf->idesc;
212 int cycles = 0;
213 {
214 int referenced = 0;
215 int UNUSED insn_referenced = abuf->written;
216 INT in_sr = -1;
217 INT in_dr = -1;
218 INT out_dr = -1;
219 in_sr = FLD (in_sr);
220 out_dr = FLD (out_dr);
221 referenced |= 1 << 0;
222 referenced |= 1 << 2;
223 cycles += m32rbf_model_m32r_d_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
224 }
225 return cycles;
226#undef FLD
227}
228
229static int
230model_m32r_d_addi (SIM_CPU *current_cpu, void *sem_arg)
231{
96baa820 232#define FLD(f) abuf->fields.sfmt_addi.f
c906108c
SS		 233 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
234 const IDESC * UNUSED idesc = abuf->idesc;
235 int cycles = 0;
236 {
237 int referenced = 0;
238 int UNUSED insn_referenced = abuf->written;
239 INT in_sr = -1;
240 INT in_dr = -1;
241 INT out_dr = -1;
242 in_dr = FLD (in_dr);
243 out_dr = FLD (out_dr);
244 referenced |= 1 << 1;
245 referenced |= 1 << 2;
246 cycles += m32rbf_model_m32r_d_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
247 }
248 return cycles;
249#undef FLD
250}
251
252static int
253model_m32r_d_addv (SIM_CPU *current_cpu, void *sem_arg)
254{
96baa820 255#define FLD(f) abuf->fields.sfmt_add.f
c906108c
SS		 256 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
257 const IDESC * UNUSED idesc = abuf->idesc;
258 int cycles = 0;
259 {
260 int referenced = 0;
261 int UNUSED insn_referenced = abuf->written;
262 INT in_sr = -1;
263 INT in_dr = -1;
264 INT out_dr = -1;
265 in_sr = FLD (in_sr);
266 in_dr = FLD (in_dr);
267 out_dr = FLD (out_dr);
268 referenced |= 1 << 0;
269 referenced |= 1 << 1;
270 referenced |= 1 << 2;
271 cycles += m32rbf_model_m32r_d_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
272 }
273 return cycles;
274#undef FLD
275}
276
277static int
278model_m32r_d_addv3 (SIM_CPU *current_cpu, void *sem_arg)
279{
96baa820 280#define FLD(f) abuf->fields.sfmt_add3.f
c906108c
SS		 281 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
282 const IDESC * UNUSED idesc = abuf->idesc;
283 int cycles = 0;
284 {
285 int referenced = 0;
286 int UNUSED insn_referenced = abuf->written;
287 INT in_sr = -1;
288 INT in_dr = -1;
289 INT out_dr = -1;
290 in_sr = FLD (in_sr);
291 out_dr = FLD (out_dr);
292 referenced |= 1 << 0;
293 referenced |= 1 << 2;
294 cycles += m32rbf_model_m32r_d_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
295 }
296 return cycles;
297#undef FLD
298}
299
300static int
301model_m32r_d_addx (SIM_CPU *current_cpu, void *sem_arg)
302{
96baa820 303#define FLD(f) abuf->fields.sfmt_add.f
c906108c
SS		 304 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
305 const IDESC * UNUSED idesc = abuf->idesc;
306 int cycles = 0;
307 {
308 int referenced = 0;
309 int UNUSED insn_referenced = abuf->written;
310 INT in_sr = -1;
311 INT in_dr = -1;
312 INT out_dr = -1;
313 in_sr = FLD (in_sr);
314 in_dr = FLD (in_dr);
315 out_dr = FLD (out_dr);
316 referenced |= 1 << 0;
317 referenced |= 1 << 1;
318 referenced |= 1 << 2;
319 cycles += m32rbf_model_m32r_d_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
320 }
321 return cycles;
322#undef FLD
323}
324
325static int
326model_m32r_d_bc8 (SIM_CPU *current_cpu, void *sem_arg)
327{
96baa820 328#define FLD(f) abuf->fields.sfmt_bl8.f
c906108c
SS		 329 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
330 const IDESC * UNUSED idesc = abuf->idesc;
331 int cycles = 0;
332 {
333 int referenced = 0;
334 int UNUSED insn_referenced = abuf->written;
335 INT in_sr = -1;
336 if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
337 cycles += m32rbf_model_m32r_d_u_cti (current_cpu, idesc, 0, referenced, in_sr);
338 }
339 return cycles;
340#undef FLD
341}
342
343static int
344model_m32r_d_bc24 (SIM_CPU *current_cpu, void *sem_arg)
345{
96baa820 346#define FLD(f) abuf->fields.sfmt_bl24.f
c906108c
SS		 347 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
348 const IDESC * UNUSED idesc = abuf->idesc;
349 int cycles = 0;
350 {
351 int referenced = 0;
352 int UNUSED insn_referenced = abuf->written;
353 INT in_sr = -1;
354 if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
355 cycles += m32rbf_model_m32r_d_u_cti (current_cpu, idesc, 0, referenced, in_sr);
356 }
357 return cycles;
358#undef FLD
359}
360
361static int
362model_m32r_d_beq (SIM_CPU *current_cpu, void *sem_arg)
363{
96baa820 364#define FLD(f) abuf->fields.sfmt_beq.f
c906108c
SS		 365 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
366 const IDESC * UNUSED idesc = abuf->idesc;
367 int cycles = 0;
368 {
369 int referenced = 0;
370 int UNUSED insn_referenced = abuf->written;
371 INT in_sr = -1;
372 if (insn_referenced & (1 << 3)) referenced |= 1 << 1;
373 cycles += m32rbf_model_m32r_d_u_cti (current_cpu, idesc, 0, referenced, in_sr);
374 }
375 {
376 int referenced = 0;
377 int UNUSED insn_referenced = abuf->written;
378 INT in_src1 = -1;
379 INT in_src2 = -1;
380 in_src1 = FLD (in_src1);
381 in_src2 = FLD (in_src2);
382 referenced |= 1 << 0;
383 referenced |= 1 << 1;
384 cycles += m32rbf_model_m32r_d_u_cmp (current_cpu, idesc, 1, referenced, in_src1, in_src2);
385 }
386 return cycles;
387#undef FLD
388}
389
390static int
391model_m32r_d_beqz (SIM_CPU *current_cpu, void *sem_arg)
392{
96baa820 393#define FLD(f) abuf->fields.sfmt_beq.f
c906108c
SS		 394 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
395 const IDESC * UNUSED idesc = abuf->idesc;
396 int cycles = 0;
397 {
398 int referenced = 0;
399 int UNUSED insn_referenced = abuf->written;
400 INT in_sr = -1;
401 if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
402 cycles += m32rbf_model_m32r_d_u_cti (current_cpu, idesc, 0, referenced, in_sr);
403 }
404 {
405 int referenced = 0;
406 int UNUSED insn_referenced = abuf->written;
407 INT in_src1 = -1;
408 INT in_src2 = -1;
409 in_src2 = FLD (in_src2);
410 referenced |= 1 << 1;
411 cycles += m32rbf_model_m32r_d_u_cmp (current_cpu, idesc, 1, referenced, in_src1, in_src2);
412 }
413 return cycles;
414#undef FLD
415}
416
417static int
418model_m32r_d_bgez (SIM_CPU *current_cpu, void *sem_arg)
419{
96baa820 420#define FLD(f) abuf->fields.sfmt_beq.f
c906108c
SS		 421 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
422 const IDESC * UNUSED idesc = abuf->idesc;
423 int cycles = 0;
424 {
425 int referenced = 0;
426 int UNUSED insn_referenced = abuf->written;
427 INT in_sr = -1;
428 if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
429 cycles += m32rbf_model_m32r_d_u_cti (current_cpu, idesc, 0, referenced, in_sr);
430 }
431 {
432 int referenced = 0;
433 int UNUSED insn_referenced = abuf->written;
434 INT in_src1 = -1;
435 INT in_src2 = -1;
436 in_src2 = FLD (in_src2);
437 referenced |= 1 << 1;
438 cycles += m32rbf_model_m32r_d_u_cmp (current_cpu, idesc, 1, referenced, in_src1, in_src2);
439 }
440 return cycles;
441#undef FLD
442}
443
444static int
445model_m32r_d_bgtz (SIM_CPU *current_cpu, void *sem_arg)
446{
96baa820 447#define FLD(f) abuf->fields.sfmt_beq.f
c906108c
SS		 448 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
449 const IDESC * UNUSED idesc = abuf->idesc;
450 int cycles = 0;
451 {
452 int referenced = 0;
453 int UNUSED insn_referenced = abuf->written;
454 INT in_sr = -1;
455 if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
456 cycles += m32rbf_model_m32r_d_u_cti (current_cpu, idesc, 0, referenced, in_sr);
457 }
458 {
459 int referenced = 0;
460 int UNUSED insn_referenced = abuf->written;
461 INT in_src1 = -1;
462 INT in_src2 = -1;
463 in_src2 = FLD (in_src2);
464 referenced |= 1 << 1;
465 cycles += m32rbf_model_m32r_d_u_cmp (current_cpu, idesc, 1, referenced, in_src1, in_src2);
466 }
467 return cycles;
468#undef FLD
469}
470
471static int
472model_m32r_d_blez (SIM_CPU *current_cpu, void *sem_arg)
473{
96baa820 474#define FLD(f) abuf->fields.sfmt_beq.f
c906108c
SS		 475 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
476 const IDESC * UNUSED idesc = abuf->idesc;
477 int cycles = 0;
478 {
479 int referenced = 0;
480 int UNUSED insn_referenced = abuf->written;
481 INT in_sr = -1;
482 if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
483 cycles += m32rbf_model_m32r_d_u_cti (current_cpu, idesc, 0, referenced, in_sr);
484 }
485 {
486 int referenced = 0;
487 int UNUSED insn_referenced = abuf->written;
488 INT in_src1 = -1;
489 INT in_src2 = -1;
490 in_src2 = FLD (in_src2);
491 referenced |= 1 << 1;
492 cycles += m32rbf_model_m32r_d_u_cmp (current_cpu, idesc, 1, referenced, in_src1, in_src2);
493 }
494 return cycles;
495#undef FLD
496}
497
498static int
499model_m32r_d_bltz (SIM_CPU *current_cpu, void *sem_arg)
500{
96baa820 501#define FLD(f) abuf->fields.sfmt_beq.f
c906108c
SS		 502 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
503 const IDESC * UNUSED idesc = abuf->idesc;
504 int cycles = 0;
505 {
506 int referenced = 0;
507 int UNUSED insn_referenced = abuf->written;
508 INT in_sr = -1;
509 if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
510 cycles += m32rbf_model_m32r_d_u_cti (current_cpu, idesc, 0, referenced, in_sr);
511 }
512 {
513 int referenced = 0;
514 int UNUSED insn_referenced = abuf->written;
515 INT in_src1 = -1;
516 INT in_src2 = -1;
517 in_src2 = FLD (in_src2);
518 referenced |= 1 << 1;
519 cycles += m32rbf_model_m32r_d_u_cmp (current_cpu, idesc, 1, referenced, in_src1, in_src2);
520 }
521 return cycles;
522#undef FLD
523}
524
525static int
526model_m32r_d_bnez (SIM_CPU *current_cpu, void *sem_arg)
527{
96baa820 528#define FLD(f) abuf->fields.sfmt_beq.f
c906108c
SS		 529 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
530 const IDESC * UNUSED idesc = abuf->idesc;
531 int cycles = 0;
532 {
533 int referenced = 0;
534 int UNUSED insn_referenced = abuf->written;
535 INT in_sr = -1;
536 if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
537 cycles += m32rbf_model_m32r_d_u_cti (current_cpu, idesc, 0, referenced, in_sr);
538 }
539 {
540 int referenced = 0;
541 int UNUSED insn_referenced = abuf->written;
542 INT in_src1 = -1;
543 INT in_src2 = -1;
544 in_src2 = FLD (in_src2);
545 referenced |= 1 << 1;
546 cycles += m32rbf_model_m32r_d_u_cmp (current_cpu, idesc, 1, referenced, in_src1, in_src2);
547 }
548 return cycles;
549#undef FLD
550}
551
552static int
553model_m32r_d_bl8 (SIM_CPU *current_cpu, void *sem_arg)
554{
96baa820 555#define FLD(f) abuf->fields.sfmt_bl8.f
c906108c
SS		 556 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
557 const IDESC * UNUSED idesc = abuf->idesc;
558 int cycles = 0;
559 {
560 int referenced = 0;
561 int UNUSED insn_referenced = abuf->written;
562 INT in_sr = -1;
563 referenced |= 1 << 1;
564 cycles += m32rbf_model_m32r_d_u_cti (current_cpu, idesc, 0, referenced, in_sr);
565 }
566 return cycles;
567#undef FLD
568}
569
570static int
571model_m32r_d_bl24 (SIM_CPU *current_cpu, void *sem_arg)
572{
96baa820 573#define FLD(f) abuf->fields.sfmt_bl24.f
c906108c
SS		 574 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
575 const IDESC * UNUSED idesc = abuf->idesc;
576 int cycles = 0;
577 {
578 int referenced = 0;
579 int UNUSED insn_referenced = abuf->written;
580 INT in_sr = -1;
581 referenced |= 1 << 1;
582 cycles += m32rbf_model_m32r_d_u_cti (current_cpu, idesc, 0, referenced, in_sr);
583 }
584 return cycles;
585#undef FLD
586}
587
588static int
589model_m32r_d_bnc8 (SIM_CPU *current_cpu, void *sem_arg)
590{
96baa820 591#define FLD(f) abuf->fields.sfmt_bl8.f
c906108c
SS		 592 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
593 const IDESC * UNUSED idesc = abuf->idesc;
594 int cycles = 0;
595 {
596 int referenced = 0;
597 int UNUSED insn_referenced = abuf->written;
598 INT in_sr = -1;
599 if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
600 cycles += m32rbf_model_m32r_d_u_cti (current_cpu, idesc, 0, referenced, in_sr);
601 }
602 return cycles;
603#undef FLD
604}
605
606static int
607model_m32r_d_bnc24 (SIM_CPU *current_cpu, void *sem_arg)
608{
96baa820 609#define FLD(f) abuf->fields.sfmt_bl24.f
c906108c
SS		 610 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
611 const IDESC * UNUSED idesc = abuf->idesc;
612 int cycles = 0;
613 {
614 int referenced = 0;
615 int UNUSED insn_referenced = abuf->written;
616 INT in_sr = -1;
617 if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
618 cycles += m32rbf_model_m32r_d_u_cti (current_cpu, idesc, 0, referenced, in_sr);
619 }
620 return cycles;
621#undef FLD
622}
623
624static int
625model_m32r_d_bne (SIM_CPU *current_cpu, void *sem_arg)
626{
96baa820 627#define FLD(f) abuf->fields.sfmt_beq.f
c906108c
SS		 628 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
629 const IDESC * UNUSED idesc = abuf->idesc;
630 int cycles = 0;
631 {
632 int referenced = 0;
633 int UNUSED insn_referenced = abuf->written;
634 INT in_sr = -1;
635 if (insn_referenced & (1 << 3)) referenced |= 1 << 1;
636 cycles += m32rbf_model_m32r_d_u_cti (current_cpu, idesc, 0, referenced, in_sr);
637 }
638 {
639 int referenced = 0;
640 int UNUSED insn_referenced = abuf->written;
641 INT in_src1 = -1;
642 INT in_src2 = -1;
643 in_src1 = FLD (in_src1);
644 in_src2 = FLD (in_src2);
645 referenced |= 1 << 0;
646 referenced |= 1 << 1;
647 cycles += m32rbf_model_m32r_d_u_cmp (current_cpu, idesc, 1, referenced, in_src1, in_src2);
648 }
649 return cycles;
650#undef FLD
651}
652
653static int
654model_m32r_d_bra8 (SIM_CPU *current_cpu, void *sem_arg)
655{
96baa820 656#define FLD(f) abuf->fields.sfmt_bl8.f
c906108c
SS		 657 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
658 const IDESC * UNUSED idesc = abuf->idesc;
659 int cycles = 0;
660 {
661 int referenced = 0;
662 int UNUSED insn_referenced = abuf->written;
663 INT in_sr = -1;
664 referenced |= 1 << 1;
665 cycles += m32rbf_model_m32r_d_u_cti (current_cpu, idesc, 0, referenced, in_sr);
666 }
667 return cycles;
668#undef FLD
669}
670
671static int
672model_m32r_d_bra24 (SIM_CPU *current_cpu, void *sem_arg)
673{
96baa820 674#define FLD(f) abuf->fields.sfmt_bl24.f
c906108c
SS		 675 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
676 const IDESC * UNUSED idesc = abuf->idesc;
677 int cycles = 0;
678 {
679 int referenced = 0;
680 int UNUSED insn_referenced = abuf->written;
681 INT in_sr = -1;
682 referenced |= 1 << 1;
683 cycles += m32rbf_model_m32r_d_u_cti (current_cpu, idesc, 0, referenced, in_sr);
684 }
685 return cycles;
686#undef FLD
687}
688
689static int
690model_m32r_d_cmp (SIM_CPU *current_cpu, void *sem_arg)
691{
96baa820 692#define FLD(f) abuf->fields.sfmt_st_plus.f
c906108c
SS		 693 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
694 const IDESC * UNUSED idesc = abuf->idesc;
695 int cycles = 0;
696 {
697 int referenced = 0;
698 int UNUSED insn_referenced = abuf->written;
699 INT in_src1 = -1;
700 INT in_src2 = -1;
701 in_src1 = FLD (in_src1);
702 in_src2 = FLD (in_src2);
703 referenced |= 1 << 0;
704 referenced |= 1 << 1;
705 cycles += m32rbf_model_m32r_d_u_cmp (current_cpu, idesc, 0, referenced, in_src1, in_src2);
706 }
707 return cycles;
708#undef FLD
709}
710
711static int
712model_m32r_d_cmpi (SIM_CPU *current_cpu, void *sem_arg)
713{
96baa820 714#define FLD(f) abuf->fields.sfmt_st_d.f
c906108c
SS		 715 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
716 const IDESC * UNUSED idesc = abuf->idesc;
717 int cycles = 0;
718 {
719 int referenced = 0;
720 int UNUSED insn_referenced = abuf->written;
721 INT in_src1 = -1;
722 INT in_src2 = -1;
723 in_src2 = FLD (in_src2);
724 referenced |= 1 << 1;
725 cycles += m32rbf_model_m32r_d_u_cmp (current_cpu, idesc, 0, referenced, in_src1, in_src2);
726 }
727 return cycles;
728#undef FLD
729}
730
731static int
732model_m32r_d_cmpu (SIM_CPU *current_cpu, void *sem_arg)
733{
96baa820 734#define FLD(f) abuf->fields.sfmt_st_plus.f
c906108c
SS		 735 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
736 const IDESC * UNUSED idesc = abuf->idesc;
737 int cycles = 0;
738 {
739 int referenced = 0;
740 int UNUSED insn_referenced = abuf->written;
741 INT in_src1 = -1;
742 INT in_src2 = -1;
743 in_src1 = FLD (in_src1);
744 in_src2 = FLD (in_src2);
745 referenced |= 1 << 0;
746 referenced |= 1 << 1;
747 cycles += m32rbf_model_m32r_d_u_cmp (current_cpu, idesc, 0, referenced, in_src1, in_src2);
748 }
749 return cycles;
750#undef FLD
751}
752
753static int
754model_m32r_d_cmpui (SIM_CPU *current_cpu, void *sem_arg)
755{
96baa820 756#define FLD(f) abuf->fields.sfmt_st_d.f
c906108c
SS		 757 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
758 const IDESC * UNUSED idesc = abuf->idesc;
759 int cycles = 0;
760 {
761 int referenced = 0;
762 int UNUSED insn_referenced = abuf->written;
763 INT in_src1 = -1;
764 INT in_src2 = -1;
765 in_src2 = FLD (in_src2);
766 referenced |= 1 << 1;
767 cycles += m32rbf_model_m32r_d_u_cmp (current_cpu, idesc, 0, referenced, in_src1, in_src2);
768 }
769 return cycles;
770#undef FLD
771}
772
773static int
774model_m32r_d_div (SIM_CPU *current_cpu, void *sem_arg)
775{
96baa820 776#define FLD(f) abuf->fields.sfmt_add.f
c906108c
SS		 777 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
778 const IDESC * UNUSED idesc = abuf->idesc;
779 int cycles = 0;
780 {
781 int referenced = 0;
782 int UNUSED insn_referenced = abuf->written;
783 INT in_sr = -1;
784 INT in_dr = -1;
785 INT out_dr = -1;
786 in_sr = FLD (in_sr);
787 in_dr = FLD (in_dr);
788 out_dr = FLD (out_dr);
789 referenced |= 1 << 0;
790 if (insn_referenced & (1 << 0)) referenced |= 1 << 1;
791 if (insn_referenced & (1 << 2)) referenced |= 1 << 2;
792 cycles += m32rbf_model_m32r_d_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
793 }
794 return cycles;
795#undef FLD
796}
797
798static int
799model_m32r_d_divu (SIM_CPU *current_cpu, void *sem_arg)
800{
96baa820 801#define FLD(f) abuf->fields.sfmt_add.f
c906108c
SS		 802 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
803 const IDESC * UNUSED idesc = abuf->idesc;
804 int cycles = 0;
805 {
806 int referenced = 0;
807 int UNUSED insn_referenced = abuf->written;
808 INT in_sr = -1;
809 INT in_dr = -1;
810 INT out_dr = -1;
811 in_sr = FLD (in_sr);
812 in_dr = FLD (in_dr);
813 out_dr = FLD (out_dr);
814 referenced |= 1 << 0;
815 if (insn_referenced & (1 << 0)) referenced |= 1 << 1;
816 if (insn_referenced & (1 << 2)) referenced |= 1 << 2;
817 cycles += m32rbf_model_m32r_d_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
818 }
819 return cycles;
820#undef FLD
821}
822
823static int
824model_m32r_d_rem (SIM_CPU *current_cpu, void *sem_arg)
825{
96baa820 826#define FLD(f) abuf->fields.sfmt_add.f
c906108c
SS		 827 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
828 const IDESC * UNUSED idesc = abuf->idesc;
829 int cycles = 0;
830 {
831 int referenced = 0;
832 int UNUSED insn_referenced = abuf->written;
833 INT in_sr = -1;
834 INT in_dr = -1;
835 INT out_dr = -1;
836 in_sr = FLD (in_sr);
837 in_dr = FLD (in_dr);
838 out_dr = FLD (out_dr);
839 referenced |= 1 << 0;
840 if (insn_referenced & (1 << 0)) referenced |= 1 << 1;
841 if (insn_referenced & (1 << 2)) referenced |= 1 << 2;
842 cycles += m32rbf_model_m32r_d_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
843 }
844 return cycles;
845#undef FLD
846}
847
848static int
849model_m32r_d_remu (SIM_CPU *current_cpu, void *sem_arg)
850{
96baa820 851#define FLD(f) abuf->fields.sfmt_add.f
c906108c
SS		 852 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
853 const IDESC * UNUSED idesc = abuf->idesc;
854 int cycles = 0;
855 {
856 int referenced = 0;
857 int UNUSED insn_referenced = abuf->written;
858 INT in_sr = -1;
859 INT in_dr = -1;
860 INT out_dr = -1;
861 in_sr = FLD (in_sr);
862 in_dr = FLD (in_dr);
863 out_dr = FLD (out_dr);
864 referenced |= 1 << 0;
865 if (insn_referenced & (1 << 0)) referenced |= 1 << 1;
866 if (insn_referenced & (1 << 2)) referenced |= 1 << 2;
867 cycles += m32rbf_model_m32r_d_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
868 }
869 return cycles;
870#undef FLD
871}
872
873static int
874model_m32r_d_jl (SIM_CPU *current_cpu, void *sem_arg)
875{
96baa820 876#define FLD(f) abuf->fields.sfmt_jl.f
c906108c
SS		 877 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
878 const IDESC * UNUSED idesc = abuf->idesc;
879 int cycles = 0;
880 {
881 int referenced = 0;
882 int UNUSED insn_referenced = abuf->written;
883 INT in_sr = -1;
884 in_sr = FLD (in_sr);
885 referenced |= 1 << 0;
886 referenced |= 1 << 1;
887 cycles += m32rbf_model_m32r_d_u_cti (current_cpu, idesc, 0, referenced, in_sr);
888 }
889 return cycles;
890#undef FLD
891}
892
893static int
894model_m32r_d_jmp (SIM_CPU *current_cpu, void *sem_arg)
895{
de8f5985 896#define FLD(f) abuf->fields.sfmt_jl.f
c906108c
SS		 897 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
898 const IDESC * UNUSED idesc = abuf->idesc;
899 int cycles = 0;
900 {
901 int referenced = 0;
902 int UNUSED insn_referenced = abuf->written;
903 INT in_sr = -1;
904 in_sr = FLD (in_sr);
905 referenced |= 1 << 0;
906 referenced |= 1 << 1;
907 cycles += m32rbf_model_m32r_d_u_cti (current_cpu, idesc, 0, referenced, in_sr);
908 }
909 return cycles;
910#undef FLD
911}
912
913static int
914model_m32r_d_ld (SIM_CPU *current_cpu, void *sem_arg)
915{
96baa820 916#define FLD(f) abuf->fields.sfmt_ld_plus.f
c906108c
SS		 917 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
918 const IDESC * UNUSED idesc = abuf->idesc;
919 int cycles = 0;
920 {
921 int referenced = 0;
922 int UNUSED insn_referenced = abuf->written;
923 INT in_sr = 0;
924 INT out_dr = 0;
925 in_sr = FLD (in_sr);
926 out_dr = FLD (out_dr);
927 referenced |= 1 << 0;
928 referenced |= 1 << 1;
929 cycles += m32rbf_model_m32r_d_u_load (current_cpu, idesc, 0, referenced, in_sr, out_dr);
930 }
931 return cycles;
932#undef FLD
933}
934
935static int
936model_m32r_d_ld_d (SIM_CPU *current_cpu, void *sem_arg)
937{
96baa820 938#define FLD(f) abuf->fields.sfmt_add3.f
c906108c
SS		 939 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
940 const IDESC * UNUSED idesc = abuf->idesc;
941 int cycles = 0;
942 {
943 int referenced = 0;
944 int UNUSED insn_referenced = abuf->written;
945 INT in_sr = 0;
946 INT out_dr = 0;
947 in_sr = FLD (in_sr);
948 out_dr = FLD (out_dr);
949 referenced |= 1 << 0;
950 referenced |= 1 << 1;
951 cycles += m32rbf_model_m32r_d_u_load (current_cpu, idesc, 0, referenced, in_sr, out_dr);
952 }
953 return cycles;
954#undef FLD
955}
956
957static int
958model_m32r_d_ldb (SIM_CPU *current_cpu, void *sem_arg)
959{
96baa820 960#define FLD(f) abuf->fields.sfmt_ld_plus.f
c906108c
SS		 961 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
962 const IDESC * UNUSED idesc = abuf->idesc;
963 int cycles = 0;
964 {
965 int referenced = 0;
966 int UNUSED insn_referenced = abuf->written;
967 INT in_sr = 0;
968 INT out_dr = 0;
969 in_sr = FLD (in_sr);
970 out_dr = FLD (out_dr);
971 referenced |= 1 << 0;
972 referenced |= 1 << 1;
973 cycles += m32rbf_model_m32r_d_u_load (current_cpu, idesc, 0, referenced, in_sr, out_dr);
974 }
975 return cycles;
976#undef FLD
977}
978
979static int
980model_m32r_d_ldb_d (SIM_CPU *current_cpu, void *sem_arg)
981{
96baa820 982#define FLD(f) abuf->fields.sfmt_add3.f
c906108c
SS		 983 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
984 const IDESC * UNUSED idesc = abuf->idesc;
985 int cycles = 0;
986 {
987 int referenced = 0;
988 int UNUSED insn_referenced = abuf->written;
989 INT in_sr = 0;
990 INT out_dr = 0;
991 in_sr = FLD (in_sr);
992 out_dr = FLD (out_dr);
993 referenced |= 1 << 0;
994 referenced |= 1 << 1;
995 cycles += m32rbf_model_m32r_d_u_load (current_cpu, idesc, 0, referenced, in_sr, out_dr);
996 }
997 return cycles;
998#undef FLD
999}
1000
1001static int
1002model_m32r_d_ldh (SIM_CPU *current_cpu, void *sem_arg)
1003{
96baa820 1004#define FLD(f) abuf->fields.sfmt_ld_plus.f
c906108c
SS		 1005 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1006 const IDESC * UNUSED idesc = abuf->idesc;
1007 int cycles = 0;
1008 {
1009 int referenced = 0;
1010 int UNUSED insn_referenced = abuf->written;
1011 INT in_sr = 0;
1012 INT out_dr = 0;
1013 in_sr = FLD (in_sr);
1014 out_dr = FLD (out_dr);
1015 referenced |= 1 << 0;
1016 referenced |= 1 << 1;
1017 cycles += m32rbf_model_m32r_d_u_load (current_cpu, idesc, 0, referenced, in_sr, out_dr);
1018 }
1019 return cycles;
1020#undef FLD
1021}
1022
1023static int
1024model_m32r_d_ldh_d (SIM_CPU *current_cpu, void *sem_arg)
1025{
96baa820 1026#define FLD(f) abuf->fields.sfmt_add3.f
c906108c
SS		 1027 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1028 const IDESC * UNUSED idesc = abuf->idesc;
1029 int cycles = 0;
1030 {
1031 int referenced = 0;
1032 int UNUSED insn_referenced = abuf->written;
1033 INT in_sr = 0;
1034 INT out_dr = 0;
1035 in_sr = FLD (in_sr);
1036 out_dr = FLD (out_dr);
1037 referenced |= 1 << 0;
1038 referenced |= 1 << 1;
1039 cycles += m32rbf_model_m32r_d_u_load (current_cpu, idesc, 0, referenced, in_sr, out_dr);
1040 }
1041 return cycles;
1042#undef FLD
1043}
1044
1045static int
1046model_m32r_d_ldub (SIM_CPU *current_cpu, void *sem_arg)
1047{
96baa820 1048#define FLD(f) abuf->fields.sfmt_ld_plus.f
c906108c
SS		 1049 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1050 const IDESC * UNUSED idesc = abuf->idesc;
1051 int cycles = 0;
1052 {
1053 int referenced = 0;
1054 int UNUSED insn_referenced = abuf->written;
1055 INT in_sr = 0;
1056 INT out_dr = 0;
1057 in_sr = FLD (in_sr);
1058 out_dr = FLD (out_dr);
1059 referenced |= 1 << 0;
1060 referenced |= 1 << 1;
1061 cycles += m32rbf_model_m32r_d_u_load (current_cpu, idesc, 0, referenced, in_sr, out_dr);
1062 }
1063 return cycles;
1064#undef FLD
1065}
1066
1067static int
1068model_m32r_d_ldub_d (SIM_CPU *current_cpu, void *sem_arg)
1069{
96baa820 1070#define FLD(f) abuf->fields.sfmt_add3.f
c906108c
SS		 1071 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1072 const IDESC * UNUSED idesc = abuf->idesc;
1073 int cycles = 0;
1074 {
1075 int referenced = 0;
1076 int UNUSED insn_referenced = abuf->written;
1077 INT in_sr = 0;
1078 INT out_dr = 0;
1079 in_sr = FLD (in_sr);
1080 out_dr = FLD (out_dr);
1081 referenced |= 1 << 0;
1082 referenced |= 1 << 1;
1083 cycles += m32rbf_model_m32r_d_u_load (current_cpu, idesc, 0, referenced, in_sr, out_dr);
1084 }
1085 return cycles;
1086#undef FLD
1087}
1088
1089static int
1090model_m32r_d_lduh (SIM_CPU *current_cpu, void *sem_arg)
1091{
96baa820 1092#define FLD(f) abuf->fields.sfmt_ld_plus.f
c906108c
SS		 1093 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1094 const IDESC * UNUSED idesc = abuf->idesc;
1095 int cycles = 0;
1096 {
1097 int referenced = 0;
1098 int UNUSED insn_referenced = abuf->written;
1099 INT in_sr = 0;
1100 INT out_dr = 0;
1101 in_sr = FLD (in_sr);
1102 out_dr = FLD (out_dr);
1103 referenced |= 1 << 0;
1104 referenced |= 1 << 1;
1105 cycles += m32rbf_model_m32r_d_u_load (current_cpu, idesc, 0, referenced, in_sr, out_dr);
1106 }
1107 return cycles;
1108#undef FLD
1109}
1110
1111static int
1112model_m32r_d_lduh_d (SIM_CPU *current_cpu, void *sem_arg)
1113{
96baa820 1114#define FLD(f) abuf->fields.sfmt_add3.f
c906108c
SS		 1115 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1116 const IDESC * UNUSED idesc = abuf->idesc;
1117 int cycles = 0;
1118 {
1119 int referenced = 0;
1120 int UNUSED insn_referenced = abuf->written;
1121 INT in_sr = 0;
1122 INT out_dr = 0;
1123 in_sr = FLD (in_sr);
1124 out_dr = FLD (out_dr);
1125 referenced |= 1 << 0;
1126 referenced |= 1 << 1;
1127 cycles += m32rbf_model_m32r_d_u_load (current_cpu, idesc, 0, referenced, in_sr, out_dr);
1128 }
1129 return cycles;
1130#undef FLD
1131}
1132
1133static int
1134model_m32r_d_ld_plus (SIM_CPU *current_cpu, void *sem_arg)
1135{
96baa820 1136#define FLD(f) abuf->fields.sfmt_ld_plus.f
c906108c
SS		 1137 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1138 const IDESC * UNUSED idesc = abuf->idesc;
1139 int cycles = 0;
1140 {
1141 int referenced = 0;
1142 int UNUSED insn_referenced = abuf->written;
1143 INT in_sr = 0;
1144 INT out_dr = 0;
1145 in_sr = FLD (in_sr);
1146 out_dr = FLD (out_dr);
1147 referenced |= 1 << 0;
1148 referenced |= 1 << 1;
1149 cycles += m32rbf_model_m32r_d_u_load (current_cpu, idesc, 0, referenced, in_sr, out_dr);
1150 }
1151 {
1152 int referenced = 0;
1153 int UNUSED insn_referenced = abuf->written;
1154 INT in_sr = -1;
1155 INT in_dr = -1;
1156 INT out_dr = -1;
1157 in_dr = FLD (in_sr);
1158 out_dr = FLD (out_sr);
1159 referenced |= 1 << 0;
1160 referenced |= 1 << 2;
1161 cycles += m32rbf_model_m32r_d_u_exec (current_cpu, idesc, 1, referenced, in_sr, in_dr, out_dr);
1162 }
1163 return cycles;
1164#undef FLD
1165}
1166
1167static int
1168model_m32r_d_ld24 (SIM_CPU *current_cpu, void *sem_arg)
1169{
96baa820 1170#define FLD(f) abuf->fields.sfmt_ld24.f
c906108c
SS		 1171 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1172 const IDESC * UNUSED idesc = abuf->idesc;
1173 int cycles = 0;
1174 {
1175 int referenced = 0;
1176 int UNUSED insn_referenced = abuf->written;
1177 INT in_sr = -1;
1178 INT in_dr = -1;
1179 INT out_dr = -1;
1180 out_dr = FLD (out_dr);
1181 referenced |= 1 << 2;
1182 cycles += m32rbf_model_m32r_d_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
1183 }
1184 return cycles;
1185#undef FLD
1186}
1187
1188static int
1189model_m32r_d_ldi8 (SIM_CPU *current_cpu, void *sem_arg)
1190{
96baa820 1191#define FLD(f) abuf->fields.sfmt_addi.f
c906108c
SS		 1192 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1193 const IDESC * UNUSED idesc = abuf->idesc;
1194 int cycles = 0;
1195 {
1196 int referenced = 0;
1197 int UNUSED insn_referenced = abuf->written;
1198 INT in_sr = -1;
1199 INT in_dr = -1;
1200 INT out_dr = -1;
1201 out_dr = FLD (out_dr);
1202 referenced |= 1 << 2;
1203 cycles += m32rbf_model_m32r_d_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
1204 }
1205 return cycles;
1206#undef FLD
1207}
1208
1209static int
1210model_m32r_d_ldi16 (SIM_CPU *current_cpu, void *sem_arg)
1211{
96baa820 1212#define FLD(f) abuf->fields.sfmt_add3.f
c906108c
SS		 1213 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1214 const IDESC * UNUSED idesc = abuf->idesc;
1215 int cycles = 0;
1216 {
1217 int referenced = 0;
1218 int UNUSED insn_referenced = abuf->written;
1219 INT in_sr = -1;
1220 INT in_dr = -1;
1221 INT out_dr = -1;
1222 out_dr = FLD (out_dr);
1223 referenced |= 1 << 2;
1224 cycles += m32rbf_model_m32r_d_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
1225 }
1226 return cycles;
1227#undef FLD
1228}
1229
1230static int
1231model_m32r_d_lock (SIM_CPU *current_cpu, void *sem_arg)
1232{
96baa820 1233#define FLD(f) abuf->fields.sfmt_ld_plus.f
c906108c
SS		 1234 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1235 const IDESC * UNUSED idesc = abuf->idesc;
1236 int cycles = 0;
1237 {
1238 int referenced = 0;
1239 int UNUSED insn_referenced = abuf->written;
1240 INT in_sr = 0;
1241 INT out_dr = 0;
1242 in_sr = FLD (in_sr);
1243 out_dr = FLD (out_dr);
1244 referenced |= 1 << 0;
1245 referenced |= 1 << 1;
1246 cycles += m32rbf_model_m32r_d_u_load (current_cpu, idesc, 0, referenced, in_sr, out_dr);
1247 }
1248 return cycles;
1249#undef FLD
1250}
1251
1252static int
1253model_m32r_d_machi (SIM_CPU *current_cpu, void *sem_arg)
1254{
96baa820 1255#define FLD(f) abuf->fields.sfmt_st_plus.f
c906108c
SS		 1256 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1257 const IDESC * UNUSED idesc = abuf->idesc;
1258 int cycles = 0;
1259 {
1260 int referenced = 0;
1261 int UNUSED insn_referenced = abuf->written;
1262 INT in_src1 = -1;
1263 INT in_src2 = -1;
1264 in_src1 = FLD (in_src1);
1265 in_src2 = FLD (in_src2);
1266 referenced |= 1 << 0;
1267 referenced |= 1 << 1;
1268 cycles += m32rbf_model_m32r_d_u_mac (current_cpu, idesc, 0, referenced, in_src1, in_src2);
1269 }
1270 return cycles;
1271#undef FLD
1272}
1273
1274static int
1275model_m32r_d_maclo (SIM_CPU *current_cpu, void *sem_arg)
1276{
96baa820 1277#define FLD(f) abuf->fields.sfmt_st_plus.f
c906108c
SS		 1278 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1279 const IDESC * UNUSED idesc = abuf->idesc;
1280 int cycles = 0;
1281 {
1282 int referenced = 0;
1283 int UNUSED insn_referenced = abuf->written;
1284 INT in_src1 = -1;
1285 INT in_src2 = -1;
1286 in_src1 = FLD (in_src1);
1287 in_src2 = FLD (in_src2);
1288 referenced |= 1 << 0;
1289 referenced |= 1 << 1;
1290 cycles += m32rbf_model_m32r_d_u_mac (current_cpu, idesc, 0, referenced, in_src1, in_src2);
1291 }
1292 return cycles;
1293#undef FLD
1294}
1295
1296static int
1297model_m32r_d_macwhi (SIM_CPU *current_cpu, void *sem_arg)
1298{
96baa820 1299#define FLD(f) abuf->fields.sfmt_st_plus.f
c906108c
SS		 1300 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1301 const IDESC * UNUSED idesc = abuf->idesc;
1302 int cycles = 0;
1303 {
1304 int referenced = 0;
1305 int UNUSED insn_referenced = abuf->written;
1306 INT in_src1 = -1;
1307 INT in_src2 = -1;
1308 in_src1 = FLD (in_src1);
1309 in_src2 = FLD (in_src2);
1310 referenced |= 1 << 0;
1311 referenced |= 1 << 1;
1312 cycles += m32rbf_model_m32r_d_u_mac (current_cpu, idesc, 0, referenced, in_src1, in_src2);
1313 }
1314 return cycles;
1315#undef FLD
1316}
1317
1318static int
1319model_m32r_d_macwlo (SIM_CPU *current_cpu, void *sem_arg)
1320{
96baa820 1321#define FLD(f) abuf->fields.sfmt_st_plus.f
c906108c
SS		 1322 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1323 const IDESC * UNUSED idesc = abuf->idesc;
1324 int cycles = 0;
1325 {
1326 int referenced = 0;
1327 int UNUSED insn_referenced = abuf->written;
1328 INT in_src1 = -1;
1329 INT in_src2 = -1;
1330 in_src1 = FLD (in_src1);
1331 in_src2 = FLD (in_src2);
1332 referenced |= 1 << 0;
1333 referenced |= 1 << 1;
1334 cycles += m32rbf_model_m32r_d_u_mac (current_cpu, idesc, 0, referenced, in_src1, in_src2);
1335 }
1336 return cycles;
1337#undef FLD
1338}
1339
1340static int
1341model_m32r_d_mul (SIM_CPU *current_cpu, void *sem_arg)
1342{
96baa820 1343#define FLD(f) abuf->fields.sfmt_add.f
c906108c
SS		 1344 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1345 const IDESC * UNUSED idesc = abuf->idesc;
1346 int cycles = 0;
1347 {
1348 int referenced = 0;
1349 int UNUSED insn_referenced = abuf->written;
1350 INT in_sr = -1;
1351 INT in_dr = -1;
1352 INT out_dr = -1;
1353 in_sr = FLD (in_sr);
1354 in_dr = FLD (in_dr);
1355 out_dr = FLD (out_dr);
1356 referenced |= 1 << 0;
1357 referenced |= 1 << 1;
1358 referenced |= 1 << 2;
1359 cycles += m32rbf_model_m32r_d_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
1360 }
1361 return cycles;
1362#undef FLD
1363}
1364
1365static int
1366model_m32r_d_mulhi (SIM_CPU *current_cpu, void *sem_arg)
1367{
96baa820 1368#define FLD(f) abuf->fields.sfmt_st_plus.f
c906108c
SS		 1369 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1370 const IDESC * UNUSED idesc = abuf->idesc;
1371 int cycles = 0;
1372 {
1373 int referenced = 0;
1374 int UNUSED insn_referenced = abuf->written;
1375 INT in_src1 = -1;
1376 INT in_src2 = -1;
1377 in_src1 = FLD (in_src1);
1378 in_src2 = FLD (in_src2);
1379 referenced |= 1 << 0;
1380 referenced |= 1 << 1;
1381 cycles += m32rbf_model_m32r_d_u_mac (current_cpu, idesc, 0, referenced, in_src1, in_src2);
1382 }
1383 return cycles;
1384#undef FLD
1385}
1386
1387static int
1388model_m32r_d_mullo (SIM_CPU *current_cpu, void *sem_arg)
1389{
96baa820 1390#define FLD(f) abuf->fields.sfmt_st_plus.f
c906108c
SS		 1391 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1392 const IDESC * UNUSED idesc = abuf->idesc;
1393 int cycles = 0;
1394 {
1395 int referenced = 0;
1396 int UNUSED insn_referenced = abuf->written;
1397 INT in_src1 = -1;
1398 INT in_src2 = -1;
1399 in_src1 = FLD (in_src1);
1400 in_src2 = FLD (in_src2);
1401 referenced |= 1 << 0;
1402 referenced |= 1 << 1;
1403 cycles += m32rbf_model_m32r_d_u_mac (current_cpu, idesc, 0, referenced, in_src1, in_src2);
1404 }
1405 return cycles;
1406#undef FLD
1407}
1408
1409static int
1410model_m32r_d_mulwhi (SIM_CPU *current_cpu, void *sem_arg)
1411{
96baa820 1412#define FLD(f) abuf->fields.sfmt_st_plus.f
c906108c
SS		 1413 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1414 const IDESC * UNUSED idesc = abuf->idesc;
1415 int cycles = 0;
1416 {
1417 int referenced = 0;
1418 int UNUSED insn_referenced = abuf->written;
1419 INT in_src1 = -1;
1420 INT in_src2 = -1;
1421 in_src1 = FLD (in_src1);
1422 in_src2 = FLD (in_src2);
1423 referenced |= 1 << 0;
1424 referenced |= 1 << 1;
1425 cycles += m32rbf_model_m32r_d_u_mac (current_cpu, idesc, 0, referenced, in_src1, in_src2);
1426 }
1427 return cycles;
1428#undef FLD
1429}
1430
1431static int
1432model_m32r_d_mulwlo (SIM_CPU *current_cpu, void *sem_arg)
1433{
96baa820 1434#define FLD(f) abuf->fields.sfmt_st_plus.f
c906108c
SS		 1435 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1436 const IDESC * UNUSED idesc = abuf->idesc;
1437 int cycles = 0;
1438 {
1439 int referenced = 0;
1440 int UNUSED insn_referenced = abuf->written;
1441 INT in_src1 = -1;
1442 INT in_src2 = -1;
1443 in_src1 = FLD (in_src1);
1444 in_src2 = FLD (in_src2);
1445 referenced |= 1 << 0;
1446 referenced |= 1 << 1;
1447 cycles += m32rbf_model_m32r_d_u_mac (current_cpu, idesc, 0, referenced, in_src1, in_src2);
1448 }
1449 return cycles;
1450#undef FLD
1451}
1452
1453static int
1454model_m32r_d_mv (SIM_CPU *current_cpu, void *sem_arg)
1455{
96baa820 1456#define FLD(f) abuf->fields.sfmt_ld_plus.f
c906108c
SS		 1457 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1458 const IDESC * UNUSED idesc = abuf->idesc;
1459 int cycles = 0;
1460 {
1461 int referenced = 0;
1462 int UNUSED insn_referenced = abuf->written;
1463 INT in_sr = -1;
1464 INT in_dr = -1;
1465 INT out_dr = -1;
1466 in_sr = FLD (in_sr);
1467 out_dr = FLD (out_dr);
1468 referenced |= 1 << 0;
1469 referenced |= 1 << 2;
1470 cycles += m32rbf_model_m32r_d_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
1471 }
1472 return cycles;
1473#undef FLD
1474}
1475
1476static int
1477model_m32r_d_mvfachi (SIM_CPU *current_cpu, void *sem_arg)
1478{
96baa820 1479#define FLD(f) abuf->fields.sfmt_seth.f
c906108c
SS		 1480 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1481 const IDESC * UNUSED idesc = abuf->idesc;
1482 int cycles = 0;
1483 {
1484 int referenced = 0;
1485 int UNUSED insn_referenced = abuf->written;
1486 INT in_sr = -1;
1487 INT in_dr = -1;
1488 INT out_dr = -1;
1489 out_dr = FLD (out_dr);
1490 referenced |= 1 << 2;
1491 cycles += m32rbf_model_m32r_d_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
1492 }
1493 return cycles;
1494#undef FLD
1495}
1496
1497static int
1498model_m32r_d_mvfaclo (SIM_CPU *current_cpu, void *sem_arg)
1499{
96baa820 1500#define FLD(f) abuf->fields.sfmt_seth.f
c906108c
SS		 1501 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1502 const IDESC * UNUSED idesc = abuf->idesc;
1503 int cycles = 0;
1504 {
1505 int referenced = 0;
1506 int UNUSED insn_referenced = abuf->written;
1507 INT in_sr = -1;
1508 INT in_dr = -1;
1509 INT out_dr = -1;
1510 out_dr = FLD (out_dr);
1511 referenced |= 1 << 2;
1512 cycles += m32rbf_model_m32r_d_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
1513 }
1514 return cycles;
1515#undef FLD
1516}
1517
1518static int
1519model_m32r_d_mvfacmi (SIM_CPU *current_cpu, void *sem_arg)
1520{
96baa820 1521#define FLD(f) abuf->fields.sfmt_seth.f
c906108c
SS		 1522 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1523 const IDESC * UNUSED idesc = abuf->idesc;
1524 int cycles = 0;
1525 {
1526 int referenced = 0;
1527 int UNUSED insn_referenced = abuf->written;
1528 INT in_sr = -1;
1529 INT in_dr = -1;
1530 INT out_dr = -1;
1531 out_dr = FLD (out_dr);
1532 referenced |= 1 << 2;
1533 cycles += m32rbf_model_m32r_d_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
1534 }
1535 return cycles;
1536#undef FLD
1537}
1538
1539static int
1540model_m32r_d_mvfc (SIM_CPU *current_cpu, void *sem_arg)
1541{
de8f5985 1542#define FLD(f) abuf->fields.sfmt_ld_plus.f
c906108c
SS		 1543 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1544 const IDESC * UNUSED idesc = abuf->idesc;
1545 int cycles = 0;
1546 {
1547 int referenced = 0;
1548 int UNUSED insn_referenced = abuf->written;
1549 INT in_sr = -1;
1550 INT in_dr = -1;
1551 INT out_dr = -1;
1552 out_dr = FLD (out_dr);
1553 referenced |= 1 << 2;
1554 cycles += m32rbf_model_m32r_d_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
1555 }
1556 return cycles;
1557#undef FLD
1558}
1559
1560static int
1561model_m32r_d_mvtachi (SIM_CPU *current_cpu, void *sem_arg)
1562{
96baa820 1563#define FLD(f) abuf->fields.sfmt_st_plus.f
c906108c
SS		 1564 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1565 const IDESC * UNUSED idesc = abuf->idesc;
1566 int cycles = 0;
1567 {
1568 int referenced = 0;
1569 int UNUSED insn_referenced = abuf->written;
1570 INT in_sr = -1;
1571 INT in_dr = -1;
1572 INT out_dr = -1;
1573 in_sr = FLD (in_src1);
1574 cycles += m32rbf_model_m32r_d_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
1575 }
1576 return cycles;
1577#undef FLD
1578}
1579
1580static int
1581model_m32r_d_mvtaclo (SIM_CPU *current_cpu, void *sem_arg)
1582{
96baa820 1583#define FLD(f) abuf->fields.sfmt_st_plus.f
c906108c
SS		 1584 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1585 const IDESC * UNUSED idesc = abuf->idesc;
1586 int cycles = 0;
1587 {
1588 int referenced = 0;
1589 int UNUSED insn_referenced = abuf->written;
1590 INT in_sr = -1;
1591 INT in_dr = -1;
1592 INT out_dr = -1;
1593 in_sr = FLD (in_src1);
1594 cycles += m32rbf_model_m32r_d_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
1595 }
1596 return cycles;
1597#undef FLD
1598}
1599
1600static int
1601model_m32r_d_mvtc (SIM_CPU *current_cpu, void *sem_arg)
1602{
de8f5985 1603#define FLD(f) abuf->fields.sfmt_ld_plus.f
c906108c
SS		 1604 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1605 const IDESC * UNUSED idesc = abuf->idesc;
1606 int cycles = 0;
1607 {
1608 int referenced = 0;
1609 int UNUSED insn_referenced = abuf->written;
1610 INT in_sr = -1;
1611 INT in_dr = -1;
1612 INT out_dr = -1;
1613 in_sr = FLD (in_sr);
1614 referenced |= 1 << 0;
1615 cycles += m32rbf_model_m32r_d_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
1616 }
1617 return cycles;
1618#undef FLD
1619}
1620
1621static int
1622model_m32r_d_neg (SIM_CPU *current_cpu, void *sem_arg)
1623{
96baa820 1624#define FLD(f) abuf->fields.sfmt_ld_plus.f
c906108c
SS		 1625 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1626 const IDESC * UNUSED idesc = abuf->idesc;
1627 int cycles = 0;
1628 {
1629 int referenced = 0;
1630 int UNUSED insn_referenced = abuf->written;
1631 INT in_sr = -1;
1632 INT in_dr = -1;
1633 INT out_dr = -1;
1634 in_sr = FLD (in_sr);
1635 out_dr = FLD (out_dr);
1636 referenced |= 1 << 0;
1637 referenced |= 1 << 2;
1638 cycles += m32rbf_model_m32r_d_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
1639 }
1640 return cycles;
1641#undef FLD
1642}
1643
1644static int
1645model_m32r_d_nop (SIM_CPU *current_cpu, void *sem_arg)
1646{
96baa820 1647#define FLD(f) abuf->fields.fmt_empty.f
c906108c
SS		 1648 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1649 const IDESC * UNUSED idesc = abuf->idesc;
1650 int cycles = 0;
1651 {
1652 int referenced = 0;
1653 int UNUSED insn_referenced = abuf->written;
1654 INT in_sr = -1;
1655 INT in_dr = -1;
1656 INT out_dr = -1;
1657 cycles += m32rbf_model_m32r_d_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
1658 }
1659 return cycles;
1660#undef FLD
1661}
1662
1663static int
1664model_m32r_d_not (SIM_CPU *current_cpu, void *sem_arg)
1665{
96baa820 1666#define FLD(f) abuf->fields.sfmt_ld_plus.f
c906108c
SS		 1667 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1668 const IDESC * UNUSED idesc = abuf->idesc;
1669 int cycles = 0;
1670 {
1671 int referenced = 0;
1672 int UNUSED insn_referenced = abuf->written;
1673 INT in_sr = -1;
1674 INT in_dr = -1;
1675 INT out_dr = -1;
1676 in_sr = FLD (in_sr);
1677 out_dr = FLD (out_dr);
1678 referenced |= 1 << 0;
1679 referenced |= 1 << 2;
1680 cycles += m32rbf_model_m32r_d_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
1681 }
1682 return cycles;
1683#undef FLD
1684}
1685
1686static int
1687model_m32r_d_rac (SIM_CPU *current_cpu, void *sem_arg)
1688{
96baa820 1689#define FLD(f) abuf->fields.fmt_empty.f
c906108c
SS		 1690 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1691 const IDESC * UNUSED idesc = abuf->idesc;
1692 int cycles = 0;
1693 {
1694 int referenced = 0;
1695 int UNUSED insn_referenced = abuf->written;
1696 INT in_src1 = -1;
1697 INT in_src2 = -1;
1698 cycles += m32rbf_model_m32r_d_u_mac (current_cpu, idesc, 0, referenced, in_src1, in_src2);
1699 }
1700 return cycles;
1701#undef FLD
1702}
1703
1704static int
1705model_m32r_d_rach (SIM_CPU *current_cpu, void *sem_arg)
1706{
96baa820 1707#define FLD(f) abuf->fields.fmt_empty.f
c906108c
SS		 1708 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1709 const IDESC * UNUSED idesc = abuf->idesc;
1710 int cycles = 0;
1711 {
1712 int referenced = 0;
1713 int UNUSED insn_referenced = abuf->written;
1714 INT in_src1 = -1;
1715 INT in_src2 = -1;
1716 cycles += m32rbf_model_m32r_d_u_mac (current_cpu, idesc, 0, referenced, in_src1, in_src2);
1717 }
1718 return cycles;
1719#undef FLD
1720}
1721
1722static int
1723model_m32r_d_rte (SIM_CPU *current_cpu, void *sem_arg)
1724{
96baa820 1725#define FLD(f) abuf->fields.fmt_empty.f
c906108c
SS		 1726 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1727 const IDESC * UNUSED idesc = abuf->idesc;
1728 int cycles = 0;
1729 {
1730 int referenced = 0;
1731 int UNUSED insn_referenced = abuf->written;
1732 INT in_sr = -1;
1733 INT in_dr = -1;
1734 INT out_dr = -1;
1735 cycles += m32rbf_model_m32r_d_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
1736 }
1737 return cycles;
1738#undef FLD
1739}
1740
1741static int
1742model_m32r_d_seth (SIM_CPU *current_cpu, void *sem_arg)
1743{
96baa820 1744#define FLD(f) abuf->fields.sfmt_seth.f
c906108c
SS		 1745 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1746 const IDESC * UNUSED idesc = abuf->idesc;
1747 int cycles = 0;
1748 {
1749 int referenced = 0;
1750 int UNUSED insn_referenced = abuf->written;
1751 INT in_sr = -1;
1752 INT in_dr = -1;
1753 INT out_dr = -1;
1754 out_dr = FLD (out_dr);
1755 referenced |= 1 << 2;
1756 cycles += m32rbf_model_m32r_d_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
1757 }
1758 return cycles;
1759#undef FLD
1760}
1761
1762static int
1763model_m32r_d_sll (SIM_CPU *current_cpu, void *sem_arg)
1764{
96baa820 1765#define FLD(f) abuf->fields.sfmt_add.f
c906108c
SS		 1766 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1767 const IDESC * UNUSED idesc = abuf->idesc;
1768 int cycles = 0;
1769 {
1770 int referenced = 0;
1771 int UNUSED insn_referenced = abuf->written;
1772 INT in_sr = -1;
1773 INT in_dr = -1;
1774 INT out_dr = -1;
1775 in_sr = FLD (in_sr);
1776 in_dr = FLD (in_dr);
1777 out_dr = FLD (out_dr);
1778 referenced |= 1 << 0;
1779 referenced |= 1 << 1;
1780 referenced |= 1 << 2;
1781 cycles += m32rbf_model_m32r_d_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
1782 }
1783 return cycles;
1784#undef FLD
1785}
1786
1787static int
1788model_m32r_d_sll3 (SIM_CPU *current_cpu, void *sem_arg)
1789{
96baa820 1790#define FLD(f) abuf->fields.sfmt_add3.f
c906108c
SS		 1791 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1792 const IDESC * UNUSED idesc = abuf->idesc;
1793 int cycles = 0;
1794 {
1795 int referenced = 0;
1796 int UNUSED insn_referenced = abuf->written;
1797 INT in_sr = -1;
1798 INT in_dr = -1;
1799 INT out_dr = -1;
1800 in_sr = FLD (in_sr);
1801 out_dr = FLD (out_dr);
1802 referenced |= 1 << 0;
1803 referenced |= 1 << 2;
1804 cycles += m32rbf_model_m32r_d_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
1805 }
1806 return cycles;
1807#undef FLD
1808}
1809
1810static int
1811model_m32r_d_slli (SIM_CPU *current_cpu, void *sem_arg)
1812{
96baa820 1813#define FLD(f) abuf->fields.sfmt_slli.f
c906108c
SS		 1814 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1815 const IDESC * UNUSED idesc = abuf->idesc;
1816 int cycles = 0;
1817 {
1818 int referenced = 0;
1819 int UNUSED insn_referenced = abuf->written;
1820 INT in_sr = -1;
1821 INT in_dr = -1;
1822 INT out_dr = -1;
1823 in_dr = FLD (in_dr);
1824 out_dr = FLD (out_dr);
1825 referenced |= 1 << 1;
1826 referenced |= 1 << 2;
1827 cycles += m32rbf_model_m32r_d_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
1828 }
1829 return cycles;
1830#undef FLD
1831}
1832
1833static int
1834model_m32r_d_sra (SIM_CPU *current_cpu, void *sem_arg)
1835{
96baa820 1836#define FLD(f) abuf->fields.sfmt_add.f
c906108c
SS		 1837 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1838 const IDESC * UNUSED idesc = abuf->idesc;
1839 int cycles = 0;
1840 {
1841 int referenced = 0;
1842 int UNUSED insn_referenced = abuf->written;
1843 INT in_sr = -1;
1844 INT in_dr = -1;
1845 INT out_dr = -1;
1846 in_sr = FLD (in_sr);
1847 in_dr = FLD (in_dr);
1848 out_dr = FLD (out_dr);
1849 referenced |= 1 << 0;
1850 referenced |= 1 << 1;
1851 referenced |= 1 << 2;
1852 cycles += m32rbf_model_m32r_d_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
1853 }
1854 return cycles;
1855#undef FLD
1856}
1857
1858static int
1859model_m32r_d_sra3 (SIM_CPU *current_cpu, void *sem_arg)
1860{
96baa820 1861#define FLD(f) abuf->fields.sfmt_add3.f
c906108c
SS		 1862 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1863 const IDESC * UNUSED idesc = abuf->idesc;
1864 int cycles = 0;
1865 {
1866 int referenced = 0;
1867 int UNUSED insn_referenced = abuf->written;
1868 INT in_sr = -1;
1869 INT in_dr = -1;
1870 INT out_dr = -1;
1871 in_sr = FLD (in_sr);
1872 out_dr = FLD (out_dr);
1873 referenced |= 1 << 0;
1874 referenced |= 1 << 2;
1875 cycles += m32rbf_model_m32r_d_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
1876 }
1877 return cycles;
1878#undef FLD
1879}
1880
1881static int
1882model_m32r_d_srai (SIM_CPU *current_cpu, void *sem_arg)
1883{
96baa820 1884#define FLD(f) abuf->fields.sfmt_slli.f
c906108c
SS		 1885 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1886 const IDESC * UNUSED idesc = abuf->idesc;
1887 int cycles = 0;
1888 {
1889 int referenced = 0;
1890 int UNUSED insn_referenced = abuf->written;
1891 INT in_sr = -1;
1892 INT in_dr = -1;
1893 INT out_dr = -1;
1894 in_dr = FLD (in_dr);
1895 out_dr = FLD (out_dr);
1896 referenced |= 1 << 1;
1897 referenced |= 1 << 2;
1898 cycles += m32rbf_model_m32r_d_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
1899 }
1900 return cycles;
1901#undef FLD
1902}
1903
1904static int
1905model_m32r_d_srl (SIM_CPU *current_cpu, void *sem_arg)
1906{
96baa820 1907#define FLD(f) abuf->fields.sfmt_add.f
c906108c
SS		 1908 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1909 const IDESC * UNUSED idesc = abuf->idesc;
1910 int cycles = 0;
1911 {
1912 int referenced = 0;
1913 int UNUSED insn_referenced = abuf->written;
1914 INT in_sr = -1;
1915 INT in_dr = -1;
1916 INT out_dr = -1;
1917 in_sr = FLD (in_sr);
1918 in_dr = FLD (in_dr);
1919 out_dr = FLD (out_dr);
1920 referenced |= 1 << 0;
1921 referenced |= 1 << 1;
1922 referenced |= 1 << 2;
1923 cycles += m32rbf_model_m32r_d_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
1924 }
1925 return cycles;
1926#undef FLD
1927}
1928
1929static int
1930model_m32r_d_srl3 (SIM_CPU *current_cpu, void *sem_arg)
1931{
96baa820 1932#define FLD(f) abuf->fields.sfmt_add3.f
c906108c
SS		 1933 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1934 const IDESC * UNUSED idesc = abuf->idesc;
1935 int cycles = 0;
1936 {
1937 int referenced = 0;
1938 int UNUSED insn_referenced = abuf->written;
1939 INT in_sr = -1;
1940 INT in_dr = -1;
1941 INT out_dr = -1;
1942 in_sr = FLD (in_sr);
1943 out_dr = FLD (out_dr);
1944 referenced |= 1 << 0;
1945 referenced |= 1 << 2;
1946 cycles += m32rbf_model_m32r_d_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
1947 }
1948 return cycles;
1949#undef FLD
1950}
1951
1952static int
1953model_m32r_d_srli (SIM_CPU *current_cpu, void *sem_arg)
1954{
96baa820 1955#define FLD(f) abuf->fields.sfmt_slli.f
c906108c
SS		 1956 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1957 const IDESC * UNUSED idesc = abuf->idesc;
1958 int cycles = 0;
1959 {
1960 int referenced = 0;
1961 int UNUSED insn_referenced = abuf->written;
1962 INT in_sr = -1;
1963 INT in_dr = -1;
1964 INT out_dr = -1;
1965 in_dr = FLD (in_dr);
1966 out_dr = FLD (out_dr);
1967 referenced |= 1 << 1;
1968 referenced |= 1 << 2;
1969 cycles += m32rbf_model_m32r_d_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
1970 }
1971 return cycles;
1972#undef FLD
1973}
1974
1975static int
1976model_m32r_d_st (SIM_CPU *current_cpu, void *sem_arg)
1977{
96baa820 1978#define FLD(f) abuf->fields.sfmt_st_plus.f
c906108c
SS		 1979 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1980 const IDESC * UNUSED idesc = abuf->idesc;
1981 int cycles = 0;
1982 {
1983 int referenced = 0;
1984 int UNUSED insn_referenced = abuf->written;
1985 INT in_src1 = 0;
1986 INT in_src2 = 0;
1987 in_src1 = FLD (in_src1);
1988 in_src2 = FLD (in_src2);
1989 referenced |= 1 << 0;
1990 referenced |= 1 << 1;
1991 cycles += m32rbf_model_m32r_d_u_store (current_cpu, idesc, 0, referenced, in_src1, in_src2);
1992 }
1993 return cycles;
1994#undef FLD
1995}
1996
1997static int
1998model_m32r_d_st_d (SIM_CPU *current_cpu, void *sem_arg)
1999{
96baa820 2000#define FLD(f) abuf->fields.sfmt_st_d.f
c906108c
SS		 2001 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2002 const IDESC * UNUSED idesc = abuf->idesc;
2003 int cycles = 0;
2004 {
2005 int referenced = 0;
2006 int UNUSED insn_referenced = abuf->written;
2007 INT in_src1 = 0;
2008 INT in_src2 = 0;
2009 in_src1 = FLD (in_src1);
2010 in_src2 = FLD (in_src2);
2011 referenced |= 1 << 0;
2012 referenced |= 1 << 1;
2013 cycles += m32rbf_model_m32r_d_u_store (current_cpu, idesc, 0, referenced, in_src1, in_src2);
2014 }
2015 return cycles;
2016#undef FLD
2017}
2018
2019static int
2020model_m32r_d_stb (SIM_CPU *current_cpu, void *sem_arg)
2021{
96baa820 2022#define FLD(f) abuf->fields.sfmt_st_plus.f
c906108c
SS		 2023 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2024 const IDESC * UNUSED idesc = abuf->idesc;
2025 int cycles = 0;
2026 {
2027 int referenced = 0;
2028 int UNUSED insn_referenced = abuf->written;
2029 INT in_src1 = 0;
2030 INT in_src2 = 0;
2031 in_src1 = FLD (in_src1);
2032 in_src2 = FLD (in_src2);
2033 referenced |= 1 << 0;
2034 referenced |= 1 << 1;
2035 cycles += m32rbf_model_m32r_d_u_store (current_cpu, idesc, 0, referenced, in_src1, in_src2);
2036 }
2037 return cycles;
2038#undef FLD
2039}
2040
2041static int
2042model_m32r_d_stb_d (SIM_CPU *current_cpu, void *sem_arg)
2043{
96baa820 2044#define FLD(f) abuf->fields.sfmt_st_d.f
c906108c
SS		 2045 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2046 const IDESC * UNUSED idesc = abuf->idesc;
2047 int cycles = 0;
2048 {
2049 int referenced = 0;
2050 int UNUSED insn_referenced = abuf->written;
2051 INT in_src1 = 0;
2052 INT in_src2 = 0;
2053 in_src1 = FLD (in_src1);
2054 in_src2 = FLD (in_src2);
2055 referenced |= 1 << 0;
2056 referenced |= 1 << 1;
2057 cycles += m32rbf_model_m32r_d_u_store (current_cpu, idesc, 0, referenced, in_src1, in_src2);
2058 }
2059 return cycles;
2060#undef FLD
2061}
2062
2063static int
2064model_m32r_d_sth (SIM_CPU *current_cpu, void *sem_arg)
2065{
96baa820 2066#define FLD(f) abuf->fields.sfmt_st_plus.f
c906108c
SS		 2067 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2068 const IDESC * UNUSED idesc = abuf->idesc;
2069 int cycles = 0;
2070 {
2071 int referenced = 0;
2072 int UNUSED insn_referenced = abuf->written;
2073 INT in_src1 = 0;
2074 INT in_src2 = 0;
2075 in_src1 = FLD (in_src1);
2076 in_src2 = FLD (in_src2);
2077 referenced |= 1 << 0;
2078 referenced |= 1 << 1;
2079 cycles += m32rbf_model_m32r_d_u_store (current_cpu, idesc, 0, referenced, in_src1, in_src2);
2080 }
2081 return cycles;
2082#undef FLD
2083}
2084
2085static int
2086model_m32r_d_sth_d (SIM_CPU *current_cpu, void *sem_arg)
2087{
96baa820 2088#define FLD(f) abuf->fields.sfmt_st_d.f
c906108c
SS		 2089 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2090 const IDESC * UNUSED idesc = abuf->idesc;
2091 int cycles = 0;
2092 {
2093 int referenced = 0;
2094 int UNUSED insn_referenced = abuf->written;
2095 INT in_src1 = 0;
2096 INT in_src2 = 0;
2097 in_src1 = FLD (in_src1);
2098 in_src2 = FLD (in_src2);
2099 referenced |= 1 << 0;
2100 referenced |= 1 << 1;
2101 cycles += m32rbf_model_m32r_d_u_store (current_cpu, idesc, 0, referenced, in_src1, in_src2);
2102 }
2103 return cycles;
2104#undef FLD
2105}
2106
2107static int
2108model_m32r_d_st_plus (SIM_CPU *current_cpu, void *sem_arg)
2109{
96baa820 2110#define FLD(f) abuf->fields.sfmt_st_plus.f
c906108c
SS		 2111 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2112 const IDESC * UNUSED idesc = abuf->idesc;
2113 int cycles = 0;
2114 {
2115 int referenced = 0;
2116 int UNUSED insn_referenced = abuf->written;
2117 INT in_src1 = 0;
2118 INT in_src2 = 0;
2119 in_src1 = FLD (in_src1);
2120 in_src2 = FLD (in_src2);
2121 referenced |= 1 << 0;
2122 referenced |= 1 << 1;
2123 cycles += m32rbf_model_m32r_d_u_store (current_cpu, idesc, 0, referenced, in_src1, in_src2);
2124 }
2125 {
2126 int referenced = 0;
2127 int UNUSED insn_referenced = abuf->written;
2128 INT in_sr = -1;
2129 INT in_dr = -1;
2130 INT out_dr = -1;
2131 in_dr = FLD (in_src2);
2132 out_dr = FLD (out_src2);
2133 cycles += m32rbf_model_m32r_d_u_exec (current_cpu, idesc, 1, referenced, in_sr, in_dr, out_dr);
2134 }
2135 return cycles;
2136#undef FLD
2137}
2138
2139static int
2140model_m32r_d_st_minus (SIM_CPU *current_cpu, void *sem_arg)
2141{
96baa820 2142#define FLD(f) abuf->fields.sfmt_st_plus.f
c906108c
SS		 2143 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2144 const IDESC * UNUSED idesc = abuf->idesc;
2145 int cycles = 0;
2146 {
2147 int referenced = 0;
2148 int UNUSED insn_referenced = abuf->written;
2149 INT in_src1 = 0;
2150 INT in_src2 = 0;
2151 in_src1 = FLD (in_src1);
2152 in_src2 = FLD (in_src2);
2153 referenced |= 1 << 0;
2154 referenced |= 1 << 1;
2155 cycles += m32rbf_model_m32r_d_u_store (current_cpu, idesc, 0, referenced, in_src1, in_src2);
2156 }
2157 {
2158 int referenced = 0;
2159 int UNUSED insn_referenced = abuf->written;
2160 INT in_sr = -1;
2161 INT in_dr = -1;
2162 INT out_dr = -1;
2163 in_dr = FLD (in_src2);
2164 out_dr = FLD (out_src2);
2165 cycles += m32rbf_model_m32r_d_u_exec (current_cpu, idesc, 1, referenced, in_sr, in_dr, out_dr);
2166 }
2167 return cycles;
2168#undef FLD
2169}
2170
2171static int
2172model_m32r_d_sub (SIM_CPU *current_cpu, void *sem_arg)
2173{
96baa820 2174#define FLD(f) abuf->fields.sfmt_add.f
c906108c
SS		 2175 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2176 const IDESC * UNUSED idesc = abuf->idesc;
2177 int cycles = 0;
2178 {
2179 int referenced = 0;
2180 int UNUSED insn_referenced = abuf->written;
2181 INT in_sr = -1;
2182 INT in_dr = -1;
2183 INT out_dr = -1;
2184 in_sr = FLD (in_sr);
2185 in_dr = FLD (in_dr);
2186 out_dr = FLD (out_dr);
2187 referenced |= 1 << 0;
2188 referenced |= 1 << 1;
2189 referenced |= 1 << 2;
2190 cycles += m32rbf_model_m32r_d_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
2191 }
2192 return cycles;
2193#undef FLD
2194}
2195
2196static int
2197model_m32r_d_subv (SIM_CPU *current_cpu, void *sem_arg)
2198{
96baa820 2199#define FLD(f) abuf->fields.sfmt_add.f
c906108c
SS		 2200 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2201 const IDESC * UNUSED idesc = abuf->idesc;
2202 int cycles = 0;
2203 {
2204 int referenced = 0;
2205 int UNUSED insn_referenced = abuf->written;
2206 INT in_sr = -1;
2207 INT in_dr = -1;
2208 INT out_dr = -1;
2209 in_sr = FLD (in_sr);
2210 in_dr = FLD (in_dr);
2211 out_dr = FLD (out_dr);
2212 referenced |= 1 << 0;
2213 referenced |= 1 << 1;
2214 referenced |= 1 << 2;
2215 cycles += m32rbf_model_m32r_d_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
2216 }
2217 return cycles;
2218#undef FLD
2219}
2220
2221static int
2222model_m32r_d_subx (SIM_CPU *current_cpu, void *sem_arg)
2223{
96baa820 2224#define FLD(f) abuf->fields.sfmt_add.f
c906108c
SS		 2225 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2226 const IDESC * UNUSED idesc = abuf->idesc;
2227 int cycles = 0;
2228 {
2229 int referenced = 0;
2230 int UNUSED insn_referenced = abuf->written;
2231 INT in_sr = -1;
2232 INT in_dr = -1;
2233 INT out_dr = -1;
2234 in_sr = FLD (in_sr);
2235 in_dr = FLD (in_dr);
2236 out_dr = FLD (out_dr);
2237 referenced |= 1 << 0;
2238 referenced |= 1 << 1;
2239 referenced |= 1 << 2;
2240 cycles += m32rbf_model_m32r_d_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
2241 }
2242 return cycles;
2243#undef FLD
2244}
2245
2246static int
2247model_m32r_d_trap (SIM_CPU *current_cpu, void *sem_arg)
2248{
96baa820 2249#define FLD(f) abuf->fields.sfmt_trap.f
c906108c
SS		 2250 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2251 const IDESC * UNUSED idesc = abuf->idesc;
2252 int cycles = 0;
2253 {
2254 int referenced = 0;
2255 int UNUSED insn_referenced = abuf->written;
2256 INT in_sr = -1;
2257 INT in_dr = -1;
2258 INT out_dr = -1;
2259 cycles += m32rbf_model_m32r_d_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr);
2260 }
2261 return cycles;
2262#undef FLD
2263}
2264
2265static int
2266model_m32r_d_unlock (SIM_CPU *current_cpu, void *sem_arg)
2267{
96baa820 2268#define FLD(f) abuf->fields.sfmt_st_plus.f
c906108c
SS		 2269 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2270 const IDESC * UNUSED idesc = abuf->idesc;
2271 int cycles = 0;
2272 {
2273 int referenced = 0;
2274 int UNUSED insn_referenced = abuf->written;
2275 INT in_sr = 0;
2276 INT out_dr = 0;
2277 cycles += m32rbf_model_m32r_d_u_load (current_cpu, idesc, 0, referenced, in_sr, out_dr);
2278 }
2279 return cycles;
2280#undef FLD
2281}
2282
2283static int
2284model_test_add (SIM_CPU *current_cpu, void *sem_arg)
2285{
96baa820 2286#define FLD(f) abuf->fields.sfmt_add.f
c906108c
SS		 2287 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2288 const IDESC * UNUSED idesc = abuf->idesc;
2289 int cycles = 0;
2290 {
2291 int referenced = 0;
2292 int UNUSED insn_referenced = abuf->written;
2293 cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
2294 }
2295 return cycles;
2296#undef FLD
2297}
2298
2299static int
2300model_test_add3 (SIM_CPU *current_cpu, void *sem_arg)
2301{
96baa820 2302#define FLD(f) abuf->fields.sfmt_add3.f
c906108c
SS		 2303 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2304 const IDESC * UNUSED idesc = abuf->idesc;
2305 int cycles = 0;
2306 {
2307 int referenced = 0;
2308 int UNUSED insn_referenced = abuf->written;
2309 cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
2310 }
2311 return cycles;
2312#undef FLD
2313}
2314
2315static int
2316model_test_and (SIM_CPU *current_cpu, void *sem_arg)
2317{
96baa820 2318#define FLD(f) abuf->fields.sfmt_add.f
c906108c
SS		 2319 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2320 const IDESC * UNUSED idesc = abuf->idesc;
2321 int cycles = 0;
2322 {
2323 int referenced = 0;
2324 int UNUSED insn_referenced = abuf->written;
2325 cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
2326 }
2327 return cycles;
2328#undef FLD
2329}
2330
2331static int
2332model_test_and3 (SIM_CPU *current_cpu, void *sem_arg)
2333{
96baa820 2334#define FLD(f) abuf->fields.sfmt_and3.f
c906108c
SS		 2335 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2336 const IDESC * UNUSED idesc = abuf->idesc;
2337 int cycles = 0;
2338 {
2339 int referenced = 0;
2340 int UNUSED insn_referenced = abuf->written;
2341 cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
2342 }
2343 return cycles;
2344#undef FLD
2345}
2346
2347static int
2348model_test_or (SIM_CPU *current_cpu, void *sem_arg)
2349{
96baa820 2350#define FLD(f) abuf->fields.sfmt_add.f
c906108c
SS		 2351 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2352 const IDESC * UNUSED idesc = abuf->idesc;
2353 int cycles = 0;
2354 {
2355 int referenced = 0;
2356 int UNUSED insn_referenced = abuf->written;
2357 cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
2358 }
2359 return cycles;
2360#undef FLD
2361}
2362
2363static int
2364model_test_or3 (SIM_CPU *current_cpu, void *sem_arg)
2365{
96baa820 2366#define FLD(f) abuf->fields.sfmt_and3.f
c906108c
SS		 2367 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2368 const IDESC * UNUSED idesc = abuf->idesc;
2369 int cycles = 0;
2370 {
2371 int referenced = 0;
2372 int UNUSED insn_referenced = abuf->written;
2373 cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
2374 }
2375 return cycles;
2376#undef FLD
2377}
2378
2379static int
2380model_test_xor (SIM_CPU *current_cpu, void *sem_arg)
2381{
96baa820 2382#define FLD(f) abuf->fields.sfmt_add.f
c906108c
SS		 2383 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2384 const IDESC * UNUSED idesc = abuf->idesc;
2385 int cycles = 0;
2386 {
2387 int referenced = 0;
2388 int UNUSED insn_referenced = abuf->written;
2389 cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
2390 }
2391 return cycles;
2392#undef FLD
2393}
2394
2395static int
2396model_test_xor3 (SIM_CPU *current_cpu, void *sem_arg)
2397{
96baa820 2398#define FLD(f) abuf->fields.sfmt_and3.f
c906108c
SS		 2399 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2400 const IDESC * UNUSED idesc = abuf->idesc;
2401 int cycles = 0;
2402 {
2403 int referenced = 0;
2404 int UNUSED insn_referenced = abuf->written;
2405 cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
2406 }
2407 return cycles;
2408#undef FLD
2409}
2410
2411static int
2412model_test_addi (SIM_CPU *current_cpu, void *sem_arg)
2413{
96baa820 2414#define FLD(f) abuf->fields.sfmt_addi.f
c906108c
SS		 2415 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2416 const IDESC * UNUSED idesc = abuf->idesc;
2417 int cycles = 0;
2418 {
2419 int referenced = 0;
2420 int UNUSED insn_referenced = abuf->written;
2421 cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
2422 }
2423 return cycles;
2424#undef FLD
2425}
2426
2427static int
2428model_test_addv (SIM_CPU *current_cpu, void *sem_arg)
2429{
96baa820 2430#define FLD(f) abuf->fields.sfmt_add.f
c906108c
SS		 2431 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2432 const IDESC * UNUSED idesc = abuf->idesc;
2433 int cycles = 0;
2434 {
2435 int referenced = 0;
2436 int UNUSED insn_referenced = abuf->written;
2437 cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
2438 }
2439 return cycles;
2440#undef FLD
2441}
2442
2443static int
2444model_test_addv3 (SIM_CPU *current_cpu, void *sem_arg)
2445{
96baa820 2446#define FLD(f) abuf->fields.sfmt_add3.f
c906108c
SS		 2447 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2448 const IDESC * UNUSED idesc = abuf->idesc;
2449 int cycles = 0;
2450 {
2451 int referenced = 0;
2452 int UNUSED insn_referenced = abuf->written;
2453 cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
2454 }
2455 return cycles;
2456#undef FLD
2457}
2458
2459static int
2460model_test_addx (SIM_CPU *current_cpu, void *sem_arg)
2461{
96baa820 2462#define FLD(f) abuf->fields.sfmt_add.f
c906108c
SS		 2463 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2464 const IDESC * UNUSED idesc = abuf->idesc;
2465 int cycles = 0;
2466 {
2467 int referenced = 0;
2468 int UNUSED insn_referenced = abuf->written;
2469 cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
2470 }
2471 return cycles;
2472#undef FLD
2473}
2474
2475static int
2476model_test_bc8 (SIM_CPU *current_cpu, void *sem_arg)
2477{
96baa820 2478#define FLD(f) abuf->fields.sfmt_bl8.f
c906108c
SS		 2479 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2480 const IDESC * UNUSED idesc = abuf->idesc;
2481 int cycles = 0;
2482 {
2483 int referenced = 0;
2484 int UNUSED insn_referenced = abuf->written;
2485 cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
2486 }
2487 return cycles;
2488#undef FLD
2489}
2490
2491static int
2492model_test_bc24 (SIM_CPU *current_cpu, void *sem_arg)
2493{
96baa820 2494#define FLD(f) abuf->fields.sfmt_bl24.f
c906108c
SS		 2495 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2496 const IDESC * UNUSED idesc = abuf->idesc;
2497 int cycles = 0;
2498 {
2499 int referenced = 0;
2500 int UNUSED insn_referenced = abuf->written;
2501 cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
2502 }
2503 return cycles;
2504#undef FLD
2505}
2506
2507static int
2508model_test_beq (SIM_CPU *current_cpu, void *sem_arg)
2509{
96baa820 2510#define FLD(f) abuf->fields.sfmt_beq.f
c906108c
SS		 2511 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2512 const IDESC * UNUSED idesc = abuf->idesc;
2513 int cycles = 0;
2514 {
2515 int referenced = 0;
2516 int UNUSED insn_referenced = abuf->written;
2517 cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
2518 }
2519 return cycles;
2520#undef FLD
2521}
2522
2523static int
2524model_test_beqz (SIM_CPU *current_cpu, void *sem_arg)
2525{
96baa820 2526#define FLD(f) abuf->fields.sfmt_beq.f
c906108c
SS		 2527 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2528 const IDESC * UNUSED idesc = abuf->idesc;
2529 int cycles = 0;
2530 {
2531 int referenced = 0;
2532 int UNUSED insn_referenced = abuf->written;
2533 cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
2534 }
2535 return cycles;
2536#undef FLD
2537}
2538
2539static int
2540model_test_bgez (SIM_CPU *current_cpu, void *sem_arg)
2541{
96baa820 2542#define FLD(f) abuf->fields.sfmt_beq.f
c906108c
SS		 2543 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2544 const IDESC * UNUSED idesc = abuf->idesc;
2545 int cycles = 0;
2546 {
2547 int referenced = 0;
2548 int UNUSED insn_referenced = abuf->written;
2549 cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
2550 }
2551 return cycles;
2552#undef FLD
2553}
2554
2555static int
2556model_test_bgtz (SIM_CPU *current_cpu, void *sem_arg)
2557{
96baa820 2558#define FLD(f) abuf->fields.sfmt_beq.f
c906108c
SS		 2559 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2560 const IDESC * UNUSED idesc = abuf->idesc;
2561 int cycles = 0;
2562 {
2563 int referenced = 0;
2564 int UNUSED insn_referenced = abuf->written;
2565 cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
2566 }
2567 return cycles;
2568#undef FLD
2569}
2570
2571static int
2572model_test_blez (SIM_CPU *current_cpu, void *sem_arg)
2573{
96baa820 2574#define FLD(f) abuf->fields.sfmt_beq.f
c906108c
SS		 2575 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2576 const IDESC * UNUSED idesc = abuf->idesc;
2577 int cycles = 0;
2578 {
2579 int referenced = 0;
2580 int UNUSED insn_referenced = abuf->written;
2581 cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
2582 }
2583 return cycles;
2584#undef FLD
2585}
2586
2587static int
2588model_test_bltz (SIM_CPU *current_cpu, void *sem_arg)
2589{
96baa820 2590#define FLD(f) abuf->fields.sfmt_beq.f
c906108c
SS		 2591 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2592 const IDESC * UNUSED idesc = abuf->idesc;
2593 int cycles = 0;
2594 {
2595 int referenced = 0;
2596 int UNUSED insn_referenced = abuf->written;
2597 cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
2598 }
2599 return cycles;
2600#undef FLD
2601}
2602
2603static int
2604model_test_bnez (SIM_CPU *current_cpu, void *sem_arg)
2605{
96baa820 2606#define FLD(f) abuf->fields.sfmt_beq.f
c906108c
SS		 2607 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2608 const IDESC * UNUSED idesc = abuf->idesc;
2609 int cycles = 0;
2610 {
2611 int referenced = 0;
2612 int UNUSED insn_referenced = abuf->written;
2613 cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
2614 }
2615 return cycles;
2616#undef FLD
2617}
2618
2619static int
2620model_test_bl8 (SIM_CPU *current_cpu, void *sem_arg)
2621{
96baa820 2622#define FLD(f) abuf->fields.sfmt_bl8.f
c906108c
SS		 2623 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2624 const IDESC * UNUSED idesc = abuf->idesc;
2625 int cycles = 0;
2626 {
2627 int referenced = 0;
2628 int UNUSED insn_referenced = abuf->written;
2629 cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
2630 }
2631 return cycles;
2632#undef FLD
2633}
2634
2635static int
2636model_test_bl24 (SIM_CPU *current_cpu, void *sem_arg)
2637{
96baa820 2638#define FLD(f) abuf->fields.sfmt_bl24.f
c906108c
SS		 2639 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2640 const IDESC * UNUSED idesc = abuf->idesc;
2641 int cycles = 0;
2642 {
2643 int referenced = 0;
2644 int UNUSED insn_referenced = abuf->written;
2645 cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
2646 }
2647 return cycles;
2648#undef FLD
2649}
2650
2651static int
2652model_test_bnc8 (SIM_CPU *current_cpu, void *sem_arg)
2653{
96baa820 2654#define FLD(f) abuf->fields.sfmt_bl8.f
c906108c
SS		 2655 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2656 const IDESC * UNUSED idesc = abuf->idesc;
2657 int cycles = 0;
2658 {
2659 int referenced = 0;
2660 int UNUSED insn_referenced = abuf->written;
2661 cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
2662 }
2663 return cycles;
2664#undef FLD
2665}
2666
2667static int
2668model_test_bnc24 (SIM_CPU *current_cpu, void *sem_arg)
2669{
96baa820 2670#define FLD(f) abuf->fields.sfmt_bl24.f
c906108c
SS		 2671 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2672 const IDESC * UNUSED idesc = abuf->idesc;
2673 int cycles = 0;
2674 {
2675 int referenced = 0;
2676 int UNUSED insn_referenced = abuf->written;
2677 cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
2678 }
2679 return cycles;
2680#undef FLD
2681}
2682
2683static int
2684model_test_bne (SIM_CPU *current_cpu, void *sem_arg)
2685{
96baa820 2686#define FLD(f) abuf->fields.sfmt_beq.f
c906108c
SS		 2687 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2688 const IDESC * UNUSED idesc = abuf->idesc;
2689 int cycles = 0;
2690 {
2691 int referenced = 0;
2692 int UNUSED insn_referenced = abuf->written;
2693 cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
2694 }
2695 return cycles;
2696#undef FLD
2697}
2698
2699static int
2700model_test_bra8 (SIM_CPU *current_cpu, void *sem_arg)
2701{
96baa820 2702#define FLD(f) abuf->fields.sfmt_bl8.f
c906108c
SS		 2703 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2704 const IDESC * UNUSED idesc = abuf->idesc;
2705 int cycles = 0;
2706 {
2707 int referenced = 0;
2708 int UNUSED insn_referenced = abuf->written;
2709 cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
2710 }
2711 return cycles;
2712#undef FLD
2713}
2714
2715static int
2716model_test_bra24 (SIM_CPU *current_cpu, void *sem_arg)
2717{
96baa820 2718#define FLD(f) abuf->fields.sfmt_bl24.f
c906108c
SS		 2719 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2720 const IDESC * UNUSED idesc = abuf->idesc;
2721 int cycles = 0;
2722 {
2723 int referenced = 0;
2724 int UNUSED insn_referenced = abuf->written;
2725 cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
2726 }
2727 return cycles;
2728#undef FLD
2729}
2730
2731static int
2732model_test_cmp (SIM_CPU *current_cpu, void *sem_arg)
2733{
96baa820 2734#define FLD(f) abuf->fields.sfmt_st_plus.f
c906108c
SS		 2735 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2736 const IDESC * UNUSED idesc = abuf->idesc;
2737 int cycles = 0;
2738 {
2739 int referenced = 0;
2740 int UNUSED insn_referenced = abuf->written;
2741 cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
2742 }
2743 return cycles;
2744#undef FLD
2745}
2746
2747static int
2748model_test_cmpi (SIM_CPU *current_cpu, void *sem_arg)
2749{
96baa820 2750#define FLD(f) abuf->fields.sfmt_st_d.f
c906108c
SS		 2751 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2752 const IDESC * UNUSED idesc = abuf->idesc;
2753 int cycles = 0;
2754 {
2755 int referenced = 0;
2756 int UNUSED insn_referenced = abuf->written;
2757 cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
2758 }
2759 return cycles;
2760#undef FLD
2761}
2762
2763static int
2764model_test_cmpu (SIM_CPU *current_cpu, void *sem_arg)
2765{
96baa820 2766#define FLD(f) abuf->fields.sfmt_st_plus.f
c906108c
SS		 2767 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2768 const IDESC * UNUSED idesc = abuf->idesc;
2769 int cycles = 0;
2770 {
2771 int referenced = 0;
2772 int UNUSED insn_referenced = abuf->written;
2773 cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
2774 }
2775 return cycles;
2776#undef FLD
2777}
2778
2779static int
2780model_test_cmpui (SIM_CPU *current_cpu, void *sem_arg)
2781{
96baa820 2782#define FLD(f) abuf->fields.sfmt_st_d.f
c906108c
SS		 2783 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2784 const IDESC * UNUSED idesc = abuf->idesc;
2785 int cycles = 0;
2786 {
2787 int referenced = 0;
2788 int UNUSED insn_referenced = abuf->written;
2789 cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
2790 }
2791 return cycles;
2792#undef FLD
2793}
2794
2795static int
2796model_test_div (SIM_CPU *current_cpu, void *sem_arg)
2797{
96baa820 2798#define FLD(f) abuf->fields.sfmt_add.f
c906108c
SS		 2799 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2800 const IDESC * UNUSED idesc = abuf->idesc;
2801 int cycles = 0;
2802 {
2803 int referenced = 0;
2804 int UNUSED insn_referenced = abuf->written;
2805 cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
2806 }
2807 return cycles;
2808#undef FLD
2809}
2810
2811static int
2812model_test_divu (SIM_CPU *current_cpu, void *sem_arg)
2813{
96baa820 2814#define FLD(f) abuf->fields.sfmt_add.f
c906108c
SS		 2815 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2816 const IDESC * UNUSED idesc = abuf->idesc;
2817 int cycles = 0;
2818 {
2819 int referenced = 0;
2820 int UNUSED insn_referenced = abuf->written;
2821 cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
2822 }
2823 return cycles;
2824#undef FLD
2825}
2826
2827static int
2828model_test_rem (SIM_CPU *current_cpu, void *sem_arg)
2829{
96baa820 2830#define FLD(f) abuf->fields.sfmt_add.f
c906108c
SS		 2831 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2832 const IDESC * UNUSED idesc = abuf->idesc;
2833 int cycles = 0;
2834 {
2835 int referenced = 0;
2836 int UNUSED insn_referenced = abuf->written;
2837 cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
2838 }
2839 return cycles;
2840#undef FLD
2841}
2842
2843static int
2844model_test_remu (SIM_CPU *current_cpu, void *sem_arg)
2845{
96baa820 2846#define FLD(f) abuf->fields.sfmt_add.f
c906108c
SS		 2847 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2848 const IDESC * UNUSED idesc = abuf->idesc;
2849 int cycles = 0;
2850 {
2851 int referenced = 0;
2852 int UNUSED insn_referenced = abuf->written;
2853 cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
2854 }
2855 return cycles;
2856#undef FLD
2857}
2858
2859static int
2860model_test_jl (SIM_CPU *current_cpu, void *sem_arg)
2861{
96baa820 2862#define FLD(f) abuf->fields.sfmt_jl.f
c906108c
SS		 2863 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2864 const IDESC * UNUSED idesc = abuf->idesc;
2865 int cycles = 0;
2866 {
2867 int referenced = 0;
2868 int UNUSED insn_referenced = abuf->written;
2869 cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
2870 }
2871 return cycles;
2872#undef FLD
2873}
2874
2875static int
2876model_test_jmp (SIM_CPU *current_cpu, void *sem_arg)
2877{
de8f5985 2878#define FLD(f) abuf->fields.sfmt_jl.f
c906108c
SS		 2879 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2880 const IDESC * UNUSED idesc = abuf->idesc;
2881 int cycles = 0;
2882 {
2883 int referenced = 0;
2884 int UNUSED insn_referenced = abuf->written;
2885 cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
2886 }
2887 return cycles;
2888#undef FLD
2889}
2890
2891static int
2892model_test_ld (SIM_CPU *current_cpu, void *sem_arg)
2893{
96baa820 2894#define FLD(f) abuf->fields.sfmt_ld_plus.f
c906108c
SS		 2895 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2896 const IDESC * UNUSED idesc = abuf->idesc;
2897 int cycles = 0;
2898 {
2899 int referenced = 0;
2900 int UNUSED insn_referenced = abuf->written;
2901 cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
2902 }
2903 return cycles;
2904#undef FLD
2905}
2906
2907static int
2908model_test_ld_d (SIM_CPU *current_cpu, void *sem_arg)
2909{
96baa820 2910#define FLD(f) abuf->fields.sfmt_add3.f
c906108c
SS		 2911 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2912 const IDESC * UNUSED idesc = abuf->idesc;
2913 int cycles = 0;
2914 {
2915 int referenced = 0;
2916 int UNUSED insn_referenced = abuf->written;
2917 cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
2918 }
2919 return cycles;
2920#undef FLD
2921}
2922
2923static int
2924model_test_ldb (SIM_CPU *current_cpu, void *sem_arg)
2925{
96baa820 2926#define FLD(f) abuf->fields.sfmt_ld_plus.f
c906108c
SS		 2927 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2928 const IDESC * UNUSED idesc = abuf->idesc;
2929 int cycles = 0;
2930 {
2931 int referenced = 0;
2932 int UNUSED insn_referenced = abuf->written;
2933 cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
2934 }
2935 return cycles;
2936#undef FLD
2937}
2938
2939static int
2940model_test_ldb_d (SIM_CPU *current_cpu, void *sem_arg)
2941{
96baa820 2942#define FLD(f) abuf->fields.sfmt_add3.f
c906108c
SS		 2943 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2944 const IDESC * UNUSED idesc = abuf->idesc;
2945 int cycles = 0;
2946 {
2947 int referenced = 0;
2948 int UNUSED insn_referenced = abuf->written;
2949 cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
2950 }
2951 return cycles;
2952#undef FLD
2953}
2954
2955static int
2956model_test_ldh (SIM_CPU *current_cpu, void *sem_arg)
2957{
96baa820 2958#define FLD(f) abuf->fields.sfmt_ld_plus.f
c906108c
SS		 2959 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2960 const IDESC * UNUSED idesc = abuf->idesc;
2961 int cycles = 0;
2962 {
2963 int referenced = 0;
2964 int UNUSED insn_referenced = abuf->written;
2965 cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
2966 }
2967 return cycles;
2968#undef FLD
2969}
2970
2971static int
2972model_test_ldh_d (SIM_CPU *current_cpu, void *sem_arg)
2973{
96baa820 2974#define FLD(f) abuf->fields.sfmt_add3.f
c906108c
SS		 2975 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2976 const IDESC * UNUSED idesc = abuf->idesc;
2977 int cycles = 0;
2978 {
2979 int referenced = 0;
2980 int UNUSED insn_referenced = abuf->written;
2981 cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
2982 }
2983 return cycles;
2984#undef FLD
2985}
2986
2987static int
2988model_test_ldub (SIM_CPU *current_cpu, void *sem_arg)
2989{
96baa820 2990#define FLD(f) abuf->fields.sfmt_ld_plus.f
c906108c
SS		 2991 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2992 const IDESC * UNUSED idesc = abuf->idesc;
2993 int cycles = 0;
2994 {
2995 int referenced = 0;
2996 int UNUSED insn_referenced = abuf->written;
2997 cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
2998 }
2999 return cycles;
3000#undef FLD
3001}
3002
3003static int
3004model_test_ldub_d (SIM_CPU *current_cpu, void *sem_arg)
3005{
96baa820 3006#define FLD(f) abuf->fields.sfmt_add3.f
c906108c
SS		 3007 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
3008 const IDESC * UNUSED idesc = abuf->idesc;
3009 int cycles = 0;
3010 {
3011 int referenced = 0;
3012 int UNUSED insn_referenced = abuf->written;
3013 cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
3014 }
3015 return cycles;
3016#undef FLD
3017}
3018
3019static int
3020model_test_lduh (SIM_CPU *current_cpu, void *sem_arg)
3021{
96baa820 3022#define FLD(f) abuf->fields.sfmt_ld_plus.f
c906108c
SS		 3023 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
3024 const IDESC * UNUSED idesc = abuf->idesc;
3025 int cycles = 0;
3026 {
3027 int referenced = 0;
3028 int UNUSED insn_referenced = abuf->written;
3029 cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
3030 }
3031 return cycles;
3032#undef FLD
3033}
3034
3035static int
3036model_test_lduh_d (SIM_CPU *current_cpu, void *sem_arg)
3037{
96baa820 3038#define FLD(f) abuf->fields.sfmt_add3.f
c906108c
SS		 3039 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
3040 const IDESC * UNUSED idesc = abuf->idesc;
3041 int cycles = 0;
3042 {
3043 int referenced = 0;
3044 int UNUSED insn_referenced = abuf->written;
3045 cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
3046 }
3047 return cycles;
3048#undef FLD
3049}
3050
3051static int
3052model_test_ld_plus (SIM_CPU *current_cpu, void *sem_arg)
3053{
96baa820 3054#define FLD(f) abuf->fields.sfmt_ld_plus.f
c906108c
SS		 3055 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
3056 const IDESC * UNUSED idesc = abuf->idesc;
3057 int cycles = 0;
3058 {
3059 int referenced = 0;
3060 int UNUSED insn_referenced = abuf->written;
3061 cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
3062 }
3063 return cycles;
3064#undef FLD
3065}
3066
3067static int
3068model_test_ld24 (SIM_CPU *current_cpu, void *sem_arg)
3069{
96baa820 3070#define FLD(f) abuf->fields.sfmt_ld24.f
c906108c
SS		 3071 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
3072 const IDESC * UNUSED idesc = abuf->idesc;
3073 int cycles = 0;
3074 {
3075 int referenced = 0;
3076 int UNUSED insn_referenced = abuf->written;
3077 cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
3078 }
3079 return cycles;
3080#undef FLD
3081}
3082
3083static int
3084model_test_ldi8 (SIM_CPU *current_cpu, void *sem_arg)
3085{
96baa820 3086#define FLD(f) abuf->fields.sfmt_addi.f
c906108c
SS		 3087 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
3088 const IDESC * UNUSED idesc = abuf->idesc;
3089 int cycles = 0;
3090 {
3091 int referenced = 0;
3092 int UNUSED insn_referenced = abuf->written;
3093 cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
3094 }
3095 return cycles;
3096#undef FLD
3097}
3098
3099static int
3100model_test_ldi16 (SIM_CPU *current_cpu, void *sem_arg)
3101{
96baa820 3102#define FLD(f) abuf->fields.sfmt_add3.f
c906108c
SS		 3103 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
3104 const IDESC * UNUSED idesc = abuf->idesc;
3105 int cycles = 0;
3106 {
3107 int referenced = 0;
3108 int UNUSED insn_referenced = abuf->written;
3109 cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
3110 }
3111 return cycles;
3112#undef FLD
3113}
3114
3115static int
3116model_test_lock (SIM_CPU *current_cpu, void *sem_arg)
3117{
96baa820 3118#define FLD(f) abuf->fields.sfmt_ld_plus.f
c906108c
SS		 3119 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
3120 const IDESC * UNUSED idesc = abuf->idesc;
3121 int cycles = 0;
3122 {
3123 int referenced = 0;
3124 int UNUSED insn_referenced = abuf->written;
3125 cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
3126 }
3127 return cycles;
3128#undef FLD
3129}
3130
3131static int
3132model_test_machi (SIM_CPU *current_cpu, void *sem_arg)
3133{
96baa820 3134#define FLD(f) abuf->fields.sfmt_st_plus.f
c906108c
SS		 3135 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
3136 const IDESC * UNUSED idesc = abuf->idesc;
3137 int cycles = 0;
3138 {
3139 int referenced = 0;
3140 int UNUSED insn_referenced = abuf->written;
3141 cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
3142 }
3143 return cycles;
3144#undef FLD
3145}
3146
3147static int
3148model_test_maclo (SIM_CPU *current_cpu, void *sem_arg)
3149{
96baa820 3150#define FLD(f) abuf->fields.sfmt_st_plus.f
c906108c
SS		 3151 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
3152 const IDESC * UNUSED idesc = abuf->idesc;
3153 int cycles = 0;
3154 {
3155 int referenced = 0;
3156 int UNUSED insn_referenced = abuf->written;
3157 cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
3158 }
3159 return cycles;
3160#undef FLD
3161}
3162
3163static int
3164model_test_macwhi (SIM_CPU *current_cpu, void *sem_arg)
3165{
96baa820 3166#define FLD(f) abuf->fields.sfmt_st_plus.f
c906108c
SS		 3167 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
3168 const IDESC * UNUSED idesc = abuf->idesc;
3169 int cycles = 0;
3170 {
3171 int referenced = 0;
3172 int UNUSED insn_referenced = abuf->written;
3173 cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
3174 }
3175 return cycles;
3176#undef FLD
3177}
3178
3179static int
3180model_test_macwlo (SIM_CPU *current_cpu, void *sem_arg)
3181{
96baa820 3182#define FLD(f) abuf->fields.sfmt_st_plus.f
c906108c
SS		 3183 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
3184 const IDESC * UNUSED idesc = abuf->idesc;
3185 int cycles = 0;
3186 {
3187 int referenced = 0;
3188 int UNUSED insn_referenced = abuf->written;
3189 cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
3190 }
3191 return cycles;
3192#undef FLD
3193}
3194
3195static int
3196model_test_mul (SIM_CPU *current_cpu, void *sem_arg)
3197{
96baa820 3198#define FLD(f) abuf->fields.sfmt_add.f
c906108c
SS		 3199 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
3200 const IDESC * UNUSED idesc = abuf->idesc;
3201 int cycles = 0;
3202 {
3203 int referenced = 0;
3204 int UNUSED insn_referenced = abuf->written;
3205 cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
3206 }
3207 return cycles;
3208#undef FLD
3209}
3210
3211static int
3212model_test_mulhi (SIM_CPU *current_cpu, void *sem_arg)
3213{
96baa820 3214#define FLD(f) abuf->fields.sfmt_st_plus.f
c906108c
SS		 3215 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
3216 const IDESC * UNUSED idesc = abuf->idesc;
3217 int cycles = 0;
3218 {
3219 int referenced = 0;
3220 int UNUSED insn_referenced = abuf->written;
3221 cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
3222 }
3223 return cycles;
3224#undef FLD
3225}
3226
3227static int
3228model_test_mullo (SIM_CPU *current_cpu, void *sem_arg)
3229{
96baa820 3230#define FLD(f) abuf->fields.sfmt_st_plus.f
c906108c
SS		 3231 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
3232 const IDESC * UNUSED idesc = abuf->idesc;
3233 int cycles = 0;
3234 {
3235 int referenced = 0;
3236 int UNUSED insn_referenced = abuf->written;
3237 cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
3238 }
3239 return cycles;
3240#undef FLD
3241}
3242
3243static int
3244model_test_mulwhi (SIM_CPU *current_cpu, void *sem_arg)
3245{
96baa820 3246#define FLD(f) abuf->fields.sfmt_st_plus.f
c906108c
SS		 3247 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
3248 const IDESC * UNUSED idesc = abuf->idesc;
3249 int cycles = 0;
3250 {
3251 int referenced = 0;
3252 int UNUSED insn_referenced = abuf->written;
3253 cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
3254 }
3255 return cycles;
3256#undef FLD
3257}
3258
3259static int
3260model_test_mulwlo (SIM_CPU *current_cpu, void *sem_arg)
3261{
96baa820 3262#define FLD(f) abuf->fields.sfmt_st_plus.f
c906108c
SS		 3263 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
3264 const IDESC * UNUSED idesc = abuf->idesc;
3265 int cycles = 0;
3266 {
3267 int referenced = 0;
3268 int UNUSED insn_referenced = abuf->written;
3269 cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
3270 }
3271 return cycles;
3272#undef FLD
3273}
3274
3275static int
3276model_test_mv (SIM_CPU *current_cpu, void *sem_arg)
3277{
96baa820 3278#define FLD(f) abuf->fields.sfmt_ld_plus.f
c906108c
SS		 3279 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
3280 const IDESC * UNUSED idesc = abuf->idesc;
3281 int cycles = 0;
3282 {
3283 int referenced = 0;
3284 int UNUSED insn_referenced = abuf->written;
3285 cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
3286 }
3287 return cycles;
3288#undef FLD
3289}
3290
3291static int
3292model_test_mvfachi (SIM_CPU *current_cpu, void *sem_arg)
3293{
96baa820 3294#define FLD(f) abuf->fields.sfmt_seth.f
c906108c
SS		 3295 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
3296 const IDESC * UNUSED idesc = abuf->idesc;
3297 int cycles = 0;
3298 {
3299 int referenced = 0;
3300 int UNUSED insn_referenced = abuf->written;
3301 cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
3302 }
3303 return cycles;
3304#undef FLD
3305}
3306
3307static int
3308model_test_mvfaclo (SIM_CPU *current_cpu, void *sem_arg)
3309{
96baa820 3310#define FLD(f) abuf->fields.sfmt_seth.f
c906108c
SS		 3311 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
3312 const IDESC * UNUSED idesc = abuf->idesc;
3313 int cycles = 0;
3314 {
3315 int referenced = 0;
3316 int UNUSED insn_referenced = abuf->written;
3317 cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
3318 }
3319 return cycles;
3320#undef FLD
3321}
3322
3323static int
3324model_test_mvfacmi (SIM_CPU *current_cpu, void *sem_arg)
3325{
96baa820 3326#define FLD(f) abuf->fields.sfmt_seth.f
c906108c
SS		 3327 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
3328 const IDESC * UNUSED idesc = abuf->idesc;
3329 int cycles = 0;
3330 {
3331 int referenced = 0;
3332 int UNUSED insn_referenced = abuf->written;
3333 cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
3334 }
3335 return cycles;
3336#undef FLD
3337}
3338
3339static int
3340model_test_mvfc (SIM_CPU *current_cpu, void *sem_arg)
3341{
de8f5985 3342#define FLD(f) abuf->fields.sfmt_ld_plus.f
c906108c
SS		 3343 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
3344 const IDESC * UNUSED idesc = abuf->idesc;
3345 int cycles = 0;
3346 {
3347 int referenced = 0;
3348 int UNUSED insn_referenced = abuf->written;
3349 cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
3350 }
3351 return cycles;
3352#undef FLD
3353}
3354
3355static int
3356model_test_mvtachi (SIM_CPU *current_cpu, void *sem_arg)
3357{
96baa820 3358#define FLD(f) abuf->fields.sfmt_st_plus.f
c906108c
SS		 3359 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
3360 const IDESC * UNUSED idesc = abuf->idesc;
3361 int cycles = 0;
3362 {
3363 int referenced = 0;
3364 int UNUSED insn_referenced = abuf->written;
3365 cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
3366 }
3367 return cycles;
3368#undef FLD
3369}
3370
3371static int
3372model_test_mvtaclo (SIM_CPU *current_cpu, void *sem_arg)
3373{
96baa820 3374#define FLD(f) abuf->fields.sfmt_st_plus.f
c906108c
SS		 3375 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
3376 const IDESC * UNUSED idesc = abuf->idesc;
3377 int cycles = 0;
3378 {
3379 int referenced = 0;
3380 int UNUSED insn_referenced = abuf->written;
3381 cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
3382 }
3383 return cycles;
3384#undef FLD
3385}
3386
3387static int
3388model_test_mvtc (SIM_CPU *current_cpu, void *sem_arg)
3389{
de8f5985 3390#define FLD(f) abuf->fields.sfmt_ld_plus.f
c906108c
SS		 3391 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
3392 const IDESC * UNUSED idesc = abuf->idesc;
3393 int cycles = 0;
3394 {
3395 int referenced = 0;
3396 int UNUSED insn_referenced = abuf->written;
3397 cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
3398 }
3399 return cycles;
3400#undef FLD
3401}
3402
3403static int
3404model_test_neg (SIM_CPU *current_cpu, void *sem_arg)
3405{
96baa820 3406#define FLD(f) abuf->fields.sfmt_ld_plus.f
c906108c
SS		 3407 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
3408 const IDESC * UNUSED idesc = abuf->idesc;
3409 int cycles = 0;
3410 {
3411 int referenced = 0;
3412 int UNUSED insn_referenced = abuf->written;
3413 cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
3414 }
3415 return cycles;
3416#undef FLD
3417}
3418
3419static int
3420model_test_nop (SIM_CPU *current_cpu, void *sem_arg)
3421{
96baa820 3422#define FLD(f) abuf->fields.fmt_empty.f
c906108c
SS		 3423 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
3424 const IDESC * UNUSED idesc = abuf->idesc;
3425 int cycles = 0;
3426 {
3427 int referenced = 0;
3428 int UNUSED insn_referenced = abuf->written;
3429 cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
3430 }
3431 return cycles;
3432#undef FLD
3433}
3434
3435static int
3436model_test_not (SIM_CPU *current_cpu, void *sem_arg)
3437{
96baa820 3438#define FLD(f) abuf->fields.sfmt_ld_plus.f
c906108c
SS		 3439 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
3440 const IDESC * UNUSED idesc = abuf->idesc;
3441 int cycles = 0;
3442 {
3443 int referenced = 0;
3444 int UNUSED insn_referenced = abuf->written;
3445 cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
3446 }
3447 return cycles;
3448#undef FLD
3449}
3450
3451static int
3452model_test_rac (SIM_CPU *current_cpu, void *sem_arg)
3453{
96baa820 3454#define FLD(f) abuf->fields.fmt_empty.f
c906108c
SS		 3455 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
3456 const IDESC * UNUSED idesc = abuf->idesc;
3457 int cycles = 0;
3458 {
3459 int referenced = 0;
3460 int UNUSED insn_referenced = abuf->written;
3461 cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
3462 }
3463 return cycles;
3464#undef FLD
3465}
3466
3467static int
3468model_test_rach (SIM_CPU *current_cpu, void *sem_arg)
3469{
96baa820 3470#define FLD(f) abuf->fields.fmt_empty.f
c906108c
SS		 3471 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
3472 const IDESC * UNUSED idesc = abuf->idesc;
3473 int cycles = 0;
3474 {
3475 int referenced = 0;
3476 int UNUSED insn_referenced = abuf->written;
3477 cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
3478 }
3479 return cycles;
3480#undef FLD
3481}
3482
3483static int
3484model_test_rte (SIM_CPU *current_cpu, void *sem_arg)
3485{
96baa820 3486#define FLD(f) abuf->fields.fmt_empty.f
c906108c
SS		 3487 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
3488 const IDESC * UNUSED idesc = abuf->idesc;
3489 int cycles = 0;
3490 {
3491 int referenced = 0;
3492 int UNUSED insn_referenced = abuf->written;
3493 cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
3494 }
3495 return cycles;
3496#undef FLD
3497}
3498
3499static int
3500model_test_seth (SIM_CPU *current_cpu, void *sem_arg)
3501{
96baa820 3502#define FLD(f) abuf->fields.sfmt_seth.f
c906108c
SS		 3503 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
3504 const IDESC * UNUSED idesc = abuf->idesc;
3505 int cycles = 0;
3506 {
3507 int referenced = 0;
3508 int UNUSED insn_referenced = abuf->written;
3509 cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
3510 }
3511 return cycles;
3512#undef FLD
3513}
3514
3515static int
3516model_test_sll (SIM_CPU *current_cpu, void *sem_arg)
3517{
96baa820 3518#define FLD(f) abuf->fields.sfmt_add.f
c906108c
SS		 3519 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
3520 const IDESC * UNUSED idesc = abuf->idesc;
3521 int cycles = 0;
3522 {
3523 int referenced = 0;
3524 int UNUSED insn_referenced = abuf->written;
3525 cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
3526 }
3527 return cycles;
3528#undef FLD
3529}
3530
3531static int
3532model_test_sll3 (SIM_CPU *current_cpu, void *sem_arg)
3533{
96baa820 3534#define FLD(f) abuf->fields.sfmt_add3.f
c906108c
SS		 3535 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
3536 const IDESC * UNUSED idesc = abuf->idesc;
3537 int cycles = 0;
3538 {
3539 int referenced = 0;
3540 int UNUSED insn_referenced = abuf->written;
3541 cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
3542 }
3543 return cycles;
3544#undef FLD
3545}
3546
3547static int
3548model_test_slli (SIM_CPU *current_cpu, void *sem_arg)
3549{
96baa820 3550#define FLD(f) abuf->fields.sfmt_slli.f
c906108c
SS		 3551 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
3552 const IDESC * UNUSED idesc = abuf->idesc;
3553 int cycles = 0;
3554 {
3555 int referenced = 0;
3556 int UNUSED insn_referenced = abuf->written;
3557 cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
3558 }
3559 return cycles;
3560#undef FLD
3561}
3562
3563static int
3564model_test_sra (SIM_CPU *current_cpu, void *sem_arg)
3565{
96baa820 3566#define FLD(f) abuf->fields.sfmt_add.f
c906108c
SS		 3567 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
3568 const IDESC * UNUSED idesc = abuf->idesc;
3569 int cycles = 0;
3570 {
3571 int referenced = 0;
3572 int UNUSED insn_referenced = abuf->written;
3573 cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
3574 }
3575 return cycles;
3576#undef FLD
3577}
3578
3579static int
3580model_test_sra3 (SIM_CPU *current_cpu, void *sem_arg)
3581{
96baa820 3582#define FLD(f) abuf->fields.sfmt_add3.f
c906108c
SS		 3583 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
3584 const IDESC * UNUSED idesc = abuf->idesc;
3585 int cycles = 0;
3586 {
3587 int referenced = 0;
3588 int UNUSED insn_referenced = abuf->written;
3589 cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
3590 }
3591 return cycles;
3592#undef FLD
3593}
3594
3595static int
3596model_test_srai (SIM_CPU *current_cpu, void *sem_arg)
3597{
96baa820 3598#define FLD(f) abuf->fields.sfmt_slli.f
c906108c
SS		 3599 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
3600 const IDESC * UNUSED idesc = abuf->idesc;
3601 int cycles = 0;
3602 {
3603 int referenced = 0;
3604 int UNUSED insn_referenced = abuf->written;
3605 cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
3606 }
3607 return cycles;
3608#undef FLD
3609}
3610
3611static int
3612model_test_srl (SIM_CPU *current_cpu, void *sem_arg)
3613{
96baa820 3614#define FLD(f) abuf->fields.sfmt_add.f
c906108c
SS		 3615 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
3616 const IDESC * UNUSED idesc = abuf->idesc;
3617 int cycles = 0;
3618 {
3619 int referenced = 0;
3620 int UNUSED insn_referenced = abuf->written;
3621 cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
3622 }
3623 return cycles;
3624#undef FLD
3625}
3626
3627static int
3628model_test_srl3 (SIM_CPU *current_cpu, void *sem_arg)
3629{
96baa820 3630#define FLD(f) abuf->fields.sfmt_add3.f
c906108c
SS		 3631 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
3632 const IDESC * UNUSED idesc = abuf->idesc;
3633 int cycles = 0;
3634 {
3635 int referenced = 0;
3636 int UNUSED insn_referenced = abuf->written;
3637 cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
3638 }
3639 return cycles;
3640#undef FLD
3641}
3642
3643static int
3644model_test_srli (SIM_CPU *current_cpu, void *sem_arg)
3645{
96baa820 3646#define FLD(f) abuf->fields.sfmt_slli.f
c906108c
SS		 3647 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
3648 const IDESC * UNUSED idesc = abuf->idesc;
3649 int cycles = 0;
3650 {
3651 int referenced = 0;
3652 int UNUSED insn_referenced = abuf->written;
3653 cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
3654 }
3655 return cycles;
3656#undef FLD
3657}
3658
3659static int
3660model_test_st (SIM_CPU *current_cpu, void *sem_arg)
3661{
96baa820 3662#define FLD(f) abuf->fields.sfmt_st_plus.f
c906108c
SS		 3663 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
3664 const IDESC * UNUSED idesc = abuf->idesc;
3665 int cycles = 0;
3666 {
3667 int referenced = 0;
3668 int UNUSED insn_referenced = abuf->written;
3669 cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
3670 }
3671 return cycles;
3672#undef FLD
3673}
3674
3675static int
3676model_test_st_d (SIM_CPU *current_cpu, void *sem_arg)
3677{
96baa820 3678#define FLD(f) abuf->fields.sfmt_st_d.f
c906108c
SS		 3679 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
3680 const IDESC * UNUSED idesc = abuf->idesc;
3681 int cycles = 0;
3682 {
3683 int referenced = 0;
3684 int UNUSED insn_referenced = abuf->written;
3685 cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
3686 }
3687 return cycles;
3688#undef FLD
3689}
3690
3691static int
3692model_test_stb (SIM_CPU *current_cpu, void *sem_arg)
3693{
96baa820 3694#define FLD(f) abuf->fields.sfmt_st_plus.f
c906108c
SS		 3695 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
3696 const IDESC * UNUSED idesc = abuf->idesc;
3697 int cycles = 0;
3698 {
3699 int referenced = 0;
3700 int UNUSED insn_referenced = abuf->written;
3701 cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
3702 }
3703 return cycles;
3704#undef FLD
3705}
3706
3707static int
3708model_test_stb_d (SIM_CPU *current_cpu, void *sem_arg)
3709{
96baa820 3710#define FLD(f) abuf->fields.sfmt_st_d.f
c906108c
SS		 3711 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
3712 const IDESC * UNUSED idesc = abuf->idesc;
3713 int cycles = 0;
3714 {
3715 int referenced = 0;
3716 int UNUSED insn_referenced = abuf->written;
3717 cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
3718 }
3719 return cycles;
3720#undef FLD
3721}
3722
3723static int
3724model_test_sth (SIM_CPU *current_cpu, void *sem_arg)
3725{
96baa820 3726#define FLD(f) abuf->fields.sfmt_st_plus.f
c906108c
SS		 3727 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
3728 const IDESC * UNUSED idesc = abuf->idesc;
3729 int cycles = 0;
3730 {
3731 int referenced = 0;
3732 int UNUSED insn_referenced = abuf->written;
3733 cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
3734 }
3735 return cycles;
3736#undef FLD
3737}
3738
3739static int
3740model_test_sth_d (SIM_CPU *current_cpu, void *sem_arg)
3741{
96baa820 3742#define FLD(f) abuf->fields.sfmt_st_d.f
c906108c
SS		 3743 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
3744 const IDESC * UNUSED idesc = abuf->idesc;
3745 int cycles = 0;
3746 {
3747 int referenced = 0;
3748 int UNUSED insn_referenced = abuf->written;
3749 cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
3750 }
3751 return cycles;
3752#undef FLD
3753}
3754
3755static int
3756model_test_st_plus (SIM_CPU *current_cpu, void *sem_arg)
3757{
96baa820 3758#define FLD(f) abuf->fields.sfmt_st_plus.f
c906108c
SS		 3759 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
3760 const IDESC * UNUSED idesc = abuf->idesc;
3761 int cycles = 0;
3762 {
3763 int referenced = 0;
3764 int UNUSED insn_referenced = abuf->written;
3765 cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
3766 }
3767 return cycles;
3768#undef FLD
3769}
3770
3771static int
3772model_test_st_minus (SIM_CPU *current_cpu, void *sem_arg)
3773{
96baa820 3774#define FLD(f) abuf->fields.sfmt_st_plus.f
c906108c
SS		 3775 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
3776 const IDESC * UNUSED idesc = abuf->idesc;
3777 int cycles = 0;
3778 {
3779 int referenced = 0;
3780 int UNUSED insn_referenced = abuf->written;
3781 cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
3782 }
3783 return cycles;
3784#undef FLD
3785}
3786
3787static int
3788model_test_sub (SIM_CPU *current_cpu, void *sem_arg)
3789{
96baa820 3790#define FLD(f) abuf->fields.sfmt_add.f
c906108c
SS		 3791 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
3792 const IDESC * UNUSED idesc = abuf->idesc;
3793 int cycles = 0;
3794 {
3795 int referenced = 0;
3796 int UNUSED insn_referenced = abuf->written;
3797 cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
3798 }
3799 return cycles;
3800#undef FLD
3801}
3802
3803static int
3804model_test_subv (SIM_CPU *current_cpu, void *sem_arg)
3805{
96baa820 3806#define FLD(f) abuf->fields.sfmt_add.f
c906108c
SS		 3807 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
3808 const IDESC * UNUSED idesc = abuf->idesc;
3809 int cycles = 0;
3810 {
3811 int referenced = 0;
3812 int UNUSED insn_referenced = abuf->written;
3813 cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
3814 }
3815 return cycles;
3816#undef FLD
3817}
3818
3819static int
3820model_test_subx (SIM_CPU *current_cpu, void *sem_arg)
3821{
96baa820 3822#define FLD(f) abuf->fields.sfmt_add.f
c906108c
SS		 3823 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
3824 const IDESC * UNUSED idesc = abuf->idesc;
3825 int cycles = 0;
3826 {
3827 int referenced = 0;
3828 int UNUSED insn_referenced = abuf->written;
3829 cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
3830 }
3831 return cycles;
3832#undef FLD
3833}
3834
3835static int
3836model_test_trap (SIM_CPU *current_cpu, void *sem_arg)
3837{
96baa820 3838#define FLD(f) abuf->fields.sfmt_trap.f
c906108c
SS		 3839 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
3840 const IDESC * UNUSED idesc = abuf->idesc;
3841 int cycles = 0;
3842 {
3843 int referenced = 0;
3844 int UNUSED insn_referenced = abuf->written;
3845 cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
3846 }
3847 return cycles;
3848#undef FLD
3849}
3850
3851static int
3852model_test_unlock (SIM_CPU *current_cpu, void *sem_arg)
3853{
96baa820 3854#define FLD(f) abuf->fields.sfmt_st_plus.f
c906108c
SS		 3855 const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
3856 const IDESC * UNUSED idesc = abuf->idesc;
3857 int cycles = 0;
3858 {
3859 int referenced = 0;
3860 int UNUSED insn_referenced = abuf->written;
3861 cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced);
3862 }
3863 return cycles;
3864#undef FLD
3865}
3866
3867/* We assume UNIT_NONE == 0 because the tables don't always terminate
3868 entries with it. */
3869
3870/* Model timing data for `m32r/d'. */
3871
3872static const INSN_TIMING m32r_d_timing[] = {
3873 { M32RBF_INSN_X_INVALID, 0, { { (int) UNIT_M32R_D_U_EXEC, 1, 1 } } },
3874 { M32RBF_INSN_X_AFTER, 0, { { (int) UNIT_M32R_D_U_EXEC, 1, 1 } } },
3875 { M32RBF_INSN_X_BEFORE, 0, { { (int) UNIT_M32R_D_U_EXEC, 1, 1 } } },
3876 { M32RBF_INSN_X_CTI_CHAIN, 0, { { (int) UNIT_M32R_D_U_EXEC, 1, 1 } } },
3877 { M32RBF_INSN_X_CHAIN, 0, { { (int) UNIT_M32R_D_U_EXEC, 1, 1 } } },
3878 { M32RBF_INSN_X_BEGIN, 0, { { (int) UNIT_M32R_D_U_EXEC, 1, 1 } } },
3879 { M32RBF_INSN_ADD, model_m32r_d_add, { { (int) UNIT_M32R_D_U_EXEC, 1, 1 } } },
3880 { M32RBF_INSN_ADD3, model_m32r_d_add3, { { (int) UNIT_M32R_D_U_EXEC, 1, 1 } } },
3881 { M32RBF_INSN_AND, model_m32r_d_and, { { (int) UNIT_M32R_D_U_EXEC, 1, 1 } } },
3882 { M32RBF_INSN_AND3, model_m32r_d_and3, { { (int) UNIT_M32R_D_U_EXEC, 1, 1 } } },
3883 { M32RBF_INSN_OR, model_m32r_d_or, { { (int) UNIT_M32R_D_U_EXEC, 1, 1 } } },
3884 { M32RBF_INSN_OR3, model_m32r_d_or3, { { (int) UNIT_M32R_D_U_EXEC, 1, 1 } } },
3885 { M32RBF_INSN_XOR, model_m32r_d_xor, { { (int) UNIT_M32R_D_U_EXEC, 1, 1 } } },
3886 { M32RBF_INSN_XOR3, model_m32r_d_xor3, { { (int) UNIT_M32R_D_U_EXEC, 1, 1 } } },
3887 { M32RBF_INSN_ADDI, model_m32r_d_addi, { { (int) UNIT_M32R_D_U_EXEC, 1, 1 } } },
3888 { M32RBF_INSN_ADDV, model_m32r_d_addv, { { (int) UNIT_M32R_D_U_EXEC, 1, 1 } } },
3889 { M32RBF_INSN_ADDV3, model_m32r_d_addv3, { { (int) UNIT_M32R_D_U_EXEC, 1, 1 } } },
3890 { M32RBF_INSN_ADDX, model_m32r_d_addx, { { (int) UNIT_M32R_D_U_EXEC, 1, 1 } } },
3891 { M32RBF_INSN_BC8, model_m32r_d_bc8, { { (int) UNIT_M32R_D_U_CTI, 1, 1 } } },
3892 { M32RBF_INSN_BC24, model_m32r_d_bc24, { { (int) UNIT_M32R_D_U_CTI, 1, 1 } } },
3893 { M32RBF_INSN_BEQ, model_m32r_d_beq, { { (int) UNIT_M32R_D_U_CTI, 1, 1 }, { (int) UNIT_M32R_D_U_CMP, 1, 0 } } },
3894 { M32RBF_INSN_BEQZ, model_m32r_d_beqz, { { (int) UNIT_M32R_D_U_CTI, 1, 1 }, { (int) UNIT_M32R_D_U_CMP, 1, 0 } } },
3895 { M32RBF_INSN_BGEZ, model_m32r_d_bgez, { { (int) UNIT_M32R_D_U_CTI, 1, 1 }, { (int) UNIT_M32R_D_U_CMP, 1, 0 } } },
3896 { M32RBF_INSN_BGTZ, model_m32r_d_bgtz, { { (int) UNIT_M32R_D_U_CTI, 1, 1 }, { (int) UNIT_M32R_D_U_CMP, 1, 0 } } },
3897 { M32RBF_INSN_BLEZ, model_m32r_d_blez, { { (int) UNIT_M32R_D_U_CTI, 1, 1 }, { (int) UNIT_M32R_D_U_CMP, 1, 0 } } },
3898 { M32RBF_INSN_BLTZ, model_m32r_d_bltz, { { (int) UNIT_M32R_D_U_CTI, 1, 1 }, { (int) UNIT_M32R_D_U_CMP, 1, 0 } } },
3899 { M32RBF_INSN_BNEZ, model_m32r_d_bnez, { { (int) UNIT_M32R_D_U_CTI, 1, 1 }, { (int) UNIT_M32R_D_U_CMP, 1, 0 } } },
3900 { M32RBF_INSN_BL8, model_m32r_d_bl8, { { (int) UNIT_M32R_D_U_CTI, 1, 1 } } },
3901 { M32RBF_INSN_BL24, model_m32r_d_bl24, { { (int) UNIT_M32R_D_U_CTI, 1, 1 } } },
3902 { M32RBF_INSN_BNC8, model_m32r_d_bnc8, { { (int) UNIT_M32R_D_U_CTI, 1, 1 } } },
3903 { M32RBF_INSN_BNC24, model_m32r_d_bnc24, { { (int) UNIT_M32R_D_U_CTI, 1, 1 } } },
3904 { M32RBF_INSN_BNE, model_m32r_d_bne, { { (int) UNIT_M32R_D_U_CTI, 1, 1 }, { (int) UNIT_M32R_D_U_CMP, 1, 0 } } },
3905 { M32RBF_INSN_BRA8, model_m32r_d_bra8, { { (int) UNIT_M32R_D_U_CTI, 1, 1 } } },
3906 { M32RBF_INSN_BRA24, model_m32r_d_bra24, { { (int) UNIT_M32R_D_U_CTI, 1, 1 } } },
3907 { M32RBF_INSN_CMP, model_m32r_d_cmp, { { (int) UNIT_M32R_D_U_CMP, 1, 1 } } },
3908 { M32RBF_INSN_CMPI, model_m32r_d_cmpi, { { (int) UNIT_M32R_D_U_CMP, 1, 1 } } },
3909 { M32RBF_INSN_CMPU, model_m32r_d_cmpu, { { (int) UNIT_M32R_D_U_CMP, 1, 1 } } },
3910 { M32RBF_INSN_CMPUI, model_m32r_d_cmpui, { { (int) UNIT_M32R_D_U_CMP, 1, 1 } } },
3911 { M32RBF_INSN_DIV, model_m32r_d_div, { { (int) UNIT_M32R_D_U_EXEC, 1, 37 } } },
3912 { M32RBF_INSN_DIVU, model_m32r_d_divu, { { (int) UNIT_M32R_D_U_EXEC, 1, 37 } } },
3913 { M32RBF_INSN_REM, model_m32r_d_rem, { { (int) UNIT_M32R_D_U_EXEC, 1, 37 } } },
3914 { M32RBF_INSN_REMU, model_m32r_d_remu, { { (int) UNIT_M32R_D_U_EXEC, 1, 37 } } },
3915 { M32RBF_INSN_JL, model_m32r_d_jl, { { (int) UNIT_M32R_D_U_CTI, 1, 1 } } },
3916 { M32RBF_INSN_JMP, model_m32r_d_jmp, { { (int) UNIT_M32R_D_U_CTI, 1, 1 } } },
3917 { M32RBF_INSN_LD, model_m32r_d_ld, { { (int) UNIT_M32R_D_U_LOAD, 1, 1 } } },
3918 { M32RBF_INSN_LD_D, model_m32r_d_ld_d, { { (int) UNIT_M32R_D_U_LOAD, 1, 2 } } },
3919 { M32RBF_INSN_LDB, model_m32r_d_ldb, { { (int) UNIT_M32R_D_U_LOAD, 1, 1 } } },
3920 { M32RBF_INSN_LDB_D, model_m32r_d_ldb_d, { { (int) UNIT_M32R_D_U_LOAD, 1, 2 } } },
3921 { M32RBF_INSN_LDH, model_m32r_d_ldh, { { (int) UNIT_M32R_D_U_LOAD, 1, 1 } } },
3922 { M32RBF_INSN_LDH_D, model_m32r_d_ldh_d, { { (int) UNIT_M32R_D_U_LOAD, 1, 2 } } },
3923 { M32RBF_INSN_LDUB, model_m32r_d_ldub, { { (int) UNIT_M32R_D_U_LOAD, 1, 1 } } },
3924 { M32RBF_INSN_LDUB_D, model_m32r_d_ldub_d, { { (int) UNIT_M32R_D_U_LOAD, 1, 2 } } },
3925 { M32RBF_INSN_LDUH, model_m32r_d_lduh, { { (int) UNIT_M32R_D_U_LOAD, 1, 1 } } },
3926 { M32RBF_INSN_LDUH_D, model_m32r_d_lduh_d, { { (int) UNIT_M32R_D_U_LOAD, 1, 2 } } },
3927 { M32RBF_INSN_LD_PLUS, model_m32r_d_ld_plus, { { (int) UNIT_M32R_D_U_LOAD, 1, 1 }, { (int) UNIT_M32R_D_U_EXEC, 1, 0 } } },
3928 { M32RBF_INSN_LD24, model_m32r_d_ld24, { { (int) UNIT_M32R_D_U_EXEC, 1, 1 } } },
3929 { M32RBF_INSN_LDI8, model_m32r_d_ldi8, { { (int) UNIT_M32R_D_U_EXEC, 1, 1 } } },
3930 { M32RBF_INSN_LDI16, model_m32r_d_ldi16, { { (int) UNIT_M32R_D_U_EXEC, 1, 1 } } },
3931 { M32RBF_INSN_LOCK, model_m32r_d_lock, { { (int) UNIT_M32R_D_U_LOAD, 1, 1 } } },
3932 { M32RBF_INSN_MACHI, model_m32r_d_machi, { { (int) UNIT_M32R_D_U_MAC, 1, 1 } } },
3933 { M32RBF_INSN_MACLO, model_m32r_d_maclo, { { (int) UNIT_M32R_D_U_MAC, 1, 1 } } },
3934 { M32RBF_INSN_MACWHI, model_m32r_d_macwhi, { { (int) UNIT_M32R_D_U_MAC, 1, 1 } } },
3935 { M32RBF_INSN_MACWLO, model_m32r_d_macwlo, { { (int) UNIT_M32R_D_U_MAC, 1, 1 } } },
3936 { M32RBF_INSN_MUL, model_m32r_d_mul, { { (int) UNIT_M32R_D_U_EXEC, 1, 4 } } },
3937 { M32RBF_INSN_MULHI, model_m32r_d_mulhi, { { (int) UNIT_M32R_D_U_MAC, 1, 1 } } },
3938 { M32RBF_INSN_MULLO, model_m32r_d_mullo, { { (int) UNIT_M32R_D_U_MAC, 1, 1 } } },
3939 { M32RBF_INSN_MULWHI, model_m32r_d_mulwhi, { { (int) UNIT_M32R_D_U_MAC, 1, 1 } } },
3940 { M32RBF_INSN_MULWLO, model_m32r_d_mulwlo, { { (int) UNIT_M32R_D_U_MAC, 1, 1 } } },
3941 { M32RBF_INSN_MV, model_m32r_d_mv, { { (int) UNIT_M32R_D_U_EXEC, 1, 1 } } },
3942 { M32RBF_INSN_MVFACHI, model_m32r_d_mvfachi, { { (int) UNIT_M32R_D_U_EXEC, 1, 2 } } },
3943 { M32RBF_INSN_MVFACLO, model_m32r_d_mvfaclo, { { (int) UNIT_M32R_D_U_EXEC, 1, 2 } } },
3944 { M32RBF_INSN_MVFACMI, model_m32r_d_mvfacmi, { { (int) UNIT_M32R_D_U_EXEC, 1, 2 } } },
3945 { M32RBF_INSN_MVFC, model_m32r_d_mvfc, { { (int) UNIT_M32R_D_U_EXEC, 1, 1 } } },
3946 { M32RBF_INSN_MVTACHI, model_m32r_d_mvtachi, { { (int) UNIT_M32R_D_U_EXEC, 1, 1 } } },
3947 { M32RBF_INSN_MVTACLO, model_m32r_d_mvtaclo, { { (int) UNIT_M32R_D_U_EXEC, 1, 1 } } },
3948 { M32RBF_INSN_MVTC, model_m32r_d_mvtc, { { (int) UNIT_M32R_D_U_EXEC, 1, 1 } } },
3949 { M32RBF_INSN_NEG, model_m32r_d_neg, { { (int) UNIT_M32R_D_U_EXEC, 1, 1 } } },
3950 { M32RBF_INSN_NOP, model_m32r_d_nop, { { (int) UNIT_M32R_D_U_EXEC, 1, 0 } } },
3951 { M32RBF_INSN_NOT, model_m32r_d_not, { { (int) UNIT_M32R_D_U_EXEC, 1, 1 } } },
3952 { M32RBF_INSN_RAC, model_m32r_d_rac, { { (int) UNIT_M32R_D_U_MAC, 1, 1 } } },
3953 { M32RBF_INSN_RACH, model_m32r_d_rach, { { (int) UNIT_M32R_D_U_MAC, 1, 1 } } },
3954 { M32RBF_INSN_RTE, model_m32r_d_rte, { { (int) UNIT_M32R_D_U_EXEC, 1, 1 } } },
3955 { M32RBF_INSN_SETH, model_m32r_d_seth, { { (int) UNIT_M32R_D_U_EXEC, 1, 1 } } },
3956 { M32RBF_INSN_SLL, model_m32r_d_sll, { { (int) UNIT_M32R_D_U_EXEC, 1, 1 } } },
3957 { M32RBF_INSN_SLL3, model_m32r_d_sll3, { { (int) UNIT_M32R_D_U_EXEC, 1, 1 } } },
3958 { M32RBF_INSN_SLLI, model_m32r_d_slli, { { (int) UNIT_M32R_D_U_EXEC, 1, 1 } } },
3959 { M32RBF_INSN_SRA, model_m32r_d_sra, { { (int) UNIT_M32R_D_U_EXEC, 1, 1 } } },
3960 { M32RBF_INSN_SRA3, model_m32r_d_sra3, { { (int) UNIT_M32R_D_U_EXEC, 1, 1 } } },
3961 { M32RBF_INSN_SRAI, model_m32r_d_srai, { { (int) UNIT_M32R_D_U_EXEC, 1, 1 } } },
3962 { M32RBF_INSN_SRL, model_m32r_d_srl, { { (int) UNIT_M32R_D_U_EXEC, 1, 1 } } },
3963 { M32RBF_INSN_SRL3, model_m32r_d_srl3, { { (int) UNIT_M32R_D_U_EXEC, 1, 1 } } },
3964 { M32RBF_INSN_SRLI, model_m32r_d_srli, { { (int) UNIT_M32R_D_U_EXEC, 1, 1 } } },
3965 { M32RBF_INSN_ST, model_m32r_d_st, { { (int) UNIT_M32R_D_U_STORE, 1, 1 } } },
3966 { M32RBF_INSN_ST_D, model_m32r_d_st_d, { { (int) UNIT_M32R_D_U_STORE, 1, 2 } } },
3967 { M32RBF_INSN_STB, model_m32r_d_stb, { { (int) UNIT_M32R_D_U_STORE, 1, 1 } } },
3968 { M32RBF_INSN_STB_D, model_m32r_d_stb_d, { { (int) UNIT_M32R_D_U_STORE, 1, 2 } } },
3969 { M32RBF_INSN_STH, model_m32r_d_sth, { { (int) UNIT_M32R_D_U_STORE, 1, 1 } } },
3970 { M32RBF_INSN_STH_D, model_m32r_d_sth_d, { { (int) UNIT_M32R_D_U_STORE, 1, 2 } } },
3971 { M32RBF_INSN_ST_PLUS, model_m32r_d_st_plus, { { (int) UNIT_M32R_D_U_STORE, 1, 1 }, { (int) UNIT_M32R_D_U_EXEC, 1, 0 } } },
3972 { M32RBF_INSN_ST_MINUS, model_m32r_d_st_minus, { { (int) UNIT_M32R_D_U_STORE, 1, 1 }, { (int) UNIT_M32R_D_U_EXEC, 1, 0 } } },
3973 { M32RBF_INSN_SUB, model_m32r_d_sub, { { (int) UNIT_M32R_D_U_EXEC, 1, 1 } } },
3974 { M32RBF_INSN_SUBV, model_m32r_d_subv, { { (int) UNIT_M32R_D_U_EXEC, 1, 1 } } },
3975 { M32RBF_INSN_SUBX, model_m32r_d_subx, { { (int) UNIT_M32R_D_U_EXEC, 1, 1 } } },
3976 { M32RBF_INSN_TRAP, model_m32r_d_trap, { { (int) UNIT_M32R_D_U_EXEC, 1, 1 } } },
3977 { M32RBF_INSN_UNLOCK, model_m32r_d_unlock, { { (int) UNIT_M32R_D_U_LOAD, 1, 1 } } },
3978};
3979
3980/* Model timing data for `test'. */
3981
3982static const INSN_TIMING test_timing[] = {
3983 { M32RBF_INSN_X_INVALID, 0, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
3984 { M32RBF_INSN_X_AFTER, 0, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
3985 { M32RBF_INSN_X_BEFORE, 0, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
3986 { M32RBF_INSN_X_CTI_CHAIN, 0, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
3987 { M32RBF_INSN_X_CHAIN, 0, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
3988 { M32RBF_INSN_X_BEGIN, 0, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
3989 { M32RBF_INSN_ADD, model_test_add, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
3990 { M32RBF_INSN_ADD3, model_test_add3, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
3991 { M32RBF_INSN_AND, model_test_and, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
3992 { M32RBF_INSN_AND3, model_test_and3, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
3993 { M32RBF_INSN_OR, model_test_or, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
3994 { M32RBF_INSN_OR3, model_test_or3, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
3995 { M32RBF_INSN_XOR, model_test_xor, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
3996 { M32RBF_INSN_XOR3, model_test_xor3, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
3997 { M32RBF_INSN_ADDI, model_test_addi, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
3998 { M32RBF_INSN_ADDV, model_test_addv, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
3999 { M32RBF_INSN_ADDV3, model_test_addv3, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
4000 { M32RBF_INSN_ADDX, model_test_addx, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
4001 { M32RBF_INSN_BC8, model_test_bc8, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
4002 { M32RBF_INSN_BC24, model_test_bc24, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
4003 { M32RBF_INSN_BEQ, model_test_beq, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
4004 { M32RBF_INSN_BEQZ, model_test_beqz, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
4005 { M32RBF_INSN_BGEZ, model_test_bgez, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
4006 { M32RBF_INSN_BGTZ, model_test_bgtz, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
4007 { M32RBF_INSN_BLEZ, model_test_blez, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
4008 { M32RBF_INSN_BLTZ, model_test_bltz, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
4009 { M32RBF_INSN_BNEZ, model_test_bnez, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
4010 { M32RBF_INSN_BL8, model_test_bl8, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
4011 { M32RBF_INSN_BL24, model_test_bl24, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
4012 { M32RBF_INSN_BNC8, model_test_bnc8, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
4013 { M32RBF_INSN_BNC24, model_test_bnc24, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
4014 { M32RBF_INSN_BNE, model_test_bne, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
4015 { M32RBF_INSN_BRA8, model_test_bra8, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
4016 { M32RBF_INSN_BRA24, model_test_bra24, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
4017 { M32RBF_INSN_CMP, model_test_cmp, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
4018 { M32RBF_INSN_CMPI, model_test_cmpi, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
4019 { M32RBF_INSN_CMPU, model_test_cmpu, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
4020 { M32RBF_INSN_CMPUI, model_test_cmpui, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
4021 { M32RBF_INSN_DIV, model_test_div, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
4022 { M32RBF_INSN_DIVU, model_test_divu, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
4023 { M32RBF_INSN_REM, model_test_rem, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
4024 { M32RBF_INSN_REMU, model_test_remu, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
4025 { M32RBF_INSN_JL, model_test_jl, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
4026 { M32RBF_INSN_JMP, model_test_jmp, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
4027 { M32RBF_INSN_LD, model_test_ld, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
4028 { M32RBF_INSN_LD_D, model_test_ld_d, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
4029 { M32RBF_INSN_LDB, model_test_ldb, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
4030 { M32RBF_INSN_LDB_D, model_test_ldb_d, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
4031 { M32RBF_INSN_LDH, model_test_ldh, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
4032 { M32RBF_INSN_LDH_D, model_test_ldh_d, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
4033 { M32RBF_INSN_LDUB, model_test_ldub, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
4034 { M32RBF_INSN_LDUB_D, model_test_ldub_d, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
4035 { M32RBF_INSN_LDUH, model_test_lduh, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
4036 { M32RBF_INSN_LDUH_D, model_test_lduh_d, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
4037 { M32RBF_INSN_LD_PLUS, model_test_ld_plus, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
4038 { M32RBF_INSN_LD24, model_test_ld24, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
4039 { M32RBF_INSN_LDI8, model_test_ldi8, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
4040 { M32RBF_INSN_LDI16, model_test_ldi16, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
4041 { M32RBF_INSN_LOCK, model_test_lock, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
4042 { M32RBF_INSN_MACHI, model_test_machi, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
4043 { M32RBF_INSN_MACLO, model_test_maclo, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
4044 { M32RBF_INSN_MACWHI, model_test_macwhi, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
4045 { M32RBF_INSN_MACWLO, model_test_macwlo, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
4046 { M32RBF_INSN_MUL, model_test_mul, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
4047 { M32RBF_INSN_MULHI, model_test_mulhi, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
4048 { M32RBF_INSN_MULLO, model_test_mullo, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
4049 { M32RBF_INSN_MULWHI, model_test_mulwhi, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
4050 { M32RBF_INSN_MULWLO, model_test_mulwlo, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
4051 { M32RBF_INSN_MV, model_test_mv, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
4052 { M32RBF_INSN_MVFACHI, model_test_mvfachi, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
4053 { M32RBF_INSN_MVFACLO, model_test_mvfaclo, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
4054 { M32RBF_INSN_MVFACMI, model_test_mvfacmi, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
4055 { M32RBF_INSN_MVFC, model_test_mvfc, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
4056 { M32RBF_INSN_MVTACHI, model_test_mvtachi, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
4057 { M32RBF_INSN_MVTACLO, model_test_mvtaclo, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
4058 { M32RBF_INSN_MVTC, model_test_mvtc, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
4059 { M32RBF_INSN_NEG, model_test_neg, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
4060 { M32RBF_INSN_NOP, model_test_nop, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
4061 { M32RBF_INSN_NOT, model_test_not, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
4062 { M32RBF_INSN_RAC, model_test_rac, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
4063 { M32RBF_INSN_RACH, model_test_rach, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
4064 { M32RBF_INSN_RTE, model_test_rte, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
4065 { M32RBF_INSN_SETH, model_test_seth, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
4066 { M32RBF_INSN_SLL, model_test_sll, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
4067 { M32RBF_INSN_SLL3, model_test_sll3, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
4068 { M32RBF_INSN_SLLI, model_test_slli, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
4069 { M32RBF_INSN_SRA, model_test_sra, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
4070 { M32RBF_INSN_SRA3, model_test_sra3, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
4071 { M32RBF_INSN_SRAI, model_test_srai, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
4072 { M32RBF_INSN_SRL, model_test_srl, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
4073 { M32RBF_INSN_SRL3, model_test_srl3, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
4074 { M32RBF_INSN_SRLI, model_test_srli, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
4075 { M32RBF_INSN_ST, model_test_st, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
4076 { M32RBF_INSN_ST_D, model_test_st_d, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
4077 { M32RBF_INSN_STB, model_test_stb, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
4078 { M32RBF_INSN_STB_D, model_test_stb_d, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
4079 { M32RBF_INSN_STH, model_test_sth, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
4080 { M32RBF_INSN_STH_D, model_test_sth_d, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
4081 { M32RBF_INSN_ST_PLUS, model_test_st_plus, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
4082 { M32RBF_INSN_ST_MINUS, model_test_st_minus, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
4083 { M32RBF_INSN_SUB, model_test_sub, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
4084 { M32RBF_INSN_SUBV, model_test_subv, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
4085 { M32RBF_INSN_SUBX, model_test_subx, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
4086 { M32RBF_INSN_TRAP, model_test_trap, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
4087 { M32RBF_INSN_UNLOCK, model_test_unlock, { { (int) UNIT_TEST_U_EXEC, 1, 1 } } },
4088};
4089
4090#endif /* WITH_PROFILE_MODEL_P */
4091
4092static void
4093m32r_d_model_init (SIM_CPU *cpu)
4094{
4095 CPU_MODEL_DATA (cpu) = (void *) zalloc (sizeof (MODEL_M32R_D_DATA));
4096}
4097
4098static void
4099test_model_init (SIM_CPU *cpu)
4100{
4101 CPU_MODEL_DATA (cpu) = (void *) zalloc (sizeof (MODEL_TEST_DATA));
4102}
4103
4104#if WITH_PROFILE_MODEL_P
4105#define TIMING_DATA(td) td
4106#else
4107#define TIMING_DATA(td) 0
4108#endif
4109
4110static const MODEL m32r_models[] =
4111{
4112 { "m32r/d", & m32r_mach, MODEL_M32R_D, TIMING_DATA (& m32r_d_timing[0]), m32r_d_model_init },
4113 { "test", & m32r_mach, MODEL_TEST, TIMING_DATA (& test_timing[0]), test_model_init },
4114 { 0 }
4115};
4116
4117/* The properties of this cpu's implementation. */
4118
4119static const MACH_IMP_PROPERTIES m32rbf_imp_properties =
4120{
4121 sizeof (SIM_CPU),
4122#if WITH_SCACHE
4123 sizeof (SCACHE)
4124#else
4125 0
4126#endif
4127};
4128
4129
4130static void
4131m32rbf_prepare_run (SIM_CPU *cpu)
4132{
4133 if (CPU_IDESC (cpu) == NULL)
4134 m32rbf_init_idesc_table (cpu);
4135}
4136
4137static const CGEN_INSN *
4138m32rbf_get_idata (SIM_CPU *cpu, int inum)
4139{
4140 return CPU_IDESC (cpu) [inum].idata;
4141}
4142
4143static void
4144m32r_init_cpu (SIM_CPU *cpu)
4145{
4146 CPU_REG_FETCH (cpu) = m32rbf_fetch_register;
4147 CPU_REG_STORE (cpu) = m32rbf_store_register;
4148 CPU_PC_FETCH (cpu) = m32rbf_h_pc_get;
4149 CPU_PC_STORE (cpu) = m32rbf_h_pc_set;
4150 CPU_GET_IDATA (cpu) = m32rbf_get_idata;
4151 CPU_MAX_INSNS (cpu) = M32RBF_INSN_MAX;
4152 CPU_INSN_NAME (cpu) = cgen_insn_name;
4153 CPU_FULL_ENGINE_FN (cpu) = m32rbf_engine_run_full;
4154#if WITH_FAST
4155 CPU_FAST_ENGINE_FN (cpu) = m32rbf_engine_run_fast;
4156#else
4157 CPU_FAST_ENGINE_FN (cpu) = m32rbf_engine_run_full;
4158#endif
4159}
4160
4161const MACH m32r_mach =
4162{
7a292a7a 4163 "m32r", "m32r", MACH_M32R,
c906108c
SS		 4164 32, 32, & m32r_models[0], & m32rbf_imp_properties,
4165 m32r_init_cpu,
4166 m32rbf_prepare_run
4167};
4168
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