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c906108c | 1 | /* Main simulator entry points specific to the M32R. |
4a94e368 | 2 | Copyright (C) 1996-2022 Free Software Foundation, Inc. |
c906108c SS |
3 | Contributed by Cygnus Support. |
4 | ||
16b47b25 | 5 | This file is part of GDB, the GNU debugger. |
c906108c | 6 | |
16b47b25 NC |
7 | This program is free software; you can redistribute it and/or modify |
8 | it under the terms of the GNU General Public License as published by | |
4744ac1b JB |
9 | the Free Software Foundation; either version 3 of the License, or |
10 | (at your option) any later version. | |
c906108c | 11 | |
16b47b25 NC |
12 | This program is distributed in the hope that it will be useful, |
13 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | GNU General Public License for more details. | |
16 | ||
4744ac1b JB |
17 | You should have received a copy of the GNU General Public License |
18 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ | |
c906108c | 19 | |
6df01ab8 MF |
20 | /* This must come before any other includes. */ |
21 | #include "defs.h" | |
22 | ||
8cfc9a18 MF |
23 | #include <string.h> |
24 | #include <stdlib.h> | |
25 | ||
26 | #include "sim/callback.h" | |
c906108c SS |
27 | #include "sim-main.h" |
28 | #include "sim-options.h" | |
29 | #include "libiberty.h" | |
30 | #include "bfd.h" | |
31 | ||
9c0c156b MF |
32 | #include "dv-m32r_uart.h" |
33 | ||
fe41f721 MF |
34 | #define M32R_DEFAULT_MEM_SIZE 0x2000000 /* 32M */ |
35 | ||
c906108c SS |
36 | static void free_state (SIM_DESC); |
37 | static void print_m32r_misc_cpu (SIM_CPU *cpu, int verbose); | |
c906108c SS |
38 | \f |
39 | /* Cover function of sim_state_free to free the cpu buffers as well. */ | |
40 | ||
41 | static void | |
42 | free_state (SIM_DESC sd) | |
43 | { | |
44 | if (STATE_MODULES (sd) != NULL) | |
45 | sim_module_uninstall (sd); | |
46 | sim_cpu_free_all (sd); | |
47 | sim_state_free (sd); | |
48 | } | |
49 | ||
1c636da0 MF |
50 | extern const SIM_MACH * const m32r_sim_machs[]; |
51 | ||
c906108c SS |
52 | /* Create an instance of the simulator. */ |
53 | ||
54 | SIM_DESC | |
81e6e8ae TT |
55 | sim_open (SIM_OPEN_KIND kind, host_callback *callback, struct bfd *abfd, |
56 | char * const *argv) | |
c906108c SS |
57 | { |
58 | SIM_DESC sd = sim_state_alloc (kind, callback); | |
59 | char c; | |
60 | int i; | |
61 | ||
ba307cdd | 62 | /* Set default options before parsing user options. */ |
1c636da0 | 63 | STATE_MACHS (sd) = m32r_sim_machs; |
d414eb3e | 64 | STATE_MODEL_NAME (sd) = "m32r/d"; |
ba307cdd | 65 | current_alignment = STRICT_ALIGNMENT; |
f9a4d543 | 66 | current_target_byte_order = BFD_ENDIAN_BIG; |
ba307cdd | 67 | |
c906108c | 68 | /* The cpu data is kept in a separately allocated chunk of memory. */ |
9a9db21d MF |
69 | if (sim_cpu_alloc_all_extra (sd, 1, sizeof (struct m32r_sim_cpu)) |
70 | != SIM_RC_OK) | |
c906108c SS |
71 | { |
72 | free_state (sd); | |
73 | return 0; | |
74 | } | |
75 | ||
c906108c SS |
76 | if (sim_pre_argv_init (sd, argv[0]) != SIM_RC_OK) |
77 | { | |
78 | free_state (sd); | |
79 | return 0; | |
80 | } | |
81 | ||
77cf2ef5 | 82 | /* The parser will print an error message for us, so we silently return. */ |
c906108c SS |
83 | if (sim_parse_args (sd, argv) != SIM_RC_OK) |
84 | { | |
85 | free_state (sd); | |
86 | return 0; | |
87 | } | |
88 | ||
89 | /* Allocate a handler for the control registers and other devices | |
90 | if no memory for that range has been allocated by the user. | |
91 | All are allocated in one chunk to keep things from being | |
9c0c156b MF |
92 | unnecessarily complicated. |
93 | TODO: Move these to the sim-model framework. */ | |
94 | sim_hw_parse (sd, "/core/%s/reg %#x %i", "m32r_uart", UART_BASE_ADDR, 0x100); | |
95 | sim_hw_parse (sd, "/core/%s/reg %#x %i", "m32r_cache", 0xfffffff0, 0x10); | |
c906108c SS |
96 | |
97 | /* Allocate core managed memory if none specified by user. | |
98 | Use address 4 here in case the user wanted address 0 unmapped. */ | |
99 | if (sim_core_read_buffer (sd, NULL, read_map, &c, 4, 1) == 0) | |
100 | sim_do_commandf (sd, "memory region 0,0x%x", M32R_DEFAULT_MEM_SIZE); | |
101 | ||
102 | /* check for/establish the reference program image */ | |
e8f20a28 | 103 | if (sim_analyze_program (sd, STATE_PROG_FILE (sd), abfd) != SIM_RC_OK) |
c906108c SS |
104 | { |
105 | free_state (sd); | |
106 | return 0; | |
107 | } | |
108 | ||
109 | /* Establish any remaining configuration options. */ | |
110 | if (sim_config (sd) != SIM_RC_OK) | |
111 | { | |
112 | free_state (sd); | |
113 | return 0; | |
114 | } | |
115 | ||
116 | if (sim_post_argv_init (sd) != SIM_RC_OK) | |
117 | { | |
118 | free_state (sd); | |
119 | return 0; | |
120 | } | |
121 | ||
122 | /* Open a copy of the cpu descriptor table. */ | |
123 | { | |
7a292a7a SS |
124 | CGEN_CPU_DESC cd = m32r_cgen_cpu_open_1 (STATE_ARCHITECTURE (sd)->printable_name, |
125 | CGEN_ENDIAN_BIG); | |
c906108c SS |
126 | for (i = 0; i < MAX_NR_PROCESSORS; ++i) |
127 | { | |
128 | SIM_CPU *cpu = STATE_CPU (sd, i); | |
129 | CPU_CPU_DESC (cpu) = cd; | |
130 | CPU_DISASSEMBLER (cpu) = sim_cgen_disassemble_insn; | |
131 | } | |
132 | m32r_cgen_init_dis (cd); | |
133 | } | |
134 | ||
c906108c SS |
135 | for (c = 0; c < MAX_NR_PROCESSORS; ++c) |
136 | { | |
137 | /* Only needed for profiling, but the structure member is small. */ | |
138 | memset (CPU_M32R_MISC_PROFILE (STATE_CPU (sd, i)), 0, | |
139 | sizeof (* CPU_M32R_MISC_PROFILE (STATE_CPU (sd, i)))); | |
140 | /* Hook in callback for reporting these stats */ | |
141 | PROFILE_INFO_CPU_CALLBACK (CPU_PROFILE_DATA (STATE_CPU (sd, i))) | |
142 | = print_m32r_misc_cpu; | |
143 | } | |
144 | ||
c906108c SS |
145 | return sd; |
146 | } | |
c906108c SS |
147 | \f |
148 | SIM_RC | |
81e6e8ae | 149 | sim_create_inferior (SIM_DESC sd, struct bfd *abfd, char * const *argv, |
54f7a83a | 150 | char * const *env) |
c906108c SS |
151 | { |
152 | SIM_CPU *current_cpu = STATE_CPU (sd, 0); | |
8cfc9a18 | 153 | host_callback *cb = STATE_CALLBACK (sd); |
c906108c SS |
154 | SIM_ADDR addr; |
155 | ||
156 | if (abfd != NULL) | |
157 | addr = bfd_get_start_address (abfd); | |
158 | else | |
159 | addr = 0; | |
160 | sim_pc_set (current_cpu, addr); | |
161 | ||
fe41f721 MF |
162 | if (STATE_ENVIRONMENT (sd) == USER_ENVIRONMENT) |
163 | { | |
164 | m32rbf_h_cr_set (current_cpu, | |
165 | m32r_decode_gdb_ctrl_regnum(SPI_REGNUM), 0x1f00000); | |
166 | m32rbf_h_cr_set (current_cpu, | |
167 | m32r_decode_gdb_ctrl_regnum(SPU_REGNUM), 0x1f00000); | |
168 | } | |
6edf0760 | 169 | |
0e967299 MF |
170 | /* Standalone mode (i.e. `run`) will take care of the argv for us in |
171 | sim_open() -> sim_parse_args(). But in debug mode (i.e. 'target sim' | |
172 | with `gdb`), we need to handle it because the user can change the | |
173 | argv on the fly via gdb's 'run'. */ | |
174 | if (STATE_PROG_ARGV (sd) != argv) | |
175 | { | |
176 | freeargv (STATE_PROG_ARGV (sd)); | |
177 | STATE_PROG_ARGV (sd) = dupargv (argv); | |
178 | } | |
c906108c | 179 | |
54f7a83a MF |
180 | if (STATE_PROG_ENVP (sd) != env) |
181 | { | |
182 | freeargv (STATE_PROG_ENVP (sd)); | |
183 | STATE_PROG_ENVP (sd) = dupargv (env); | |
184 | } | |
185 | ||
8cfc9a18 MF |
186 | cb->argv = STATE_PROG_ARGV (sd); |
187 | cb->envp = STATE_PROG_ENVP (sd); | |
188 | ||
c906108c SS |
189 | return SIM_RC_OK; |
190 | } | |
191 | ||
192 | /* PROFILE_CPU_CALLBACK */ | |
193 | ||
194 | static void | |
195 | print_m32r_misc_cpu (SIM_CPU *cpu, int verbose) | |
196 | { | |
197 | SIM_DESC sd = CPU_STATE (cpu); | |
198 | char buf[20]; | |
199 | ||
200 | if (CPU_PROFILE_FLAGS (cpu) [PROFILE_INSN_IDX]) | |
201 | { | |
202 | sim_io_printf (sd, "Miscellaneous Statistics\n\n"); | |
203 | sim_io_printf (sd, " %-*s %s\n\n", | |
204 | PROFILE_LABEL_WIDTH, "Fill nops:", | |
205 | sim_add_commas (buf, sizeof (buf), | |
206 | CPU_M32R_MISC_PROFILE (cpu)->fillnop_count)); | |
2df3850c JM |
207 | if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_m32rx) |
208 | sim_io_printf (sd, " %-*s %s\n\n", | |
209 | PROFILE_LABEL_WIDTH, "Parallel insns:", | |
210 | sim_add_commas (buf, sizeof (buf), | |
211 | CPU_M32R_MISC_PROFILE (cpu)->parallel_count)); | |
16b47b25 NC |
212 | if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_m32r2) |
213 | sim_io_printf (sd, " %-*s %s\n\n", | |
214 | PROFILE_LABEL_WIDTH, "Parallel insns:", | |
215 | sim_add_commas (buf, sizeof (buf), | |
216 | CPU_M32R_MISC_PROFILE (cpu)->parallel_count)); | |
c906108c SS |
217 | } |
218 | } |