[thirdparty/binutils-gdb.git] / sim / m32r / sim-if.c

/* Main simulator entry points specific to the M32R.
   Copyright (C) 1996-2021 Free Software Foundation, Inc.
   Contributed by Cygnus Support.

   This file is part of GDB, the GNU debugger.

   This program is free software; you can redistribute it and/or modify
   it under the terms of the GNU General Public License as published by
   the Free Software Foundation; either version 3 of the License, or
   (at your option) any later version.

   This program is distributed in the hope that it will be useful,
   but WITHOUT ANY WARRANTY; without even the implied warranty of
   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
   GNU General Public License for more details.

   You should have received a copy of the GNU General Public License
   along with this program.  If not, see <http://www.gnu.org/licenses/>.  */

#include "sim-main.h"
#include "sim-options.h"
#include "libiberty.h"
#include "bfd.h"

#include <string.h>
#include <stdlib.h>

#include "dv-m32r_uart.h"

static void free_state (SIM_DESC);
static void print_m32r_misc_cpu (SIM_CPU *cpu, int verbose);
\f
/* Cover function of sim_state_free to free the cpu buffers as well.  */

static void
free_state (SIM_DESC sd)
{
  if (STATE_MODULES (sd) != NULL)
    sim_module_uninstall (sd);
  sim_cpu_free_all (sd);
  sim_state_free (sd);
}

/* Create an instance of the simulator.  */

SIM_DESC
sim_open (kind, callback, abfd, argv)
     SIM_OPEN_KIND kind;
     host_callback *callback;
     struct bfd *abfd;
     char * const *argv;
{
  SIM_DESC sd = sim_state_alloc (kind, callback);
  char c;
  int i;

  /* The cpu data is kept in a separately allocated chunk of memory.  */
  if (sim_cpu_alloc_all (sd, 1, cgen_cpu_max_extra_bytes ()) != SIM_RC_OK)
    {
      free_state (sd);
      return 0;
    }

#if 0 /* FIXME: pc is in mach-specific struct */
  /* FIXME: watchpoints code shouldn't need this */
  {
    SIM_CPU *current_cpu = STATE_CPU (sd, 0);
    STATE_WATCHPOINTS (sd)->pc = &(PC);
    STATE_WATCHPOINTS (sd)->sizeof_pc = sizeof (PC);
  }
#endif

  if (sim_pre_argv_init (sd, argv[0]) != SIM_RC_OK)
    {
      free_state (sd);
      return 0;
    }

  /* The parser will print an error message for us, so we silently return.  */
  if (sim_parse_args (sd, argv) != SIM_RC_OK)
    {
      free_state (sd);
      return 0;
    }

  /* Allocate a handler for the control registers and other devices
     if no memory for that range has been allocated by the user.
     All are allocated in one chunk to keep things from being
     unnecessarily complicated.
     TODO: Move these to the sim-model framework.  */
  sim_hw_parse (sd, "/core/%s/reg %#x %i", "m32r_uart", UART_BASE_ADDR, 0x100);
  sim_hw_parse (sd, "/core/%s/reg %#x %i", "m32r_cache", 0xfffffff0, 0x10);

  /* Allocate core managed memory if none specified by user.
     Use address 4 here in case the user wanted address 0 unmapped.  */
  if (sim_core_read_buffer (sd, NULL, read_map, &c, 4, 1) == 0)
    sim_do_commandf (sd, "memory region 0,0x%x", M32R_DEFAULT_MEM_SIZE);

  /* check for/establish the reference program image */
  if (sim_analyze_program (sd,
			   (STATE_PROG_ARGV (sd) != NULL
			    ? *STATE_PROG_ARGV (sd)
			    : NULL),
			   abfd) != SIM_RC_OK)
    {
      free_state (sd);
      return 0;
    }

  /* Establish any remaining configuration options.  */
  if (sim_config (sd) != SIM_RC_OK)
    {
      free_state (sd);
      return 0;
    }

  if (sim_post_argv_init (sd) != SIM_RC_OK)
    {
      free_state (sd);
      return 0;
    }

  /* Open a copy of the cpu descriptor table.  */
  {
    CGEN_CPU_DESC cd = m32r_cgen_cpu_open_1 (STATE_ARCHITECTURE (sd)->printable_name,
					     CGEN_ENDIAN_BIG);
    for (i = 0; i < MAX_NR_PROCESSORS; ++i)
      {
	SIM_CPU *cpu = STATE_CPU (sd, i);
	CPU_CPU_DESC (cpu) = cd;
	CPU_DISASSEMBLER (cpu) = sim_cgen_disassemble_insn;
      }
    m32r_cgen_init_dis (cd);
  }

  /* Initialize various cgen things not done by common framework.
     Must be done after m32r_cgen_cpu_open.  */
  cgen_init (sd);

  for (c = 0; c < MAX_NR_PROCESSORS; ++c)
    {
      /* Only needed for profiling, but the structure member is small.  */
      memset (CPU_M32R_MISC_PROFILE (STATE_CPU (sd, i)), 0,
	      sizeof (* CPU_M32R_MISC_PROFILE (STATE_CPU (sd, i))));
      /* Hook in callback for reporting these stats */
      PROFILE_INFO_CPU_CALLBACK (CPU_PROFILE_DATA (STATE_CPU (sd, i)))
	= print_m32r_misc_cpu;
    }

  return sd;
}
\f
SIM_RC
sim_create_inferior (sd, abfd, argv, envp)
     SIM_DESC sd;
     struct bfd *abfd;
     char * const *argv;
     char * const *envp;
{
  SIM_CPU *current_cpu = STATE_CPU (sd, 0);
  SIM_ADDR addr;

  if (abfd != NULL)
    addr = bfd_get_start_address (abfd);
  else
    addr = 0;
  sim_pc_set (current_cpu, addr);

#ifdef M32R_LINUX
  m32rbf_h_cr_set (current_cpu,
                    m32r_decode_gdb_ctrl_regnum(SPI_REGNUM), 0x1f00000);
  m32rbf_h_cr_set (current_cpu,
                    m32r_decode_gdb_ctrl_regnum(SPU_REGNUM), 0x1f00000);
#endif

  /* Standalone mode (i.e. `run`) will take care of the argv for us in
     sim_open() -> sim_parse_args().  But in debug mode (i.e. 'target sim'
     with `gdb`), we need to handle it because the user can change the
     argv on the fly via gdb's 'run'.  */
  if (STATE_PROG_ARGV (sd) != argv)
    {
      freeargv (STATE_PROG_ARGV (sd));
      STATE_PROG_ARGV (sd) = dupargv (argv);
    }

  return SIM_RC_OK;
}

/* PROFILE_CPU_CALLBACK */

static void
print_m32r_misc_cpu (SIM_CPU *cpu, int verbose)
{
  SIM_DESC sd = CPU_STATE (cpu);
  char buf[20];

  if (CPU_PROFILE_FLAGS (cpu) [PROFILE_INSN_IDX])
    {
      sim_io_printf (sd, "Miscellaneous Statistics\n\n");
      sim_io_printf (sd, "  %-*s %s\n\n",
		     PROFILE_LABEL_WIDTH, "Fill nops:",
		     sim_add_commas (buf, sizeof (buf),
				     CPU_M32R_MISC_PROFILE (cpu)->fillnop_count));
      if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_m32rx)
	sim_io_printf (sd, "  %-*s %s\n\n",
		       PROFILE_LABEL_WIDTH, "Parallel insns:",
		       sim_add_commas (buf, sizeof (buf),
				       CPU_M32R_MISC_PROFILE (cpu)->parallel_count));
      if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_m32r2)
	sim_io_printf (sd, "  %-*s %s\n\n",
		       PROFILE_LABEL_WIDTH, "Parallel insns:",
		       sim_add_commas (buf, sizeof (buf),
				       CPU_M32R_MISC_PROFILE (cpu)->parallel_count));
    }
}
Commit	Line	Data
c906108c	1	/* Main simulator entry points specific to the M32R.
3666a048	2	Copyright (C) 1996-2021 Free Software Foundation, Inc.
c906108c SS	3	Contributed by Cygnus Support.
c906108c SS	4
16b47b25	5	This file is part of GDB, the GNU debugger.
c906108c	6
16b47b25 NC	7	This program is free software; you can redistribute it and/or modify
16b47b25 NC	8	it under the terms of the GNU General Public License as published by
4744ac1b JB	9	the Free Software Foundation; either version 3 of the License, or
4744ac1b JB	10	(at your option) any later version.
c906108c	11
16b47b25 NC	12	This program is distributed in the hope that it will be useful,
	13	but WITHOUT ANY WARRANTY; without even the implied warranty of
	14	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	15	GNU General Public License for more details.
	16
4744ac1b JB	17	You should have received a copy of the GNU General Public License
4744ac1b JB	18	along with this program. If not, see <http://www.gnu.org/licenses/>. */
c906108c SS	19
	20	#include "sim-main.h"
	21	#include "sim-options.h"
	22	#include "libiberty.h"
	23	#include "bfd.h"
	24
c906108c	25	#include <string.h>
c906108c	26	#include <stdlib.h>
c906108c	27
9c0c156b MF	28	#include "dv-m32r_uart.h"
9c0c156b MF	29
c906108c SS	30	static void free_state (SIM_DESC);
c906108c SS	31	static void print_m32r_misc_cpu (SIM_CPU *cpu, int verbose);
c906108c SS	32	\f
	33	/* Cover function of sim_state_free to free the cpu buffers as well. */
	34
	35	static void
	36	free_state (SIM_DESC sd)
	37	{
	38	if (STATE_MODULES (sd) != NULL)
	39	sim_module_uninstall (sd);
	40	sim_cpu_free_all (sd);
	41	sim_state_free (sd);
	42	}
	43
	44	/* Create an instance of the simulator. */
	45
	46	SIM_DESC
	47	sim_open (kind, callback, abfd, argv)
	48	SIM_OPEN_KIND kind;
	49	host_callback *callback;
6b4a8935	50	struct bfd *abfd;
2e3d4f4d	51	char * const *argv;
c906108c SS	52	{
	53	SIM_DESC sd = sim_state_alloc (kind, callback);
	54	char c;
	55	int i;
	56
	57	/* The cpu data is kept in a separately allocated chunk of memory. */
	58	if (sim_cpu_alloc_all (sd, 1, cgen_cpu_max_extra_bytes ()) != SIM_RC_OK)
	59	{
	60	free_state (sd);
	61	return 0;
	62	}
	63
	64	#if 0 /* FIXME: pc is in mach-specific struct */
	65	/* FIXME: watchpoints code shouldn't need this */
	66	{
	67	SIM_CPU *current_cpu = STATE_CPU (sd, 0);
	68	STATE_WATCHPOINTS (sd)->pc = &(PC);
	69	STATE_WATCHPOINTS (sd)->sizeof_pc = sizeof (PC);
	70	}
	71	#endif
	72
	73	if (sim_pre_argv_init (sd, argv[0]) != SIM_RC_OK)
	74	{
	75	free_state (sd);
	76	return 0;
	77	}
	78
77cf2ef5	79	/* The parser will print an error message for us, so we silently return. */
c906108c SS	80	if (sim_parse_args (sd, argv) != SIM_RC_OK)
	81	{
	82	free_state (sd);
	83	return 0;
	84	}
	85
	86	/* Allocate a handler for the control registers and other devices
	87	if no memory for that range has been allocated by the user.
	88	All are allocated in one chunk to keep things from being
9c0c156b MF	89	unnecessarily complicated.
	90	TODO: Move these to the sim-model framework. */
	91	sim_hw_parse (sd, "/core/%s/reg %#x %i", "m32r_uart", UART_BASE_ADDR, 0x100);
	92	sim_hw_parse (sd, "/core/%s/reg %#x %i", "m32r_cache", 0xfffffff0, 0x10);
c906108c SS	93
	94	/* Allocate core managed memory if none specified by user.
	95	Use address 4 here in case the user wanted address 0 unmapped. */
	96	if (sim_core_read_buffer (sd, NULL, read_map, &c, 4, 1) == 0)
	97	sim_do_commandf (sd, "memory region 0,0x%x", M32R_DEFAULT_MEM_SIZE);
	98
	99	/* check for/establish the reference program image */
	100	if (sim_analyze_program (sd,
	101	(STATE_PROG_ARGV (sd) != NULL
	102	? *STATE_PROG_ARGV (sd)
	103	: NULL),
	104	abfd) != SIM_RC_OK)
	105	{
	106	free_state (sd);
	107	return 0;
	108	}
	109
	110	/* Establish any remaining configuration options. */
	111	if (sim_config (sd) != SIM_RC_OK)
	112	{
	113	free_state (sd);
	114	return 0;
	115	}
	116
	117	if (sim_post_argv_init (sd) != SIM_RC_OK)
	118	{
	119	free_state (sd);
	120	return 0;
	121	}
	122
	123	/* Open a copy of the cpu descriptor table. */
	124	{
7a292a7a SS	125	CGEN_CPU_DESC cd = m32r_cgen_cpu_open_1 (STATE_ARCHITECTURE (sd)->printable_name,
7a292a7a SS	126	CGEN_ENDIAN_BIG);
c906108c SS	127	for (i = 0; i < MAX_NR_PROCESSORS; ++i)
	128	{
	129	SIM_CPU *cpu = STATE_CPU (sd, i);
	130	CPU_CPU_DESC (cpu) = cd;
	131	CPU_DISASSEMBLER (cpu) = sim_cgen_disassemble_insn;
	132	}
	133	m32r_cgen_init_dis (cd);
	134	}
	135
	136	/* Initialize various cgen things not done by common framework.
	137	Must be done after m32r_cgen_cpu_open. */
	138	cgen_init (sd);
	139
	140	for (c = 0; c < MAX_NR_PROCESSORS; ++c)
	141	{
	142	/* Only needed for profiling, but the structure member is small. */
	143	memset (CPU_M32R_MISC_PROFILE (STATE_CPU (sd, i)), 0,
	144	sizeof (* CPU_M32R_MISC_PROFILE (STATE_CPU (sd, i))));
	145	/* Hook in callback for reporting these stats */
	146	PROFILE_INFO_CPU_CALLBACK (CPU_PROFILE_DATA (STATE_CPU (sd, i)))
	147	= print_m32r_misc_cpu;
	148	}
	149
c906108c SS	150	return sd;
c906108c SS	151	}
c906108c SS	152	\f
	153	SIM_RC
	154	sim_create_inferior (sd, abfd, argv, envp)
	155	SIM_DESC sd;
6b4a8935	156	struct bfd *abfd;
2e3d4f4d MF	157	char * const *argv;
2e3d4f4d MF	158	char * const *envp;
c906108c SS	159	{
	160	SIM_CPU *current_cpu = STATE_CPU (sd, 0);
	161	SIM_ADDR addr;
	162
	163	if (abfd != NULL)
	164	addr = bfd_get_start_address (abfd);
	165	else
	166	addr = 0;
	167	sim_pc_set (current_cpu, addr);
	168
6edf0760 NC	169	#ifdef M32R_LINUX
	170	m32rbf_h_cr_set (current_cpu,
	171	m32r_decode_gdb_ctrl_regnum(SPI_REGNUM), 0x1f00000);
	172	m32rbf_h_cr_set (current_cpu,
	173	m32r_decode_gdb_ctrl_regnum(SPU_REGNUM), 0x1f00000);
	174	#endif
	175
0e967299 MF	176	/* Standalone mode (i.e. `run`) will take care of the argv for us in
	177	sim_open() -> sim_parse_args(). But in debug mode (i.e. 'target sim'
	178	with `gdb`), we need to handle it because the user can change the
	179	argv on the fly via gdb's 'run'. */
	180	if (STATE_PROG_ARGV (sd) != argv)
	181	{
	182	freeargv (STATE_PROG_ARGV (sd));
	183	STATE_PROG_ARGV (sd) = dupargv (argv);
	184	}
c906108c SS	185
	186	return SIM_RC_OK;
	187	}
	188
	189	/* PROFILE_CPU_CALLBACK */
	190
	191	static void
	192	print_m32r_misc_cpu (SIM_CPU *cpu, int verbose)
	193	{
	194	SIM_DESC sd = CPU_STATE (cpu);
	195	char buf[20];
	196
	197	if (CPU_PROFILE_FLAGS (cpu) [PROFILE_INSN_IDX])
	198	{
	199	sim_io_printf (sd, "Miscellaneous Statistics\n\n");
	200	sim_io_printf (sd, " %-*s %s\n\n",
	201	PROFILE_LABEL_WIDTH, "Fill nops:",
	202	sim_add_commas (buf, sizeof (buf),
	203	CPU_M32R_MISC_PROFILE (cpu)->fillnop_count));
2df3850c JM	204	if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_m32rx)
	205	sim_io_printf (sd, " %-*s %s\n\n",
	206	PROFILE_LABEL_WIDTH, "Parallel insns:",
	207	sim_add_commas (buf, sizeof (buf),
	208	CPU_M32R_MISC_PROFILE (cpu)->parallel_count));
16b47b25 NC	209	if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_m32r2)
	210	sim_io_printf (sd, " %-*s %s\n\n",
	211	PROFILE_LABEL_WIDTH, "Parallel insns:",
	212	sim_add_commas (buf, sizeof (buf),
	213	CPU_M32R_MISC_PROFILE (cpu)->parallel_count));
c906108c SS	214	}
c906108c SS	215	}