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sim: m32r: include sim-hw.h for sim_hw_parse
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c906108c 1/* Main simulator entry points specific to the M32R.
4a94e368 2 Copyright (C) 1996-2022 Free Software Foundation, Inc.
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3 Contributed by Cygnus Support.
4
16b47b25 5 This file is part of GDB, the GNU debugger.
c906108c 6
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7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
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9 the Free Software Foundation; either version 3 of the License, or
10 (at your option) any later version.
c906108c 11
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12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
16
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17 You should have received a copy of the GNU General Public License
18 along with this program. If not, see <http://www.gnu.org/licenses/>. */
c906108c 19
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20/* This must come before any other includes. */
21#include "defs.h"
22
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23#include <string.h>
24#include <stdlib.h>
25
26#include "sim/callback.h"
c906108c 27#include "sim-main.h"
7dc3ab91 28#include "sim-hw.h"
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29#include "sim-options.h"
30#include "libiberty.h"
31#include "bfd.h"
32
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33#include "dv-m32r_uart.h"
34
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35#define M32R_DEFAULT_MEM_SIZE 0x2000000 /* 32M */
36
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37static void free_state (SIM_DESC);
38static void print_m32r_misc_cpu (SIM_CPU *cpu, int verbose);
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39\f
40/* Cover function of sim_state_free to free the cpu buffers as well. */
41
42static void
43free_state (SIM_DESC sd)
44{
45 if (STATE_MODULES (sd) != NULL)
46 sim_module_uninstall (sd);
47 sim_cpu_free_all (sd);
48 sim_state_free (sd);
49}
50
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51extern const SIM_MACH * const m32r_sim_machs[];
52
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53/* Create an instance of the simulator. */
54
55SIM_DESC
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56sim_open (SIM_OPEN_KIND kind, host_callback *callback, struct bfd *abfd,
57 char * const *argv)
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58{
59 SIM_DESC sd = sim_state_alloc (kind, callback);
60 char c;
61 int i;
62
ba307cdd 63 /* Set default options before parsing user options. */
1c636da0 64 STATE_MACHS (sd) = m32r_sim_machs;
d414eb3e 65 STATE_MODEL_NAME (sd) = "m32r/d";
ba307cdd 66 current_alignment = STRICT_ALIGNMENT;
f9a4d543 67 current_target_byte_order = BFD_ENDIAN_BIG;
ba307cdd 68
c906108c 69 /* The cpu data is kept in a separately allocated chunk of memory. */
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70 if (sim_cpu_alloc_all_extra (sd, 1, sizeof (struct m32r_sim_cpu))
71 != SIM_RC_OK)
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72 {
73 free_state (sd);
74 return 0;
75 }
76
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77 if (sim_pre_argv_init (sd, argv[0]) != SIM_RC_OK)
78 {
79 free_state (sd);
80 return 0;
81 }
82
77cf2ef5 83 /* The parser will print an error message for us, so we silently return. */
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84 if (sim_parse_args (sd, argv) != SIM_RC_OK)
85 {
86 free_state (sd);
87 return 0;
88 }
89
90 /* Allocate a handler for the control registers and other devices
91 if no memory for that range has been allocated by the user.
92 All are allocated in one chunk to keep things from being
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93 unnecessarily complicated.
94 TODO: Move these to the sim-model framework. */
95 sim_hw_parse (sd, "/core/%s/reg %#x %i", "m32r_uart", UART_BASE_ADDR, 0x100);
96 sim_hw_parse (sd, "/core/%s/reg %#x %i", "m32r_cache", 0xfffffff0, 0x10);
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97
98 /* Allocate core managed memory if none specified by user.
99 Use address 4 here in case the user wanted address 0 unmapped. */
100 if (sim_core_read_buffer (sd, NULL, read_map, &c, 4, 1) == 0)
101 sim_do_commandf (sd, "memory region 0,0x%x", M32R_DEFAULT_MEM_SIZE);
102
103 /* check for/establish the reference program image */
e8f20a28 104 if (sim_analyze_program (sd, STATE_PROG_FILE (sd), abfd) != SIM_RC_OK)
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105 {
106 free_state (sd);
107 return 0;
108 }
109
110 /* Establish any remaining configuration options. */
111 if (sim_config (sd) != SIM_RC_OK)
112 {
113 free_state (sd);
114 return 0;
115 }
116
117 if (sim_post_argv_init (sd) != SIM_RC_OK)
118 {
119 free_state (sd);
120 return 0;
121 }
122
123 /* Open a copy of the cpu descriptor table. */
124 {
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125 CGEN_CPU_DESC cd = m32r_cgen_cpu_open_1 (STATE_ARCHITECTURE (sd)->printable_name,
126 CGEN_ENDIAN_BIG);
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127 for (i = 0; i < MAX_NR_PROCESSORS; ++i)
128 {
129 SIM_CPU *cpu = STATE_CPU (sd, i);
130 CPU_CPU_DESC (cpu) = cd;
131 CPU_DISASSEMBLER (cpu) = sim_cgen_disassemble_insn;
132 }
133 m32r_cgen_init_dis (cd);
134 }
135
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136 for (c = 0; c < MAX_NR_PROCESSORS; ++c)
137 {
138 /* Only needed for profiling, but the structure member is small. */
139 memset (CPU_M32R_MISC_PROFILE (STATE_CPU (sd, i)), 0,
140 sizeof (* CPU_M32R_MISC_PROFILE (STATE_CPU (sd, i))));
141 /* Hook in callback for reporting these stats */
142 PROFILE_INFO_CPU_CALLBACK (CPU_PROFILE_DATA (STATE_CPU (sd, i)))
143 = print_m32r_misc_cpu;
144 }
145
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146 return sd;
147}
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148\f
149SIM_RC
81e6e8ae 150sim_create_inferior (SIM_DESC sd, struct bfd *abfd, char * const *argv,
54f7a83a 151 char * const *env)
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152{
153 SIM_CPU *current_cpu = STATE_CPU (sd, 0);
8cfc9a18 154 host_callback *cb = STATE_CALLBACK (sd);
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155 SIM_ADDR addr;
156
157 if (abfd != NULL)
158 addr = bfd_get_start_address (abfd);
159 else
160 addr = 0;
161 sim_pc_set (current_cpu, addr);
162
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163 if (STATE_ENVIRONMENT (sd) == USER_ENVIRONMENT)
164 {
165 m32rbf_h_cr_set (current_cpu,
166 m32r_decode_gdb_ctrl_regnum(SPI_REGNUM), 0x1f00000);
167 m32rbf_h_cr_set (current_cpu,
168 m32r_decode_gdb_ctrl_regnum(SPU_REGNUM), 0x1f00000);
169 }
6edf0760 170
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171 /* Standalone mode (i.e. `run`) will take care of the argv for us in
172 sim_open() -> sim_parse_args(). But in debug mode (i.e. 'target sim'
173 with `gdb`), we need to handle it because the user can change the
174 argv on the fly via gdb's 'run'. */
175 if (STATE_PROG_ARGV (sd) != argv)
176 {
177 freeargv (STATE_PROG_ARGV (sd));
178 STATE_PROG_ARGV (sd) = dupargv (argv);
179 }
c906108c 180
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181 if (STATE_PROG_ENVP (sd) != env)
182 {
183 freeargv (STATE_PROG_ENVP (sd));
184 STATE_PROG_ENVP (sd) = dupargv (env);
185 }
186
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187 cb->argv = STATE_PROG_ARGV (sd);
188 cb->envp = STATE_PROG_ENVP (sd);
189
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190 return SIM_RC_OK;
191}
192
193/* PROFILE_CPU_CALLBACK */
194
195static void
196print_m32r_misc_cpu (SIM_CPU *cpu, int verbose)
197{
198 SIM_DESC sd = CPU_STATE (cpu);
199 char buf[20];
200
201 if (CPU_PROFILE_FLAGS (cpu) [PROFILE_INSN_IDX])
202 {
203 sim_io_printf (sd, "Miscellaneous Statistics\n\n");
204 sim_io_printf (sd, " %-*s %s\n\n",
205 PROFILE_LABEL_WIDTH, "Fill nops:",
206 sim_add_commas (buf, sizeof (buf),
207 CPU_M32R_MISC_PROFILE (cpu)->fillnop_count));
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208 if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_m32rx)
209 sim_io_printf (sd, " %-*s %s\n\n",
210 PROFILE_LABEL_WIDTH, "Parallel insns:",
211 sim_add_commas (buf, sizeof (buf),
212 CPU_M32R_MISC_PROFILE (cpu)->parallel_count));
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213 if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_m32r2)
214 sim_io_printf (sd, " %-*s %s\n\n",
215 PROFILE_LABEL_WIDTH, "Parallel insns:",
216 sim_add_commas (buf, sizeof (buf),
217 CPU_M32R_MISC_PROFILE (cpu)->parallel_count));
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218 }
219}