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[thirdparty/binutils-gdb.git] / sim / mips / ChangeLog
CommitLineData
7a292a7a
SS		 11999-04-21 Frank Ch. Eigler <fche@cygnus.com>
2
3 * mips.igen (bc0f): For the TX39 only, decode this as a no-op stub.
4
5Thu Apr 15 14:15:17 1999 Andrew Cagney <cagney@amy.cygnus.com>
6
7 * configure.in: Any mips64vr5*-*-* target should have
8 -DTARGET_ENABLE_FR=1.
9 (default_endian): Any mips64vr*el-*-* target should default to
10 LITTLE_ENDIAN.
11 * configure: Re-generate.
12
131999-02-19 Gavin Romig-Koch <gavin@cygnus.com>
14
15 * mips.igen (ldl): Extend from _16_, not 32.
16
17Wed Jan 27 18:51:38 1999 Andrew Cagney <cagney@chook.cygnus.com>
18
19 * interp.c (sim_store_register): Force registers written to by GDB
20 into an un-interpreted state.
21
c906108c
SS		 221999-02-05 Frank Ch. Eigler <fche@cygnus.com>
23
24 * dv-tx3904sio.c (tx3904sio_tickle): After a polled I/O from the
25 CPU, start periodic background I/O polls.
26 (tx3904sio_poll): New function: periodic I/O poller.
27
281998-12-30 Frank Ch. Eigler <fche@cygnus.com>
29
30 * mips.igen (BREAK): Call signal_exception instead of sim_engine_halt.
31
32Tue Dec 29 16:03:53 1998 Rainer Orth <ro@TechFak.Uni-Bielefeld.DE>
33
34 * configure.in, configure (mips64vr5*-*-*): Added missing ;; in
35 case statement.
36
371998-12-29 Frank Ch. Eigler <fche@cygnus.com>
38
39 * interp.c (sim_open): Allocate jm3904 memory in smaller chunks.
40 (load_word): Call SIM_CORE_SIGNAL hook on error.
41 (signal_exception): Call SIM_CPU_EXCEPTION_TRIGGER hook before
42 starting. For exception dispatching, pass PC instead of NULL_CIA.
43 (decode_coproc): Use COP0_BADVADDR to store faulting address.
44 * sim-main.h (COP0_BADVADDR): Define.
45 (SIM_CORE_SIGNAL): Define hook to call mips_core_signal.
46 (SIM_CPU_EXCEPTION*): Define hooks to call mips_cpu_exception*().
47 (_sim_cpu): Add exc_* fields to store register value snapshots.
48 * mips.igen (*): Replace memory-related SignalException* calls
49 with references to SIM_CORE_SIGNAL hook.
50
51 * dv-tx3904irc.c (tx3904irc_port_event): printf format warning
52 fix.
53 * sim-main.c (*): Minor warning cleanups.
54
551998-12-24 Gavin Romig-Koch <gavin@cygnus.com>
56
57 * m16.igen (DADDIU5): Correct type-o.
58
59Mon Dec 21 10:34:48 1998 Andrew Cagney <cagney@chook>
60
61 * mips.igen (do_ddiv, do_ddivu): Pacify GCC. Update hi/lo via tmp
62 variables.
63
64Wed Dec 16 18:20:28 1998 Andrew Cagney <cagney@chook>
65
66 * Makefile.in (SIM_EXTRA_CFLAGS): No longer need to add .../newlib
67 to include path.
68 (interp.o): Add dependency on itable.h
69 (oengine.c, gencode): Delete remaining references.
70 (BUILT_SRC_FROM_GEN): Clean up.
71
721998-12-16 Gavin Romig-Koch <gavin@cygnus.com>
73
74 * vr4run.c: New.
75 * Makefile.in (SIM_HACK_OBJ,HACK_OBJS,HACK_GEN_SRCS,libhack.a,
76 tmp-hack,tmp-m32-hack,tmp-m16-hack,tmp-itable-hack,
77 tmp-run-hack) : New.
78 * m16.igen (LD,DADDIU,DADDUI5,DADJSP,DADDIUSP,DADDI,DADDU,DSUBU,
79 DSLL,DSRL,DSRA,DSLLV,DSRAV,DMULT,DMULTU,DDIV,DDIVU,JALX32,JALX):
80 Drop the "64" qualifier to get the HACK generator working.
81 Use IMMEDIATE rather than IMMED. Use SHAMT rather than SHIFT.
82 * mips.igen (do_daddiu,do_ddiv,do_divu): Remove the 64-only
83 qualifier to get the hack generator working.
84 (do_dsll,do_dsllv,do_dsra,do_dsrl,do_dsrlv): New.
85 (DSLL): Use do_dsll.
86 (DSLLV): Use do_dsllv.
87 (DSRA): Use do_dsra.
88 (DSRL): Use do_dsrl.
89 (DSRLV): Use do_dsrlv.
90 (BC1): Move *vr4100 to get the HACK generator working.
91 (CxC1, DMxC1, MxC1,MACCU,MACCHI,MACCHIU): Rename to
92 get the HACK generator working.
93 (MACC) Rename to get the HACK generator working.
94 (DMACC,MACCS,DMACCS): Add the 64.
95
961998-12-12 Gavin Romig-Koch <gavin@cygnus.com>
97
98 * mips.igen (BC1): Renamed to BC1a and BC1b to avoid conflicts.
99 * sim-main.h (SizeFGR): Handle TARGET_ENABLE_FR.
100
1011998-12-11 Gavin Romig-Koch <gavin@cygnus.com>
102
103 * mips/interp.c (DEBUG): Cleanups.
104
1051998-12-10 Frank Ch. Eigler <fche@cygnus.com>
106
107 * dv-tx3904sio.c (tx3904sio_io_read_buffer): Endianness fixes.
108 (tx3904sio_tickle): fflush after a stdout character output.
109
1101998-12-03 Frank Ch. Eigler <fche@cygnus.com>
111
112 * interp.c (sim_close): Uninstall modules.
113
114Wed Nov 25 13:41:03 1998 Andrew Cagney <cagney@b1.cygnus.com>
115
116 * sim-main.h, interp.c (sim_monitor): Change to global
117 function.
118
119Wed Nov 25 17:33:24 1998 Andrew Cagney <cagney@b1.cygnus.com>
120
121 * configure.in (vr4100): Only include vr4100 instructions in
122 simulator.
123 * configure: Re-generate.
124 * m16.igen (*): Tag all mips16 instructions as also being vr4100.
125
126Mon Nov 23 18:20:36 1998 Andrew Cagney <cagney@b1.cygnus.com>
127
128 * Makefile.in (SIM_CFLAGS): Do not define WITH_IGEN.
129 * sim-main.h, sim-main.c, interp.c: Delete #if WITH_IGEN keeping
130 true alternative.
131
132 * configure.in (sim_default_gen, sim_use_gen): Replace with
133 sim_gen.
134 (--enable-sim-igen): Delete config option. Always using IGEN.
135 * configure: Re-generate.
136
137 * Makefile.in (gencode): Kill, kill, kill.
138 * gencode.c: Ditto.
139
140Mon Nov 23 18:07:36 1998 Andrew Cagney <cagney@b1.cygnus.com>
141
142 * configure.in: Configure mips64vr4100-elf nee mips64vr41* as a 64
143 bit mips16 igen simulator.
144 * configure: Re-generate.
145
146 * mips.igen (check_div_hilo, check_mult_hilo, check_mf_hilo): Mark
147 as part of vr4100 ISA.
148 * vr.igen: Mark all instructions as 64 bit only.
149
150Mon Nov 23 17:07:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
151
152 * interp.c (get_cell, sim_monitor, fetch_str, CoProcPresent):
153 Pacify GCC.
154
155Mon Nov 23 13:23:40 1998 Andrew Cagney <cagney@b1.cygnus.com>
156
157 * configure.in: Configure mips-lsi-elf nee mips*lsi* as a
158 mipsIII/mips16 igen simulator. Fix sim_gen VS sim_igen typos.
159 * configure: Re-generate.
160
161 * m16.igen (BREAK): Define breakpoint instruction.
162 (JALX32): Mark instruction as mips16 and not r3900.
163 * mips.igen (C.cond.fmt): Fix typo in instruction format.
164
165 * sim-main.h (PENDING_FILL): Wrap C statements in do/while.
166
167Sat Nov 7 09:54:38 1998 Andrew Cagney <cagney@b1.cygnus.com>
168
169 * gencode.c (build_instruction - BREAK): For MIPS16, handle BREAK
170 insn as a debug breakpoint.
171
172 * sim-main.h (PENDING_SLOT_BIT): Fix, was incorrectly defined as
173 pending.slot_size.
174 (PENDING_SCHED): Clean up trace statement.
175 (PENDING_SCHED): Increment PENDING_IN and PENDING_TOTAL.
176 (PENDING_FILL): Delay write by only one cycle.
177 (PENDING_FILL): For FSRs, write fmt_uninterpreted to FPR_STATE.
178
179 * sim-main.c (pending_tick): Clean up trace statements. Add trace
180 of pending writes.
181 (pending_tick): Fix sizes in switch statements, 4 & 8 instead of
182 32 & 64.
183 (pending_tick): Move incrementing of index to FOR statement.
184 (pending_tick): Only update PENDING_OUT after a write has occured.
185
186 * configure.in: Add explicit mips-lsi-* target. Use gencode to
187 build simulator.
188 * configure: Re-generate.
189
190 * interp.c (sim_engine_run OLD): Delete explicit call to
191 PENDING_TICK. Now called via ENGINE_ISSUE_PREFIX_HOOK.
192
193Sat Oct 30 09:49:10 1998 Frank Ch. Eigler <fche@cygnus.com>
194
195 * dv-tx3904cpu.c (deliver_tx3904cpu_interrupt): Add dummy
196 interrupt level number to match changed SignalExceptionInterrupt
197 macro.
198
199Fri Oct 9 18:02:25 1998 Doug Evans <devans@canuck.cygnus.com>
200
201 * interp.c: #include "itable.h" if WITH_IGEN.
202 (get_insn_name): New function.
203 (sim_open): Initialize CPU_INSN_NAME,CPU_MAX_INSNS.
204 * sim-main.h (MAX_INSNS,INSN_NAME): Delete.
205
206Mon Sep 14 12:36:44 1998 Frank Ch. Eigler <fche@cygnus.com>
207
208 * configure: Rebuilt to inhale new common/aclocal.m4.
209
210Tue Sep 1 15:39:18 1998 Frank Ch. Eigler <fche@cygnus.com>
211
212 * dv-tx3904sio.c: Include sim-assert.h.
213
214Tue Aug 25 12:49:46 1998 Frank Ch. Eigler <fche@cygnus.com>
215
216 * dv-tx3904sio.c: New file: tx3904 serial I/O module.
217 * configure.in: Add dv-tx3904sio, dv-sockser for tx39 target.
218 Reorganize target-specific sim-hardware checks.
219 * configure: rebuilt.
220 * interp.c (sim_open): For tx39 target boards, set
221 OPERATING_ENVIRONMENT, add tx3904sio devices.
222 * tconfig.in: For tx39 target, set SIM_HANDLES_LMA for loading
223 ROM executables. Install dv-sockser into sim-modules list.
224
225 * dv-tx3904irc.c: Compiler warning clean-up.
226 * dv-tx3904tmr.c: Compiler warning clean-up. Remove particularly
227 frequent hw-trace messages.
228
229Fri Jul 31 18:14:16 1998 Andrew Cagney <cagney@b1.cygnus.com>
230
231 * vr.igen (MulAcc): Identify as a vr4100 specific function.
232
233Sat Jul 25 16:03:14 1998 Andrew Cagney <cagney@b1.cygnus.com>
234
235 * Makefile.in (IGEN_INCLUDE): Add vr.igen.
236
237 * vr.igen: New file.
238 (MAC/MADD16, DMAC/DMADD16): Implement using code from gencode.c.
239 * mips.igen: Define vr4100 model. Include vr.igen.
240Mon Jun 29 09:21:07 1998 Gavin Koch <gavin@cygnus.com>
241
242 * mips.igen (check_mf_hilo): Correct check.
243
244Wed Jun 17 12:20:49 1998 Andrew Cagney <cagney@b1.cygnus.com>
245
246 * sim-main.h (interrupt_event): Add prototype.
247
248 * dv-tx3904tmr.c (tx3904tmr_io_write_buffer): Delete unused
249 register_ptr, register_value.
250 (deliver_tx3904tmr_tick): Fix types passed to printf fmt.
251
252 * sim-main.h (tracefh): Make extern.
253
254Tue Jun 16 14:39:00 1998 Frank Ch. Eigler <fche@cygnus.com>
255
256 * dv-tx3904tmr.c: Deschedule timer event after dispatching.
257 Reduce unnecessarily high timer event frequency.
258 * dv-tx3904cpu.c: Ditto for interrupt event.
259
260Wed Jun 10 13:22:32 1998 Frank Ch. Eigler <fche@cygnus.com>
261
262 * interp.c (decode_coproc): For TX39, add stub COP0 register #7,
263 to allay warnings.
264 (interrupt_event): Made non-static.
265
266 * dv-tx3904tmr.c (deliver_tx3904tmr_tick): Correct accidental
267 interchange of configuration values for external vs. internal
268 clock dividers.
269
270Tue Jun 9 12:46:24 1998 Ian Carmichael <iancarm@cygnus.com>
271
272 * mips.igen (BREAK): Moved code to here for
273 simulator-reserved break instructions.
274 * gencode.c (build_instruction): Ditto.
275 * interp.c (signal_exception): Code moved from here. Non-
276 reserved instructions now use exception vector, rather
277 than halting sim.
278 * sim-main.h: Moved magic constants to here.
279
280Tue Jun 9 12:29:50 1998 Frank Ch. Eigler <fche@cygnus.com>
281
282 * dv-tx3904cpu.c (deliver_*_interrupt,*_port_event): Set the CAUSE
283 register upon non-zero interrupt event level, clear upon zero
284 event value.
285 * dv-tx3904irc.c (*_port_event): Handle deactivated interrupt signal
286 by passing zero event value.
287 (*_io_{read,write}_buffer): Endianness fixes.
288 * dv-tx3904tmr.c (*_io_{read,write}_buffer): Endianness fixes.
289 (deliver_*_tick): Reduce sim event interval to 75% of count interval.
290
291 * interp.c (sim_open): Added jmr3904pal board type that adds PAL-based
292 serial I/O and timer module at base address 0xFFFF0000.
293
294Tue Jun 9 11:52:29 1998 Gavin Koch <gavin@cygnus.com>
295
296 * mips.igen (SWC1) : Correct the handling of ReverseEndian
297 and BigEndianCPU.
298
299Tue Jun 9 11:40:57 1998 Gavin Koch <gavin@cygnus.com>
300
301 * configure.in (mips_fpu_bitsize) : Set this correctly for 32-bit mips
302 parts.
303 * configure: Update.
304
305Thu Jun 4 15:37:33 1998 Frank Ch. Eigler <fche@cygnus.com>
306
307 * dv-tx3904tmr.c: New file - implements tx3904 timer.
308 * dv-tx3904{irc,cpu}.c: Mild reformatting.
309 * configure.in: Include tx3904tmr in hw_device list.
310 * configure: Rebuilt.
311 * interp.c (sim_open): Instantiate three timer instances.
312 Fix address typo of tx3904irc instance.
313
314Tue Jun 2 15:48:02 1998 Ian Carmichael <iancarm@cygnus.com>
315
316 * interp.c (signal_exception): SystemCall exception now uses
317 the exception vector.
318
319Mon Jun 1 18:18:26 1998 Frank Ch. Eigler <fche@cygnus.com>
320
321 * interp.c (decode_coproc): For TX39, add stub COP0 register #3,
322 to allay warnings.
323
324Fri May 29 11:40:39 1998 Andrew Cagney <cagney@b1.cygnus.com>
325
326 * configure.in (sim_igen_filter): Match mips*tx39 not mipst*tx39.
327
328Mon May 25 20:47:45 1998 Andrew Cagney <cagney@b1.cygnus.com>
329
330 * dv-tx3904cpu.c, dv-tx3904irc.c: Rename *_callback to *_method.
331
332 * dv-tx3904cpu.c, dv-tx3904irc.c: Include hw-main.h and
333 sim-main.h. Declare a struct hw_descriptor instead of struct
334 hw_device_descriptor.
335
336Mon May 25 12:41:38 1998 Andrew Cagney <cagney@b1.cygnus.com>
337
338 * mips.igen (do_store_left, do_load_left): Compute nr of left and
339 right bits and then re-align left hand bytes to correct byte
340 lanes. Fix incorrect computation in do_store_left when loading
341 bytes from second word.
342
343Fri May 22 13:34:20 1998 Andrew Cagney <cagney@b1.cygnus.com>
344
345 * configure.in (SIM_AC_OPTION_HARDWARE): Only enable when tx3904.
346 * interp.c (sim_open): Only create a device tree when HW is
347 enabled.
348
349 * dv-tx3904irc.c (tx3904irc_finish): Pacify GCC.
350 * interp.c (signal_exception): Ditto.
351
352Thu May 21 14:24:11 1998 Gavin Koch <gavin@cygnus.com>
353
354 * gencode.c: Mark BEGEZALL as LIKELY.
355
356Thu May 21 18:57:19 1998 Andrew Cagney <cagney@b1.cygnus.com>
357
358 * sim-main.h (ALU32_END): Sign extend 32 bit results.
359 * mips.igen (ADD, SUB, ADDI, DADD, DSUB): Trace.
360
361Mon May 18 18:22:42 1998 Frank Ch. Eigler <fche@cygnus.com>
362
363 * configure.in (SIM_AC_OPTION_HARDWARE): Added common hardware
364 modules. Recognize TX39 target with "mips*tx39" pattern.
365 * configure: Rebuilt.
366 * sim-main.h (*): Added many macros defining bits in
367 TX39 control registers.
368 (SignalInterrupt): Send actual PC instead of NULL.
369 (SignalNMIReset): New exception type.
370 * interp.c (board): New variable for future use to identify
371 a particular board being simulated.
372 (mips_option_handler,mips_options): Added "--board" option.
373 (interrupt_event): Send actual PC.
374 (sim_open): Make memory layout conditional on board setting.
375 (signal_exception): Initial implementation of hardware interrupt
376 handling. Accept another break instruction variant for simulator
377 exit.
378 (decode_coproc): Implement RFE instruction for TX39.
379 (mips.igen): Decode RFE instruction as such.
380 * configure.in (tx3904cpu,tx3904irc): Added devices for tx3904.
381 * interp.c: Define "jmr3904" and "jmr3904debug" board types and
382 bbegin to implement memory map.
383 * dv-tx3904cpu.c: New file.
384 * dv-tx3904irc.c: New file.
385
386Wed May 13 14:40:11 1998 Gavin Koch <gavin@cygnus.com>
387
388 * mips.igen (check_mt_hilo): Create a separate r3900 version.
389
390Wed May 13 14:11:46 1998 Gavin Koch <gavin@cygnus.com>
391
392 * tx.igen (madd,maddu): Replace calls to check_op_hilo
393 with calls to check_div_hilo.
394
395Wed May 13 09:59:27 1998 Gavin Koch <gavin@cygnus.com>
396
397 * mips/mips.igen (check_op_hilo,check_mult_hilo,check_div_hilo):
398 Replace check_op_hilo with check_mult_hilo and check_div_hilo.
399 Add special r3900 version of do_mult_hilo.
400 (do_dmultx,do_mult,do_multu): Replace calls to check_op_hilo
401 with calls to check_mult_hilo.
402 (do_ddiv,do_ddivu,do_div,do_divu): Replace calls to check_op_hilo
403 with calls to check_div_hilo.
404
405Tue May 12 15:22:11 1998 Andrew Cagney <cagney@b1.cygnus.com>
406
407 * configure.in (SUBTARGET_R3900): Define for mipstx39 target.
408 Document a replacement.
409
410Fri May 8 17:48:19 1998 Ian Carmichael <iancarm@cygnus.com>
411
412 * interp.c (sim_monitor): Make mon_printf work.
413
414Wed May 6 19:42:19 1998 Doug Evans <devans@canuck.cygnus.com>
415
416 * sim-main.h (INSN_NAME): New arg `cpu'.
417
418Tue Apr 28 18:33:31 1998 Geoffrey Noer <noer@cygnus.com>
419
420 * configure: Regenerated to track ../common/aclocal.m4 changes.
421
422Sun Apr 26 15:31:55 1998 Tom Tromey <tromey@creche>
423
424 * configure: Regenerated to track ../common/aclocal.m4 changes.
425 * config.in: Ditto.
426
427Sun Apr 26 15:20:01 1998 Tom Tromey <tromey@cygnus.com>
428
429 * acconfig.h: New file.
430 * configure.in: Reverted change of Apr 24; use sinclude again.
431
432Fri Apr 24 14:16:40 1998 Tom Tromey <tromey@creche>
433
434 * configure: Regenerated to track ../common/aclocal.m4 changes.
435 * config.in: Ditto.
436
437Fri Apr 24 11:19:20 1998 Tom Tromey <tromey@cygnus.com>
438
439 * configure.in: Don't call sinclude.
440
441Fri Apr 24 11:35:01 1998 Andrew Cagney <cagney@chook.cygnus.com>
442
443 * mips.igen (do_store_left): Pass 0 not NULL to store_memory.
444
445Tue Apr 21 11:59:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
446
447 * mips.igen (ERET): Implement.
448
449 * interp.c (decode_coproc): Return sign-extended EPC.
450
451 * mips.igen (ANDI, LUI, MFC0): Add tracing code.
452
453 * interp.c (signal_exception): Do not ignore Trap.
454 (signal_exception): On TRAP, restart at exception address.
455 (HALT_INSTRUCTION, HALT_INSTRUCTION_MASK): Define.
456 (signal_exception): Update.
457 (sim_open): Patch V_COMMON interrupt vector with an abort sequence
458 so that TRAP instructions are caught.
459
460Mon Apr 20 11:26:55 1998 Andrew Cagney <cagney@b1.cygnus.com>
461
462 * sim-main.h (struct hilo_access, struct hilo_history): Define,
463 contains HI/LO access history.
464 (struct _sim_cpu): Make hiaccess and loaccess of type hilo_access.
465 (HIACCESS, LOACCESS): Delete, replace with
466 (HIHISTORY, LOHISTORY): New macros.
467 (CHECKHILO): Delete all, moved to mips.igen
468
469 * gencode.c (build_instruction): Do not generate checks for
470 correct HI/LO register usage.
471
472 * interp.c (old_engine_run): Delete checks for correct HI/LO
473 register usage.
474
475 * mips.igen (check_mt_hilo, check_mf_hilo, check_op_hilo,
476 check_mf_cycles): New functions.
477 (do_mfhi, do_mflo, "mthi", "mtlo", do_ddiv, do_ddivu, do_div,
478 do_divu, domultx, do_mult, do_multu): Use.
479
480 * tx.igen ("madd", "maddu"): Use.
481
482Wed Apr 15 18:31:54 1998 Andrew Cagney <cagney@b1.cygnus.com>
483
484 * mips.igen (DSRAV): Use function do_dsrav.
485 (SRAV): Use new function do_srav.
486
487 * m16.igen (BEQZ, BNEZ): Compare GPR[TRX] not GPR[RX].
488 (B): Sign extend 11 bit immediate.
489 (EXT-B*): Shift 16 bit immediate left by 1.
490 (ADDIU*): Don't sign extend immediate value.
491
492Wed Apr 15 10:32:15 1998 Andrew Cagney <cagney@b1.cygnus.com>
493
494 * m16run.c (sim_engine_run): Restore CIA after handling an event.
495
496 * sim-main.h (DELAY_SLOT, NULLIFY_NEXT_INSTRUCTION): For IGEN, use
497 functions.
498
499 * mips.igen (delayslot32, nullify_next_insn): New functions.
500 (m16.igen): Always include.
501 (do_*): Add more tracing.
502
503 * m16.igen (delayslot16): Add NIA argument, could be called by a
504 32 bit MIPS16 instruction.
505
506 * interp.c (ifetch16): Move function from here.
507 * sim-main.c (ifetch16): To here.
508
509 * sim-main.c (ifetch16, ifetch32): Update to match current
510 implementations of LH, LW.
511 (signal_exception): Don't print out incorrect hex value of illegal
512 instruction.
513
514Wed Apr 15 00:17:25 1998 Andrew Cagney <cagney@b1.cygnus.com>
515
516 * m16run.c (sim_engine_run): Use IMEM16 and IMEM32 to fetch an
517 instruction.
518
519 * m16.igen: Implement MIPS16 instructions.
520
521 * mips.igen (do_addiu, do_addu, do_and, do_daddiu, do_daddu,
522 do_ddiv, do_ddivu, do_div, do_divu, do_dmultx, do_dmultu, do_srav,
523 do_dsubu, do_mfhi, do_mflo, do_mult, do_multu, do_nor, do_or,
524 do_sll, do_sllv, do_slt, do_slti, do_sltiu, do_sltu, do_sra,
525 do_srl, do_srlv, do_subu, do_xor, do_xori): New functions. Move
526 bodies of corresponding code from 32 bit insn to these. Also used
527 by MIPS16 versions of functions.
528
529 * sim-main.h (RAIDX, T8IDX, T8, SPIDX): Define.
530 (IMEM16): Drop NR argument from macro.
531
532Sat Apr 4 22:39:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
533
534 * Makefile.in (SIM_OBJS): Add sim-main.o.
535
536 * sim-main.h (address_translation, load_memory, store_memory,
537 cache_op, sync_operation, prefetch, ifetch32, pending_tick): Mark
538 as INLINE_SIM_MAIN.
539 (pr_addr, pr_uword64): Declare.
540 (sim-main.c): Include when H_REVEALS_MODULE_P.
541
542 * interp.c (address_translation, load_memory, store_memory,
543 cache_op, sync_operation, prefetch, ifetch32, pending_tick): Move
544 from here.
545 * sim-main.c: To here. Fix compilation problems.
546
547 * configure.in: Enable inlining.
548 * configure: Re-config.
549
550Sat Apr 4 20:36:25 1998 Andrew Cagney <cagney@b1.cygnus.com>
551
552 * configure: Regenerated to track ../common/aclocal.m4 changes.
553
554Fri Apr 3 04:32:35 1998 Andrew Cagney <cagney@b1.cygnus.com>
555
556 * mips.igen: Include tx.igen.
557 * Makefile.in (IGEN_INCLUDE): Add tx.igen.
558 * tx.igen: New file, contains MADD and MADDU.
559
560 * interp.c (load_memory): When shifting bytes, use LOADDRMASK not
561 the hardwired constant `7'.
562 (store_memory): Ditto.
563 (LOADDRMASK): Move definition to sim-main.h.
564
565 mips.igen (MTC0): Enable for r3900.
566 (ADDU): Add trace.
567
568 mips.igen (do_load_byte): Delete.
569 (do_load, do_store, do_load_left, do_load_write, do_store_left,
570 do_store_right): New functions.
571 (SW*, LW*, SD*, LD*, SH, LH, SB, LB): Use.
572
573 configure.in: Let the tx39 use igen again.
574 configure: Update.
575
576Thu Apr 2 10:59:39 1998 Andrew Cagney <cagney@b1.cygnus.com>
577
578 * interp.c (sim_monitor): get_mem_info returns a 4 byte quantity,
579 not an address sized quantity. Return zero for cache sizes.
580
581Wed Apr 1 23:47:53 1998 Andrew Cagney <cagney@b1.cygnus.com>
582
583 * mips.igen (r3900): r3900 does not support 64 bit integer
584 operations.
585
586Mon Mar 30 14:46:05 1998 Gavin Koch <gavin@cygnus.com>
587
588 * configure.in (mipstx39*-*-*): Use gencode simulator rather
589 than igen one.
590 * configure : Rebuild.
591
592Fri Mar 27 16:15:52 1998 Andrew Cagney <cagney@b1.cygnus.com>
593
594 * configure: Regenerated to track ../common/aclocal.m4 changes.
595
596Fri Mar 27 15:01:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
597
598 * interp.c (mips_option_handler): Iterate over MAX_NR_PROCESSORS.
599
600Wed Mar 25 16:44:27 1998 Ian Carmichael <iancarm@cygnus.com>
601
602 * configure: Regenerated to track ../common/aclocal.m4 changes.
603 * config.in: Regenerated to track ../common/aclocal.m4 changes.
604
605Wed Mar 25 12:35:29 1998 Andrew Cagney <cagney@b1.cygnus.com>
606
607 * configure: Regenerated to track ../common/aclocal.m4 changes.
608
609Wed Mar 25 10:05:46 1998 Andrew Cagney <cagney@b1.cygnus.com>
610
611 * interp.c (Max, Min): Comment out functions. Not yet used.
612
613Wed Mar 18 12:38:12 1998 Andrew Cagney <cagney@b1.cygnus.com>
614
615 * configure: Regenerated to track ../common/aclocal.m4 changes.
616
617Tue Mar 17 19:05:20 1998 Frank Ch. Eigler <fche@cygnus.com>
618
619 * Makefile.in (MIPS_EXTRA_LIBS, SIM_EXTRA_LIBS): Added
620 configurable settings for stand-alone simulator.
621
622 * configure.in: Added X11 search, just in case.
623
624 * configure: Regenerated.
625
626Wed Mar 11 14:09:10 1998 Andrew Cagney <cagney@b1.cygnus.com>
627
628 * interp.c (sim_write, sim_read, load_memory, store_memory):
629 Replace sim_core_*_map with read_map, write_map, exec_map resp.
630
631Tue Mar 3 13:58:43 1998 Andrew Cagney <cagney@b1.cygnus.com>
632
633 * sim-main.h (GETFCC): Return an unsigned value.
634
635Tue Mar 3 13:21:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
636
637 * mips.igen (DIV): Fix check for -1 / MIN_INT.
638 (DADD): Result destination is RD not RT.
639
640Fri Feb 27 13:49:49 1998 Andrew Cagney <cagney@b1.cygnus.com>
641
642 * sim-main.h (HIACCESS, LOACCESS): Always define.
643
644 * mdmx.igen (Maxi, Mini): Rename Max, Min.
645
646 * interp.c (sim_info): Delete.
647
648Fri Feb 27 18:41:01 1998 Doug Evans <devans@canuck.cygnus.com>
649
650 * interp.c (DECLARE_OPTION_HANDLER): Use it.
651 (mips_option_handler): New argument `cpu'.
652 (sim_open): Update call to sim_add_option_table.
653
654Wed Feb 25 18:56:22 1998 Andrew Cagney <cagney@b1.cygnus.com>
655
656 * mips.igen (CxC1): Add tracing.
657
658Fri Feb 20 17:43:21 1998 Andrew Cagney <cagney@b1.cygnus.com>
659
660 * sim-main.h (Max, Min): Declare.
661
662 * interp.c (Max, Min): New functions.
663
664 * mips.igen (BC1): Add tracing.
665
666Thu Feb 19 14:50:00 1998 John Metzler <jmetzler@cygnus.com>
667
668 * interp.c Added memory map for stack in vr4100
669
670Thu Feb 19 10:21:21 1998 Gavin Koch <gavin@cygnus.com>
671
672 * interp.c (load_memory): Add missing "break"'s.
673
674Tue Feb 17 12:45:35 1998 Andrew Cagney <cagney@b1.cygnus.com>
675
676 * interp.c (sim_store_register, sim_fetch_register): Pass in
677 length parameter. Return -1.
678
679Tue Feb 10 11:57:40 1998 Ian Carmichael <iancarm@cygnus.com>
680
681 * interp.c: Added hardware init hook, fixed warnings.
682
683Sat Feb 7 17:16:20 1998 Andrew Cagney <cagney@b1.cygnus.com>
684
685 * Makefile.in (itable.h itable.c): Depend on SIM_@sim_gen@_ALL.
686
687Tue Feb 3 11:36:02 1998 Andrew Cagney <cagney@b1.cygnus.com>
688
689 * interp.c (ifetch16): New function.
690
691 * sim-main.h (IMEM32): Rename IMEM.
692 (IMEM16_IMMED): Define.
693 (IMEM16): Define.
694 (DELAY_SLOT): Update.
695
696 * m16run.c (sim_engine_run): New file.
697
698 * m16.igen: All instructions except LB.
699 (LB): Call do_load_byte.
700 * mips.igen (do_load_byte): New function.
701 (LB): Call do_load_byte.
702
703 * mips.igen: Move spec for insn bit size and high bit from here.
704 * Makefile.in (tmp-igen, tmp-m16): To here.
705
706 * m16.dc: New file, decode mips16 instructions.
707
708 * Makefile.in (SIM_NO_ALL): Define.
709 (tmp-m16): Generate both 16 bit and 32 bit simulator engines.
710
711Tue Feb 3 11:28:00 1998 Andrew Cagney <cagney@b1.cygnus.com>
712
713 * configure.in (mips_fpu_bitsize): For tx39, restrict floating
714 point unit to 32 bit registers.
715 * configure: Re-generate.
716
717Sun Feb 1 15:47:14 1998 Andrew Cagney <cagney@b1.cygnus.com>
718
719 * configure.in (sim_use_gen): Make IGEN the default simulator
720 generator for generic 32 and 64 bit mips targets.
721 * configure: Re-generate.
722
723Sun Feb 1 16:52:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
724
725 * sim-main.h (SizeFGR): Determine from floating-point and not gpr
726 bitsize.
727
728 * interp.c (sim_fetch_register, sim_store_register): Read/write
729 FGR from correct location.
730 (sim_open): Set size of FGR's according to
731 WITH_TARGET_FLOATING_POINT_BITSIZE.
732
733 * sim-main.h (FGR): Store floating point registers in a separate
734 array.
735
736Sun Feb 1 16:47:51 1998 Andrew Cagney <cagney@b1.cygnus.com>
737
738 * configure: Regenerated to track ../common/aclocal.m4 changes.
739
740Tue Feb 3 00:10:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
741
742 * interp.c (ColdReset): Call PENDING_INVALIDATE.
743
744 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Call PENDING_TICK.
745
746 * interp.c (pending_tick): New function. Deliver pending writes.
747
748 * sim-main.h (PENDING_FILL, PENDING_TICK, PENDING_SCHED,
749 PENDING_BIT, PENDING_INVALIDATE): Re-write pipeline code so that
750 it can handle mixed sized quantites and single bits.
751
752Mon Feb 2 17:43:15 1998 Andrew Cagney <cagney@b1.cygnus.com>
753
754 * interp.c (oengine.h): Do not include when building with IGEN.
755 (sim_open): Replace GPRLEN by WITH_TARGET_WORD_BITSIZE.
756 (sim_info): Ditto for PROCESSOR_64BIT.
757 (sim_monitor): Replace ut_reg with unsigned_word.
758 (*): Ditto for t_reg.
759 (LOADDRMASK): Define.
760 (sim_open): Remove defunct check that host FP is IEEE compliant,
761 using software to emulate floating point.
762 (value_fpr, ...): Always compile, was conditional on HASFPU.
763
764Sun Feb 1 11:15:29 1998 Andrew Cagney <cagney@b1.cygnus.com>
765
766 * sim-main.h (sim_state): Make the cpu array MAX_NR_PROCESSORS in
767 size.
768
769 * interp.c (SD, CPU): Define.
770 (mips_option_handler): Set flags in each CPU.
771 (interrupt_event): Assume CPU 0 is the one being iterrupted.
772 (sim_close): Do not clear STATE, deleted anyway.
773 (sim_write, sim_read): Assume CPU zero's vm should be used for
774 data transfers.
775 (sim_create_inferior): Set the PC for all processors.
776 (sim_monitor, store_word, load_word, mips16_entry): Add cpu
777 argument.
778 (mips16_entry): Pass correct nr of args to store_word, load_word.
779 (ColdReset): Cold reset all cpu's.
780 (signal_exception): Pass cpu to sim_monitor & mips16_entry.
781 (sim_monitor, load_memory, store_memory, signal_exception): Use
782 `CPU' instead of STATE_CPU.
783
784
785 * sim-main.h: Replace uses of STATE_CPU with CPU. Replace sd with
786 SD or CPU_.
787
788 * sim-main.h (signal_exception): Add sim_cpu arg.
789 (SignalException*): Pass both SD and CPU to signal_exception.
790 * interp.c (signal_exception): Update.
791
792 * sim-main.h (value_fpr, store_fpr, dotrace, ifetch32), interp.c:
793 Ditto
794 (sync_operation, prefetch, cache_op, store_memory, load_memory,
795 address_translation): Ditto
796 (decode_coproc, cop_lw, cop_ld, cop_sw, cop_sd): Ditto.
797
798Sat Jan 31 18:15:41 1998 Andrew Cagney <cagney@b1.cygnus.com>
799
800 * configure: Regenerated to track ../common/aclocal.m4 changes.
801
802Sat Jan 31 14:49:24 1998 Andrew Cagney <cagney@b1.cygnus.com>
803
804 * interp.c (sim_engine_run): Add `nr_cpus' argument.
805
806 * mips.igen (model): Map processor names onto BFD name.
807
808 * sim-main.h (CPU_CIA): Delete.
809 (SET_CIA, GET_CIA): Define
810
811Wed Jan 21 16:16:27 1998 Andrew Cagney <cagney@b1.cygnus.com>
812
813 * sim-main.h (GPR_SET): Define, used by igen when zeroing a
814 regiser.
815
816 * configure.in (default_endian): Configure a big-endian simulator
817 by default.
818 * configure: Re-generate.
819
820Mon Jan 19 22:26:29 1998 Doug Evans <devans@seba>
821
822 * configure: Regenerated to track ../common/aclocal.m4 changes.
823
824Mon Jan 5 20:38:54 1998 Mark Alexander <marka@cygnus.com>
825
826 * interp.c (sim_monitor): Handle Densan monitor outbyte
827 and inbyte functions.
828
8291997-12-29 Felix Lee <flee@cygnus.com>
830
831 * interp.c (sim_engine_run): msvc cpp barfs on #if (a==b!=c).
832
833Wed Dec 17 14:48:20 1997 Jeffrey A Law (law@cygnus.com)
834
835 * Makefile.in (tmp-igen): Arrange for $zero to always be
836 reset to zero after every instruction.
837
838Mon Dec 15 23:17:11 1997 Andrew Cagney <cagney@b1.cygnus.com>
839
840 * configure: Regenerated to track ../common/aclocal.m4 changes.
841 * config.in: Ditto.
842
843Wed Dec 10 17:10:45 1997 Jeffrey A Law (law@cygnus.com)
844
845 * mips.igen (MSUB): Fix to work like MADD.
846 * gencode.c (MSUB): Similarly.
847
848Thu Dec 4 09:21:05 1997 Doug Evans <devans@canuck.cygnus.com>
849
850 * configure: Regenerated to track ../common/aclocal.m4 changes.
851
852Wed Nov 26 11:00:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
853
854 * mips.igen (LWC1): Correct assembler - lwc1 not swc1.
855
856Sun Nov 23 01:45:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
857
858 * sim-main.h (sim-fpu.h): Include.
859
860 * interp.c (convert, SquareRoot, Recip, Divide, Multiply, Sub,
861 Add, Negate, AbsoluteValue, Equal, Less, Infinity, NaN): Rewrite
862 using host independant sim_fpu module.
863
864Thu Nov 20 19:56:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
865
866 * interp.c (signal_exception): Report internal errors with SIGABRT
867 not SIGQUIT.
868
869 * sim-main.h (C0_CONFIG): New register.
870 (signal.h): No longer include.
871
872 * interp.c (decode_coproc): Allow access C0_CONFIG to register.
873
874Tue Nov 18 15:33:48 1997 Doug Evans <devans@canuck.cygnus.com>
875
876 * Makefile.in (SIM_OBJS): Use $(SIM_NEW_COMMON_OBJS).
877
878Fri Nov 14 11:56:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
879
880 * mips.igen: Tag vr5000 instructions.
881 (ANDI): Was missing mipsIV model, fix assembler syntax.
882 (do_c_cond_fmt): New function.
883 (C.cond.fmt): Handle mips I-III which do not support CC field
884 separatly.
885 (bc1): Handle mips IV which do not have a delaed FCC separatly.
886 (SDR): Mask paddr when BigEndianMem, not the converse as specified
887 in IV3.2 spec.
888 (DMULT, DMULTU): Force use of hosts 64bit multiplication. Handle
889 vr5000 which saves LO in a GPR separatly.
890
891 * configure.in (enable-sim-igen): For vr5000, select vr5000
892 specific instructions.
893 * configure: Re-generate.
894
895Wed Nov 12 14:42:52 1997 Andrew Cagney <cagney@b1.cygnus.com>
896
897 * Makefile.in (SIM_OBJS): Add sim-fpu module.
898
899 * interp.c (store_fpr), sim-main.h: Add separate fmt_uninterpreted_32 and
900 fmt_uninterpreted_64 bit cases to switch. Convert to
901 fmt_formatted,
902
903 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Define,
904
905 * mips.igen (SWR): Mask paddr when BigEndianMem, not the converse
906 as specified in IV3.2 spec.
907 (MTC1, DMTC1): Call StoreFPR to store the GPR in the FPR.
908
909Tue Nov 11 12:38:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
910
911 * mips.igen: Delay slot branches add OFFSET to NIA not CIA.
912 (MFC0, MTC0, SWC1, LWC1, SDC1, LDC1): Implement.
913 (MTC1, MFC1, DMTC1, DMFC1, CFC1, CTC1): Implement separate non
914 PENDING_FILL versions of instructions. Simplify.
915 (X): New function.
916 (MULT, MULTU): Implement separate RD==0 and RD!=0 versions of
917 instructions.
918 (BEQZ, ..., SLT, SLTI, TLT, TLE, TLI, ...): Explicitly cast GPR to
919 a signed value.
920 (MTHI, MFHI): Disable code checking HI-LO.
921
922 * sim-main.h (dotrace,tracefh), interp.c: Make dotrace & tracefh
923 global.
924 (NULLIFY_NEXT_INSTRUCTION): Call dotrace.
925
926Thu Nov 6 16:36:35 1997 Andrew Cagney <cagney@b1.cygnus.com>
927
928 * gencode.c (build_mips16_operands): Replace IPC with cia.
929
930 * interp.c (sim_monitor, signal_exception, cache_op, store_fpr,
931 value_fpr, cop_ld, cop_lw, cop_sw, cop_sd, decode_coproc): Replace
932 IPC to `cia'.
933 (UndefinedResult): Replace function with macro/function
934 combination.
935 (sim_engine_run): Don't save PC in IPC.
936
937 * sim-main.h (IPC): Delete.
938
939
940 * interp.c (signal_exception, store_word, load_word,
941 address_translation, load_memory, store_memory, cache_op,
942 prefetch, sync_operation, ifetch, value_fpr, store_fpr, convert,
943 cop_lw, cop_ld, cop_sw, cop_sd, decode_coproc, sim_monitor): Add
944 current instruction address - cia - argument.
945 (sim_read, sim_write): Call address_translation directly.
946 (sim_engine_run): Rename variable vaddr to cia.
947 (signal_exception): Pass cia to sim_monitor
948
949 * sim-main.h (SignalException, LoadWord, StoreWord, CacheOp,
950 Prefetch, SyncOperation, ValueFPR, StoreFPR, Convert, COP_LW,
951 COP_LD, COP_SW, COP_SD, DecodeCoproc): Update.
952
953 * sim-main.h (SignalExceptionSimulatorFault): Delete definition.
954 * interp.c (sim_open): Replace SignalExceptionSimulatorFault with
955 SIM_ASSERT.
956
957 * interp.c (signal_exception): Pass restart address to
958 sim_engine_restart.
959
960 * Makefile.in (semantics.o, engine.o, support.o, itable.o,
961 idecode.o): Add dependency.
962
963 * sim-main.h (SIM_ENGINE_HALT_HOOK, SIM_ENGINE_RESUME_HOOK):
964 Delete definitions
965 (DELAY_SLOT): Update NIA not PC with branch address.
966 (NULLIFY_NEXT_INSTRUCTION): Set NIA to instruction after next.
967
968 * mips.igen: Use CIA not PC in branch calculations.
969 (illegal): Call SignalException.
970 (BEQ, ADDIU): Fix assembler.
971
972Wed Nov 5 12:19:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
973
974 * m16.igen (JALX): Was missing.
975
976 * configure.in (enable-sim-igen): New configuration option.
977 * configure: Re-generate.
978
979 * sim-main.h (MAX_INSNS, INSN_NAME): Define.
980
981 * interp.c (load_memory, store_memory): Delete parameter RAW.
982 (sim_read, sim_write): Use sim_core_{read,write}_buffer directly
983 bypassing {load,store}_memory.
984
985 * sim-main.h (ByteSwapMem): Delete definition.
986
987 * Makefile.in (SIM_OBJS): Add sim-memopt module.
988
989 * interp.c (sim_do_command, sim_commands): Delete mips specific
990 commands. Handled by module sim-options.
991
992 * sim-main.h (SIM_HAVE_FLATMEM): Undefine, use sim-core.o module.
993 (WITH_MODULO_MEMORY): Define.
994
995 * interp.c (sim_info): Delete code printing memory size.
996
997 * interp.c (mips_size): Nee sim_size, delete function.
998 (power2): Delete.
999 (monitor, monitor_base, monitor_size): Delete global variables.
1000 (sim_open, sim_close): Delete code creating monitor and other
1001 memory regions. Use sim-memopts module, via sim_do_commandf, to
1002 manage memory regions.
1003 (load_memory, store_memory): Use sim-core for memory model.
1004
1005 * interp.c (address_translation): Delete all memory map code
1006 except line forcing 32 bit addresses.
1007
1008Wed Nov 5 11:21:11 1997 Andrew Cagney <cagney@b1.cygnus.com>
1009
1010 * sim-main.h (WITH_TRACE): Delete definition. Enables common
1011 trace options.
1012
1013 * interp.c (logfh, logfile): Delete globals.
1014 (sim_open, sim_close): Delete code opening & closing log file.
1015 (mips_option_handler): Delete -l and -n options.
1016 (OPTION mips_options): Ditto.
1017
1018 * interp.c (OPTION mips_options): Rename option trace to dinero.
1019 (mips_option_handler): Update.
1020
1021Wed Nov 5 09:35:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
1022
1023 * interp.c (fetch_str): New function.
1024 (sim_monitor): Rewrite using sim_read & sim_write.
1025 (sim_open): Check magic number.
1026 (sim_open): Write monitor vectors into memory using sim_write.
1027 (MONITOR_BASE, MONITOR_SIZE, MEM_SIZE): Define.
1028 (sim_read, sim_write): Simplify - transfer data one byte at a
1029 time.
1030 (load_memory, store_memory): Clarify meaning of parameter RAW.
1031
1032 * sim-main.h (isHOST): Defete definition.
1033 (isTARGET): Mark as depreciated.
1034 (address_translation): Delete parameter HOST.
1035
1036 * interp.c (address_translation): Delete parameter HOST.
1037
1038Wed Oct 29 11:13:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
1039
1040 * mips.igen:
1041
1042 * Makefile.in (IGEN_INCLUDE): Files included by mips.igen.
1043 (tmp-igen, tmp-m16): Depend on IGEN_INCLUDE.
1044
1045Tue Oct 28 11:06:47 1997 Andrew Cagney <cagney@b1.cygnus.com>
1046
1047 * mips.igen: Add model filter field to records.
1048
1049Mon Oct 27 17:53:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
1050
1051 * Makefile.in (SIM_NO_CFLAGS): Define. Define WITH_IGEN=0.
1052
1053 interp.c (sim_engine_run): Do not compile function sim_engine_run
1054 when WITH_IGEN == 1.
1055
1056 * configure.in (sim_igen_flags, sim_m16_flags): Set according to
1057 target architecture.
1058
1059 Makefile.in (tmp-igen, tmp-m16): Drop -F and -M options to
1060 igen. Replace with configuration variables sim_igen_flags /
1061 sim_m16_flags.
1062
1063 * m16.igen: New file. Copy mips16 insns here.
1064 * mips.igen: From here.
1065
1066Mon Oct 27 13:53:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
1067
1068 * Makefile.in (SIM_NO_OBJ): Define, move SIM_M16_OBJ, SIM_IGEN_OBJ
1069 to top.
1070 (tmp-igen, tmp-m16): Pass -I srcdir to igen.
1071
1072Sat Oct 25 16:51:40 1997 Gavin Koch <gavin@cygnus.com>
1073
1074 * gencode.c (build_instruction): Follow sim_write's lead in using
1075 BigEndianMem instead of !ByteSwapMem.
1076
1077Fri Oct 24 17:41:49 1997 Andrew Cagney <cagney@b1.cygnus.com>
1078
1079 * configure.in (sim_gen): Dependent on target, select type of
1080 generator. Always select old style generator.
1081
1082 configure: Re-generate.
1083
1084 Makefile.in (tmp-igen, tmp-m16, clean-m16, clean-igen): New
1085 targets.
1086 (SIM_M16_CFLAGS, SIM_M16_ALL, SIM_M16_OBJ, BUILT_SRC_FROM_M16,
1087 SIM_IGEN_CFLAGS, SIM_IGEN_ALL, SIM_IGEN_OBJ, BUILT_SRC_FROM_IGEN,
1088 IGEN_TRACE, IGEN_INSN, IGEN_DC): Define
1089 (SIM_EXTRA_CFLAGS, SIM_EXTRA_ALL, SIM_OBJS): Add member
1090 SIM_@sim_gen@_*, set by autoconf.
1091
1092Wed Oct 22 12:52:06 1997 Andrew Cagney <cagney@b1.cygnus.com>
1093
1094 * sim-main.h (NULLIFY_NEXT_INSTRUCTION, DELAY_SLOT): Define.
1095
1096 * interp.c (ColdReset): Remove #ifdef HASFPU, check
1097 CURRENT_FLOATING_POINT instead.
1098
1099 * interp.c (ifetch32): New function. Fetch 32 bit instruction.
1100 (address_translation): Raise exception InstructionFetch when
1101 translation fails and isINSTRUCTION.
1102
1103 * interp.c (sim_open, sim_write, sim_monitor, store_word,
1104 sim_engine_run): Change type of of vaddr and paddr to
1105 address_word.
1106 (address_translation, prefetch, load_memory, store_memory,
1107 cache_op): Change type of vAddr and pAddr to address_word.
1108
1109 * gencode.c (build_instruction): Change type of vaddr and paddr to
1110 address_word.
1111
1112Mon Oct 20 15:29:04 1997 Andrew Cagney <cagney@b1.cygnus.com>
1113
1114 * sim-main.h (ALU64_END, ALU32_END): Use ALU*_OVERFLOW_RESULT
1115 macro to obtain result of ALU op.
1116
1117Tue Oct 21 17:39:14 1997 Andrew Cagney <cagney@b1.cygnus.com>
1118
1119 * interp.c (sim_info): Call profile_print.
1120
1121Mon Oct 20 13:31:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1122
1123 * Makefile.in (SIM_OBJS): Add sim-profile.o module.
1124
1125 * sim-main.h (WITH_PROFILE): Do not define, defined in
1126 common/sim-config.h. Use sim-profile module.
1127 (simPROFILE): Delete defintion.
1128
1129 * interp.c (PROFILE): Delete definition.
1130 (mips_option_handler): Delete 'p', 'y' and 'x' profile options.
1131 (sim_close): Delete code writing profile histogram.
1132 (mips_set_profile, mips_set_profile_size, writeout16, writeout32):
1133 Delete.
1134 (sim_engine_run): Delete code profiling the PC.
1135
1136Mon Oct 20 13:31:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1137
1138 * sim-main.h (SIGNEXTEND): Force type of result to unsigned_word.
1139
1140 * interp.c (sim_monitor): Make register pointers of type
1141 unsigned_word*.
1142
1143 * sim-main.h: Make registers of type unsigned_word not
1144 signed_word.
1145
1146Thu Oct 16 10:31:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
1147
1148 * interp.c (sync_operation): Rename from SyncOperation, make
1149 global, add SD argument.
1150 (prefetch): Rename from Prefetch, make global, add SD argument.
1151 (decode_coproc): Make global.
1152
1153 * sim-main.h (SyncOperation, DecodeCoproc, Pefetch): Define.
1154
1155 * gencode.c (build_instruction): Generate DecodeCoproc not
1156 decode_coproc calls.
1157
1158 * interp.c (SETFCC, GETFCC, PREVCOC1): Move to sim-main.h
1159 (SizeFGR): Move to sim-main.h
1160 (simHALTEX, simHALTIN, simTRACE, simPROFILE, simDELAYSLOT,
1161 simSIGINT, simJALDELAYSLOT): Move to sim-main.h
1162 (FP_FLAGS, FP_ENABLE, FP_CAUSE, IR, UF, OF, DZ, IO, UO): Move to
1163 sim-main.h.
1164 (FP_FS, FP_MASK_RM, FP_SH_RM, FP_RM_NEAREST, FP_RM_TOPINF,
1165 FP_RM_TOMINF, GETRM): Move to sim-main.h.
1166 (Uncached, CachedNoncoherent, CachedCoherent, Cached,
1167 isINSTRUCTION, ..., AccessLength_BYTE, ...): Move to sim-main.h.
1168 (UserMode, BigEndianMem, ByteSwapMem, ReverseEndian,
1169 BigEndianCPU, status_KSU_mask, ...). Moved to sim-main.h
1170
1171 * sim-main.h (ALU32_END, ALU64_END): Define. When overflow raise
1172 exception.
1173 (sim-alu.h): Include.
1174 (NULLIFY_NIA, NULL_CIA, CPU_CIA): Define.
1175 (sim_cia): Typedef to instruction_address.
1176
1177Thu Oct 16 10:31:41 1997 Andrew Cagney <cagney@b1.cygnus.com>
1178
1179 * Makefile.in (interp.o): Rename generated file engine.c to
1180 oengine.c.
1181
1182 * interp.c: Update.
1183
1184Thu Oct 16 10:31:40 1997 Andrew Cagney <cagney@b1.cygnus.com>
1185
1186 * gencode.c (build_instruction): Use FPR_STATE not fpr_state.
1187
1188Thu Oct 16 10:31:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
1189
1190 * gencode.c (build_instruction): For "FPSQRT", output correct
1191 number of arguments to Recip.
1192
1193Tue Oct 14 17:38:18 1997 Andrew Cagney <cagney@b1.cygnus.com>
1194
1195 * Makefile.in (interp.o): Depends on sim-main.h
1196
1197 * interp.c (mips16_entry, ColdReset,dotrace): Add SD argument. Use GPR not registers.
1198
1199 * sim-main.h (sim_cpu): Add registers, register_widths, fpr_state,
1200 ipc, dspc, pending_*, hiaccess, loaccess, state, dsstate fields.
1201 (REGISTERS, REGISTER_WIDTHS, FPR_STATE, IPC, DSPC, PENDING_*,
1202 STATE, DSSTATE): Define
1203 (GPR, FGRIDX, ..): Define.
1204
1205 * interp.c (registers, register_widths, fpr_state, ipc, dspc,
1206 pending_*, hiaccess, loaccess, state, dsstate): Delete globals.
1207 (GPR, FGRIDX, ...): Delete macros.
1208
1209 * interp.c: Update names to match defines from sim-main.h
1210
1211Tue Oct 14 15:11:45 1997 Andrew Cagney <cagney@b1.cygnus.com>
1212
1213 * interp.c (sim_monitor): Add SD argument.
1214 (sim_warning): Delete. Replace calls with calls to
1215 sim_io_eprintf.
1216 (sim_error): Delete. Replace calls with sim_io_error.
1217 (open_trace, writeout32, writeout16, getnum): Add SD argument.
1218 (mips_set_profile): Rename from sim_set_profile. Add SD argument.
1219 (mips_set_profile_size): Rename from sim_set_profile_size. Add SD
1220 argument.
1221 (mips_size): Rename from sim_size. Add SD argument.
1222
1223 * interp.c (simulator): Delete global variable.
1224 (callback): Delete global variable.
1225 (mips_option_handler, sim_open, sim_write, sim_read,
1226 sim_store_register, sim_fetch_register, sim_info, sim_do_command,
1227 sim_size,sim_monitor): Use sim_io_* not callback->*.
1228 (sim_open): ZALLOC simulator struct.
1229 (PROFILE): Do not define.
1230
1231Tue Oct 14 13:35:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
1232
1233 * interp.c (sim_open), support.h: Replace CHECKSIM macro found in
1234 support.h with corresponding code.
1235
1236 * sim-main.h (word64, uword64), support.h: Move definition to
1237 sim-main.h.
1238 (WORD64LO, WORD64HI, SET64LO, SET64HI, WORD64, UWORD64): Ditto.
1239
1240 * support.h: Delete
1241 * Makefile.in: Update dependencies
1242 * interp.c: Do not include.
1243
1244Tue Oct 14 13:35:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
1245
1246 * interp.c (address_translation, load_memory, store_memory,
1247 cache_op): Rename to from AddressTranslation et.al., make global,
1248 add SD argument
1249
1250 * sim-main.h (AddressTranslation, LoadMemory, StoreMemory,
1251 CacheOp): Define.
1252
1253 * interp.c (SignalException): Rename to signal_exception, make
1254 global.
1255
1256 * interp.c (Interrupt, ...): Move definitions to sim-main.h.
1257
1258 * sim-main.h (SignalException, SignalExceptionInterrupt,
1259 SignalExceptionInstructionFetch, SignalExceptionAddressStore,
1260 SignalExceptionAddressLoad, SignalExceptionSimulatorFault,
1261 SignalExceptionIntegerOverflow, SignalExceptionCoProcessorUnusable):
1262 Define.
1263
1264 * interp.c, support.h: Use.
1265
1266Tue Oct 14 13:19:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1267
1268 * interp.c (ValueFPR, StoreFPR), sim-main.h: Make global, rename
1269 to value_fpr / store_fpr. Add SD argument.
1270 (NaN, Infinity, Less, Equal, AbsoluteValue, Negate, Add, Sub,
1271 Multiply, Divide, Recip, SquareRoot, Convert): Make global.
1272
1273 * sim-main.h (ValueFPR, StoreFPR): Define.
1274
1275Tue Oct 14 13:06:55 1997 Andrew Cagney <cagney@b1.cygnus.com>
1276
1277 * interp.c (sim_engine_run): Check consistency between configure
1278 WITH_TARGET_WORD_BITSIZE and WITH_FLOATING_POINT and gensim GPRLEN
1279 and HASFPU.
1280
1281 * configure.in (mips_bitsize): Configure WITH_TARGET_WORD_BITSIZE.
1282 (mips_fpu): Configure WITH_FLOATING_POINT.
1283 (mips_endian): Configure WITH_TARGET_ENDIAN.
1284 * configure: Update.
1285
1286Fri Oct 3 09:28:00 1997 Andrew Cagney <cagney@b1.cygnus.com>
1287
1288 * configure: Regenerated to track ../common/aclocal.m4 changes.
1289
1290Mon Sep 29 14:45:00 1997 Bob Manson <manson@charmed.cygnus.com>
1291
1292 * configure: Regenerated.
1293
1294Fri Sep 26 12:48:18 1997 Mark Alexander <marka@cygnus.com>
1295
1296 * interp.c: Allow Debug, DEPC, and EPC registers to be examined in GDB.
1297
1298Thu Sep 25 11:15:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
1299
1300 * gencode.c (print_igen_insn_models): Assume certain architectures
1301 include all mips* instructions.
1302 (print_igen_insn_format): Use data_size==-1 as marker for MIPS16
1303 instruction.
1304
1305 * Makefile.in (tmp.igen): Add target. Generate igen input from
1306 gencode file.
1307
1308 * gencode.c (FEATURE_IGEN): Define.
1309 (main): Add --igen option. Generate output in igen format.
1310 (process_instructions): Format output according to igen option.
1311 (print_igen_insn_format): New function.
1312 (print_igen_insn_models): New function.
1313 (process_instructions): Only issue warnings and ignore
1314 instructions when no FEATURE_IGEN.
1315
1316Wed Sep 24 17:38:57 1997 Andrew Cagney <cagney@b1.cygnus.com>
1317
1318 * interp.c (COP_SD, COP_LD): Add UNUSED to pacify GCC for some
1319 MIPS targets.
1320
1321Tue Sep 23 11:04:38 1997 Andrew Cagney <cagney@b1.cygnus.com>
1322
1323 * configure: Regenerated to track ../common/aclocal.m4 changes.
1324
1325Tue Sep 23 10:19:51 1997 Andrew Cagney <cagney@b1.cygnus.com>
1326
1327 * Makefile.in (SIM_ALIGNMENT, SIM_ENDIAN, SIM_HOSTENDIAN,
1328 SIM_RESERVED_BITS): Delete, moved to common.
1329 (SIM_EXTRA_CFLAGS): Update.
1330
1331Mon Sep 22 11:46:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1332
1333 * configure.in: Configure non-strict memory alignment.
1334 * configure: Regenerated to track ../common/aclocal.m4 changes.
1335
1336Fri Sep 19 17:45:25 1997 Andrew Cagney <cagney@b1.cygnus.com>
1337
1338 * configure: Regenerated to track ../common/aclocal.m4 changes.
1339
1340Sat Sep 20 14:07:28 1997 Gavin Koch <gavin@cygnus.com>
1341
1342 * gencode.c (SDBBP,DERET): Added (3900) insns.
1343 (RFE): Turn on for 3900.
1344 * interp.c (DebugBreakPoint,DEPC,Debug,Debug_*): Added.
1345 (dsstate): Made global.
1346 (SUBTARGET_R3900): Added.
1347 (CANCELDELAYSLOT): New.
1348 (SignalException): Ignore SystemCall rather than ignore and
1349 terminate. Add DebugBreakPoint handling.
1350 (decode_coproc): New insns RFE, DERET; and new registers Debug
1351 and DEPC protected by SUBTARGET_R3900.
1352 (sim_engine_run): Use CANCELDELAYSLOT rather than clearing
1353 bits explicitly.
1354 * Makefile.in,configure.in: Add mips subtarget option.
1355 * configure: Update.
1356
1357Fri Sep 19 09:33:27 1997 Gavin Koch <gavin@cygnus.com>
1358
1359 * gencode.c: Add r3900 (tx39).
1360
1361
1362Tue Sep 16 15:52:04 1997 Gavin Koch <gavin@cygnus.com>
1363
1364 * gencode.c (build_instruction): Don't need to subtract 4 for
1365 JALR, just 2.
1366
1367Tue Sep 16 11:32:28 1997 Gavin Koch <gavin@cygnus.com>
1368
1369 * interp.c: Correct some HASFPU problems.
1370
1371Mon Sep 15 17:36:15 1997 Andrew Cagney <cagney@b1.cygnus.com>
1372
1373 * configure: Regenerated to track ../common/aclocal.m4 changes.
1374
1375Fri Sep 12 12:01:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
1376
1377 * interp.c (mips_options): Fix samples option short form, should
1378 be `x'.
1379
1380Thu Sep 11 09:35:29 1997 Andrew Cagney <cagney@b1.cygnus.com>
1381
1382 * interp.c (sim_info): Enable info code. Was just returning.
1383
1384Tue Sep 9 17:30:57 1997 Andrew Cagney <cagney@b1.cygnus.com>
1385
1386 * interp.c (decode_coproc): Clarify warning about unsuported MTC0,
1387 MFC0.
1388
1389Tue Sep 9 16:28:28 1997 Andrew Cagney <cagney@b1.cygnus.com>
1390
1391 * gencode.c (build_instruction): Use SIGNED64 for 64 bit
1392 constants.
1393 (build_instruction): Ditto for LL.
1394
1395Thu Sep 4 17:21:23 1997 Doug Evans <dje@seba>
1396
1397 * configure: Regenerated to track ../common/aclocal.m4 changes.
1398
1399Wed Aug 27 18:13:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
1400
1401 * configure: Regenerated to track ../common/aclocal.m4 changes.
1402 * config.in: Ditto.
1403
1404Wed Aug 27 14:12:27 1997 Andrew Cagney <cagney@b1.cygnus.com>
1405
1406 * interp.c (sim_open): Add call to sim_analyze_program, update
1407 call to sim_config.
1408
1409Tue Aug 26 10:40:07 1997 Andrew Cagney <cagney@b1.cygnus.com>
1410
1411 * interp.c (sim_kill): Delete.
1412 (sim_create_inferior): Add ABFD argument. Set PC from same.
1413 (sim_load): Move code initializing trap handlers from here.
1414 (sim_open): To here.
1415 (sim_load): Delete, use sim-hload.c.
1416
1417 * Makefile.in (SIM_OBJS): Add sim-hload.o module.
1418
1419Mon Aug 25 17:50:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
1420
1421 * configure: Regenerated to track ../common/aclocal.m4 changes.
1422 * config.in: Ditto.
1423
1424Mon Aug 25 15:59:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
1425
1426 * interp.c (sim_open): Add ABFD argument.
1427 (sim_load): Move call to sim_config from here.
1428 (sim_open): To here. Check return status.
1429
1430Fri Jul 25 15:00:45 1997 Gavin Koch <gavin@cygnus.com>
1431
1432 * gencode.c (build_instruction): Two arg MADD should
1433 not assign result to $0.
1434
1435Thu Jun 26 12:13:17 1997 Angela Marie Thomas (angela@cygnus.com)
1436
1437 * sim/mips/configure: Change default_sim_endian to 0 (bi-endian)
1438 * sim/mips/configure.in: Regenerate.
1439
1440Wed Jul 9 10:29:21 1997 Andrew Cagney <cagney@critters.cygnus.com>
1441
1442 * interp.c (SUB_REG_UW, SUB_REG_SW, SUB_REG_*): Use more explicit
1443 signed8, unsigned8 et.al. types.
1444
1445 * interp.c (SUB_REG_FETCH): Handle both little and big endian
1446 hosts when selecting subreg.
1447
1448Wed Jul 2 11:54:10 1997 Jeffrey A Law (law@cygnus.com)
1449
1450 * interp.c (sim_engine_run): Reset the ZERO register to zero
1451 regardless of FEATURE_WARN_ZERO.
1452 * gencode.c (FEATURE_WARNINGS): Remove FEATURE_WARN_ZERO.
1453
1454Wed Jun 4 10:43:14 1997 Andrew Cagney <cagney@b1.cygnus.com>
1455
1456 * interp.c (decode_coproc): Implement MTC0 N, CAUSE.
1457 (SignalException): For BreakPoints ignore any mode bits and just
1458 save the PC.
1459 (SignalException): Always set the CAUSE register.
1460
1461Tue Jun 3 05:00:33 1997 Andrew Cagney <cagney@b1.cygnus.com>
1462
1463 * interp.c (SignalException): Clear the simDELAYSLOT flag when an
1464 exception has been taken.
1465
1466 * interp.c: Implement the ERET and mt/f sr instructions.
1467
1468Sat May 31 00:44:16 1997 Andrew Cagney <cagney@b1.cygnus.com>
1469
1470 * interp.c (SignalException): Don't bother restarting an
1471 interrupt.
1472
1473Fri May 30 23:41:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
1474
1475 * interp.c (SignalException): Really take an interrupt.
1476 (interrupt_event): Only deliver interrupts when enabled.
1477
1478Tue May 27 20:08:06 1997 Andrew Cagney <cagney@b1.cygnus.com>
1479
1480 * interp.c (sim_info): Only print info when verbose.
1481 (sim_info) Use sim_io_printf for output.
1482
1483Tue May 27 14:22:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
1484
1485 * interp.c (CoProcPresent): Add UNUSED attribute - not used by all
1486 mips architectures.
1487
1488Tue May 27 14:22:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
1489
1490 * interp.c (sim_do_command): Check for common commands if a
1491 simulator specific command fails.
1492
1493Thu May 22 09:32:03 1997 Gavin Koch <gavin@cygnus.com>
1494
1495 * interp.c (sim_engine_run): ifdef out uses of simSTOP, simSTEP
1496 and simBE when DEBUG is defined.
1497
1498Wed May 21 09:08:10 1997 Andrew Cagney <cagney@b1.cygnus.com>
1499
1500 * interp.c (interrupt_event): New function. Pass exception event
1501 onto exception handler.
1502
1503 * configure.in: Check for stdlib.h.
1504 * configure: Regenerate.
1505
1506 * gencode.c (build_instruction): Add UNUSED attribute to tempS
1507 variable declaration.
1508 (build_instruction): Initialize memval1.
1509 (build_instruction): Add UNUSED attribute to byte, bigend,
1510 reverse.
1511 (build_operands): Ditto.
1512
1513 * interp.c: Fix GCC warnings.
1514 (sim_get_quit_code): Delete.
1515
1516 * configure.in: Add INLINE, ENDIAN, HOSTENDIAN and WARNINGS.
1517 * Makefile.in: Ditto.
1518 * configure: Re-generate.
1519
1520 * Makefile.in (SIM_OBJS): Add sim-watch.o module.
1521
1522Tue May 20 15:08:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
1523
1524 * interp.c (mips_option_handler): New function parse argumes using
1525 sim-options.
1526 (myname): Replace with STATE_MY_NAME.
1527 (sim_open): Delete check for host endianness - performed by
1528 sim_config.
1529 (simHOSTBE, simBE): Delete, replaced by sim-endian flags.
1530 (sim_open): Move much of the initialization from here.
1531 (sim_load): To here. After the image has been loaded and
1532 endianness set.
1533 (sim_open): Move ColdReset from here.
1534 (sim_create_inferior): To here.
1535 (sim_open): Make FP check less dependant on host endianness.
1536
1537 * Makefile.in (SIM_RUN_OBJS): Set to nrun.o - use new version or
1538 run.
1539 * interp.c (sim_set_callbacks): Delete.
1540
1541 * interp.c (membank, membank_base, membank_size): Replace with
1542 STATE_MEMORY, STATE_MEM_SIZE, STATE_MEM_BASE.
1543 (sim_open): Remove call to callback->init. gdb/run do this.
1544
1545 * interp.c: Update
1546
1547 * sim-main.h (SIM_HAVE_FLATMEM): Define.
1548
1549 * interp.c (big_endian_p): Delete, replaced by
1550 current_target_byte_order.
1551
1552Tue May 20 13:55:00 1997 Andrew Cagney <cagney@b1.cygnus.com>
1553
1554 * interp.c (host_read_long, host_read_word, host_swap_word,
1555 host_swap_long): Delete. Using common sim-endian.
1556 (sim_fetch_register, sim_store_register): Use H2T.
1557 (pipeline_ticks): Delete. Handled by sim-events.
1558 (sim_info): Update.
1559 (sim_engine_run): Update.
1560
1561Tue May 20 13:42:03 1997 Andrew Cagney <cagney@b1.cygnus.com>
1562
1563 * interp.c (sim_stop_reason): Move code determining simEXCEPTION
1564 reason from here.
1565 (SignalException): To here. Signal using sim_engine_halt.
1566 (sim_stop_reason): Delete, moved to common.
1567
1568Tue May 20 10:19:48 1997 Andrew Cagney <cagney@b2.cygnus.com>
1569
1570 * interp.c (sim_open): Add callback argument.
1571 (sim_set_callbacks): Delete SIM_DESC argument.
1572 (sim_size): Ditto.
1573
1574Mon May 19 18:20:38 1997 Andrew Cagney <cagney@b1.cygnus.com>
1575
1576 * Makefile.in (SIM_OBJS): Add common modules.
1577
1578 * interp.c (sim_set_callbacks): Also set SD callback.
1579 (set_endianness, xfer_*, swap_*): Delete.
1580 (host_read_word, host_read_long, host_swap_word, host_swap_long):
1581 Change to functions using sim-endian macros.
1582 (control_c, sim_stop): Delete, use common version.
1583 (simulate): Convert into.
1584 (sim_engine_run): This function.
1585 (sim_resume): Delete.
1586
1587 * interp.c (simulation): New variable - the simulator object.
1588 (sim_kind): Delete global - merged into simulation.
1589 (sim_load): Cleanup. Move PC assignment from here.
1590 (sim_create_inferior): To here.
1591
1592 * sim-main.h: New file.
1593 * interp.c (sim-main.h): Include.
1594
1595Thu Apr 24 00:39:51 1997 Doug Evans <dje@canuck.cygnus.com>
1596
1597 * configure: Regenerated to track ../common/aclocal.m4 changes.
1598
1599Wed Apr 23 17:32:19 1997 Doug Evans <dje@canuck.cygnus.com>
1600
1601 * tconfig.in (SIM_HAVE_BIENDIAN): Define.
1602
1603Mon Apr 21 17:16:13 1997 Gavin Koch <gavin@cygnus.com>
1604
1605 * gencode.c (build_instruction): DIV instructions: check
1606 for division by zero and integer overflow before using
1607 host's division operation.
1608
1609Thu Apr 17 03:18:14 1997 Doug Evans <dje@canuck.cygnus.com>
1610
1611 * Makefile.in (SIM_OBJS): Add sim-load.o.
1612 * interp.c: #include bfd.h.
1613 (target_byte_order): Delete.
1614 (sim_kind, myname, big_endian_p): New static locals.
1615 (sim_open): Set sim_kind, myname. Move call to set_endianness to
1616 after argument parsing. Recognize -E arg, set endianness accordingly.
1617 (sim_load): Return SIM_RC. New arg abfd. Call sim_load_file to
1618 load file into simulator. Set PC from bfd.
1619 (sim_create_inferior): Return SIM_RC. Delete arg start_address.
1620 (set_endianness): Use big_endian_p instead of target_byte_order.
1621
1622Wed Apr 16 17:55:37 1997 Andrew Cagney <cagney@b1.cygnus.com>
1623
1624 * interp.c (sim_size): Delete prototype - conflicts with
1625 definition in remote-sim.h. Correct definition.
1626
1627Mon Apr 7 15:45:02 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
1628
1629 * configure: Regenerated to track ../common/aclocal.m4 changes.
1630 * config.in: Ditto.
1631
1632Wed Apr 2 15:06:28 1997 Doug Evans <dje@canuck.cygnus.com>
1633
1634 * interp.c (sim_open): New arg `kind'.
1635
1636 * configure: Regenerated to track ../common/aclocal.m4 changes.
1637
1638Wed Apr 2 14:34:19 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
1639
1640 * configure: Regenerated to track ../common/aclocal.m4 changes.
1641
1642Tue Mar 25 11:38:22 1997 Doug Evans <dje@canuck.cygnus.com>
1643
1644 * interp.c (sim_open): Set optind to 0 before calling getopt.
1645
1646Wed Mar 19 01:14:00 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
1647
1648 * configure: Regenerated to track ../common/aclocal.m4 changes.
1649
1650Mon Mar 17 10:52:59 1997 Gavin Koch <gavin@cetus.cygnus.com>
1651
1652 * interp.c : Replace uses of pr_addr with pr_uword64
1653 where the bit length is always 64 independent of SIM_ADDR.
1654 (pr_uword64) : added.
1655
1656Mon Mar 17 15:10:07 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
1657
1658 * configure: Re-generate.
1659
1660Fri Mar 14 10:34:11 1997 Michael Meissner <meissner@cygnus.com>
1661
1662 * configure: Regenerate to track ../common/aclocal.m4 changes.
1663
1664Thu Mar 13 12:51:36 1997 Doug Evans <dje@canuck.cygnus.com>
1665
1666 * interp.c (sim_open): New SIM_DESC result. Argument is now
1667 in argv form.
1668 (other sim_*): New SIM_DESC argument.
1669
1670Mon Feb 24 22:47:14 1997 Dawn Perchik <dawn@cygnus.com>
1671
1672 * interp.c: Fix printing of addresses for non-64-bit targets.
1673 (pr_addr): Add function to print address based on size.
1674
1675Wed Feb 19 14:42:09 1997 Mark Alexander <marka@cygnus.com>
1676
1677 * interp.c (simopen): Add support for LSI MiniRISC PMON vectors.
1678
1679Thu Feb 13 14:08:30 1997 Ian Lance Taylor <ian@cygnus.com>
1680
1681 * gencode.c (build_mips16_operands): Correct computation of base
1682 address for extended PC relative instruction.
1683
1684Thu Feb 6 17:16:15 1997 Ian Lance Taylor <ian@cygnus.com>
1685
1686 * interp.c (mips16_entry): Add support for floating point cases.
1687 (SignalException): Pass floating point cases to mips16_entry.
1688 (ValueFPR): Don't restrict fmt_single and fmt_word to even
1689 registers.
1690 (StoreFPR): Likewise. Also, don't clobber fpr + 1 for fmt_single
1691 or fmt_word.
1692 (COP_LW): Pass fmt_word rather than fmt_uninterpreted to StoreFPR,
1693 and then set the state to fmt_uninterpreted.
1694 (COP_SW): Temporarily set the state to fmt_word while calling
1695 ValueFPR.
1696
1697Tue Feb 4 16:48:25 1997 Ian Lance Taylor <ian@cygnus.com>
1698
1699 * gencode.c (build_instruction): The high order may be set in the
1700 comparison flags at any ISA level, not just ISA 4.
1701
1702Tue Feb 4 13:33:30 1997 Doug Evans <dje@canuck.cygnus.com>
1703
1704 * Makefile.in (@COMMON_MAKEFILE_FRAG): Use
1705 COMMON_{PRE,POST}_CONFIG_FRAG instead.
1706 * configure.in: sinclude ../common/aclocal.m4.
1707 * configure: Regenerated.
1708
1709Fri Jan 31 11:11:45 1997 Ian Lance Taylor <ian@cygnus.com>
1710
1711 * configure: Rebuild after change to aclocal.m4.
1712
1713Thu Jan 23 11:46:23 1997 Stu Grossman (grossman@critters.cygnus.com)
1714
1715 * configure configure.in Makefile.in: Update to new configure
1716 scheme which is more compatible with WinGDB builds.
1717 * configure.in: Improve comment on how to run autoconf.
1718 * configure: Re-run autoconf to get new ../common/aclocal.m4.
1719 * Makefile.in: Use autoconf substitution to install common
1720 makefile fragment.
1721
1722Wed Jan 8 12:39:03 1997 Jim Wilson <wilson@cygnus.com>
1723
1724 * gencode.c (build_instruction): Use BigEndianCPU instead of
1725 ByteSwapMem.
1726
1727Thu Jan 02 22:23:04 1997 Mark Alexander <marka@cygnus.com>
1728
1729 * interp.c (sim_monitor): Make output to stdout visible in
1730 wingdb's I/O log window.
1731
1732Tue Dec 31 07:04:00 1996 Mark Alexander <marka@cygnus.com>
1733
1734 * support.h: Undo previous change to SIGTRAP
1735 and SIGQUIT values.
1736
1737Mon Dec 30 17:36:06 1996 Ian Lance Taylor <ian@cygnus.com>
1738
1739 * interp.c (store_word, load_word): New static functions.
1740 (mips16_entry): New static function.
1741 (SignalException): Look for mips16 entry and exit instructions.
1742 (simulate): Use the correct index when setting fpr_state after
1743 doing a pending move.
1744
1745Sun Dec 29 09:37:18 1996 Mark Alexander <marka@cygnus.com>
1746
1747 * interp.c: Fix byte-swapping code throughout to work on
1748 both little- and big-endian hosts.
1749
1750Sun Dec 29 09:18:32 1996 Mark Alexander <marka@cygnus.com>
1751
1752 * support.h: Make definitions of SIGTRAP and SIGQUIT consistent
1753 with gdb/config/i386/xm-windows.h.
1754
1755Fri Dec 27 22:48:51 1996 Mark Alexander <marka@cygnus.com>
1756
1757 * gencode.c (build_instruction): Work around MSVC++ code gen bug
1758 that messes up arithmetic shifts.
1759
1760Fri Dec 20 11:04:05 1996 Stu Grossman (grossman@critters.cygnus.com)
1761
1762 * support.h: Use _WIN32 instead of __WIN32__. Also add defs for
1763 SIGTRAP and SIGQUIT for _WIN32.
1764
1765Thu Dec 19 14:07:27 1996 Ian Lance Taylor <ian@cygnus.com>
1766
1767 * gencode.c (build_instruction) [MUL]: Cast operands to word64, to
1768 force a 64 bit multiplication.
1769 (build_instruction) [OR]: In mips16 mode, don't do anything if the
1770 destination register is 0, since that is the default mips16 nop
1771 instruction.
1772
1773Mon Dec 16 14:59:38 1996 Ian Lance Taylor <ian@cygnus.com>
1774
1775 * gencode.c (MIPS16_DECODE): SWRASP is I8, not RI.
1776 (build_endian_shift): Don't check proc64.
1777 (build_instruction): Always set memval to uword64. Cast op2 to
1778 uword64 when shifting it left in memory instructions. Always use
1779 the same code for stores--don't special case proc64.
1780
1781 * gencode.c (build_mips16_operands): Fix base PC value for PC
1782 relative operands.
1783 (build_instruction): Call JALDELAYSLOT rather than DELAYSLOT for a
1784 jal instruction.
1785 * interp.c (simJALDELAYSLOT): Define.
1786 (JALDELAYSLOT): Define.
1787 (INDELAYSLOT, INJALDELAYSLOT): Define.
1788 (simulate): Clear simJALDELAYSLOT when simDELAYSLOT is cleared.
1789
1790Tue Dec 24 22:11:20 1996 Angela Marie Thomas (angela@cygnus.com)
1791
1792 * interp.c (sim_open): add flush_cache as a PMON routine
1793 (sim_monitor): handle flush_cache by ignoring it
1794
1795Wed Dec 11 13:53:51 1996 Jim Wilson <wilson@cygnus.com>
1796
1797 * gencode.c (build_instruction): Use !ByteSwapMem instead of
1798 BigEndianMem.
1799 * interp.c (CONFIG, config_EP_{mask,shift,D,DxxDxx, config_BE): Delete.
1800 (BigEndianMem): Rename to ByteSwapMem and change sense.
1801 (BigEndianCPU, sim_write, LoadMemory, StoreMemory): Change
1802 BigEndianMem references to !ByteSwapMem.
1803 (set_endianness): New function, with prototype.
1804 (sim_open): Call set_endianness.
1805 (sim_info): Use simBE instead of BigEndianMem.
1806 (xfer_direct_word, xfer_direct_long, swap_direct_word,
1807 swap_direct_long, xfer_big_word, xfer_big_long, xfer_little_word,
1808 xfer_little_long, swap_word, swap_long): Delete unnecessary MSC_VER
1809 ifdefs, keeping the prototype declaration.
1810 (swap_word): Rewrite correctly.
1811 (ColdReset): Delete references to CONFIG. Delete endianness related
1812 code; moved to set_endianness.
1813
1814Tue Dec 10 11:32:04 1996 Jim Wilson <wilson@cygnus.com>
1815
1816 * gencode.c (build_instruction, case JUMP): Truncate PC to 32 bits.
1817 * interp.c (CHECKHILO): Define away.
1818 (simSIGINT): New macro.
1819 (membank_size): Increase from 1MB to 2MB.
1820 (control_c): New function.
1821 (sim_resume): Rename parameter signal to signal_number. Add local
1822 variable prev. Call signal before and after simulate.
1823 (sim_stop_reason): Add simSIGINT support.
1824 (sim_warning, sim_error, dotrace, SignalException): Define as stdarg
1825 functions always.
1826 (sim_warning): Delete call to SignalException. Do call printf_filtered
1827 if logfh is NULL.
1828 (AddressTranslation): Add #ifdef DEBUG around debugging message and
1829 a call to sim_warning.
1830
1831Wed Nov 27 11:53:50 1996 Ian Lance Taylor <ian@cygnus.com>
1832
1833 * gencode.c (process_instructions): If ! proc64, skip DOUBLEWORD
1834 16 bit instructions.
1835
1836Tue Nov 26 11:53:12 1996 Ian Lance Taylor <ian@cygnus.com>
1837
1838 Add support for mips16 (16 bit MIPS implementation):
1839 * gencode.c (inst_type): Add mips16 instruction encoding types.
1840 (GETDATASIZEINSN): Define.
1841 (MIPS_DECODE): Add REG flag to dsllv, dsrav, and dsrlv. Add
1842 jalx. Add LEFT flag to mfhi and mflo. Add RIGHT flag to mthi and
1843 mtlo.
1844 (MIPS16_DECODE): New table, for mips16 instructions.
1845 (bitmap_val): New static function.
1846 (struct mips16_op): Define.
1847 (mips16_op_table): New table, for mips16 operands.
1848 (build_mips16_operands): New static function.
1849 (process_instructions): If PC is odd, decode a mips16
1850 instruction. Break out instruction handling into new
1851 build_instruction function.
1852 (build_instruction): New static function, broken out of
1853 process_instructions. Check modifiers rather than flags for SHIFT
1854 bit count and m[ft]{hi,lo} direction.
1855 (usage): Pass program name to fprintf.
1856 (main): Remove unused variable this_option_optind. Change
1857 ``*loptarg++'' to ``loptarg++''.
1858 (my_strtoul): Parenthesize && within ||.
1859 * interp.c (LoadMemory): Accept a halfword pAddr if vAddr is odd.
1860 (simulate): If PC is odd, fetch a 16 bit instruction, and
1861 increment PC by 2 rather than 4.
1862 * configure.in: Add case for mips16*-*-*.
1863 * configure: Rebuild.
1864
1865Fri Nov 22 08:49:36 1996 Mark Alexander <marka@cygnus.com>
1866
1867 * interp.c: Allow -t to enable tracing in standalone simulator.
1868 Fix garbage output in trace file and error messages.
1869
1870Wed Nov 20 01:54:37 1996 Doug Evans <dje@canuck.cygnus.com>
1871
1872 * Makefile.in: Delete stuff moved to ../common/Make-common.in.
1873 (SIM_{OBJS,EXTRA_CFLAGS,EXTRA_CLEAN}): Define.
1874 * configure.in: Simplify using macros in ../common/aclocal.m4.
1875 * configure: Regenerated.
1876 * tconfig.in: New file.
1877
1878Tue Nov 12 13:34:00 1996 Dawn Perchik <dawn@cygnus.com>
1879
1880 * interp.c: Fix bugs in 64-bit port.
1881 Use ansi function declarations for msvc compiler.
1882 Initialize and test file pointer in trace code.
1883 Prevent duplicate definition of LAST_EMED_REGNUM.
1884
1885Tue Oct 15 11:07:06 1996 Mark Alexander <marka@cygnus.com>
1886
1887 * interp.c (xfer_big_long): Prevent unwanted sign extension.
1888
1889Thu Sep 26 17:35:00 1996 James G. Smith <jsmith@cygnus.co.uk>
1890
1891 * interp.c (SignalException): Check for explicit terminating
1892 breakpoint value.
1893 * gencode.c: Pass instruction value through SignalException()
1894 calls for Trap, Breakpoint and Syscall.
1895
1896Thu Sep 26 11:35:17 1996 James G. Smith <jsmith@cygnus.co.uk>
1897
1898 * interp.c (SquareRoot): Add HAVE_SQRT check to ensure sqrt() is
1899 only used on those hosts that provide it.
1900 * configure.in: Add sqrt() to list of functions to be checked for.
1901 * config.in: Re-generated.
1902 * configure: Re-generated.
1903
1904Fri Sep 20 15:47:12 1996 Ian Lance Taylor <ian@cygnus.com>
1905
1906 * gencode.c (process_instructions): Call build_endian_shift when
1907 expanding STORE RIGHT, to fix swr.
1908 * support.h (SIGNEXTEND): If the sign bit is not set, explicitly
1909 clear the high bits.
1910 * interp.c (Convert): Fix fmt_single to fmt_long to not truncate.
1911 Fix float to int conversions to produce signed values.
1912
1913Thu Sep 19 15:34:17 1996 Ian Lance Taylor <ian@cygnus.com>
1914
1915 * gencode.c (MIPS_DECODE): Set UNSIGNED for multu instruction.
1916 (process_instructions): Correct handling of nor instruction.
1917 Correct shift count for 32 bit shift instructions. Correct sign
1918 extension for arithmetic shifts to not shift the number of bits in
1919 the type. Fix 64 bit multiply high word calculation. Fix 32 bit
1920 unsigned multiply. Fix ldxc1 and friends to use coprocessor 1.
1921 Fix madd.
1922 * interp.c (CHECKHILO): Don't set HIACCESS, LOACCESS, or HLPC.
1923 It's OK to have a mult follow a mult. What's not OK is to have a
1924 mult follow an mfhi.
1925 (Convert): Comment out incorrect rounding code.
1926
1927Mon Sep 16 11:38:16 1996 James G. Smith <jsmith@cygnus.co.uk>
1928
1929 * interp.c (sim_monitor): Improved monitor printf
1930 simulation. Tidied up simulator warnings, and added "--log" option
1931 for directing warning message output.
1932 * gencode.c: Use sim_warning() rather than WARNING macro.
1933
1934Thu Aug 22 15:03:12 1996 Ian Lance Taylor <ian@cygnus.com>
1935
1936 * Makefile.in (gencode): Depend upon gencode.o, getopt.o, and
1937 getopt1.o, rather than on gencode.c. Link objects together.
1938 Don't link against -liberty.
1939 (gencode.o, getopt.o, getopt1.o): New targets.
1940 * gencode.c: Include <ctype.h> and "ansidecl.h".
1941 (AND): Undefine after including "ansidecl.h".
1942 (ULONG_MAX): Define if not defined.
1943 (OP_*): Don't define macros; now defined in opcode/mips.h.
1944 (main): Call my_strtoul rather than strtoul.
1945 (my_strtoul): New static function.
1946
1947Wed Jul 17 18:12:38 1996 Stu Grossman (grossman@critters.cygnus.com)
1948
1949 * gencode.c (process_instructions): Generate word64 and uword64
1950 instead of `long long' and `unsigned long long' data types.
1951 * interp.c: #include sysdep.h to get signals, and define default
1952 for SIGBUS.
1953 * (Convert): Work around for Visual-C++ compiler bug with type
1954 conversion.
1955 * support.h: Make things compile under Visual-C++ by using
1956 __int64 instead of `long long'. Change many refs to long long
1957 into word64/uword64 typedefs.
1958
1959Wed Jun 26 12:24:55 1996 Jason Molenda (crash@godzilla.cygnus.co.jp)
1960
1961 * Makefile.in (bindir, libdir, datadir, mandir, infodir, includedir,
1962 INSTALL_PROGRAM, INSTALL_DATA): Use autoconf-set values.
1963 (docdir): Removed.
1964 * configure.in (AC_PREREQ): autoconf 2.5 or higher.
1965 (AC_PROG_INSTALL): Added.
1966 (AC_PROG_CC): Moved to before configure.host call.
1967 * configure: Rebuilt.
1968
1969Wed Jun 5 08:28:13 1996 James G. Smith <jsmith@cygnus.co.uk>
1970
1971 * configure.in: Define @SIMCONF@ depending on mips target.
1972 * configure: Rebuild.
1973 * Makefile.in (run): Add @SIMCONF@ to control simulator
1974 construction.
1975 * gencode.c: Change LOADDRMASK to 64bit memory model only.
1976 * interp.c: Remove some debugging, provide more detailed error
1977 messages, update memory accesses to use LOADDRMASK.
1978
1979Mon Jun 3 11:55:03 1996 Ian Lance Taylor <ian@cygnus.com>
1980
1981 * configure.in: Add calls to AC_CONFIG_HEADER, AC_CHECK_HEADERS,
1982 AC_CHECK_LIB, and AC_CHECK_FUNCS. Change AC_OUTPUT to set
1983 stamp-h.
1984 * configure: Rebuild.
1985 * config.in: New file, generated by autoheader.
1986 * interp.c: Include "config.h". Include <stdlib.h>, <string.h>,
1987 and <strings.h> if they exist. Replace #ifdef sun with #ifdef
1988 HAVE_ANINT and HAVE_AINT, as appropriate.
1989 * Makefile.in (run): Use @LIBS@ rather than -lm.
1990 (interp.o): Depend upon config.h.
1991 (Makefile): Just rebuild Makefile.
1992 (clean): Remove stamp-h.
1993 (mostlyclean): Make the same as clean, not as distclean.
1994 (config.h, stamp-h): New targets.
1995
1996Fri May 10 00:41:17 1996 James G. Smith <jsmith@cygnus.co.uk>
1997
1998 * interp.c (ColdReset): Fix boolean test. Make all simulator
1999 globals static.
2000
2001Wed May 8 15:12:58 1996 James G. Smith <jsmith@cygnus.co.uk>
2002
2003 * interp.c (xfer_direct_word, xfer_direct_long,
2004 swap_direct_word, swap_direct_long, xfer_big_word,
2005 xfer_big_long, xfer_little_word, xfer_little_long,
2006 swap_word,swap_long): Added.
2007 * interp.c (ColdReset): Provide function indirection to
2008 host<->simulated_target transfer routines.
2009 * interp.c (sim_store_register, sim_fetch_register): Updated to
2010 make use of indirected transfer routines.
2011
2012Fri Apr 19 15:48:24 1996 James G. Smith <jsmith@cygnus.co.uk>
2013
2014 * gencode.c (process_instructions): Ensure FP ABS instruction
2015 recognised.
2016 * interp.c (AbsoluteValue): Add routine. Also provide simple PMON
2017 system call support.
2018
2019Wed Apr 10 09:51:38 1996 James G. Smith <jsmith@cygnus.co.uk>
2020
2021 * interp.c (sim_do_command): Complain if callback structure not
2022 initialised.
2023
2024Thu Mar 28 13:50:51 1996 James G. Smith <jsmith@cygnus.co.uk>
2025
2026 * interp.c (Convert): Provide round-to-nearest and round-to-zero
2027 support for Sun hosts.
2028 * Makefile.in (gencode): Ensure the host compiler and libraries
2029 used for cross-hosted build.
2030
2031Wed Mar 27 14:42:12 1996 James G. Smith <jsmith@cygnus.co.uk>
2032
2033 * interp.c, gencode.c: Some more (TODO) tidying.
2034
2035Thu Mar 7 11:19:33 1996 James G. Smith <jsmith@cygnus.co.uk>
2036
2037 * gencode.c, interp.c: Replaced explicit long long references with
2038 WORD64HI, WORD64LO, SET64HI and SET64LO macro calls.
2039 * support.h (SET64LO, SET64HI): Macros added.
2040
2041Wed Feb 21 12:16:21 1996 Ian Lance Taylor <ian@cygnus.com>
2042
2043 * configure: Regenerate with autoconf 2.7.
2044
2045Tue Jan 30 08:48:18 1996 Fred Fish <fnf@cygnus.com>
2046
2047 * interp.c (LoadMemory): Enclose text following #endif in /* */.
2048 * support.h: Remove superfluous "1" from #if.
2049 * support.h (CHECKSIM): Remove stray 'a' at end of line.
2050
2051Mon Dec 4 11:44:40 1995 Jamie Smith <jsmith@cygnus.com>
2052
2053 * interp.c (StoreFPR): Control UndefinedResult() call on
2054 WARN_RESULT manifest.
2055
2056Fri Dec 1 16:37:19 1995 James G. Smith <jsmith@cygnus.co.uk>
2057
2058 * gencode.c: Tidied instruction decoding, and added FP instruction
2059 support.
2060
2061 * interp.c: Added dineroIII, and BSD profiling support. Also
2062 run-time FP handling.
2063
2064Sun Oct 22 00:57:18 1995 James G. Smith <jsmith@pasanda.cygnus.co.uk>
2065
2066 * Changelog, Makefile.in, README.Cygnus, configure, configure.in,
2067 gencode.c, interp.c, support.h: created.
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