projects / thirdparty / binutils-gdb.git / blame
| Commit | Line | Data |
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| cfe9ea23 CD |
1 | /*> cp1.h <*/ |
| 2 | /* MIPS Simulator FPU (CoProcessor 1) definitions. | |
| 6aba47ca | 3 | Copyright (C) 1997, 1998, 2002, 2007 Free Software Foundation, Inc. |
| cfe9ea23 | 4 | Derived from sim-main.h contributed by Cygnus Solutions, |
| dd69d292 CD |
5 | modified substantially by Ed Satterthwaite of Broadcom Corporation |
| 6 | (SiByte). | |
| cfe9ea23 CD |
7 | |
| 8 | This file is part of GDB, the GNU debugger. | |
| 9 | ||
| 10 | This program is free software; you can redistribute it and/or modify | |
| 11 | it under the terms of the GNU General Public License as published by | |
| 12 | the Free Software Foundation; either version 2, or (at your option) | |
| 13 | any later version. | |
| 14 | ||
| 15 | This program is distributed in the hope that it will be useful, | |
| 16 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
| 17 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
| 18 | GNU General Public License for more details. | |
| 19 | ||
| 20 | You should have received a copy of the GNU General Public License along | |
| 21 | with this program; if not, write to the Free Software Foundation, Inc., | |
| 22 | 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ | |
| 23 | ||
| 24 | #ifndef CP1_H | |
| 25 | #define CP1_H | |
| 26 | ||
| 27 | /* See sim-main.h for allocation of registers FCR0 and FCR31 (FCSR) | |
| 28 | in CPU state (struct sim_cpu), and for FPU functions. */ | |
| 29 | ||
| 30 | #define fcsr_FCC_mask (0xFE800000) | |
| 31 | #define fcsr_FCC_shift (23) | |
| 32 | #define fcsr_FCC_bit(cc) ((cc) == 0 ? 23 : (24 + (cc))) | |
| 33 | #define fcsr_FS (1 << 24) /* MIPS III onwards : Flush to Zero */ | |
| 34 | #define fcsr_ZERO_mask (0x007C0000) | |
| 35 | #define fcsr_CAUSE_mask (0x0003F000) | |
| 36 | #define fcsr_CAUSE_shift (12) | |
| 37 | #define fcsr_ENABLES_mask (0x00000F80) | |
| 38 | #define fcsr_ENABLES_shift (7) | |
| 39 | #define fcsr_FLAGS_mask (0x0000007C) | |
| 40 | #define fcsr_FLAGS_shift (2) | |
| 41 | #define fcsr_RM_mask (0x00000003) | |
| 42 | #define fcsr_RM_shift (0) | |
| 43 | ||
| 52714ff9 | 44 | #define fenr_FS (0x00000004) |
| cfe9ea23 CD |
45 | |
| 46 | /* Macros to update and retrieve the FCSR condition-code bits. This | |
| 47 | is complicated by the fact that there is a hole in the index range | |
| 48 | of the bits within the FCSR register. (Note that the number of bits | |
| 49 | visible depends on the ISA in use, but that is handled elsewhere.) */ | |
| 50 | #define SETFCC(cc,v) \ | |
| 51 | do { \ | |
| 52 | (FCSR = ((FCSR & ~(1 << fcsr_FCC_bit(cc))) | ((v) << fcsr_FCC_bit(cc)))); \ | |
| 53 | } while (0) | |
| 54 | #define GETFCC(cc) ((FCSR & (1 << fcsr_FCC_bit(cc))) != 0 ? 1 : 0) | |
| 55 | ||
| 56 | ||
| 57 | /* Read flush-to-zero bit (not right-justified). */ | |
| 58 | #define GETFS() ((int)(FCSR & fcsr_FS)) | |
| 59 | ||
| 60 | ||
| 61 | /* FCSR flag bits definitions and access macros. */ | |
| 62 | #define IR 0 /* I: Inexact Result */ | |
| 63 | #define UF 1 /* U: UnderFlow */ | |
| 64 | #define OF 2 /* O: OverFlow */ | |
| 65 | #define DZ 3 /* Z: Division by Zero */ | |
| 66 | #define IO 4 /* V: Invalid Operation */ | |
| 67 | #define UO 5 /* E: Unimplemented Operation (CAUSE field only) */ | |
| 68 | ||
| 69 | #define FP_FLAGS(b) (1 << ((b) + fcsr_FLAGS_shift)) | |
| 70 | #define FP_ENABLE(b) (1 << ((b) + fcsr_ENABLES_shift)) | |
| 71 | #define FP_CAUSE(b) (1 << ((b) + fcsr_CAUSE_shift)) | |
| 72 | ||
| 73 | ||
| 74 | /* Rounding mode bit definitions and access macros. */ | |
| 75 | #define FP_RM_NEAREST 0 /* Round to nearest (Round). */ | |
| 76 | #define FP_RM_TOZERO 1 /* Round to zero (Trunc). */ | |
| 77 | #define FP_RM_TOPINF 2 /* Round to Plus infinity (Ceil). */ | |
| 78 | #define FP_RM_TOMINF 3 /* Round to Minus infinity (Floor). */ | |
| 79 | ||
| 80 | #define GETRM() ((FCSR >> fcsr_RM_shift) & fcsr_RM_mask) | |
| 81 | ||
| 82 | ||
| 83 | #endif /* CP1_H */ |