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[thirdparty/binutils-gdb.git] / sim / mips / sim-main.h
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c906108c 1/* MIPS Simulator definition.
4c54fc26 2 Copyright (C) 1997, 1998, 2003 Free Software Foundation, Inc.
c906108c
SS		 3 Contributed by Cygnus Support.
4
5This file is part of GDB, the GNU debugger.
6
7This program is free software; you can redistribute it and/or modify
8it under the terms of the GNU General Public License as published by
9the Free Software Foundation; either version 2, or (at your option)
10any later version.
11
12This program is distributed in the hope that it will be useful,
13but WITHOUT ANY WARRANTY; without even the implied warranty of
14MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15GNU General Public License for more details.
16
17You should have received a copy of the GNU General Public License along
18with this program; if not, write to the Free Software Foundation, Inc.,
1959 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
20
21#ifndef SIM_MAIN_H
22#define SIM_MAIN_H
23
24/* This simulator doesn't cache the Current Instruction Address */
25/* #define SIM_ENGINE_HALT_HOOK(SD, LAST_CPU, CIA) */
26/* #define SIM_ENGINE_RESUME_HOOK(SD, LAST_CPU, CIA) */
27
28#define SIM_HAVE_BIENDIAN
29
30
31/* hobble some common features for moment */
32#define WITH_WATCHPOINTS 1
33#define WITH_MODULO_MEMORY 1
34
35
36#define SIM_CORE_SIGNAL(SD,CPU,CIA,MAP,NR_BYTES,ADDR,TRANSFER,ERROR) \
37mips_core_signal ((SD), (CPU), (CIA), (MAP), (NR_BYTES), (ADDR), (TRANSFER), (ERROR))
38
39#include "sim-basics.h"
40
41typedef address_word sim_cia;
42
43#include "sim-base.h"
4c54fc26 44#include "bfd.h"
c906108c 45
5accf1ff 46/* Deprecated macros and types for manipulating 64bit values. Use
c906108c
SS		 47 ../common/sim-bits.h and ../common/sim-endian.h macros instead. */
48
49typedef signed64 word64;
50typedef unsigned64 uword64;
51
52#define WORD64LO(t) (unsigned int)((t)&0xFFFFFFFF)
53#define WORD64HI(t) (unsigned int)(((uword64)(t))>>32)
54#define SET64LO(t) (((uword64)(t))&0xFFFFFFFF)
55#define SET64HI(t) (((uword64)(t))<<32)
56#define WORD64(h,l) ((word64)((SET64HI(h)|SET64LO(l))))
57#define UWORD64(h,l) (SET64HI(h)|SET64LO(l))
58
c906108c
SS		 59/* Check if a value will fit within a halfword: */
60#define NOTHALFWORDVALUE(v) ((((((uword64)(v)>>16) == 0) && !((v) & ((unsigned)1 << 15))) || (((((uword64)(v)>>32) == 0xFFFFFFFF) && ((((uword64)(v)>>16) & 0xFFFF) == 0xFFFF)) && ((v) & ((unsigned)1 << 15)))) ? (1 == 0) : (1 == 1))
61
62
63
64/* Floating-point operations: */
65
66#include "sim-fpu.h"
cfe9ea23 67#include "cp1.h"
c906108c
SS		 68
69/* FPU registers must be one of the following types. All other values
70 are reserved (and undefined). */
71typedef enum {
72 fmt_single = 0,
73 fmt_double = 1,
74 fmt_word = 4,
75 fmt_long = 5,
3a2b820e 76 fmt_ps = 6,
c906108c
SS		 77 /* The following are well outside the normal acceptable format
78 range, and are used in the register status vector. */
79 fmt_unknown = 0x10000000,
80 fmt_uninterpreted = 0x20000000,
81 fmt_uninterpreted_32 = 0x40000000,
82 fmt_uninterpreted_64 = 0x80000000U,
83} FP_formats;
84
e7e81181
CD		 85/* For paired word (pw) operations, the opcode representation is fmt_word,
86 but register transfers (StoreFPR, ValueFPR, etc.) are done as fmt_long. */
87#define fmt_pw fmt_long
88
c906108c
SS		 89/* This should be the COC1 value at the start of the preceding
90 instruction: */
91#define PREVCOC1() ((STATE & simPCOC1) ? 1 : 0)
92
93#ifdef TARGET_ENABLE_FR
94/* FIXME: this should be enabled for all targets, but needs testing first. */
95#define SizeFGR() (((WITH_TARGET_FLOATING_POINT_BITSIZE) == 64) \
96 ? ((SR & status_FR) ? 64 : 32) \
97 : (WITH_TARGET_FLOATING_POINT_BITSIZE))
98#else
99#define SizeFGR() (WITH_TARGET_FLOATING_POINT_BITSIZE)
100#endif
101
c906108c
SS		 102
103
104
105
106/* HI/LO register accesses */
107
108/* For some MIPS targets, the HI/LO registers have certain timing
109 restrictions in that, for instance, a read of a HI register must be
110 separated by at least three instructions from a preceeding read.
111
112 The struct below is used to record the last access by each of A MT,
113 MF or other OP instruction to a HI/LO register. See mips.igen for
114 more details. */
115
116typedef struct _hilo_access {
117 signed64 timestamp;
118 address_word cia;
119} hilo_access;
120
121typedef struct _hilo_history {
122 hilo_access mt;
123 hilo_access mf;
124 hilo_access op;
125} hilo_history;
126
127
128
129
130/* Integer ALU operations: */
131
132#include "sim-alu.h"
133
134#define ALU32_END(ANS) \
135 if (ALU32_HAD_OVERFLOW) \
136 SignalExceptionIntegerOverflow (); \
137 (ANS) = (signed32) ALU32_OVERFLOW_RESULT
138
139
140#define ALU64_END(ANS) \
141 if (ALU64_HAD_OVERFLOW) \
142 SignalExceptionIntegerOverflow (); \
143 (ANS) = ALU64_OVERFLOW_RESULT;
144
145
146
147
148
149/* The following is probably not used for MIPS IV onwards: */
150/* Slots for delayed register updates. For the moment we just have a
151 fixed number of slots (rather than a more generic, dynamic
152 system). This keeps the simulator fast. However, we only allow
153 for the register update to be delayed for a single instruction
154 cycle. */
155#define PSLOTS (8) /* Maximum number of instruction cycles */
156
157typedef struct _pending_write_queue {
158 int in;
159 int out;
160 int total;
161 int slot_delay[PSLOTS];
162 int slot_size[PSLOTS];
163 int slot_bit[PSLOTS];
164 void *slot_dest[PSLOTS];
165 unsigned64 slot_value[PSLOTS];
166} pending_write_queue;
167
168#ifndef PENDING_TRACE
169#define PENDING_TRACE 0
170#endif
171#define PENDING_IN ((CPU)->pending.in)
172#define PENDING_OUT ((CPU)->pending.out)
173#define PENDING_TOTAL ((CPU)->pending.total)
174#define PENDING_SLOT_SIZE ((CPU)->pending.slot_size)
175#define PENDING_SLOT_BIT ((CPU)->pending.slot_bit)
176#define PENDING_SLOT_DELAY ((CPU)->pending.slot_delay)
177#define PENDING_SLOT_DEST ((CPU)->pending.slot_dest)
178#define PENDING_SLOT_VALUE ((CPU)->pending.slot_value)
179
180/* Invalidate the pending write queue, all pending writes are
181 discarded. */
182
183#define PENDING_INVALIDATE() \
184memset (&(CPU)->pending, 0, sizeof ((CPU)->pending))
185
186/* Schedule a write to DEST for N cycles time. For 64 bit
187 destinations, schedule two writes. For floating point registers,
188 the caller should schedule a write to both the dest register and
189 the FPR_STATE register. When BIT is non-negative, only BIT of DEST
190 is updated. */
191
192#define PENDING_SCHED(DEST,VAL,DELAY,BIT) \
193 do { \
194 if (PENDING_SLOT_DEST[PENDING_IN] != NULL) \
195 sim_engine_abort (SD, CPU, cia, \
196 "PENDING_SCHED - buffer overflow\n"); \
197 if (PENDING_TRACE) \
198 sim_io_eprintf (SD, "PENDING_SCHED - 0x%lx - dest 0x%lx, val 0x%lx, bit %d, size %d, pending_in %d, pending_out %d, pending_total %d\n", \
199 (unsigned long) cia, (unsigned long) &(DEST), \
200 (unsigned long) (VAL), (BIT), (int) sizeof (DEST),\
201 PENDING_IN, PENDING_OUT, PENDING_TOTAL); \
202 PENDING_SLOT_DELAY[PENDING_IN] = (DELAY) + 1; \
203 PENDING_SLOT_DEST[PENDING_IN] = &(DEST); \
204 PENDING_SLOT_VALUE[PENDING_IN] = (VAL); \
205 PENDING_SLOT_SIZE[PENDING_IN] = sizeof (DEST); \
206 PENDING_SLOT_BIT[PENDING_IN] = (BIT); \
207 PENDING_IN = (PENDING_IN + 1) % PSLOTS; \
208 PENDING_TOTAL += 1; \
209 } while (0)
210
211#define PENDING_WRITE(DEST,VAL,DELAY) PENDING_SCHED(DEST,VAL,DELAY,-1)
212#define PENDING_BIT(DEST,VAL,DELAY,BIT) PENDING_SCHED(DEST,VAL,DELAY,BIT)
213
214#define PENDING_TICK() pending_tick (SD, CPU, cia)
215
216#define PENDING_FLUSH() abort () /* think about this one */
217#define PENDING_FP() abort () /* think about this one */
218
219/* For backward compatibility */
220#define PENDING_FILL(R,VAL) \
221do { \
ee7254b0 222 if ((R) >= FGR_BASE && (R) < FGR_BASE + NR_FGR) \
c906108c 223 { \
ee7254b0
CD		 224 PENDING_SCHED(FGR[(R) - FGR_BASE], VAL, 1, -1); \
225 PENDING_SCHED(FPR_STATE[(R) - FGR_BASE], fmt_uninterpreted, 1, -1); \
c906108c
SS		 226 } \
227 else \
228 PENDING_SCHED(GPR[(R)], VAL, 1, -1); \
229} while (0)
230
231
9e52972e
FF		 232enum float_operation
233 {
234 FLOP_ADD, FLOP_SUB, FLOP_MUL, FLOP_MADD,
235 FLOP_MSUB, FLOP_MAX=10, FLOP_MIN, FLOP_ABS,
236 FLOP_ITOF0=14, FLOP_FTOI0=18, FLOP_NEG=23
237 };
238
c906108c 239
f4f1b9f1
CD		 240/* The internal representation of an MDMX accumulator.
241 Note that 24 and 48 bit accumulator elements are represented in
242 32 or 64 bits. Since the accumulators are 2's complement with
243 overflow suppressed, high-order bits can be ignored in most contexts. */
244
245typedef signed32 signed24;
246typedef signed64 signed48;
247
248typedef union {
249 signed24 ob[8];
250 signed48 qh[4];
251} MDMX_accumulator;
252
253
254/* Conventional system arguments. */
255#define SIM_STATE sim_cpu *cpu, address_word cia
256#define SIM_ARGS CPU, cia
257
c906108c
SS		 258struct _sim_cpu {
259
260
261 /* The following are internal simulator state variables: */
262#define CIA_GET(CPU) ((CPU)->registers[PCIDX] + 0)
263#define CIA_SET(CPU,CIA) ((CPU)->registers[PCIDX] = (CIA))
264 address_word dspc; /* delay-slot PC */
265#define DSPC ((CPU)->dspc)
266
267#define DELAY_SLOT(TARGET) NIA = delayslot32 (SD_, (TARGET))
268#define NULLIFY_NEXT_INSTRUCTION() NIA = nullify_next_insn32 (SD_)
269
270
271 /* State of the simulator */
272 unsigned int state;
273 unsigned int dsstate;
274#define STATE ((CPU)->state)
275#define DSSTATE ((CPU)->dsstate)
276
277/* Flags in the "state" variable: */
278#define simHALTEX (1 << 2) /* 0 = run; 1 = halt on exception */
279#define simHALTIN (1 << 3) /* 0 = run; 1 = halt on interrupt */
280#define simTRACE (1 << 8) /* 0 = do nothing; 1 = trace address activity */
281#define simPCOC0 (1 << 17) /* COC[1] from current */
282#define simPCOC1 (1 << 18) /* COC[1] from previous */
283#define simDELAYSLOT (1 << 24) /* 0 = do nothing; 1 = delay slot entry exists */
284#define simSKIPNEXT (1 << 25) /* 0 = do nothing; 1 = skip instruction */
285#define simSIGINT (1 << 28) /* 0 = do nothing; 1 = SIGINT has occured */
286#define simJALDELAYSLOT (1 << 29) /* 1 = in jal delay slot */
287
fb891446 288#ifndef ENGINE_ISSUE_PREFIX_HOOK
c906108c
SS		 289#define ENGINE_ISSUE_PREFIX_HOOK() \
290 { \
291 /* Perform any pending writes */ \
292 PENDING_TICK(); \
293 /* Set previous flag, depending on current: */ \
294 if (STATE & simPCOC0) \
295 STATE |= simPCOC1; \
296 else \
297 STATE &= ~simPCOC1; \
298 /* and update the current value: */ \
299 if (GETFCC(0)) \
300 STATE |= simPCOC0; \
301 else \
302 STATE &= ~simPCOC0; \
303 }
fb891446 304#endif /* ENGINE_ISSUE_PREFIX_HOOK */
c906108c
SS		 305
306
307/* This is nasty, since we have to rely on matching the register
308 numbers used by GDB. Unfortunately, depending on the MIPS target
309 GDB uses different register numbers. We cannot just include the
310 relevant "gdb/tm.h" link, since GDB may not be configured before
311 the sim world, and also the GDB header file requires too much other
312 state. */
313
314#ifndef TM_MIPS_H
315#define LAST_EMBED_REGNUM (89)
316#define NUM_REGS (LAST_EMBED_REGNUM + 1)
317
ee7254b0
CD		 318#define FP0_REGNUM 38 /* Floating point register 0 (single float) */
319#define FCRCS_REGNUM 70 /* FP control/status */
320#define FCRIR_REGNUM 71 /* FP implementation/revision */
c906108c
SS		 321#endif
322
323
c906108c
SS		 324/* To keep this default simulator simple, and fast, we use a direct
325 vector of registers. The internal simulator engine then uses
326 manifests to access the correct slot. */
327
328 unsigned_word registers[LAST_EMBED_REGNUM + 1];
329
330 int register_widths[NUM_REGS];
331#define REGISTERS ((CPU)->registers)
332
333#define GPR (&REGISTERS[0])
334#define GPR_SET(N,VAL) (REGISTERS[(N)] = (VAL))
335
c906108c
SS		 336#define LO (REGISTERS[33])
337#define HI (REGISTERS[34])
338#define PCIDX 37
339#define PC (REGISTERS[PCIDX])
340#define CAUSE (REGISTERS[36])
341#define SRIDX (32)
342#define SR (REGISTERS[SRIDX]) /* CPU status register */
343#define FCR0IDX (71)
344#define FCR0 (REGISTERS[FCR0IDX]) /* really a 32bit register */
345#define FCR31IDX (70)
346#define FCR31 (REGISTERS[FCR31IDX]) /* really a 32bit register */
347#define FCSR (FCR31)
348#define Debug (REGISTERS[86])
349#define DEPC (REGISTERS[87])
350#define EPC (REGISTERS[88])
c906108c
SS		 351
352 /* All internal state modified by signal_exception() that may need to be
353 rolled back for passing moment-of-exception image back to gdb. */
354 unsigned_word exc_trigger_registers[LAST_EMBED_REGNUM + 1];
355 unsigned_word exc_suspend_registers[LAST_EMBED_REGNUM + 1];
356 int exc_suspended;
357
358#define SIM_CPU_EXCEPTION_TRIGGER(SD,CPU,CIA) mips_cpu_exception_trigger(SD,CPU,CIA)
359#define SIM_CPU_EXCEPTION_SUSPEND(SD,CPU,EXC) mips_cpu_exception_suspend(SD,CPU,EXC)
360#define SIM_CPU_EXCEPTION_RESUME(SD,CPU,EXC) mips_cpu_exception_resume(SD,CPU,EXC)
361
362 unsigned_word c0_config_reg;
363#define C0_CONFIG ((CPU)->c0_config_reg)
364
365/* The following are pseudonyms for standard registers */
366#define ZERO (REGISTERS[0])
367#define V0 (REGISTERS[2])
368#define A0 (REGISTERS[4])
369#define A1 (REGISTERS[5])
370#define A2 (REGISTERS[6])
371#define A3 (REGISTERS[7])
372#define T8IDX 24
373#define T8 (REGISTERS[T8IDX])
374#define SPIDX 29
375#define SP (REGISTERS[SPIDX])
376#define RAIDX 31
377#define RA (REGISTERS[RAIDX])
378
379 /* While space is allocated in the main registers arrray for some of
380 the COP0 registers, that space isn't sufficient. Unknown COP0
381 registers overflow into the array below */
382
383#define NR_COP0_GPR 32
384 unsigned_word cop0_gpr[NR_COP0_GPR];
385#define COP0_GPR ((CPU)->cop0_gpr)
386#define COP0_BADVADDR ((unsigned32)(COP0_GPR[8]))
387
ee7254b0
CD		 388 /* While space is allocated for the floating point registers in the
389 main registers array, they are stored separatly. This is because
390 their size may not necessarily match the size of either the
391 general-purpose or system specific registers. */
392#define NR_FGR (32)
393#define FGR_BASE FP0_REGNUM
394 fp_word fgr[NR_FGR];
395#define FGR ((CPU)->fgr)
396
c906108c
SS		 397 /* Keep the current format state for each register: */
398 FP_formats fpr_state[32];
399#define FPR_STATE ((CPU)->fpr_state)
400
401 pending_write_queue pending;
402
f4f1b9f1
CD		 403 /* The MDMX accumulator (used only for MDMX ASE). */
404 MDMX_accumulator acc;
405#define ACC ((CPU)->acc)
406
c906108c
SS		 407 /* LLBIT = Load-Linked bit. A bit of "virtual" state used by atomic
408 read-write instructions. It is set when a linked load occurs. It
409 is tested and cleared by the conditional store. It is cleared
410 (during other CPU operations) when a store to the location would
411 no longer be atomic. In particular, it is cleared by exception
412 return instructions. */
413 int llbit;
414#define LLBIT ((CPU)->llbit)
415
416
417/* The HIHISTORY and LOHISTORY timestamps are used to ensure that
418 corruptions caused by using the HI or LO register too close to a
419 following operation is spotted. See mips.igen for more details. */
420
421 hilo_history hi_history;
422#define HIHISTORY (&(CPU)->hi_history)
423 hilo_history lo_history;
424#define LOHISTORY (&(CPU)->lo_history)
425
c906108c
SS		 426
427 sim_cpu_base base;
428};
429
430
431/* MIPS specific simulator watch config */
432
433void watch_options_install PARAMS ((SIM_DESC sd));
434
435struct swatch {
436 sim_event *pc;
437 sim_event *clock;
438 sim_event *cycles;
439};
440
441
442/* FIXME: At present much of the simulator is still static */
443struct sim_state {
444
445 struct swatch watch;
446
447 sim_cpu cpu[MAX_NR_PROCESSORS];
448#if (WITH_SMP)
449#define STATE_CPU(sd,n) (&(sd)->cpu[n])
450#else
451#define STATE_CPU(sd,n) (&(sd)->cpu[0])
452#endif
453
454
455 sim_state_base base;
456};
457
458
459
460/* Status information: */
461
462/* TODO : these should be the bitmasks for these bits within the
463 status register. At the moment the following are VR4300
464 bit-positions: */
465#define status_KSU_mask (0x18) /* mask for KSU bits */
466#define status_KSU_shift (3) /* shift for field */
467#define ksu_kernel (0x0)
468#define ksu_supervisor (0x1)
469#define ksu_user (0x2)
470#define ksu_unknown (0x3)
471
472#define SR_KSU ((SR & status_KSU_mask) >> status_KSU_shift)
473
474#define status_IE (1 << 0) /* Interrupt enable */
475#define status_EIE (1 << 16) /* Enable Interrupt Enable */
476#define status_EXL (1 << 1) /* Exception level */
477#define status_RE (1 << 25) /* Reverse Endian in user mode */
478#define status_FR (1 << 26) /* enables MIPS III additional FP registers */
479#define status_SR (1 << 20) /* soft reset or NMI */
480#define status_BEV (1 << 22) /* Location of general exception vectors */
481#define status_TS (1 << 21) /* TLB shutdown has occurred */
482#define status_ERL (1 << 2) /* Error level */
483#define status_IM7 (1 << 15) /* Timer Interrupt Mask */
484#define status_RP (1 << 27) /* Reduced Power mode */
485
486/* Specializations for TX39 family */
487#define status_IEc (1 << 0) /* Interrupt enable (current) */
488#define status_KUc (1 << 1) /* Kernel/User mode */
489#define status_IEp (1 << 2) /* Interrupt enable (previous) */
490#define status_KUp (1 << 3) /* Kernel/User mode */
491#define status_IEo (1 << 4) /* Interrupt enable (old) */
492#define status_KUo (1 << 5) /* Kernel/User mode */
493#define status_IM_mask (0xff) /* Interrupt mask */
494#define status_IM_shift (8)
495#define status_NMI (1 << 20) /* NMI */
496#define status_NMI (1 << 20) /* NMI */
497
d35d4f70
CD		 498/* Status bits used by MIPS32/MIPS64. */
499#define status_UX (1 << 5) /* 64-bit user addrs */
500#define status_SX (1 << 6) /* 64-bit supervisor addrs */
501#define status_KX (1 << 7) /* 64-bit kernel addrs */
502#define status_TS (1 << 21) /* TLB shutdown has occurred */
503#define status_PX (1 << 23) /* Enable 64 bit operations */
504#define status_MX (1 << 24) /* Enable MDMX resources */
505#define status_CU0 (1 << 28) /* Coprocessor 0 usable */
506#define status_CU1 (1 << 29) /* Coprocessor 1 usable */
507#define status_CU2 (1 << 30) /* Coprocessor 2 usable */
508#define status_CU3 (1 << 31) /* Coprocessor 3 usable */
7cbea089
CD		 509/* Bits reserved for implementations: */
510#define status_SBX (1 << 16) /* Enable SiByte SB-1 extensions. */
d35d4f70 511
c906108c
SS		 512#define cause_BD ((unsigned)1 << 31) /* L1 Exception in branch delay slot */
513#define cause_BD2 (1 << 30) /* L2 Exception in branch delay slot */
514#define cause_CE_mask 0x30000000 /* Coprocessor exception */
515#define cause_CE_shift 28
516#define cause_EXC2_mask 0x00070000
517#define cause_EXC2_shift 16
518#define cause_IP7 (1 << 15) /* Interrupt pending */
519#define cause_SIOP (1 << 12) /* SIO pending */
520#define cause_IP3 (1 << 11) /* Int 0 pending */
521#define cause_IP2 (1 << 10) /* Int 1 pending */
522
523#define cause_EXC_mask (0x1c) /* Exception code */
524#define cause_EXC_shift (2)
525
526#define cause_SW0 (1 << 8) /* Software interrupt 0 */
527#define cause_SW1 (1 << 9) /* Software interrupt 1 */
528#define cause_IP_mask (0x3f) /* Interrupt pending field */
529#define cause_IP_shift (10)
530
531#define cause_set_EXC(x) CAUSE = (CAUSE & ~cause_EXC_mask) | ((x << cause_EXC_shift) & cause_EXC_mask)
532#define cause_set_EXC2(x) CAUSE = (CAUSE & ~cause_EXC2_mask) | ((x << cause_EXC2_shift) & cause_EXC2_mask)
533
534
535/* NOTE: We keep the following status flags as bit values (1 for true,
536 0 for false). This allows them to be used in binary boolean
537 operations without worrying about what exactly the non-zero true
538 value is. */
539
540/* UserMode */
541#ifdef SUBTARGET_R3900
542#define UserMode ((SR & status_KUc) ? 1 : 0)
543#else
544#define UserMode ((((SR & status_KSU_mask) >> status_KSU_shift) == ksu_user) ? 1 : 0)
545#endif /* SUBTARGET_R3900 */
546
547/* BigEndianMem */
548/* Hardware configuration. Affects endianness of LoadMemory and
549 StoreMemory and the endianness of Kernel and Supervisor mode
550 execution. The value is 0 for little-endian; 1 for big-endian. */
551#define BigEndianMem (CURRENT_TARGET_BYTE_ORDER == BIG_ENDIAN)
552/*(state & simBE) ? 1 : 0)*/
553
554/* ReverseEndian */
555/* This mode is selected if in User mode with the RE bit being set in
556 SR (Status Register). It reverses the endianness of load and store
557 instructions. */
558#define ReverseEndian (((SR & status_RE) && UserMode) ? 1 : 0)
559
560/* BigEndianCPU */
561/* The endianness for load and store instructions (0=little;1=big). In
562 User mode this endianness may be switched by setting the state_RE
563 bit in the SR register. Thus, BigEndianCPU may be computed as
564 (BigEndianMem EOR ReverseEndian). */
565#define BigEndianCPU (BigEndianMem ^ ReverseEndian) /* Already bits */
566
567
568
569/* Exceptions: */
570
571/* NOTE: These numbers depend on the processor architecture being
572 simulated: */
573enum ExceptionCause {
574 Interrupt = 0,
575 TLBModification = 1,
576 TLBLoad = 2,
577 TLBStore = 3,
578 AddressLoad = 4,
579 AddressStore = 5,
580 InstructionFetch = 6,
581 DataReference = 7,
582 SystemCall = 8,
583 BreakPoint = 9,
584 ReservedInstruction = 10,
585 CoProcessorUnusable = 11,
586 IntegerOverflow = 12, /* Arithmetic overflow (IDT monitor raises SIGFPE) */
587 Trap = 13,
588 FPE = 15,
d35d4f70
CD		 589 DebugBreakPoint = 16, /* Impl. dep. in MIPS32/MIPS64. */
590 MDMX = 22,
c906108c 591 Watch = 23,
d35d4f70
CD		 592 MCheck = 24,
593 CacheErr = 30,
594 NMIReset = 31, /* Reserved in MIPS32/MIPS64. */
c906108c
SS		 595
596
597/* The following exception code is actually private to the simulator
598 world. It is *NOT* a processor feature, and is used to signal
599 run-time errors in the simulator. */
600 SimulatorFault = 0xFFFFFFFF
601};
602
603#define TLB_REFILL (0)
604#define TLB_INVALID (1)
605
606
607/* The following break instructions are reserved for use by the
608 simulator. The first is used to halt the simulation. The second
609 is used by gdb for break-points. NOTE: Care must be taken, since
610 this value may be used in later revisions of the MIPS ISA. */
611#define HALT_INSTRUCTION_MASK (0x03FFFFC0)
612
613#define HALT_INSTRUCTION (0x03ff000d)
614#define HALT_INSTRUCTION2 (0x0000ffcd)
615
616
617#define BREAKPOINT_INSTRUCTION (0x0005000d)
618#define BREAKPOINT_INSTRUCTION2 (0x0000014d)
619
620
621
622void interrupt_event (SIM_DESC sd, void *data);
623
624void signal_exception (SIM_DESC sd, sim_cpu *cpu, address_word cia, int exception, ...);
625#define SignalException(exc,instruction) signal_exception (SD, CPU, cia, (exc), (instruction))
626#define SignalExceptionInterrupt(level) signal_exception (SD, CPU, cia, Interrupt, level)
627#define SignalExceptionInstructionFetch() signal_exception (SD, CPU, cia, InstructionFetch)
628#define SignalExceptionAddressStore() signal_exception (SD, CPU, cia, AddressStore)
629#define SignalExceptionAddressLoad() signal_exception (SD, CPU, cia, AddressLoad)
630#define SignalExceptionDataReference() signal_exception (SD, CPU, cia, DataReference)
631#define SignalExceptionSimulatorFault(buf) signal_exception (SD, CPU, cia, SimulatorFault, buf)
632#define SignalExceptionFPE() signal_exception (SD, CPU, cia, FPE)
633#define SignalExceptionIntegerOverflow() signal_exception (SD, CPU, cia, IntegerOverflow)
3ad6f714 634#define SignalExceptionCoProcessorUnusable(cop) signal_exception (SD, CPU, cia, CoProcessorUnusable)
c906108c
SS		 635#define SignalExceptionNMIReset() signal_exception (SD, CPU, cia, NMIReset)
636#define SignalExceptionTLBRefillStore() signal_exception (SD, CPU, cia, TLBStore, TLB_REFILL)
637#define SignalExceptionTLBRefillLoad() signal_exception (SD, CPU, cia, TLBLoad, TLB_REFILL)
638#define SignalExceptionTLBInvalidStore() signal_exception (SD, CPU, cia, TLBStore, TLB_INVALID)
639#define SignalExceptionTLBInvalidLoad() signal_exception (SD, CPU, cia, TLBLoad, TLB_INVALID)
640#define SignalExceptionTLBModification() signal_exception (SD, CPU, cia, TLBModification)
d35d4f70
CD		 641#define SignalExceptionMDMX() signal_exception (SD, CPU, cia, MDMX)
642#define SignalExceptionWatch() signal_exception (SD, CPU, cia, Watch)
643#define SignalExceptionMCheck() signal_exception (SD, CPU, cia, MCheck)
644#define SignalExceptionCacheErr() signal_exception (SD, CPU, cia, CacheErr)
c906108c
SS		 645
646/* Co-processor accesses */
647
3ad6f714
CD		 648/* XXX FIXME: For now, assume that FPU (cp1) is always usable. */
649#define COP_Usable(coproc_num) (coproc_num == 1)
650
c906108c
SS		 651void cop_lw PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, int coproc_num, int coproc_reg, unsigned int memword));
652void cop_ld PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, int coproc_num, int coproc_reg, uword64 memword));
653unsigned int cop_sw PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, int coproc_num, int coproc_reg));
654uword64 cop_sd PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, int coproc_num, int coproc_reg));
655
656#define COP_LW(coproc_num,coproc_reg,memword) \
657cop_lw (SD, CPU, cia, coproc_num, coproc_reg, memword)
658#define COP_LD(coproc_num,coproc_reg,memword) \
659cop_ld (SD, CPU, cia, coproc_num, coproc_reg, memword)
660#define COP_SW(coproc_num,coproc_reg) \
661cop_sw (SD, CPU, cia, coproc_num, coproc_reg)
662#define COP_SD(coproc_num,coproc_reg) \
663cop_sd (SD, CPU, cia, coproc_num, coproc_reg)
664
665
666void decode_coproc PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, unsigned int instruction));
667#define DecodeCoproc(instruction) \
668decode_coproc (SD, CPU, cia, (instruction))
669
8030f857 670int sim_monitor (SIM_DESC sd, sim_cpu *cpu, address_word cia, unsigned int arg);
c906108c
SS		 671
672
18d8a52d
CD		 673/* FPR access. */
674unsigned64 value_fpr (SIM_STATE, int fpr, FP_formats);
675#define ValueFPR(FPR,FMT) value_fpr (SIM_ARGS, (FPR), (FMT))
676void store_fpr (SIM_STATE, int fpr, FP_formats fmt, unsigned64 value);
677#define StoreFPR(FPR,FMT,VALUE) store_fpr (SIM_ARGS, (FPR), (FMT), (VALUE))
3a2b820e
CD		 678unsigned64 ps_lower (SIM_STATE, unsigned64 op);
679#define PSLower(op) ps_lower (SIM_ARGS, op)
680unsigned64 ps_upper (SIM_STATE, unsigned64 op);
681#define PSUpper(op) ps_upper (SIM_ARGS, op)
682unsigned64 pack_ps (SIM_STATE, unsigned64 op1, unsigned64 op2, FP_formats from);
683#define PackPS(op1,op2) pack_ps (SIM_ARGS, op1, op2, fmt_single)
18d8a52d
CD		 684
685
cfe9ea23
CD		 686/* FCR access. */
687unsigned_word value_fcr (SIM_STATE, int fcr);
688#define ValueFCR(FCR) value_fcr (SIM_ARGS, (FCR))
689void store_fcr (SIM_STATE, int fcr, unsigned_word value);
690#define StoreFCR(FCR,VALUE) store_fcr (SIM_ARGS, (FCR), (VALUE))
691void test_fcsr (SIM_STATE);
692#define TestFCSR() test_fcsr (SIM_ARGS)
693
694
18d8a52d 695/* FPU operations. */
cfe9ea23
CD		 696void fp_cmp (SIM_STATE, unsigned64 op1, unsigned64 op2, FP_formats fmt, int abs, int cond, int cc);
697#define Compare(op1,op2,fmt,cond,cc) fp_cmp(SIM_ARGS, op1, op2, fmt, 0, cond, cc)
ba46ddd0
CD		 698unsigned64 fp_abs (SIM_STATE, unsigned64 op, FP_formats fmt);
699#define AbsoluteValue(op,fmt) fp_abs(SIM_ARGS, op, fmt)
700unsigned64 fp_neg (SIM_STATE, unsigned64 op, FP_formats fmt);
701#define Negate(op,fmt) fp_neg(SIM_ARGS, op, fmt)
702unsigned64 fp_add (SIM_STATE, unsigned64 op1, unsigned64 op2, FP_formats fmt);
703#define Add(op1,op2,fmt) fp_add(SIM_ARGS, op1, op2, fmt)
704unsigned64 fp_sub (SIM_STATE, unsigned64 op1, unsigned64 op2, FP_formats fmt);
705#define Sub(op1,op2,fmt) fp_sub(SIM_ARGS, op1, op2, fmt)
706unsigned64 fp_mul (SIM_STATE, unsigned64 op1, unsigned64 op2, FP_formats fmt);
707#define Multiply(op1,op2,fmt) fp_mul(SIM_ARGS, op1, op2, fmt)
708unsigned64 fp_div (SIM_STATE, unsigned64 op1, unsigned64 op2, FP_formats fmt);
709#define Divide(op1,op2,fmt) fp_div(SIM_ARGS, op1, op2, fmt)
710unsigned64 fp_recip (SIM_STATE, unsigned64 op, FP_formats fmt);
711#define Recip(op,fmt) fp_recip(SIM_ARGS, op, fmt)
712unsigned64 fp_sqrt (SIM_STATE, unsigned64 op, FP_formats fmt);
713#define SquareRoot(op,fmt) fp_sqrt(SIM_ARGS, op, fmt)
f3c08b7e
CD		 714unsigned64 fp_rsqrt (SIM_STATE, unsigned64 op, FP_formats fmt);
715#define RSquareRoot(op,fmt) fp_rsqrt(SIM_ARGS, op, fmt)
716unsigned64 fp_madd (SIM_STATE, unsigned64 op1, unsigned64 op2,
717 unsigned64 op3, FP_formats fmt);
718#define MultiplyAdd(op1,op2,op3,fmt) fp_madd(SIM_ARGS, op1, op2, op3, fmt)
719unsigned64 fp_msub (SIM_STATE, unsigned64 op1, unsigned64 op2,
720 unsigned64 op3, FP_formats fmt);
721#define MultiplySub(op1,op2,op3,fmt) fp_msub(SIM_ARGS, op1, op2, op3, fmt)
722unsigned64 fp_nmadd (SIM_STATE, unsigned64 op1, unsigned64 op2,
723 unsigned64 op3, FP_formats fmt);
724#define NegMultiplyAdd(op1,op2,op3,fmt) fp_nmadd(SIM_ARGS, op1, op2, op3, fmt)
725unsigned64 fp_nmsub (SIM_STATE, unsigned64 op1, unsigned64 op2,
726 unsigned64 op3, FP_formats fmt);
727#define NegMultiplySub(op1,op2,op3,fmt) fp_nmsub(SIM_ARGS, op1, op2, op3, fmt)
18d8a52d
CD		 728unsigned64 convert (SIM_STATE, int rm, unsigned64 op, FP_formats from, FP_formats to);
729#define Convert(rm,op,from,to) convert (SIM_ARGS, rm, op, from, to)
3a2b820e
CD		 730unsigned64 convert_ps (SIM_STATE, int rm, unsigned64 op, FP_formats from,
731 FP_formats to);
732#define ConvertPS(rm,op,from,to) convert_ps (SIM_ARGS, rm, op, from, to)
18d8a52d
CD		 733
734
e7e81181
CD		 735/* MIPS-3D ASE operations. */
736#define CompareAbs(op1,op2,fmt,cond,cc) \
737fp_cmp(SIM_ARGS, op1, op2, fmt, 1, cond, cc)
738unsigned64 fp_add_r (SIM_STATE, unsigned64 op1, unsigned64 op2, FP_formats fmt);
739#define AddR(op1,op2,fmt) fp_add_r(SIM_ARGS, op1, op2, fmt)
740unsigned64 fp_mul_r (SIM_STATE, unsigned64 op1, unsigned64 op2, FP_formats fmt);
741#define MultiplyR(op1,op2,fmt) fp_mul_r(SIM_ARGS, op1, op2, fmt)
742unsigned64 fp_recip1 (SIM_STATE, unsigned64 op, FP_formats fmt);
743#define Recip1(op,fmt) fp_recip1(SIM_ARGS, op, fmt)
744unsigned64 fp_recip2 (SIM_STATE, unsigned64 op1, unsigned64 op2, FP_formats fmt);
745#define Recip2(op1,op2,fmt) fp_recip2(SIM_ARGS, op1, op2, fmt)
746unsigned64 fp_rsqrt1 (SIM_STATE, unsigned64 op, FP_formats fmt);
747#define RSquareRoot1(op,fmt) fp_rsqrt1(SIM_ARGS, op, fmt)
748unsigned64 fp_rsqrt2 (SIM_STATE, unsigned64 op1, unsigned64 op2, FP_formats fmt);
749#define RSquareRoot2(op1,op2,fmt) fp_rsqrt2(SIM_ARGS, op1, op2, fmt)
750
751
f4f1b9f1
CD		 752/* MDMX access. */
753
754typedef unsigned int MX_fmtsel; /* MDMX format select field (5 bits). */
755#define ob_fmtsel(sel) (((sel)<<1)|0x0)
756#define qh_fmtsel(sel) (((sel)<<2)|0x1)
757
758#define fmt_mdmx fmt_uninterpreted
759
760#define MX_VECT_AND (0)
761#define MX_VECT_NOR (1)
762#define MX_VECT_OR (2)
763#define MX_VECT_XOR (3)
764#define MX_VECT_SLL (4)
765#define MX_VECT_SRL (5)
f4f1b9f1
CD		 766#define MX_VECT_ADD (6)
767#define MX_VECT_SUB (7)
768#define MX_VECT_MIN (8)
769#define MX_VECT_MAX (9)
770#define MX_VECT_MUL (10)
771#define MX_VECT_MSGN (11)
772#define MX_VECT_SRA (12)
7cbea089
CD		 773#define MX_VECT_ABSD (13) /* SB-1 only. */
774#define MX_VECT_AVG (14) /* SB-1 only. */
f4f1b9f1
CD		 775
776unsigned64 mdmx_cpr_op (SIM_STATE, int op, unsigned64 op1, int vt, MX_fmtsel fmtsel);
777#define MX_Add(op1,vt,fmtsel) mdmx_cpr_op(SIM_ARGS, MX_VECT_ADD, op1, vt, fmtsel)
778#define MX_And(op1,vt,fmtsel) mdmx_cpr_op(SIM_ARGS, MX_VECT_AND, op1, vt, fmtsel)
779#define MX_Max(op1,vt,fmtsel) mdmx_cpr_op(SIM_ARGS, MX_VECT_MAX, op1, vt, fmtsel)
780#define MX_Min(op1,vt,fmtsel) mdmx_cpr_op(SIM_ARGS, MX_VECT_MIN, op1, vt, fmtsel)
781#define MX_Msgn(op1,vt,fmtsel) mdmx_cpr_op(SIM_ARGS, MX_VECT_MSGN, op1, vt, fmtsel)
782#define MX_Mul(op1,vt,fmtsel) mdmx_cpr_op(SIM_ARGS, MX_VECT_MUL, op1, vt, fmtsel)
783#define MX_Nor(op1,vt,fmtsel) mdmx_cpr_op(SIM_ARGS, MX_VECT_NOR, op1, vt, fmtsel)
784#define MX_Or(op1,vt,fmtsel) mdmx_cpr_op(SIM_ARGS, MX_VECT_OR, op1, vt, fmtsel)
785#define MX_ShiftLeftLogical(op1,vt,fmtsel) mdmx_cpr_op(SIM_ARGS, MX_VECT_SLL, op1, vt, fmtsel)
786#define MX_ShiftRightArith(op1,vt,fmtsel) mdmx_cpr_op(SIM_ARGS, MX_VECT_SRA, op1, vt, fmtsel)
787#define MX_ShiftRightLogical(op1,vt,fmtsel) mdmx_cpr_op(SIM_ARGS, MX_VECT_SRL, op1, vt, fmtsel)
788#define MX_Sub(op1,vt,fmtsel) mdmx_cpr_op(SIM_ARGS, MX_VECT_SUB, op1, vt, fmtsel)
789#define MX_Xor(op1,vt,fmtsel) mdmx_cpr_op(SIM_ARGS, MX_VECT_XOR, op1, vt, fmtsel)
7cbea089
CD		 790#define MX_AbsDiff(op1,vt,fmtsel) mdmx_cpr_op(SIM_ARGS, MX_VECT_ABSD, op1, vt, fmtsel)
791#define MX_Avg(op1,vt,fmtsel) mdmx_cpr_op(SIM_ARGS, MX_VECT_AVG, op1, vt, fmtsel)
f4f1b9f1
CD		 792
793#define MX_C_EQ 0x1
794#define MX_C_LT 0x4
795
796void mdmx_cc_op (SIM_STATE, int cond, unsigned64 op1, int vt, MX_fmtsel fmtsel);
797#define MX_Comp(op1,cond,vt,fmtsel) mdmx_cc_op(SIM_ARGS, cond, op1, vt, fmtsel)
798
799unsigned64 mdmx_pick_op (SIM_STATE, int tf, unsigned64 op1, int vt, MX_fmtsel fmtsel);
800#define MX_Pick(tf,op1,vt,fmtsel) mdmx_pick_op(SIM_ARGS, tf, op1, vt, fmtsel)
801
802#define MX_VECT_ADDA (0)
803#define MX_VECT_ADDL (1)
804#define MX_VECT_MULA (2)
805#define MX_VECT_MULL (3)
806#define MX_VECT_MULS (4)
807#define MX_VECT_MULSL (5)
808#define MX_VECT_SUBA (6)
809#define MX_VECT_SUBL (7)
7cbea089 810#define MX_VECT_ABSDA (8) /* SB-1 only. */
f4f1b9f1
CD		 811
812void mdmx_acc_op (SIM_STATE, int op, unsigned64 op1, int vt, MX_fmtsel fmtsel);
813#define MX_AddA(op1,vt,fmtsel) mdmx_acc_op(SIM_ARGS, MX_VECT_ADDA, op1, vt, fmtsel)
814#define MX_AddL(op1,vt,fmtsel) mdmx_acc_op(SIM_ARGS, MX_VECT_ADDL, op1, vt, fmtsel)
815#define MX_MulA(op1,vt,fmtsel) mdmx_acc_op(SIM_ARGS, MX_VECT_MULA, op1, vt, fmtsel)
816#define MX_MulL(op1,vt,fmtsel) mdmx_acc_op(SIM_ARGS, MX_VECT_MULL, op1, vt, fmtsel)
817#define MX_MulS(op1,vt,fmtsel) mdmx_acc_op(SIM_ARGS, MX_VECT_MULS, op1, vt, fmtsel)
818#define MX_MulSL(op1,vt,fmtsel) mdmx_acc_op(SIM_ARGS, MX_VECT_MULSL, op1, vt, fmtsel)
819#define MX_SubA(op1,vt,fmtsel) mdmx_acc_op(SIM_ARGS, MX_VECT_SUBA, op1, vt, fmtsel)
820#define MX_SubL(op1,vt,fmtsel) mdmx_acc_op(SIM_ARGS, MX_VECT_SUBL, op1, vt, fmtsel)
7cbea089 821#define MX_AbsDiffC(op1,vt,fmtsel) mdmx_acc_op(SIM_ARGS, MX_VECT_ABSDA, op1, vt, fmtsel)
f4f1b9f1
CD		 822
823#define MX_FMT_OB (0)
824#define MX_FMT_QH (1)
825
826/* The following codes chosen to indicate the units of shift. */
827#define MX_RAC_L (0)
828#define MX_RAC_M (1)
829#define MX_RAC_H (2)
830
831unsigned64 mdmx_rac_op (SIM_STATE, int, int);
832#define MX_RAC(op,fmt) mdmx_rac_op(SIM_ARGS, op, fmt)
833
834void mdmx_wacl (SIM_STATE, int, unsigned64, unsigned64);
835#define MX_WACL(fmt,vs,vt) mdmx_wacl(SIM_ARGS, fmt, vs, vt)
836void mdmx_wach (SIM_STATE, int, unsigned64);
837#define MX_WACH(fmt,vs) mdmx_wach(SIM_ARGS, fmt, vs)
838
839#define MX_RND_AS (0)
840#define MX_RND_AU (1)
841#define MX_RND_ES (2)
842#define MX_RND_EU (3)
843#define MX_RND_ZS (4)
844#define MX_RND_ZU (5)
845
846unsigned64 mdmx_round_op (SIM_STATE, int, int, MX_fmtsel);
847#define MX_RNAS(vt,fmt) mdmx_round_op(SIM_ARGS, MX_RND_AS, vt, fmt)
848#define MX_RNAU(vt,fmt) mdmx_round_op(SIM_ARGS, MX_RND_AU, vt, fmt)
849#define MX_RNES(vt,fmt) mdmx_round_op(SIM_ARGS, MX_RND_ES, vt, fmt)
850#define MX_RNEU(vt,fmt) mdmx_round_op(SIM_ARGS, MX_RND_EU, vt, fmt)
851#define MX_RZS(vt,fmt) mdmx_round_op(SIM_ARGS, MX_RND_ZS, vt, fmt)
852#define MX_RZU(vt,fmt) mdmx_round_op(SIM_ARGS, MX_RND_ZU, vt, fmt)
853
854unsigned64 mdmx_shuffle (SIM_STATE, int, unsigned64, unsigned64);
855#define MX_SHFL(shop,op1,op2) mdmx_shuffle(SIM_ARGS, shop, op1, op2)
856
857
c906108c
SS		 858
859/* Memory accesses */
860
861/* The following are generic to all versions of the MIPS architecture
862 to date: */
863
864/* Memory Access Types (for CCA): */
865#define Uncached (0)
866#define CachedNoncoherent (1)
867#define CachedCoherent (2)
868#define Cached (3)
869
870#define isINSTRUCTION (1 == 0) /* FALSE */
871#define isDATA (1 == 1) /* TRUE */
872#define isLOAD (1 == 0) /* FALSE */
873#define isSTORE (1 == 1) /* TRUE */
874#define isREAL (1 == 0) /* FALSE */
875#define isRAW (1 == 1) /* TRUE */
876/* The parameter HOST (isTARGET / isHOST) is ignored */
877#define isTARGET (1 == 0) /* FALSE */
878/* #define isHOST (1 == 1) TRUE */
879
880/* The "AccessLength" specifications for Loads and Stores. NOTE: This
881 is the number of bytes minus 1. */
882#define AccessLength_BYTE (0)
883#define AccessLength_HALFWORD (1)
884#define AccessLength_TRIPLEBYTE (2)
885#define AccessLength_WORD (3)
886#define AccessLength_QUINTIBYTE (4)
887#define AccessLength_SEXTIBYTE (5)
888#define AccessLength_SEPTIBYTE (6)
889#define AccessLength_DOUBLEWORD (7)
890#define AccessLength_QUADWORD (15)
891
892#define LOADDRMASK (WITH_TARGET_WORD_BITSIZE == 64 \
893 ? AccessLength_DOUBLEWORD /*7*/ \
894 : AccessLength_WORD /*3*/)
895#define PSIZE (WITH_TARGET_ADDRESS_BITSIZE)
896
897
898INLINE_SIM_MAIN (int) address_translation PARAMS ((SIM_DESC sd, sim_cpu *, address_word cia, address_word vAddr, int IorD, int LorS, address_word *pAddr, int *CCA, int raw));
899#define AddressTranslation(vAddr,IorD,LorS,pAddr,CCA,host,raw) \
900address_translation (SD, CPU, cia, vAddr, IorD, LorS, pAddr, CCA, raw)
901
902INLINE_SIM_MAIN (void) load_memory PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, uword64* memvalp, uword64* memval1p, int CCA, unsigned int AccessLength, address_word pAddr, address_word vAddr, int IorD));
903#define LoadMemory(memvalp,memval1p,CCA,AccessLength,pAddr,vAddr,IorD,raw) \
904load_memory (SD, CPU, cia, memvalp, memval1p, CCA, AccessLength, pAddr, vAddr, IorD)
905
906INLINE_SIM_MAIN (void) store_memory PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, int CCA, unsigned int AccessLength, uword64 MemElem, uword64 MemElem1, address_word pAddr, address_word vAddr));
907#define StoreMemory(CCA,AccessLength,MemElem,MemElem1,pAddr,vAddr,raw) \
908store_memory (SD, CPU, cia, CCA, AccessLength, MemElem, MemElem1, pAddr, vAddr)
909
910INLINE_SIM_MAIN (void) cache_op PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, int op, address_word pAddr, address_word vAddr, unsigned int instruction));
911#define CacheOp(op,pAddr,vAddr,instruction) \
912cache_op (SD, CPU, cia, op, pAddr, vAddr, instruction)
913
914INLINE_SIM_MAIN (void) sync_operation PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, int stype));
915#define SyncOperation(stype) \
916sync_operation (SD, CPU, cia, (stype))
917
918INLINE_SIM_MAIN (void) prefetch PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, int CCA, address_word pAddr, address_word vAddr, int DATA, int hint));
919#define Prefetch(CCA,pAddr,vAddr,DATA,hint) \
920prefetch (SD, CPU, cia, CCA, pAddr, vAddr, DATA, hint)
921
402586aa
CD		 922void unpredictable_action (sim_cpu *cpu, address_word cia);
923#define NotWordValue(val) not_word_value (SD_, (val))
924#define Unpredictable() unpredictable (SD_)
f4f1b9f1 925#define UnpredictableResult() /* For now, do nothing. */
b96e7ef1 926
c906108c
SS		 927INLINE_SIM_MAIN (unsigned32) ifetch32 PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, address_word vaddr));
928#define IMEM32(CIA) ifetch32 (SD, CPU, (CIA), (CIA))
929INLINE_SIM_MAIN (unsigned16) ifetch16 PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, address_word vaddr));
930#define IMEM16(CIA) ifetch16 (SD, CPU, (CIA), ((CIA) & ~1))
931#define IMEM16_IMMED(CIA,NR) ifetch16 (SD, CPU, (CIA), ((CIA) & ~1) + 2 * (NR))
932
933void dotrace PARAMS ((SIM_DESC sd, sim_cpu *cpu, FILE *tracefh, int type, SIM_ADDR address, int width, char *comment, ...));
934extern FILE *tracefh;
935
936INLINE_SIM_MAIN (void) pending_tick PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia));
937extern SIM_CORE_SIGNAL_FN mips_core_signal;
938
939char* pr_addr PARAMS ((SIM_ADDR addr));
940char* pr_uword64 PARAMS ((uword64 addr));
941
942
4c0deff4 943#define GPR_CLEAR(N) do { GPR_SET((N),0); } while (0)
4c0deff4 944
c906108c
SS		 945void mips_cpu_exception_trigger(SIM_DESC sd, sim_cpu* cpu, address_word pc);
946void mips_cpu_exception_suspend(SIM_DESC sd, sim_cpu* cpu, int exception);
947void mips_cpu_exception_resume(SIM_DESC sd, sim_cpu* cpu, int exception);
948
4c54fc26
CD		 949#ifdef MIPS_MACH_MULTI
950extern int mips_mach_multi(SIM_DESC sd);
951#define MIPS_MACH(SD) mips_mach_multi(SD)
952#else
953#define MIPS_MACH(SD) MIPS_MACH_DEFAULT
954#endif
c906108c
SS		 955
956#if H_REVEALS_MODULE_P (SIM_MAIN_INLINE)
957#include "sim-main.c"
958#endif
959
960#endif
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