]> git.ipfire.org Git - thirdparty/binutils-gdb.git/blame - sim/mn10300/ChangeLog
don't sanitize out empty directories if they're not here (e.g., 'cvs co -P')
[thirdparty/binutils-gdb.git] / sim / mn10300 / ChangeLog
CommitLineData
b45caf05
AC
1Fri Sep 19 17:45:25 1997 Andrew Cagney <cagney@b1.cygnus.com>
2
3 * configure: Regenerated to track ../common/aclocal.m4 changes.
4
5Mon Sep 15 17:36:15 1997 Andrew Cagney <cagney@b1.cygnus.com>
6
7 * configure: Regenerated to track ../common/aclocal.m4 changes.
8
6fea4763
DE
9Thu Sep 4 17:21:23 1997 Doug Evans <dje@seba>
10
11 * configure: Regenerated to track ../common/aclocal.m4 changes.
12
88117054
AC
13Wed Aug 27 18:13:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
14
15 * configure: Regenerated to track ../common/aclocal.m4 changes.
16 * config.in: Ditto.
17
7230ff0f
AC
18Tue Aug 26 10:41:07 1997 Andrew Cagney <cagney@b1.cygnus.com>
19
20 * interp.c (sim_kill): Delete.
fafce69a
AC
21 (sim_create_inferior): Add ABFD argument.
22 (sim_load): Move setting of PC from here.
23 (sim_create_inferior): To here.
7230ff0f 24
247fccde
AC
25Mon Aug 25 17:50:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
26
27 * configure: Regenerated to track ../common/aclocal.m4 changes.
28 * config.in: Ditto.
29
30Mon Aug 25 16:14:44 1997 Andrew Cagney <cagney@b1.cygnus.com>
31
32 * interp.c (sim_open): Add ABFD argument.
33
34Tue Jun 24 13:46:20 1997 Jeffrey A Law (law@cygnus.com)
35
36 * interp.c (sim_resume): Clear State.exited.
37 (sim_stop_reason): If State.exited is nonzero, then indicate that
38 the simulator exited instead of stopped.
39 * mn10300_sim.h (struct _state): Add exited field.
40 * simops.c (syscall): Set State.exited for SYS_exit.
41
c370b3cd
JL
42Wed Jun 11 22:07:56 1997 Jeffrey A Law (law@cygnus.com)
43
44 * simops.c: Fix thinko in last change.
45
0a8fa63c
JL
46Tue Jun 10 12:31:32 1997 Jeffrey A Law (law@cygnus.com)
47
dbdb5bd8
JL
48 * simops.c: "call" stores the callee saved registers into the
49 stack! Update the stack pointer properly when done with
50 register saves.
51
0a8fa63c
JL
52 * simops.c: Fix return address computation for "call" instructions.
53
54Thu May 22 01:43:11 1997 Jeffrey A Law (law@cygnus.com)
55
56 * interp.c (sim_open): Fix typo.
57
09e142d5
JL
58Wed May 21 23:27:58 1997 Jeffrey A Law (law@cygnus.com)
59
60 * interp.c (sim_resume): Add missing case in big switch
61 statement (for extb instruction).
62
003c91be
JL
63Tue May 20 17:51:30 1997 Jeffrey A Law (law@cygnus.com)
64
65 * interp.c: Replace all references to load_mem and store_mem
66 with references to load_byte, load_half, load_3_byte, load_word
67 and store_byte, store_half, store_3_byte, store_word.
68 (INLINE): Delete definition.
69 (load_mem_big): Likewise.
70 (max_mem): Make it global.
71 (dispatch): Make this function inline.
72 (load_mem, store_mem): Delete functions.
73 * mn10300_sim.h (INLINE): Define.
74 (RLW): Delete unused definition.
75 (load_mem, store_mem): Delete declarations.
76 (load_mem_big): New definition.
77 (load_byte, load_half, load_3_byte, load_word): New functions.
78 (store_byte, store_half, store_3_byte, store_word): New functions.
79 * simops.c: Replace all references to load_mem and store_mem
80 with references to load_byte, load_half, load_3_byte, load_word
81 and store_byte, store_half, store_3_byte, store_word.
82
83Tue May 20 10:21:51 1997 Andrew Cagney <cagney@b1.cygnus.com>
84
85 * interp.c (sim_open): Add callback to arguments.
86 (sim_set_callbacks): Delete SIM_DESC argument.
87
4df7aeb3
JL
88Mon May 19 13:54:22 1997 Jeffrey A Law (law@cygnus.com)
89
90 * interp.c (dispatch): Make this an inline function.
91
92 * simops.c (syscall): Use callback->write regardless of
93 what file descriptor we're writing too.
94
b07a1e78
JL
95Sun May 18 16:46:31 1997 Jeffrey A Law (law@cygnus.com)
96
97 * interp.c (load_mem_big): Remove function. It's now a macro
98 defined elsewhere.
99 (compare_simops): New function.
100 (sim_open): Sort the Simops table before inserting entries
101 into the hash table.
102 * mn10300_sim.h: Remove unused #defines.
103 (load_mem_big): Define.
104
234a9a49
JL
105Fri May 16 16:36:17 1997 Jeffrey A Law (law@cygnus.com)
106
107 * interp.c (load_mem): If we get a load from an out of range
108 address, abort.
109 (store_mem): Likewise for stores.
110 (max_mem): New variable.
111
baa83bcc
JL
112Tue May 6 13:24:36 1997 Jeffrey A Law (law@cygnus.com)
113
8def9220
JL
114 * mn10300_sim.h: Fix ordering of bits in the PSW.
115
baa83bcc
JL
116 * interp.c: Improve hashing routine to avoid long list
117 traversals for common instructions. Add HASH_STAT support.
118 Rewrite opcode dispatch code using a big switch instead of
119 cascaded if/else statements. Avoid useless calls to load_mem.
120
26e9f63c
JL
121Mon May 5 18:07:48 1997 Jeffrey A Law (law@cygnus.com)
122
123 * mn10300_sim.h (struct _state): Add space for mdrq register.
124 (REG_MDRQ): Define.
125 * simops.c: Don't abort for trap. Add support for the extended
126 instructions, "getx", "putx", "mulq", "mulqu", "sat16", "sat24",
127 and "bsch".
128
129Thu Apr 24 00:39:51 1997 Doug Evans <dje@canuck.cygnus.com>
130
131 * configure: Regenerated to track ../common/aclocal.m4 changes.
132
8517f62b
AC
133Fri Apr 18 14:04:04 1997 Andrew Cagney <cagney@b1.cygnus.com>
134
135 * interp.c (sim_stop): Add stub function.
136
6cc6987e
DE
137Thu Apr 17 03:26:59 1997 Doug Evans <dje@canuck.cygnus.com>
138
139 * Makefile.in (SIM_OBJS): Add sim-load.o.
140 * interp.c (sim_kind, myname): New static locals.
141 (sim_open): Set sim_kind, myname. Ignore -E arg.
142 (sim_load): Return SIM_RC. New arg abfd. Call sim_load_file to
143 load file into simulator. Set start address from bfd.
144 (sim_create_inferior): Return SIM_RC. Delete arg start_address.
145
87e43259
AC
146Wed Apr 16 19:30:44 1997 Andrew Cagney <cagney@b1.cygnus.com>
147
148 * simops.c (OP_F020): SYS_execv, SYS_time, SYS_times, SYS_utime
149 only include if implemented by host.
150 (OP_F020): Typecast arg passed to time function;
151
152Mon Apr 7 23:57:49 1997 Jeffrey A Law (law@cygnus.com)
153
154 * simops.c (syscall): Handle new mn10300 calling conventions.
155
08db4a65
AC
156Mon Apr 7 15:45:02 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
157
158 * configure: Regenerated to track ../common/aclocal.m4 changes.
159 * config.in: Ditto.
160
ea553f56
ILT
161Fri Apr 4 20:02:37 1997 Ian Lance Taylor <ian@cygnus.com>
162
163 * Makefile.in: Change mn10300-opc.o to m10300-opc.o, to match
164 corresponding change in opcodes directory.
165
fbda74b1
DE
166Wed Apr 2 15:06:28 1997 Doug Evans <dje@canuck.cygnus.com>
167
8a7c3105
DE
168 * interp.c (sim_open): New arg `kind'.
169
fbda74b1
DE
170 * configure: Regenerated to track ../common/aclocal.m4 changes.
171
a35e91c3
AC
172Wed Apr 2 14:34:19 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
173
174 * configure: Regenerated to track ../common/aclocal.m4 changes.
175
176Thu Mar 20 11:58:02 1997 Jeffrey A Law (law@cygnus.com)
177
178 * simops.c: Fix register extraction for a two "movbu" variants.
179 Somewhat simplify "sub" instructions.
180 Correctly sign extend operands for "mul". Put the correct
181 half of the result in MDR for "mul" and "mulu".
182 Implement remaining instructions.
183 Tweak opcode for "syscall".
184
185Tue Mar 18 14:21:21 1997 Jeffrey A Law (law@cygnus.com)
186
187 * simops.c: Do syscall emulation in "syscall" instruction. Add
188 dummy "trap" instruction.
189
c695046a
AC
190Wed Mar 19 01:14:00 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
191
192 * configure: Regenerated to track ../common/aclocal.m4 changes.
193
a77aa7ec
AC
194Mon Mar 17 15:10:07 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
195
196 * configure: Re-generate.
197
601fb8ae
MM
198Fri Mar 14 10:34:11 1997 Michael Meissner <meissner@cygnus.com>
199
200 * configure: Regenerate to track ../common/aclocal.m4 changes.
201
53b9417e
DE
202Thu Mar 13 12:54:45 1997 Doug Evans <dje@canuck.cygnus.com>
203
204 * interp.c (sim_open): New SIM_DESC result. Argument is now
205 in argv form.
206 (other sim_*): New SIM_DESC argument.
207
09eef8af
JL
208Wed Mar 12 15:04:00 1997 Jeffrey A Law (law@cygnus.com)
209
0ade484f
JL
210 * simops.c: Fix carry bit computation for "add" instructions.
211
09eef8af
JL
212 * simops.c: Fix typos in bset insns. Fix arguments to store_mem
213 for bset imm8,(d8,an) and bclr imm8,(d8,an).
214
215Wed Mar 5 15:00:10 1997 Jeffrey A Law (law@cygnus.com)
216
217 * simops.c: Fix register references when computing Z and N bits
218 for lsr imm8,dn.
219
220Tue Feb 4 13:33:30 1997 Doug Evans <dje@canuck.cygnus.com>
221
222 * Makefile.in (@COMMON_MAKEFILE_FRAG): Use
223 COMMON_{PRE,POST}_CONFIG_FRAG instead.
224 * configure.in: sinclude ../common/aclocal.m4.
225 * configure: Regenerated.
226
018f9eb4
JL
227Fri Jan 24 10:47:25 1997 Jeffrey A Law (law@cygnus.com)
228
229 * interp.c (init_system): Allocate 2^19 bytes of space for the
230 simulator.
231
295dbbe4
SG
232Thu Jan 23 11:46:23 1997 Stu Grossman (grossman@critters.cygnus.com)
233
234 * configure configure.in Makefile.in: Update to new configure
235 scheme which is more compatible with WinGDB builds.
236 * configure.in: Improve comment on how to run autoconf.
237 * configure: Re-run autoconf to get new ../common/aclocal.m4.
238 * Makefile.in: Use autoconf substitution to install common
239 makefile fragment.
240
f95251f0
JL
241Tue Jan 21 15:03:04 1997 Jeffrey A Law (law@cygnus.com)
242
243 * simops.c: Undo last change to "rol" and "ror", original code
244 was correct!
245
b4b290a0
JL
246Thu Jan 16 11:28:14 1997 Jeffrey A Law (law@cygnus.com)
247
248 * simops.c: Fix "rol" and "ror".
249
250Wed Jan 15 06:45:58 1997 Jeffrey A Law (law@cygnus.com)
251
252 * simops.c: Fix typo in last change.
253
2da0bc1b
JL
254Mon Jan 13 13:22:35 1997 Jeffrey A Law (law@cygnus.com)
255
256 * simops.c: Use REG macros in few places not using them yet.
257
bbd17062
JL
258Mon Jan 6 16:21:19 1997 Jeffrey A Law (law@cygnus.com)
259
260 * mn10300_sim.h (struct _state): Fix number of registers!
261
b774c0e4
JL
262Tue Dec 31 16:20:41 1996 Jeffrey A Law (law@cygnus.com)
263
264 * mn10300_sim.h (struct _state): Put all registers into a single
265 array to make gdb implementation easier.
266 (REG_*): Add definitions for all registers in the state array.
267 (SEXT32, SEXT40, SEXT44, SEXT60): Remove unused macros.
268 * simops.c: Related changes.
269
d657034d
JL
270Wed Dec 18 10:10:45 1996 Jeffrey A Law (law@cygnus.com)
271
272 * interp.c (sim_resume): Handle 0xff as a single byte insn.
273
274 * simops.c: Fix overflow computation for "add" and "inc"
275 instructions.
276
16d2e2b6
JL
277Mon Dec 16 10:03:52 1996 Jeffrey A Law (law@cygnus.com)
278
093e9a32
JL
279 * simops.c: Handle "break" instruction.
280
16d2e2b6
JL
281 * simops.c: Fix restoring the PC for "ret" and "retf" instructions.
282
283Wed Dec 11 09:53:10 1996 Jeffrey A Law (law@cygnus.com)
284
285 * gencode.c (write_opcodes): Also write out the format of the
286 opcode.
287 * mn10300_sim.h (simops): Add "format" field.
288 * interp.c (sim_resume): Deal with endianness issues here.
289
95d18eb7
JL
290Tue Dec 10 15:05:37 1996 Jeffrey A Law (law@cygnus.com)
291
292 * simops.c (REG0_4): Define.
293 Use REG0_4 for indexed loads/stores.
294
2e8f4133
JL
295Sat Dec 7 09:50:28 1996 Jeffrey A Law (law@cygnus.com)
296
297 * simops.c (REG0_16): Fix typo.
298
d2523010
JL
299Fri Dec 6 14:13:34 1996 Jeffrey A Law (law@cygnus.com)
300
b2f7a7e5
JL
301 * simops.c: Call abort for any instruction that's not currently
302 simulated.
303
9f4a551e
JL
304 * simops.c: Define accessor macros to extract register
305 values from instructions. Use them consistently.
306
7c52bf32
JL
307 * interp.c: Delete unused global variable "OP".
308 (sim_resume): Remove unused variable "opcode".
309 * simops.c: Fix some uninitialized variable problems, add
310 parens to fix various -Wall warnings.
311
d2523010
JL
312 * gencode.c (write_header): Add "insn" and "extension" arguments
313 to the OP_* declarations.
314 (write_template): Similarly for function templates.
315 * interp.c (insn, extension): Remove global variables. Instead
316 pass them as arguments to the OP_* functions.
317 * mn10300_sim.h: Remove decls for "insn" and "extension".
318 * simops.c (OP_*): Accept "insn" and "extension" as arguments
319 instead of using globals.
320
4d8ced6c
JL
321Thu Dec 5 22:26:31 1996 Jeffrey A Law (law@cygnus.com)
322
e5a7a537
JL
323 * simops.c: Fix typos in "mov am,(d16,an)" and "mov am,(d32,an)"
324
4d8ced6c
JL
325 * simops.c: Fix thinkos in last change to "inc dn".
326
61ecca95
JL
327Wed Dec 4 10:57:53 1996 Jeffrey A Law (law@cygnus.com)
328
329 * simops.c: "add imm,sp" does not effect the condition codes.
330 "inc dn" does effect the condition codes.
331
e4e13022
JL
332Tue Dec 3 17:37:45 1996 Jeffrey A Law (law@cygnus.com)
333
334 * simops.c: Treat both operands as signed values for
335 "div" instruction.
336
337 * simops.c: Fix simulation of division instructions.
338 Fix typos/thinkos in several "cmp" and "sub" instructions.
339
fcfaf40d
JL
340Mon Dec 2 12:31:40 1996 Jeffrey A Law (law@cygnus.com)
341
e4e13022
JL
342 * simops.c: Fix carry bit handling in "sub" and "cmp"
343 instructions.
344
fcfaf40d
JL
345 * simops.c: Fix "mov imm8,an" and "mov imm16,dn".
346
6db7fc49
JL
347Sun Dec 1 16:05:42 1996 Jeffrey A Law (law@cygnus.com)
348
b7b89deb
JL
349 * simops.c: Fix overflow computation for many instructions.
350
e5a7a537 351 * simops.c: Fix "mov dm, an", "movbu dm, (an)", and "movhu dm, (an)".
af388638 352
c8f0171f
JL
353 * simops.c: Fix "mov am, dn".
354
6db7fc49
JL
355 * simops.c: Fix more bugs in "add imm,an" and
356 "add imm,dn".
357
f5f13c1d
JL
358Wed Nov 27 09:20:42 1996 Jeffrey A Law (law@cygnus.com)
359
6e7a01c1
JL
360 * simops.c: Fix bugs in "movm" and "add imm,an".
361
3bb3fe44
JL
362 * simops.c: Don't lose the upper 24 bits of the return
363 pointer in "call" and "calls" instructions. Rough cut
364 at emulated system calls.
365
de0dce7c
JL
366 * simops.c: Implement the remaining 5, 6 and 7 byte instructions.
367
ecb4b5a3
JL
368 * simops.c: Implement remaining 4 byte instructions.
369
370 * simops.c: Implement remaining 3 byte instructions.
2e35551c 371
f5f13c1d
JL
372 * simops.c: Implement remaining 2 byte instructions. Call
373 abort for instructions we're not implementing now.
374
73e65298
JL
375Tue Nov 26 15:43:41 1996 Jeffrey A Law (law@cygnus.com)
376
707641f6
JL
377 * simops.c: Implement lots of random instructions.
378
1f3bea21
JL
379 * simops.c: Implement "movm" and "bCC" insns.
380
92284aaa
JL
381 * mn10300_sim.h (_state): Add another register (MDR).
382 (REG_MDR): Define.
383 * simops.c: Implement "cmp", "calls", "rets", "jmp" and
384 a few additional random insns.
385
73e65298
JL
386 * mn10300_sim.h (PSW_*): Define for CC status tracking.
387 (REG_D0, REG_A0, REG_SP): Define.
388 * simops.c: Implement "add", "addc" and a few other random
389 instructions.
b5f831ac
JL
390
391 * gencode.c, interp.c: Snapshot current simulator code.
392
05ccbdfd
JL
393Mon Nov 25 12:46:38 1996 Jeffrey A Law (law@cygnus.com)
394
395 * Makefile.in, config.in, configure, configure.in: New files.
396 * gencode.c, interp.c, mn10300_sim.h, simops.c: New files.
397