* aclocal.m4 (SIM_AC_COMMON): Move contents of Make-common.in

[thirdparty/binutils-gdb.git] / sim / mn10300 / ChangeLog

Tue Jan 21 15:03:04 1997  Jeffrey A Law  (law@cygnus.com)

	* simops.c: Undo last change to "rol" and "ror", original code
	was correct!

Thu Jan 16 11:28:14 1997  Jeffrey A Law  (law@cygnus.com)

	* simops.c: Fix "rol" and "ror".

Wed Jan 15 06:45:58 1997  Jeffrey A Law  (law@cygnus.com)

	* simops.c: Fix typo in last change.

Mon Jan 13 13:22:35 1997  Jeffrey A Law  (law@cygnus.com)

	* simops.c: Use REG macros in few places not using them yet.

Mon Jan  6 16:21:19 1997  Jeffrey A Law  (law@cygnus.com)

	* mn10300_sim.h (struct _state): Fix number of registers!

Tue Dec 31 16:20:41 1996  Jeffrey A Law  (law@cygnus.com)

	* mn10300_sim.h (struct _state): Put all registers into a single
	array to make gdb implementation easier.
	(REG_*): Add definitions for all registers in the state array.
	(SEXT32, SEXT40, SEXT44, SEXT60): Remove unused macros.
	* simops.c: Related changes.

Wed Dec 18 10:10:45 1996  Jeffrey A Law  (law@cygnus.com)

	* interp.c (sim_resume): Handle 0xff as a single byte insn.

	* simops.c: Fix overflow computation for "add" and "inc"
	instructions.

Mon Dec 16 10:03:52 1996  Jeffrey A Law  (law@cygnus.com)

	* simops.c: Handle "break" instruction.

	* simops.c: Fix restoring the PC for "ret" and "retf" instructions.

Wed Dec 11 09:53:10 1996  Jeffrey A Law  (law@cygnus.com)

	* gencode.c (write_opcodes): Also write out the format of the
	opcode.
	* mn10300_sim.h (simops): Add "format" field.
	* interp.c (sim_resume): Deal with endianness issues here.

Tue Dec 10 15:05:37 1996  Jeffrey A Law  (law@cygnus.com)

	* simops.c (REG0_4): Define.
	Use REG0_4 for indexed loads/stores.

Sat Dec  7 09:50:28 1996  Jeffrey A Law  (law@cygnus.com)

	* simops.c (REG0_16): Fix typo.

Fri Dec  6 14:13:34 1996  Jeffrey A Law  (law@cygnus.com)

	* simops.c: Call abort for any instruction that's not currently
	simulated.

	* simops.c: Define accessor macros to extract register
	values from instructions.  Use them consistently.

	* interp.c: Delete unused global variable "OP".
	(sim_resume): Remove unused variable "opcode".
	* simops.c: Fix some uninitialized variable problems, add
	parens to fix various -Wall warnings.

	* gencode.c (write_header): Add "insn" and "extension" arguments
	to the OP_* declarations.
	(write_template): Similarly for function templates.
	* interp.c (insn, extension): Remove global variables.  Instead
	pass them as arguments to the OP_* functions.
	* mn10300_sim.h: Remove decls for "insn" and "extension".
	* simops.c (OP_*): Accept "insn" and "extension" as arguments
	instead of using globals.

Thu Dec  5 22:26:31 1996  Jeffrey A Law  (law@cygnus.com)

	* simops.c: Fix typos in "mov am,(d16,an)" and "mov am,(d32,an)"

	* simops.c: Fix thinkos in last change to "inc dn".

Wed Dec  4 10:57:53 1996  Jeffrey A Law  (law@cygnus.com)

	* simops.c: "add imm,sp" does not effect the condition codes.
	"inc dn" does effect the condition codes.

Tue Dec  3 17:37:45 1996  Jeffrey A Law  (law@cygnus.com)

	* simops.c: Treat both operands as signed values for
	"div" instruction.

	* simops.c: Fix simulation of division instructions.
	Fix typos/thinkos in several "cmp" and "sub" instructions.

Mon Dec  2 12:31:40 1996  Jeffrey A Law  (law@cygnus.com)

	* simops.c: Fix carry bit handling in "sub" and "cmp"
	instructions.

	* simops.c: Fix "mov imm8,an" and "mov imm16,dn".

Sun Dec  1 16:05:42 1996  Jeffrey A Law  (law@cygnus.com)

	* simops.c: Fix overflow computation for many instructions.

	* simops.c: Fix "mov dm, an", "movbu dm, (an)", and "movhu dm, (an)".

	* simops.c: Fix "mov am, dn".

	* simops.c: Fix more bugs in "add imm,an" and
	"add imm,dn".

Wed Nov 27 09:20:42 1996  Jeffrey A Law  (law@cygnus.com)

	* simops.c: Fix bugs in "movm" and "add imm,an".

	* simops.c: Don't lose the upper 24 bits of the return
	pointer in "call" and "calls" instructions.  Rough cut
	at emulated system calls.

	* simops.c: Implement the remaining 5, 6 and 7 byte instructions.

	* simops.c: Implement remaining 4 byte instructions.

	* simops.c: Implement remaining 3 byte instructions.

	* simops.c: Implement remaining 2 byte instructions.  Call
	abort for instructions we're not implementing now.

Tue Nov 26 15:43:41 1996  Jeffrey A Law  (law@cygnus.com)

	* simops.c: Implement lots of random instructions.

	* simops.c: Implement "movm" and "bCC" insns.

	* mn10300_sim.h (_state): Add another register (MDR).
	(REG_MDR): Define.
	* simops.c: Implement "cmp", "calls", "rets", "jmp" and
	a few additional random insns.

	* mn10300_sim.h (PSW_*): Define for CC status tracking.
	(REG_D0, REG_A0, REG_SP): Define.
	* simops.c: Implement "add", "addc" and a few other random
	instructions.

	* gencode.c, interp.c: Snapshot current simulator code.

Mon Nov 25 12:46:38 1996  Jeffrey A Law  (law@cygnus.com)

	* Makefile.in, config.in, configure, configure.in: New files.
	* gencode.c, interp.c, mn10300_sim.h, simops.c: New files.