projects / thirdparty / binutils-gdb.git / blame
| Commit | Line | Data |
|---|---|---|
| f5f13c1d JL |
1 | Wed Nov 27 09:20:42 1996 Jeffrey A Law (law@cygnus.com) |
| 2 | ||
| ecb4b5a3 JL |
3 | * simops.c: Implement remaining 4 byte instructions. |
| 4 | ||
| 5 | * simops.c: Implement remaining 3 byte instructions. | |
| 2e35551c | 6 | |
| f5f13c1d JL |
7 | * simops.c: Implement remaining 2 byte instructions. Call |
| 8 | abort for instructions we're not implementing now. | |
| 9 | ||
| 73e65298 JL |
10 | Tue Nov 26 15:43:41 1996 Jeffrey A Law (law@cygnus.com) |
| 11 | ||
| 707641f6 JL |
12 | * simops.c: Implement lots of random instructions. |
| 13 | ||
| 1f3bea21 JL |
14 | * simops.c: Implement "movm" and "bCC" insns. |
| 15 | ||
| 92284aaa JL |
16 | * mn10300_sim.h (_state): Add another register (MDR). |
| 17 | (REG_MDR): Define. | |
| 18 | * simops.c: Implement "cmp", "calls", "rets", "jmp" and | |
| 19 | a few additional random insns. | |
| 20 | ||
| 73e65298 JL |
21 | * mn10300_sim.h (PSW_*): Define for CC status tracking. |
| 22 | (REG_D0, REG_A0, REG_SP): Define. | |
| 23 | * simops.c: Implement "add", "addc" and a few other random | |
| 24 | instructions. | |
| b5f831ac JL |
25 | |
| 26 | * gencode.c, interp.c: Snapshot current simulator code. | |
| 27 | ||
| 05ccbdfd JL |
28 | Mon Nov 25 12:46:38 1996 Jeffrey A Law (law@cygnus.com) |
| 29 | ||
| 30 | * Makefile.in, config.in, configure, configure.in: New files. | |
| 31 | * gencode.c, interp.c, mn10300_sim.h, simops.c: New files. | |
| 32 |