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* am33.igen: Fix Z bit for remaining addc/subc instructions.
[thirdparty/binutils-gdb.git] / sim / mn10300 / am33.igen
CommitLineData
9c55817e
JL		 1// Helper:
2//
3// Given an extended register number, translate it into an index into the
4// register array. This is necessary as the upper 8 extended registers are
5// actually synonyms for the d0-d3/a0-a3 registers.
6//
7//
8
9:function:::int:translate_rreg:int rreg
10{
11
12 /* The higher register numbers actually correspond to the
13 basic machine's address and data registers. */
14 if (rreg > 7 && rreg < 12)
15 return REG_A0 + rreg - 8;
16 else if (rreg > 11 && rreg < 16)
17 return REG_D0 + rreg - 12;
18 else
19 return REG_E0 + rreg;
20}
21
0f7d7385
JL		 22// 1111 0000 0010 00An; mov USP,An
238.0xf0+4.0x2,00,2.AN0:D0m:::mov
24"mov"
25*am33
26{
27 PC = cia;
28 State.regs[REG_A0 + AN0] = State.regs[REG_USP];
29}
30
31
32// 1111 0000 0010 01An; mov SSP,An
338.0xf0+4.0x2,01,2.AN0:D0n:::mov
34"mov"
35*am33
36{
37 PC = cia;
38 State.regs[REG_A0 + AN0] = State.regs[REG_SSP];
39}
40
41
42// 1111 0000 0010 10An; mov MSP,An
438.0xf0+4.0x2,10,2.AN0:D0o:::mov
44"mov"
45*am33
46{
47 PC = cia;
48 State.regs[REG_A0 + AN0] = State.regs[REG_MSP];
49}
50
51
52// 1111 0000 0010 11An; mov PC,An
538.0xf0+4.0x2,11,2.AN0:D0p:::mov
54"mov"
55*am33
56{
57 PC = cia;
58 State.regs[REG_A0 + AN0] = PC;
59}
60
61
62// 1111 0000 0011 Am00; mov Am,USP
638.0xf0+4.0x3,2.AM1,00:D0q:::mov
64"mov"
3e75ff7e 65*am33
0f7d7385
JL		 66{
67 PC = cia;
68 State.regs[REG_USP] = State.regs[REG_A0 + AM1];
69}
70
71// 1111 0000 0011 Am01; mov Am,SSP
728.0xf0+4.0x3,2.AM1,01:D0r:::mov
73"mov"
3e75ff7e 74*am33
0f7d7385
JL		 75{
76 PC = cia;
77 State.regs[REG_SSP] = State.regs[REG_A0 + AM1];
78}
79
80// 1111 0000 0011 Am10; mov Am,MSP
818.0xf0+4.0x3,2.AM1,10:D0s:::mov
82"mov"
3e75ff7e 83*am33
0f7d7385
JL		 84{
85 PC = cia;
86 State.regs[REG_MSP] = State.regs[REG_A0 + AM1];
87}
88
89
90// 1111 0000 1110 imm4; syscall
918.0xf0+4.0xe,IMM4:D0t:::syscall
92"syscall"
93*am33
94{
95 unsigned int sp, next_pc;
96
97 PC = cia;
98 sp = State.regs[REG_SP];
99 next_pc = State.regs[REG_PC] + 2;
100 store_word (sp - 4, next_pc);
101 store_word (sp - 8, PSW);
102 State.regs[REG_PC] = 0x40000000 + IMM4 * 8;
103 nia = PC;
104}
105
106
107// 1111 0010 1110 11Dn; mov EPSW,Dn
1088.0xf2+4.0xe,11,2.DN0:D0u:::mov
109"mov"
110*am33
111{
112 PC = cia;
113 State.regs[REG_D0 + DN0] = PSW;
114}
115
116
117// 1111 0010 1111 Dm01; mov Dm,EPSW
1188.0xf2+4.0xf,2.DM1,01:D0v:::mov
119"mov"
120*am33
121{
122 PC = cia;
123 PSW = State.regs[REG_D0 + DM1];
124}
125
126// 1111 0101 00Am Rn; mov Am,Rn
1278.0xf5+00,2.AM1,4.RN0:D0w:::mov
128"mov"
129*am33
130{
9c55817e
JL		 131 int destreg = translate_rreg (SD_, RN0);
132
0f7d7385 133 PC = cia;
9c55817e 134 State.regs[destreg] = State.regs[REG_A0 + AM1];
0f7d7385
JL		 135}
136
137// 1111 0101 01Dm Rn; mov Dm,Rn
1388.0xf5+01,2.DM1,4.RN0:D0x:::mov
139"mov"
140*am33
141{
9c55817e
JL		 142 int destreg = translate_rreg (SD_, RN0);
143
0f7d7385 144 PC = cia;
9c55817e 145 State.regs[destreg] = State.regs[REG_D0 + DM1];
0f7d7385
JL		 146}
147
148// 1111 0101 10Rm An; mov Rm,An
1498.0xf5+10,4.RM1,2.AN0:D0y:::mov
150"mov"
151*am33
152{
9c55817e
JL		 153 int destreg = translate_rreg (SD_, RM1);
154
0f7d7385 155 PC = cia;
9c55817e 156 State.regs[REG_A0 + AN0] = State.regs[destreg];
0f7d7385
JL		 157}
158
159// 1111 0101 11Rm Dn; mov Rm,Dn
1608.0xf5+11,4.RM1,2.DN0:D0z:::mov
161"mov"
162*am33
163{
9c55817e
JL		 164 int destreg = translate_rreg (SD_, RM1);
165
0f7d7385 166 PC = cia;
9c55817e 167 State.regs[REG_D0 + DN0] = State.regs[destreg];
0f7d7385
JL		 168}
169
170
171// 1111 1000 1100 1110 regs....; movm (USP),regs
1728.0xf8+8.0xce+8.REGS:D1a:::movm
173"movm"
3e75ff7e 174*am33
0f7d7385
JL		 175{
176 unsigned long usp = State.regs[REG_USP];
177 unsigned long mask;
178
179 PC = cia;
180 mask = REGS;
181
182 if (mask & 0x8)
183 {
184 usp += 4;
185 State.regs[REG_LAR] = load_word (usp);
186 usp += 4;
187 State.regs[REG_LIR] = load_word (usp);
188 usp += 4;
189 State.regs[REG_MDR] = load_word (usp);
190 usp += 4;
191 State.regs[REG_A0 + 1] = load_word (usp);
192 usp += 4;
193 State.regs[REG_A0] = load_word (usp);
194 usp += 4;
195 State.regs[REG_D0 + 1] = load_word (usp);
196 usp += 4;
197 State.regs[REG_D0] = load_word (usp);
198 usp += 4;
199 }
200
201 if (mask & 0x10)
202 {
203 State.regs[REG_A0 + 3] = load_word (usp);
204 usp += 4;
205 }
206
207 if (mask & 0x20)
208 {
209 State.regs[REG_A0 + 2] = load_word (usp);
210 usp += 4;
211 }
212
213 if (mask & 0x40)
214 {
215 State.regs[REG_D0 + 3] = load_word (usp);
216 usp += 4;
217 }
218
219 if (mask & 0x80)
220 {
221 State.regs[REG_D0 + 2] = load_word (usp);
222 usp += 4;
223 }
224
225 /* start-sanitize-am33 */
226 if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_am33)
227 {
228 if (mask & 0x1)
229 {
230 /* Need to restore MDQR, MCRH, MCRL, and MCVF */
231 usp += 16;
232 State.regs[REG_E0 + 1] = load_word (usp);
233 usp += 4;
234 State.regs[REG_E0 + 0] = load_word (usp);
235 usp += 4;
236 }
237
238 if (mask & 0x2)
239 {
240 State.regs[REG_E0 + 7] = load_word (usp);
241 usp += 4;
242 State.regs[REG_E0 + 6] = load_word (usp);
243 usp += 4;
244 State.regs[REG_E0 + 5] = load_word (usp);
245 usp += 4;
246 State.regs[REG_E0 + 4] = load_word (usp);
247 usp += 4;
248 }
249
250 if (mask & 0x4)
251 {
252 State.regs[REG_E0 + 3] = load_word (usp);
253 usp += 4;
254 State.regs[REG_E0 + 2] = load_word (usp);
255 usp += 4;
256 }
257 }
258 /* end-sanitize-am33 */
259
260 /* And make sure to update the stack pointer. */
261 State.regs[REG_USP] = usp;
262}
263
264// 1111 1000 1100 1111 regs....; movm (USP),regs
2658.0xf8+8.0xcf+8.REGS:D1b:::movm
266"movm"
3e75ff7e 267*am33
0f7d7385
JL		 268{
269 unsigned long usp = State.regs[REG_USP];
270 unsigned long mask;
271
272 if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_am33)
273 {
274 if (mask & 0x4)
275 {
276 usp -= 4;
277 store_word (usp, State.regs[REG_E0 + 2]);
278 usp -= 4;
279 store_word (usp, State.regs[REG_E0 + 3]);
280 }
281
282 if (mask & 0x2)
283 {
284 usp -= 4;
285 store_word (usp, State.regs[REG_E0 + 4]);
286 usp -= 4;
287 store_word (usp, State.regs[REG_E0 + 5]);
288 usp -= 4;
289 store_word (usp, State.regs[REG_E0 + 6]);
290 usp -= 4;
291 store_word (usp, State.regs[REG_E0 + 7]);
292 }
293
294 if (mask & 0x1)
295 {
296 usp -= 4;
297 store_word (usp, State.regs[REG_E0 + 0]);
298 usp -= 4;
299 store_word (usp, State.regs[REG_E0 + 1]);
300 usp -= 16;
301 /* Need to save MDQR, MCRH, MCRL, and MCVF */
302 }
303 }
304 /* end-sanitize-am33 */
305
306 if (mask & 0x80)
307 {
308 usp -= 4;
309 store_word (usp, State.regs[REG_D0 + 2]);
310 }
311
312 if (mask & 0x40)
313 {
314 usp -= 4;
315 store_word (usp, State.regs[REG_D0 + 3]);
316 }
317
318 if (mask & 0x20)
319 {
320 usp -= 4;
321 store_word (usp, State.regs[REG_A0 + 2]);
322 }
323
324 if (mask & 0x10)
325 {
326 usp -= 4;
327 store_word (usp, State.regs[REG_A0 + 3]);
328 }
329
330 if (mask & 0x8)
331 {
332 usp -= 4;
333 store_word (usp, State.regs[REG_D0]);
334 usp -= 4;
335 store_word (usp, State.regs[REG_D0 + 1]);
336 usp -= 4;
337 store_word (usp, State.regs[REG_A0]);
338 usp -= 4;
339 store_word (usp, State.regs[REG_A0 + 1]);
340 usp -= 4;
341 store_word (usp, State.regs[REG_MDR]);
342 usp -= 4;
343 store_word (usp, State.regs[REG_LIR]);
344 usp -= 4;
345 store_word (usp, State.regs[REG_LAR]);
346 usp -= 4;
347 }
348
349 /* And make sure to update the stack pointer. */
350 State.regs[REG_USP] = usp;
351}
352
353// 1111 1100 1111 1100 imm32...; and imm32,EPSW
3548.0xfc+8.0xfc+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:4a:::and
355"and"
356*am33
357{
358 PC = cia;
359 PSW &= FETCH32(IMM32A, IMM32B, IMM32C, IMM32D);
360}
361
362// 1111 1100 1111 1101 imm32...; or imm32,EPSW
3638.0xfc+8.0xfd+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4a:::or
364"or"
365*am33
366{
367 PC = cia;
368 PSW |= FETCH32(IMM32A, IMM32B, IMM32C, IMM32D);
369}
370
371// 1111 1001 0000 1000 Rm Rn; mov Rm,Rn (Rm != Rn)
3728.0xf9+8.0x08+4.RM2,4.RN0!RM2:D1g:::mov
373"mov"
374*am33
375{
376 int srcreg, dstreg;
377
378 PC = cia;
379
9c55817e
JL		 380 srcreg = translate_rreg (SD_, RM2);
381 dstreg = translate_rreg (SD_, RN0);
0f7d7385
JL		 382 State.regs[dstreg] = State.regs[srcreg];
383}
384
385// 1111 1001 0001 1000 Rn Rn; ext Rn
3868.0xf9+8.0x18+4.RN0,4.RN2=RN0:D1:::ext
387"mov"
388*am33
389{
9c55817e 390 int srcreg;
0f7d7385
JL		 391
392 PC = cia;
9c55817e 393 srcreg = translate_rreg (SD_, RN0);
0f7d7385
JL		 394 if (State.regs[srcreg] & 0x80000000)
395 State.regs[REG_MDR] = -1;
396 else
397 State.regs[REG_MDR] = 0;
398}
399
400// 1111 1001 0010 1000 Rm Rn; extb Rm,Rn
4018.0xf9+8.0x28+4.RM2,4.RN0!RM2:D1:::extb
402"extb"
403*am33
404{
405 int srcreg, dstreg;
406
407 PC = cia;
9c55817e
JL		 408 srcreg = translate_rreg (SD_, RM2);
409 dstreg = translate_rreg (SD_, RN0);
0f7d7385
JL		 410 State.regs[dstreg] = EXTEND8 (State.regs[srcreg]);
411}
412
413// 1111 1001 0011 1000 Rm Rn; extbu Rm,Rn
4148.0xf9+8.0x38+4.RM2,4.RN0!RM2:D1:::extbu
415"extbu"
416*am33
417{
418 int srcreg, dstreg;
419
420 PC = cia;
9c55817e
JL		 421 srcreg = translate_rreg (SD_, RM2);
422 dstreg = translate_rreg (SD_, RN0);
0f7d7385
JL		 423 State.regs[dstreg] = State.regs[srcreg] & 0xff;
424}
425
426// 1111 1001 0100 1000 Rm Rn; exth Rm,Rn
4278.0xf9+8.0x48+4.RM2,4.RN0!RM2:D1:::exth
428"exth"
429*am33
430{
431 int srcreg, dstreg;
432
433 PC = cia;
9c55817e
JL		 434 srcreg = translate_rreg (SD_, RM2);
435 dstreg = translate_rreg (SD_, RN0);
0f7d7385
JL		 436 State.regs[dstreg] = EXTEND16 (State.regs[srcreg]);
437}
438
439// 1111 1001 0101 1000 Rm Rn; exthu Rm,Rn
4408.0xf9+8.0x58+4.RM2,4.RN0!RM2:D1:::exthu
441"exthu"
442*am33
443{
444 int srcreg, dstreg;
445
446 PC = cia;
9c55817e
JL		 447 srcreg = translate_rreg (SD_, RM2);
448 dstreg = translate_rreg (SD_, RN0);
0f7d7385
JL		 449 State.regs[dstreg] = State.regs[srcreg] & 0xffff;
450}
451
452// 1111 1001 0110 1000 Rn Rn; clr Rn
4538.0xf9+8.0x68+4.RM2,4.RN0=RM2:D1:::clr
454"clr"
455*am33
456{
9c55817e 457 int dstreg;
0f7d7385
JL		 458
459 PC = cia;
9c55817e 460 dstreg = translate_rreg (SD_, RN0);
0f7d7385 461 State.regs[dstreg] = 0;
0f7d7385
JL		 462 PSW |= PSW_Z;
463 PSW &= ~(PSW_V | PSW_C | PSW_N);
464}
465
466// 1111 1001 0111 1000 Rm Rn; add Rm,Rn
4678.0xf9+8.0x78+4.RM2,4.RN0:D1b:::add
468"add"
469*am33
470{
471 int srcreg, dstreg;
472
473 PC = cia;
9c55817e
JL		 474 srcreg = translate_rreg (SD_, RM2);
475 dstreg = translate_rreg (SD_, RN0);
0f7d7385
JL		 476 genericAdd (State.regs[srcreg], dstreg);
477}
478
479// 1111 1001 1000 1000 Rm Rn; addc Rm,Rn
4808.0xf9+8.0x88+4.RM2,4.RN0:D1b:::addc
481"addc"
482*am33
483{
484 int srcreg, dstreg;
485 int z, c, n, v;
486 unsigned long reg1, reg2, sum;
487
488 PC = cia;
9c55817e
JL		 489 srcreg = translate_rreg (SD_, RM2);
490 dstreg = translate_rreg (SD_, RN0);
0f7d7385
JL		 491
492 reg1 = State.regs[srcreg];
493 reg2 = State.regs[dstreg];
494 sum = reg1 + reg2 + ((PSW & PSW_C) != 0);
495 State.regs[dstreg] = sum;
496
4e86afb8 497 z = ((PSW & PSW_Z) != 0) && (sum == 0);
0f7d7385
JL		 498 n = (sum & 0x80000000);
499 c = (sum < reg1) || (sum < reg2);
500 v = ((reg2 & 0x80000000) == (reg1 & 0x80000000)
501 && (reg2 & 0x80000000) != (sum & 0x80000000));
502
503 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
504 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
505 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
506}
507
508// 1111 1001 1001 1000 Rm Rn; sub Rm,Rn
5098.0xf9+8.0x98+4.RM2,4.RN0:D1b:::sub
510"sub"
511*am33
512{
513 int srcreg, dstreg;
514
515 PC = cia;
9c55817e
JL		 516 srcreg = translate_rreg (SD_, RM2);
517 dstreg = translate_rreg (SD_, RN0);
0f7d7385
JL		 518 genericSub (State.regs[srcreg], dstreg);
519}
520
521// 1111 1001 1010 1000 Rm Rn; subc Rm,Rn
5228.0xf9+8.0xa8+4.RM2,4.RN0:D1b:::subc
523"subc"
524*am33
525{
526 int srcreg, dstreg;
527 int z, c, n, v;
528 unsigned long reg1, reg2, difference;
529
530 PC = cia;
9c55817e
JL		 531 srcreg = translate_rreg (SD_, RM2);
532 dstreg = translate_rreg (SD_, RN0);
0f7d7385
JL		 533
534 reg1 = State.regs[srcreg];
535 reg2 = State.regs[dstreg];
536 difference = reg2 - reg1 - ((PSW & PSW_C) != 0);
537 State.regs[dstreg] = difference;
538
4e86afb8 539 z = ((PSW & PSW_Z) != 0) && (difference == 0);
0f7d7385
JL		 540 n = (difference & 0x80000000);
541 c = (reg1 > reg2);
542 v = ((reg2 & 0x80000000) == (reg1 & 0x80000000)
543 && (reg2 & 0x80000000) != (difference & 0x80000000));
544
545 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
546 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
547 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
548}
549
550// 1111 1001 1011 1000 Rn Rn; inc Rn
5518.0xf9+8.0xb8+4.RN0,4.RN2=RN0:D1:::inc
552"inc"
553*am33
554{
555 int dstreg;
556
557 PC = cia;
9c55817e 558 dstreg = translate_rreg (SD_, RN0);
0f7d7385
JL		 559 genericAdd (1, dstreg);
560}
561
562// 1111 1001 1101 1000 Rn Rn; inc Rn
5638.0xf9+8.0xc8+4.RN0,4.RN2=RN0:D1:::inc4
564"inc4"
565*am33
566{
567 int dstreg;
568
569 PC = cia;
9c55817e 570 dstreg = translate_rreg (SD_, RN0);
0f7d7385
JL		 571 State.regs[dstreg] += 4;
572}
573
574// 1111 1001 1101 1000 Rm Rn; cmp Rm,Rn
5758.0xf9+8.0xd8+4.RM2,4.RN0:D1:::cmp
576"cmp"
577*am33
578{
579 int srcreg1, srcreg2;
580
581 PC = cia;
9c55817e
JL		 582 srcreg1 = translate_rreg (SD_, RN0);
583 srcreg2 = translate_rreg (SD_, RM2);
0f7d7385
JL		 584 genericCmp (State.regs[srcreg2], State.regs[srcreg1]);
585}
586
587// 1111 1001 1110 1000 XRm Rn; mov XRm,Rn
5888.0xf9+8.0xe8+4.XRM2,4.RN0:D1l:::mov
589"mov"
590*am33
591{
9c55817e 592 int dstreg;
0f7d7385
JL		 593
594 PC = cia;
9c55817e 595 dstreg = translate_rreg (SD_, RN0);
0f7d7385
JL		 596
597 if (XRM2 == 0)
598 {
599 State.regs[dstreg] = State.regs[REG_SP];
600 }
601 else
602 abort ();
603}
604
605// 1111 1001 1111 1000 Rm XRn; mov Rm,XRn
6068.0xf9+8.0xf8+4.RM2,4.XRN0:D1m:::mov
607"mov"
608*am33
609{
610 int srcreg;
611
612 PC = cia;
9c55817e 613 srcreg = translate_rreg (SD_, RM2);
0f7d7385
JL		 614
615 if (XRN0 == 0)
616 {
617 State.regs[REG_SP] = State.regs[srcreg];
618 }
619 else
620 abort ();
621}
622
623// 1111 1001 0000 1001 Rm Rn; and Rm,Rn
6248.0xf9+8.0x09+4.RM2,4.RN0:D1a:::and
625"and"
626*am33
627{
628 int srcreg, dstreg;
629 int z, n;
630
631 PC = cia;
632
9c55817e
JL		 633 srcreg = translate_rreg (SD_, RM2);
634 dstreg = translate_rreg (SD_, RN0);
0f7d7385
JL		 635
636 State.regs[dstreg] &= State.regs[srcreg];
637 z = (State.regs[dstreg] == 0);
638 n = (State.regs[dstreg] & 0x80000000) != 0;
639 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
640 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
641}
642
643// 1111 1001 0001 1001 Rm Rn; or Rm,Rn
6448.0xf9+8.0x19+4.RM2,4.RN0:D1a:::or
645"or"
646*am33
647{
648 int srcreg, dstreg;
649 int z, n;
650
651 PC = cia;
9c55817e
JL		 652 srcreg = translate_rreg (SD_, RM2);
653 dstreg = translate_rreg (SD_, RN0);
0f7d7385
JL		 654
655 State.regs[dstreg] |= State.regs[srcreg];
656 z = (State.regs[dstreg] == 0);
657 n = (State.regs[dstreg] & 0x80000000) != 0;
658 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
659 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
660}
661
662// 1111 1001 0010 1001 Rm Rn; xor Rm,Rn
6638.0xf9+8.0x29+4.RM2,4.RN0:D1a:::xor
664"xor"
665*am33
666{
667 int srcreg, dstreg;
668 int z, n;
669
670 PC = cia;
9c55817e
JL		 671 srcreg = translate_rreg (SD_, RM2);
672 dstreg = translate_rreg (SD_, RN0);
0f7d7385
JL		 673
674 State.regs[dstreg] ^= State.regs[srcreg];
675 z = (State.regs[dstreg] == 0);
676 n = (State.regs[dstreg] & 0x80000000) != 0;
677 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
678 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
679}
680
681// 1111 1001 0011 1001 Rn Rn; not Rn
6828.0xf9+8.0x39+4.RM2,4.RN0=RM2:D1:::not
683"not"
684*am33
685{
686 int dstreg;
687 int z, n;
688
689 PC = cia;
9c55817e 690 dstreg = translate_rreg (SD_, RN0);
0f7d7385
JL		 691
692 State.regs[dstreg] = ~State.regs[dstreg];
693 z = (State.regs[dstreg] == 0);
694 n = (State.regs[dstreg] & 0x80000000) != 0;
695 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
696 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
697}
698
699// 1111 1001 0100 1001 Rm Rn; asr Rm,Rn
7008.0xf9+8.0x49+4.RM2,4.RN0:D1a:::asr
701"asr"
702*am33
703{
704 int srcreg, dstreg;
705 long temp;
706 int c, z, n;
707
708 PC = cia;
9c55817e
JL		 709 srcreg = translate_rreg (SD_, RM2);
710 dstreg = translate_rreg (SD_, RN0);
0f7d7385
JL		 711
712 temp = State.regs[dstreg];
713 c = temp & 1;
714 temp >>= State.regs[srcreg];
715 State.regs[dstreg] = temp;
716 z = (State.regs[dstreg] == 0);
717 n = (State.regs[dstreg] & 0x80000000) != 0;
718 PSW &= ~(PSW_Z | PSW_N | PSW_C);
719 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
720}
721
722// 1111 1001 0101 1001 Rm Rn; lsr Rm,Rn
7238.0xf9+8.0x59+4.RM2,4.RN0:D1a:::lsr
724"lsr"
725*am33
726{
727 int srcreg, dstreg;
728 int z, n, c;
729
730 PC = cia;
731
9c55817e
JL		 732 srcreg = translate_rreg (SD_, RM2);
733 dstreg = translate_rreg (SD_, RN0);
0f7d7385
JL		 734
735 c = State.regs[dstreg] & 1;
736 State.regs[dstreg] >>= State.regs[srcreg];
737 z = (State.regs[dstreg] == 0);
738 n = (State.regs[dstreg] & 0x80000000) != 0;
739 PSW &= ~(PSW_Z | PSW_N | PSW_C);
740 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
741}
742
743// 1111 1001 0110 1001 Rm Rn; asl Rm,Rn
7448.0xf9+8.0x69+4.RM2,4.RN0:D1a:::asl
745"asl"
746*am33
747{
748 int srcreg, dstreg;
749 int z, n;
750
751 PC = cia;
9c55817e
JL		 752 srcreg = translate_rreg (SD_, RM2);
753 dstreg = translate_rreg (SD_, RN0);
0f7d7385
JL		 754
755 State.regs[dstreg] <<= State.regs[srcreg];
756 z = (State.regs[dstreg] == 0);
757 n = (State.regs[dstreg] & 0x80000000) != 0;
758 PSW &= ~(PSW_Z | PSW_N);
759 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
760}
761
762// 1111 1001 0111 1001 Rn Rn; asl2 Rn
7638.0xf9+8.0x79+4.RM2,4.RN0=RM2:D1:::asl2
764"asl2"
765*am33
766{
767 int dstreg;
768 int n, z;
769
770 PC = cia;
9c55817e 771 dstreg = translate_rreg (SD_, RN0);
0f7d7385
JL		 772
773 State.regs[dstreg] <<= 2;
774 z = (State.regs[dstreg] == 0);
775 n = (State.regs[dstreg] & 0x80000000) != 0;
776 PSW &= ~(PSW_Z | PSW_N);
777 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
778}
779
780// 1111 1001 1000 1001 Rn Rn; ror Rn
7818.0xf9+8.0x89+4.RM2,4.RN0=RM2:D1:::ror
782"ror"
783*am33
784{
785 int dstreg;
786 int c, n, z;
787 unsigned long value;
788
789 PC = cia;
9c55817e 790 dstreg = translate_rreg (SD_, RN0);
0f7d7385
JL		 791
792 value = State.regs[dstreg];
793 c = (value & 0x1);
794
795 value >>= 1;
796 value |= ((PSW & PSW_C) != 0) ? 0x80000000 : 0;
797 State.regs[dstreg] = value;
798 z = (value == 0);
799 n = (value & 0x80000000) != 0;
800 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
801 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
802}
803
804// 1111 1001 1001 1001 Rn Rn; rol Rn
8058.0xf9+8.0x99+4.RM2,4.RN0=RM2:D1:::rol
806"rol"
807*am33
808{
809 int dstreg;
810 int c, n, z;
811 unsigned long value;
812
813 PC = cia;
9c55817e 814 dstreg = translate_rreg (SD_, RN0);
0f7d7385
JL		 815
816 value = State.regs[dstreg];
817 c = (value & 0x80000000) ? 1 : 0;
818
819 value <<= 1;
820 value |= ((PSW & PSW_C) != 0);
821 State.regs[dstreg] = value;
822 z = (value == 0);
823 n = (value & 0x80000000) != 0;
824 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
825 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
826}
827
828// 1111 1001 1010 1001 Rm Rn; mul Rm,Rn
8298.0xf9+8.0xa9+4.RM2,4.RN0:D1b:::mul
830"mul"
831*am33
832{
833 int srcreg, dstreg;
834 unsigned long long temp;
835 int n, z;
836
837 PC = cia;
9c55817e
JL		 838 srcreg = translate_rreg (SD_, RM2);
839 dstreg = translate_rreg (SD_, RN0);
0f7d7385
JL		 840
841 temp = ((signed64)(signed32)State.regs[dstreg]
842 * (signed64)(signed32)State.regs[srcreg]);
843 State.regs[dstreg] = temp & 0xffffffff;
844 State.regs[REG_MDR] = (temp & 0xffffffff00000000LL) >> 32;;
845 z = (State.regs[dstreg] == 0);
846 n = (State.regs[dstreg] & 0x80000000) != 0;
847 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
848 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
849}
850
851// 1111 1001 1011 1001 Rm Rn; mulu Rm,Rn
8528.0xf9+8.0xb9+4.RM2,4.RN0:D1b:::mulu
853"mulu"
854*am33
855{
856 int srcreg, dstreg;
857 unsigned long long temp;
858 int n, z;
859
860 PC = cia;
9c55817e
JL		 861 srcreg = translate_rreg (SD_, RM2);
862 dstreg = translate_rreg (SD_, RN0);
0f7d7385
JL		 863
864 temp = ((unsigned64)State.regs[dstreg]
865 * (unsigned64)State.regs[srcreg]);
866 State.regs[dstreg] = temp & 0xffffffff;
867 State.regs[REG_MDR] = (temp & 0xffffffff00000000LL) >> 32;
868 z = (State.regs[dstreg] == 0);
869 n = (State.regs[dstreg] & 0x80000000) != 0;
870 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
871 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
872}
873
874// 1111 1001 1100 1001 Rm Rn; div Rm,Rn
8758.0xf9+8.0xc9+4.RM2,4.RN0:D1b:::div
876"div"
877*am33
878{
879 int srcreg, dstreg;
377e53bb 880 long long temp;
0f7d7385
JL		 881 int n, z;
882
883 PC = cia;
9c55817e
JL		 884 srcreg = translate_rreg (SD_, RM2);
885 dstreg = translate_rreg (SD_, RN0);
0f7d7385
JL		 886
887 temp = State.regs[REG_MDR];
888 temp <<= 32;
889 temp |= State.regs[dstreg];
377e53bb 890 State.regs[REG_MDR] = temp % (signed32)State.regs[srcreg];
4e86afb8 891 temp /= (signed32)State.regs[srcreg];
0f7d7385
JL		 892 State.regs[dstreg] = temp & 0xffffffff;
893 z = (State.regs[dstreg] == 0);
894 n = (State.regs[dstreg] & 0x80000000) != 0;
895 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
896 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
897}
898
899// 1111 1001 1101 1001 Rm Rn; divu Rm,Rn
9008.0xf9+8.0xd9+4.RM2,4.RN0:D1b:::divu
901"divu"
902*am33
903{
904 int srcreg, dstreg;
905 unsigned long long temp;
906 int n, z;
907
908 PC = cia;
9c55817e
JL		 909 srcreg = translate_rreg (SD_, RM2);
910 dstreg = translate_rreg (SD_, RN0);
0f7d7385
JL		 911
912 temp = State.regs[REG_MDR];
913 temp <<= 32;
914 temp |= State.regs[dstreg];
915 State.regs[REG_MDR] = temp % State.regs[srcreg];
916 temp /= State.regs[srcreg];
917 State.regs[dstreg] = temp & 0xffffffff;
918 z = (State.regs[dstreg] == 0);
919 n = (State.regs[dstreg] & 0x80000000) != 0;
920 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
921 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
922}
923
924
925// 1111 1001 0000 1010 Rm Rn; mov (Rm),Rn
3e75ff7e 9268.0xf9+8.0x0a+4.RN2,4.RM0:D1h:::mov
0f7d7385
JL		 927"mov"
928*am33
929{
930 int srcreg, dstreg;
931
932 PC = cia;
9c55817e
JL		 933 srcreg = translate_rreg (SD_, RM0);
934 dstreg = translate_rreg (SD_, RN2);
0f7d7385
JL		 935 State.regs[dstreg] = load_word (State.regs[srcreg]);
936}
937
938// 1111 1001 0001 1010 Rm Rn; mov Rm,(Rn)
9398.0xf9+8.0x1a+4.RM2,4.RN0:D1i:::mov
940"mov"
941*am33
942{
943 int srcreg, dstreg;
944
945 PC = cia;
9c55817e
JL		 946 srcreg = translate_rreg (SD_, RM2);
947 dstreg = translate_rreg (SD_, RN0);
0f7d7385
JL		 948 store_word (State.regs[dstreg], State.regs[srcreg]);
949}
950
951// 1111 1001 0010 1010 Rm Rn; movbu (Rm),Rn
3e75ff7e 9528.0xf9+8.0x2a+4.RN2,4.RM0:D1g:::movbu
0f7d7385
JL		 953"movbu"
954*am33
955{
956 int srcreg, dstreg;
957
958 PC = cia;
9c55817e
JL		 959 srcreg = translate_rreg (SD_, RM0);
960 dstreg = translate_rreg (SD_, RN2);
0f7d7385
JL		 961 State.regs[dstreg] = load_byte (State.regs[srcreg]);
962}
963
964// 1111 1001 0011 1010 Rm Rn; movbu Rm,(Rn)
9658.0xf9+8.0x3a+4.RM2,4.RN0:D1i:::movbu
966"movbu"
967*am33
968{
969 int srcreg, dstreg;
970
971 PC = cia;
9c55817e
JL		 972 srcreg = translate_rreg (SD_, RM2);
973 dstreg = translate_rreg (SD_, RN0);
0f7d7385
JL		 974 store_byte (State.regs[dstreg], State.regs[srcreg]);
975}
976
977// 1111 1001 0100 1010 Rm Rn; movhu (Rm),Rn
3e75ff7e 9788.0xf9+8.0x4a+4.RN2,4.RM0:D1g:::movhu
0f7d7385
JL		 979"movhu"
980*am33
981{
982 int srcreg, dstreg;
983
984 PC = cia;
9c55817e
JL		 985 srcreg = translate_rreg (SD_, RM0);
986 dstreg = translate_rreg (SD_, RN2);
0f7d7385
JL		 987 State.regs[dstreg] = load_half (State.regs[srcreg]);
988}
989
990// 1111 1001 0101 1010 Rm Rn; movhu Rm,(Rn)
9918.0xf9+8.0x5a+4.RM2,4.RN0:D1i:::movhu
992"movhu"
993*am33
994{
995 int srcreg, dstreg;
996
997 PC = cia;
9c55817e
JL		 998 srcreg = translate_rreg (SD_, RM2);
999 dstreg = translate_rreg (SD_, RN0);
0f7d7385
JL		 1000 store_half (State.regs[dstreg], State.regs[srcreg]);
1001}
1002
377e53bb
JL		 1003// 1111 1001 0110 1010 Rm Rn; mov (Rm+),Rn
10048.0xf9+8.0x6a+4.RN2,4.RM0:D1y:::mov
1005"mov"
1006*am33
1007{
1008 int srcreg, dstreg;
1009
1010 PC = cia;
9c55817e
JL		 1011 srcreg = translate_rreg (SD_, RM0);
1012 dstreg = translate_rreg (SD_, RN2);
377e53bb
JL		 1013 State.regs[dstreg] = load_word (State.regs[srcreg]);
1014 State.regs[srcreg] += 4;
1015}
1016
1017// 1111 1001 0111 1010 Rm Rn; mov Rm,(Rn+)
10188.0xf9+8.0x7a+4.RM2,4.RN0:D1z:::mov
1019"mov"
1020*am33
1021{
1022 int srcreg, dstreg;
1023
1024 PC = cia;
9c55817e
JL		 1025 srcreg = translate_rreg (SD_, RM2);
1026 dstreg = translate_rreg (SD_, RN0);
377e53bb
JL		 1027 store_word (State.regs[dstreg], State.regs[srcreg]);
1028 State.regs[dstreg] += 4;
1029}
0f7d7385
JL		 1030
1031// 1111 1001 1000 1010 Rn 0000; mov (sp),Rn
10328.0xf9+8.0x8a+4.RN2,4.0000:D1j:::mov
1033"mov"
1034*am33
1035{
9c55817e 1036 int dstreg;
0f7d7385
JL		 1037
1038 PC = cia;
9c55817e 1039 dstreg = translate_rreg (SD_, RN2);
0f7d7385
JL		 1040 State.regs[dstreg] = load_word (State.regs[REG_SP]);
1041}
1042
1043// 1111 1001 1001 1010 Rm 0000; mov Rm, (sp)
10448.0xf9+8.0x9a+4.RM2,4.0000:D1k:::mov
1045"mov"
1046*am33
1047{
9c55817e 1048 int srcreg;
0f7d7385
JL		 1049
1050 PC = cia;
9c55817e
JL		 1051 srcreg = translate_rreg (SD_, RM2);
1052 store_word (State.regs[REG_SP], State.regs[srcreg]);
0f7d7385
JL		 1053}
1054
1055// 1111 1001 1010 1010 Rn 0000; mobvu (sp),Rn
10568.0xf9+8.0xaa+4.RN2,4.0000:D1j:::movbu
1057"movbu"
1058*am33
1059{
9c55817e 1060 int dstreg;
0f7d7385
JL		 1061
1062 PC = cia;
9c55817e 1063 dstreg = translate_rreg (SD_, RN2);
0f7d7385
JL		 1064 State.regs[dstreg] = load_byte (State.regs[REG_SP]);
1065}
1066
1067// 1111 1001 1011 1010 Rm 0000; movbu Rm, (sp)
10688.0xf9+8.0xba+4.RM2,4.0000:D1k:::movbu
1069"movbu"
1070*am33
1071{
9c55817e 1072 int srcreg;
0f7d7385
JL		 1073
1074 PC = cia;
9c55817e
JL		 1075 srcreg = translate_rreg (SD_, RM2);
1076 store_byte (State.regs[REG_SP], State.regs[srcreg]);
0f7d7385
JL		 1077}
1078
1079// 1111 1001 1000 1100 Rn 0000; movhu (sp),Rn
10808.0xf9+8.0xca+4.RN2,4.0000:D1j:::movhu
1081"movhu"
1082*am33
1083{
9c55817e 1084 int dstreg;
0f7d7385
JL		 1085
1086 PC = cia;
9c55817e 1087 dstreg = translate_rreg (SD_, RN2);
0f7d7385
JL		 1088 State.regs[dstreg] = load_half (State.regs[REG_SP]);
1089}
1090
1091// 1111 1001 1001 1101 Rm 0000; movhu Rm, (sp)
10928.0xf9+8.0xda+4.RM2,4.0000:D1k:::movhu
1093"movhu"
1094*am33
1095{
9c55817e 1096 int srcreg;
0f7d7385
JL		 1097
1098 PC = cia;
9c55817e
JL		 1099 srcreg = translate_rreg (SD_, RM2);
1100 store_half (State.regs[REG_SP], State.regs[srcreg]);
0f7d7385
JL		 1101}
1102
377e53bb
JL		 1103// 1111 1001 1110 1010 Rm Rn; movhu (Rm+),Rn
11048.0xf9+8.0xea+4.RN2,4.RM0:D1y:::movhu
1105"movhu"
0f7d7385
JL		 1106*am33
1107{
377e53bb 1108 int srcreg, dstreg;
0f7d7385
JL		 1109
1110 PC = cia;
9c55817e
JL		 1111 srcreg = translate_rreg (SD_, RM0);
1112 dstreg = translate_rreg (SD_, RN2);
377e53bb
JL		 1113 State.regs[dstreg] = load_half (State.regs[srcreg]);
1114 State.regs[srcreg] += 2;
0f7d7385
JL		 1115}
1116
377e53bb
JL		 1117// 1111 1001 1111 1010 Rm Rn; movhu Rm,(Rn+)
11188.0xf9+8.0xfa+4.RM2,4.RN0:D1z:::movhu
1119"movhu"
0f7d7385
JL		 1120*am33
1121{
377e53bb 1122 int srcreg, dstreg;
0f7d7385
JL		 1123
1124 PC = cia;
9c55817e
JL		 1125 srcreg = translate_rreg (SD_, RM2);
1126 dstreg = translate_rreg (SD_, RN0);
377e53bb
JL		 1127 store_half (State.regs[dstreg], State.regs[srcreg]);
1128 State.regs[dstreg] += 2;
0f7d7385
JL		 1129}
1130
377e53bb
JL		 1131
1132// 1111 1001 0000 1011 Rm Rn; mac Rm,Rn
11338.0xf9+8.0x0b+4.RM2,4.RN0:D1:::mac
1134"mac"
0f7d7385
JL		 1135*am33
1136{
377e53bb
JL		 1137 int srcreg1, srcreg2;
1138 long long temp, sum;
1139 int c, v;
0f7d7385
JL		 1140
1141 PC = cia;
9c55817e
JL		 1142 srcreg1 = translate_rreg (SD_, RM2);
1143 srcreg2 = translate_rreg (SD_, RN0);
0f7d7385 1144
4e86afb8
JL		 1145 temp = ((signed64)(signed32)State.regs[srcreg2]
1146 * (signed64)(signed32)State.regs[srcreg1]);
377e53bb
JL		 1147 sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
1148 c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
1149 State.regs[REG_MCRL] = sum;
1150 temp >>= 32;
1151 temp &= 0xffffffff;
1152 sum = State.regs[REG_MCRH] + temp + c;
1153 v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
1154 && (temp & 0x80000000) != (sum & 0x80000000));
1155 State.regs[REG_MCRH] = sum;
1156 if (v)
1157 State.regs[REG_MCVF] = 1;
0f7d7385
JL		 1158}
1159
377e53bb
JL		 1160// 1111 1001 0001 1011 Rm Rn; macu Rm,Rn
11618.0xf9+8.0x1b+4.RM2,4.RN0:D1:::macu
1162"macu"
0f7d7385
JL		 1163*am33
1164{
377e53bb
JL		 1165 int srcreg1, srcreg2;
1166 unsigned long long temp, sum;
1167 int c, v;
0f7d7385
JL		 1168
1169 PC = cia;
9c55817e
JL		 1170 srcreg1 = translate_rreg (SD_, RM2);
1171 srcreg2 = translate_rreg (SD_, RN0);
0f7d7385 1172
377e53bb
JL		 1173 temp = ((unsigned64)State.regs[srcreg2]
1174 * (unsigned64)State.regs[srcreg1]);
1175 sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
1176 c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
1177 State.regs[REG_MCRL] = sum;
1178 temp >>= 32;
1179 temp &= 0xffffffff;
1180 sum = State.regs[REG_MCRH] + temp + c;
1181 v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
1182 && (temp & 0x80000000) != (sum & 0x80000000));
1183 State.regs[REG_MCRH] = sum;
1184 if (v)
1185 State.regs[REG_MCVF] = 1;
0f7d7385
JL		 1186}
1187
377e53bb
JL		 1188// 1111 1001 0010 1011 Rm Rn; macb Rm,Rn
11898.0xf9+8.0x2b+4.RM2,4.RN0:D1:::macb
1190"macb"
0f7d7385
JL		 1191*am33
1192{
377e53bb
JL		 1193 int srcreg1, srcreg2;
1194 long temp, sum;
1195 int v;
0f7d7385
JL		 1196
1197 PC = cia;
9c55817e
JL		 1198 srcreg1 = translate_rreg (SD_, RM2);
1199 srcreg2 = translate_rreg (SD_, RN0);
0f7d7385 1200
4e86afb8
JL		 1201 temp = ((signed32)(signed8)(State.regs[srcreg2] & 0xff)
1202 * (signed32)(signed8)(State.regs[srcreg1] & 0xff));
377e53bb
JL		 1203 sum = State.regs[REG_MCRL] + temp;
1204 v = ((State.regs[REG_MCRL] & 0x80000000) == (temp & 0x80000000)
1205 && (temp & 0x80000000) != (sum & 0x80000000));
1206 State.regs[REG_MCRL] = sum;
1207 if (v)
1208 State.regs[REG_MCVF] = 1;
0f7d7385
JL		 1209}
1210
377e53bb
JL		 1211// 1111 1001 0011 1011 Rm Rn; macbu Rm,Rn
12128.0xf9+8.0x3b+4.RM2,4.RN0:D1:::macbu
1213"macbu"
0f7d7385
JL		 1214*am33
1215{
377e53bb
JL		 1216 int srcreg1, srcreg2;
1217 long long temp, sum;
1218 int v;
0f7d7385
JL		 1219
1220 PC = cia;
9c55817e
JL		 1221 srcreg1 = translate_rreg (SD_, RM2);
1222 srcreg2 = translate_rreg (SD_, RN0);
0f7d7385 1223
377e53bb
JL		 1224 temp = ((unsigned32)(State.regs[srcreg2] & 0xff)
1225 * (unsigned32)(State.regs[srcreg1] & 0xff));
1226 sum = State.regs[REG_MCRL] + temp;
1227 v = ((State.regs[REG_MCRL] & 0x80000000) == (temp & 0x80000000)
1228 && (temp & 0x80000000) != (sum & 0x80000000));
1229 State.regs[REG_MCRL] = sum;
1230 if (v)
1231 State.regs[REG_MCVF] = 1;
0f7d7385
JL		 1232}
1233
377e53bb
JL		 1234// 1111 1001 0100 1011 Rm Rn; mach Rm,Rn
12358.0xf9+8.0x4b+4.RM2,4.RN0:D1:::mach
1236"mach"
0f7d7385
JL		 1237*am33
1238{
377e53bb
JL		 1239 int srcreg1, srcreg2;
1240 long long temp, sum;
1241 int c, v;
0f7d7385
JL		 1242
1243 PC = cia;
9c55817e
JL		 1244 srcreg1 = translate_rreg (SD_, RM2);
1245 srcreg2 = translate_rreg (SD_, RN0);
0f7d7385 1246
4e86afb8
JL		 1247 temp = ((unsigned64)(signed16)(State.regs[srcreg2] & 0xffff)
1248 * (unsigned64)(signed16)(State.regs[srcreg1] & 0xffff));
377e53bb
JL		 1249 sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
1250 c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
1251 State.regs[REG_MCRL] = sum;
1252 temp >>= 32;
1253 temp &= 0xffffffff;
1254 sum = State.regs[REG_MCRH] + temp + c;
1255 v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
1256 && (temp & 0x80000000) != (sum & 0x80000000));
1257 State.regs[REG_MCRH] = sum;
1258 if (v)
1259 State.regs[REG_MCVF] = 1;
0f7d7385
JL		 1260}
1261
377e53bb
JL		 1262// 1111 1001 0101 1011 Rm Rn; machu Rm,Rn
12638.0xf9+8.0x5b+4.RM2,4.RN0:D1:::machu
1264"machu"
0f7d7385
JL		 1265*am33
1266{
377e53bb
JL		 1267 int srcreg1, srcreg2;
1268 long long temp, sum;
1269 int c, v;
0f7d7385
JL		 1270
1271 PC = cia;
9c55817e
JL		 1272 srcreg1 = translate_rreg (SD_, RM2);
1273 srcreg2 = translate_rreg (SD_, RN0);
377e53bb
JL		 1274
1275 temp = ((unsigned64)(State.regs[srcreg2] & 0xffff)
1276 * (unsigned64)(State.regs[srcreg1] & 0xffff));
1277 sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
1278 c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
1279 State.regs[REG_MCRL] = sum;
1280 temp >>= 32;
1281 temp &= 0xffffffff;
1282 sum = State.regs[REG_MCRH] + temp + c;
1283 v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
1284 && (temp & 0x80000000) != (sum & 0x80000000));
1285 State.regs[REG_MCRH] = sum;
1286 if (v)
1287 State.regs[REG_MCVF] = 1;
0f7d7385
JL		 1288}
1289
377e53bb
JL		 1290// 1111 1001 0110 1011 Rm Rn; dmach Rm,Rn
12918.0xf9+8.0x6b+4.RM2,4.RN0:D1:::dmach
1292"dmach"
0f7d7385
JL		 1293*am33
1294{
377e53bb
JL		 1295 int srcreg1, srcreg2;
1296 long temp, temp2, sum;
1297 int v;
0f7d7385
JL		 1298
1299 PC = cia;
9c55817e
JL		 1300 srcreg1 = translate_rreg (SD_, RM2);
1301 srcreg2 = translate_rreg (SD_, RN0);
0f7d7385 1302
4e86afb8
JL		 1303 temp = ((signed32)(signed16)(State.regs[srcreg2] & 0xffff)
1304 * (signed32)(signed16)(State.regs[srcreg1] & 0xffff));
1305 temp2 = ((signed32)(signed16)((State.regs[srcreg1] >> 16) & 0xffff)
1306 * (signed32)(signed16)((State.regs[srcreg2] >> 16) & 0xffff));
377e53bb
JL		 1307 sum = temp + temp2 + State.regs[REG_MCRL];
1308 v = ((State.regs[REG_MCRL] & 0x80000000) == (temp & 0x80000000)
1309 && (temp & 0x80000000) != (sum & 0x80000000));
1310 State.regs[REG_MCRL] = sum;
1311 if (v)
1312 State.regs[REG_MCVF] = 1;
0f7d7385
JL		 1313}
1314
377e53bb
JL		 1315// 1111 1001 0111 1011 Rm Rn; dmachu Rm,Rn
13168.0xf9+8.0x7b+4.RM2,4.RN0:D1:::dmachu
1317"dmachu"
0f7d7385
JL		 1318*am33
1319{
377e53bb
JL		 1320 int srcreg1, srcreg2;
1321 unsigned long temp, temp2, sum;
1322 int v;
0f7d7385
JL		 1323
1324 PC = cia;
9c55817e
JL		 1325 srcreg1 = translate_rreg (SD_, RM2);
1326 srcreg2 = translate_rreg (SD_, RN0);
0f7d7385 1327
377e53bb
JL		 1328 temp = ((unsigned32)(State.regs[srcreg2] & 0xffff)
1329 * (unsigned32)(State.regs[srcreg1] & 0xffff));
1330 temp2 = ((unsigned32)((State.regs[srcreg1] >> 16) & 0xffff)
1331 * (unsigned32)((State.regs[srcreg2] >> 16) & 0xffff));
1332 sum = temp + temp2 + State.regs[REG_MCRL];
1333 v = ((State.regs[REG_MCRL] & 0x80000000) == (temp & 0x80000000)
1334 && (temp & 0x80000000) != (sum & 0x80000000));
1335 State.regs[REG_MCRL] = sum;
1336 if (v)
1337 State.regs[REG_MCVF] = 1;
0f7d7385
JL		 1338}
1339
377e53bb
JL		 1340// 1111 1001 1000 1011 Rm Rn; dmulh Rm,Rn
13418.0xf9+8.0x8b+4.RM2,4.RN0:D1:::dmulh
1342"dmulh"
0f7d7385
JL		 1343*am33
1344{
377e53bb
JL		 1345 int srcreg, dstreg;
1346 long temp;
0f7d7385
JL		 1347
1348 PC = cia;
9c55817e
JL		 1349 srcreg = translate_rreg (SD_, RM2);
1350 dstreg = translate_rreg (SD_, RN0);
0f7d7385 1351
4e86afb8
JL		 1352 temp = ((signed32)(signed16)(State.regs[dstreg] & 0xffff)
1353 * (signed32)(signed16)(State.regs[srcreg] & 0xffff));
377e53bb 1354 State.regs[REG_MDRQ] = temp;
4e86afb8
JL		 1355 temp = ((signed32)(signed16)((State.regs[dstreg] >> 16) & 0xffff)
1356 * (signed32)(signed16)((State.regs[srcreg] >>16) & 0xffff));
377e53bb 1357 State.regs[dstreg] = temp;
0f7d7385
JL		 1358}
1359
377e53bb
JL		 1360// 1111 1001 1001 1011 Rm Rn; dmulhu Rm,Rn
13618.0xf9+8.0x9b+4.RM2,4.RN0:D1:::dumachu
1362"dmachu"
0f7d7385
JL		 1363*am33
1364{
377e53bb
JL		 1365 int srcreg, dstreg;
1366 unsigned long temp;
0f7d7385
JL		 1367
1368 PC = cia;
9c55817e
JL		 1369 srcreg = translate_rreg (SD_, RM2);
1370 dstreg = translate_rreg (SD_, RN0);
0f7d7385 1371
377e53bb
JL		 1372 temp = ((unsigned32)(State.regs[dstreg] & 0xffff)
1373 * (unsigned32)(State.regs[srcreg] & 0xffff));
1374 State.regs[REG_MDRQ] = temp;
1375 temp = ((unsigned32)((State.regs[dstreg] >> 16) & 0xffff)
1376 * (unsigned32)((State.regs[srcreg] >>16) & 0xffff));
0f7d7385 1377 State.regs[dstreg] = temp;
0f7d7385
JL		 1378}
1379
377e53bb
JL		 1380// 1111 1001 1010 1011 Rm Rn; sat16 Rm,Rn
13818.0xf9+8.0xab+4.RM2,4.RN0:D1:::sat16
1382"sat16"
0f7d7385
JL		 1383*am33
1384{
377e53bb 1385 int srcreg, dstreg;
4e86afb8 1386 int value, z, n;
0f7d7385
JL		 1387
1388 PC = cia;
9c55817e
JL		 1389 srcreg = translate_rreg (SD_, RM2);
1390 dstreg = translate_rreg (SD_, RN0);
0f7d7385 1391
377e53bb
JL		 1392 value = State.regs[srcreg];
1393
1394 if (value >= 0x7fff)
1395 State.regs[dstreg] = 0x7fff;
1396 else if (value <= 0xffff8000)
1397 State.regs[dstreg] = 0xffff8000;
1398 else
1399 State.regs[dstreg] = value;
4e86afb8
JL		 1400
1401 n = (State.regs[dstreg] & 0x8000) != 0;
1402 z = (State.regs[dstreg] == 0);
1403 PSW &= ~(PSW_Z | PSW_N);
1404 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
0f7d7385
JL		 1405}
1406
1f0ba346
JL		 1407// 1111 1001 1011 1011 Rm Rn; mcste Rm,Rn
14088.0xf9+8.0xbb+4.RM2,4.RN0:D1:::mcste
1409"mcste"
1410*am33
1411{
1412 int srcreg, dstreg;
1413
1414 PC = cia;
1415 srcreg = translate_rreg (SD_, RM2);
1416 dstreg = translate_rreg (SD_, RN0);
1417
1418 PSW &= ~(PSW_V | PSW_C);
1419 PSW |= (State.regs[REG_MCVF] ? PSW_V : 0);
1420
1421 /* 32bit saturation. */
1422 if (State.regs[srcreg] == 0x20)
1423 {
1424 long long tmp;
1425
1426 tmp = State.regs[REG_MCRH];
1427 tmp <<= 32;
1428 tmp += State.regs[REG_MCRL];
1429
1430 if (tmp > 0x7fffffff)
1431 State.regs[dstreg] = 0x7fffffff;
1432 else if (tmp < 0xffffffff80000000LL)
1433 State.regs[dstreg] = 0x80000000;
1434 else
1435 State.regs[dstreg] = tmp;
1436 }
1437 /* 16bit saturation */
1438 else if (State.regs[srcreg] == 0x10)
1439 {
1440 long long tmp;
1441
1442 tmp = State.regs[REG_MCRH];
1443 tmp <<= 32;
1444 tmp += State.regs[REG_MCRL];
1445
1446 if (tmp > 0x7fff)
1447 State.regs[dstreg] = 0x7fff;
1448 else if (tmp < 0xffffffffffff8000LL)
1449 State.regs[dstreg] = 0x8000;
1450 else
1451 State.regs[dstreg] = tmp;
1452 }
1453 /* 8 bit saturation */
1454 else if (State.regs[srcreg] == 0x8)
1455 {
1456 long long tmp;
1457
1458 tmp = State.regs[REG_MCRH];
1459 tmp <<= 32;
1460 tmp += State.regs[REG_MCRL];
1461
1462 if (tmp > 0x7f)
1463 State.regs[dstreg] = 0x7f;
1464 else if (tmp < 0xffffffffffffff80LL)
1465 State.regs[dstreg] = 0x80;
1466 else
1467 State.regs[dstreg] = tmp;
1468 }
1469 /* 9 bit saturation */
1470 else if (State.regs[srcreg] == 0x9)
1471 {
1472 long long tmp;
1473
1474 tmp = State.regs[REG_MCRH];
1475 tmp <<= 32;
1476 tmp += State.regs[REG_MCRL];
1477
1478 if (tmp > 0x80)
1479 State.regs[dstreg] = 0x80;
1480 else if (tmp < 0xffffffffffffff81LL)
1481 State.regs[dstreg] = 0x81;
1482 else
1483 State.regs[dstreg] = tmp;
1484 }
1485 /* 9 bit saturation */
1486 else if (State.regs[srcreg] == 0x30)
1487 {
1488 long long tmp;
1489
1490 tmp = State.regs[REG_MCRH];
1491 tmp <<= 32;
1492 tmp += State.regs[REG_MCRL];
1493
1494 if (tmp > 0x7fffffffffffLL)
1495 tmp = 0x7fffffffffffLL;
1496 else if (tmp < 0xffff800000000000LL)
1497 tmp = 0xffff800000000000LL;
1498
1499 tmp >>= 16;
1500 State.regs[dstreg] = tmp;
1501 }
1502}
377e53bb
JL		 1503
1504// 1111 1001 1100 1011 Rm Rn; swap Rm,Rn
15058.0xf9+8.0xcb+4.RM2,4.RN0:D1:::swap
1506"swap"
0f7d7385
JL		 1507*am33
1508{
1509 int srcreg, dstreg;
0f7d7385 1510
9c55817e
JL		 1511 PC = cia;
1512 srcreg = translate_rreg (SD_, RM2);
1513 dstreg = translate_rreg (SD_, RN0);
0f7d7385 1514
377e53bb
JL		 1515 State.regs[dstreg] = (((State.regs[srcreg] & 0xff) << 24)
1516 | (((State.regs[srcreg] >> 8) & 0xff) << 16)
1517 | (((State.regs[srcreg] >> 16) & 0xff) << 8)
1518 | ((State.regs[srcreg] >> 24) & 0xff));
0f7d7385
JL		 1519}
1520
377e53bb
JL		 1521// 1111 1101 1101 1011 Rm Rn; swaph Rm,Rn
15228.0xf9+8.0xdb+4.RM2,4.RN0:D1:::swaph
1523"swaph"
0f7d7385
JL		 1524*am33
1525{
377e53bb 1526 int srcreg, dstreg;
0f7d7385 1527
9c55817e
JL		 1528 PC = cia;
1529 srcreg = translate_rreg (SD_, RM2);
1530 dstreg = translate_rreg (SD_, RN0);
0f7d7385 1531
377e53bb
JL		 1532 State.regs[dstreg] = (((State.regs[srcreg] & 0xff) << 8)
1533 | ((State.regs[srcreg] >> 8) & 0xff)
1534 | (((State.regs[srcreg] >> 16) & 0xff) << 24)
1535 | (((State.regs[srcreg] >> 24) & 0xff) << 16));
0f7d7385
JL		 1536}
1537
377e53bb
JL		 1538// 1111 1001 1110 1011 Rm Rn; swhw Rm,Rn
15398.0xf9+8.0xeb+4.RM2,4.RN0:D1:::swhw
1540"swhw"
0f7d7385
JL		 1541*am33
1542{
377e53bb 1543 int srcreg, dstreg;
0f7d7385 1544
9c55817e
JL		 1545 PC = cia;
1546 srcreg = translate_rreg (SD_, RM2);
1547 dstreg = translate_rreg (SD_, RN0);
0f7d7385 1548
377e53bb
JL		 1549 State.regs[dstreg] = (((State.regs[srcreg] & 0xffff) << 16)
1550 | ((State.regs[srcreg] >> 16) & 0xffff));
0f7d7385
JL		 1551}
1552
377e53bb
JL		 1553// 1111 1001 1111 1011 Rm Rn; bsch Rm,Rn
15548.0xf9+8.0xfb+4.RM2,4.RN0:D1:::bsch
1555"bsch"
3e75ff7e
JL		 1556*am33
1557{
377e53bb
JL		 1558 int temp, c, i;
1559 int srcreg, dstreg;
1560 int start;
3e75ff7e
JL		 1561
1562 PC = cia;
9c55817e
JL		 1563 srcreg = translate_rreg (SD_, RM2);
1564 dstreg = translate_rreg (SD_, RN0);
377e53bb
JL		 1565
1566 temp = State.regs[srcreg];
1567 start = (State.regs[dstreg] & 0x1f) - 1;
1568 if (start == -1)
1569 start = 31;
1570
1571 for (i = start; i >= 0; i--)
1572 {
1573 if (temp & (1 << i))
1574 {
1575 c = 1;
1576 State.regs[dstreg] = i;
1577 break;
1578 }
1579 }
3e75ff7e 1580
377e53bb
JL		 1581 if (i < 0)
1582 {
1583 c = 0;
1584 State.regs[dstreg] = 0;
1585 }
1586 PSW &= ~(PSW_C);
1587 PSW |= (c ? PSW_C : 0);
3e75ff7e
JL		 1588}
1589
0f7d7385 1590
377e53bb
JL		 1591// 1111 1011 0000 1000 Rn Rn IMM8; mov IMM8,Rn
15928.0xfb+8.0x08+4.RM2,4.RN0=RM2+8.IMM8:D2j:::mov
0f7d7385 1593"mov"
3e75ff7e 1594*am33
0f7d7385 1595{
377e53bb 1596 int dstreg;
0f7d7385
JL		 1597
1598 PC = cia;
9c55817e 1599 dstreg = translate_rreg (SD_, RN0);
377e53bb 1600 State.regs[dstreg] = EXTEND8 (IMM8);
0f7d7385
JL		 1601}
1602
377e53bb
JL		 1603// 1111 1011 0001 1000 Rn Rn IMM8; movu IMM8,Rn
16048.0xfb+8.0x18+4.RM2,4.RN0=RM2+8.IMM8:D2:::movu
1605"movu"
1606*am33
0f7d7385 1607{
377e53bb 1608 int dstreg;
0f7d7385
JL		 1609
1610 PC = cia;
9c55817e 1611 dstreg = translate_rreg (SD_, RN0);
377e53bb 1612 State.regs[dstreg] = IMM8 & 0xff;
0f7d7385
JL		 1613}
1614
377e53bb
JL		 1615// 1111 1011 0111 1000 Rn Rn IMM8; add IMM8,Rn
16168.0xfb+8.0x78+4.RM2,4.RN0=RM2+8.IMM8:D2d:::add
1617"add"
1618*am33
0f7d7385 1619{
377e53bb 1620 int dstreg;
0f7d7385
JL		 1621
1622 PC = cia;
9c55817e 1623 dstreg = translate_rreg (SD_, RN0);
377e53bb 1624 genericAdd (EXTEND8 (IMM8), dstreg);
0f7d7385
JL		 1625}
1626
377e53bb
JL		 1627// 1111 1011 1000 1000 Rn Rn IMM8; addc IMM8,Rn
16288.0xfb+8.0x88+4.RM2,4.RN0=RM2+8.IMM8:D2d:::addc
1629"addc"
1630*am33
0f7d7385 1631{
377e53bb
JL		 1632 int dstreg, imm;
1633 int z, c, n, v;
1634 unsigned long reg1, reg2, sum;
0f7d7385
JL		 1635
1636 PC = cia;
9c55817e 1637 dstreg = translate_rreg (SD_, RN0);
0f7d7385 1638
377e53bb
JL		 1639 imm = EXTEND8 (IMM8);
1640 reg2 = State.regs[dstreg];
1641 sum = imm + reg2 + ((PSW & PSW_C) != 0);
1642 State.regs[dstreg] = sum;
1643
080ee2ba 1644 z = ((PSW & PSW_Z) != 0) && (sum == 0);
377e53bb
JL		 1645 n = (sum & 0x80000000);
1646 c = (sum < imm) || (sum < reg2);
1647 v = ((reg2 & 0x80000000) == (imm & 0x80000000)
1648 && (reg2 & 0x80000000) != (sum & 0x80000000));
1649
1650 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1651 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1652 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
0f7d7385
JL		 1653}
1654
377e53bb
JL		 1655// 1111 1011 1001 1000 Rn Rn IMM8; sub IMM8,Rn
16568.0xfb+8.0x98+4.RM2,4.RN0=RM2+8.IMM8:D2d:::sub
1657"sub"
1658*am33
0f7d7385 1659{
377e53bb 1660 int dstreg;
0f7d7385
JL		 1661
1662 PC = cia;
9c55817e 1663 dstreg = translate_rreg (SD_, RN0);
0f7d7385 1664
377e53bb 1665 genericSub (EXTEND8 (IMM8), dstreg);
0f7d7385
JL		 1666}
1667
377e53bb
JL		 1668// 1111 1011 1010 1000 Rn Rn IMM8; subc IMM8,Rn
16698.0xfb+8.0xa8+4.RM2,4.RN0=RM2+8.IMM8:D2d:::subc
1670"subc"
1671*am33
0f7d7385 1672{
377e53bb
JL		 1673 int imm, dstreg;
1674 int z, c, n, v;
1675 unsigned long reg1, reg2, difference;
0f7d7385
JL		 1676
1677 PC = cia;
9c55817e 1678 dstreg = translate_rreg (SD_, RN0);
0f7d7385 1679
377e53bb
JL		 1680 imm = EXTEND8 (IMM8);
1681 reg2 = State.regs[dstreg];
1682 difference = reg2 - imm - ((PSW & PSW_C) != 0);
1683 State.regs[dstreg] = difference;
0f7d7385 1684
080ee2ba 1685 z = ((PSW & PSW_Z) != 0) && (difference == 0);
377e53bb
JL		 1686 n = (difference & 0x80000000);
1687 c = (imm > reg2);
1688 v = ((reg2 & 0x80000000) == (imm & 0x80000000)
1689 && (reg2 & 0x80000000) != (difference & 0x80000000));
0f7d7385 1690
377e53bb
JL		 1691 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1692 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1693 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1694}
1695
1696// 1111 1011 1101 1000 Rn Rn IMM8; cmp IMM8,Rn
16978.0xfb+8.0xd8+4.RM2,4.RN0=RM2+8.IMM8:D2b:::cmp
1698"cmp"
1699*am33
0f7d7385 1700{
377e53bb 1701 int srcreg;
0f7d7385
JL		 1702
1703 PC = cia;
9c55817e 1704 srcreg = translate_rreg (SD_, RN0);
377e53bb 1705 genericCmp (EXTEND8 (IMM8), State.regs[srcreg]);
0f7d7385
JL		 1706}
1707
377e53bb
JL		 1708// 1111 1011 1111 1000 XRn XRn IMM8; mov IMM8,XRn
17098.0xfb+8.0xf8+4.XRM2,4.XRN0=XRM2+8.IMM8:D2k:::mov
0f7d7385 1710"mov"
377e53bb 1711*am33
0f7d7385 1712{
377e53bb 1713 int dstreg;
0f7d7385
JL		 1714
1715 PC = cia;
1716
377e53bb 1717 if (XRN0 == 0)
080ee2ba 1718 State.regs[REG_SP] = IMM8;
0f7d7385 1719 else
377e53bb 1720 abort ();
0f7d7385
JL		 1721}
1722
377e53bb
JL		 1723// 1111 1011 0000 1001 Rn Rn IMM8; and IMM8,Rn
17248.0xfb+8.0x09+4.RM2,4.RN0=RM2+8.IMM8:D2d:::and
1725"and"
1726*am33
0f7d7385
JL		 1727{
1728 int dstreg;
377e53bb 1729 int z, n;
0f7d7385
JL		 1730
1731 PC = cia;
9c55817e 1732 dstreg = translate_rreg (SD_, RN0);
0f7d7385 1733
377e53bb
JL		 1734 State.regs[dstreg] &= (IMM8 & 0xff);
1735 z = (State.regs[dstreg] == 0);
1736 n = (State.regs[dstreg] & 0x80000000) != 0;
1737 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1738 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
0f7d7385
JL		 1739}
1740
377e53bb
JL		 1741// 1111 1011 0001 1001 Rn Rn IMM8; or IMM8,Rn
17428.0xfb+8.0x19+4.RM2,4.RN0=RM2+8.IMM8:D2d:::or
1743"or"
1744*am33
0f7d7385 1745{
377e53bb
JL		 1746 int dstreg;
1747 int z, n;
0f7d7385
JL		 1748
1749 PC = cia;
9c55817e 1750 dstreg = translate_rreg (SD_, RN0);
0f7d7385 1751
377e53bb
JL		 1752 State.regs[dstreg] |= (IMM8 & 0xff);
1753 z = (State.regs[dstreg] == 0);
1754 n = (State.regs[dstreg] & 0x80000000) != 0;
1755 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1756 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
0f7d7385
JL		 1757}
1758
377e53bb
JL		 1759// 1111 1011 0010 1001 Rn Rn IMM8; xor IMM8,Rn
17608.0xfb+8.0x29+4.RM2,4.RN0=RM2+8.IMM8:D2d:::xor
1761"xor"
1762*am33
0f7d7385
JL		 1763{
1764 int dstreg;
377e53bb 1765 int z, n;
0f7d7385
JL		 1766
1767 PC = cia;
9c55817e 1768 dstreg = translate_rreg (SD_, RN0);
0f7d7385 1769
377e53bb
JL		 1770 State.regs[dstreg] ^= (IMM8 & 0xff);
1771 z = (State.regs[dstreg] == 0);
1772 n = (State.regs[dstreg] & 0x80000000) != 0;
1773 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1774 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
0f7d7385
JL		 1775}
1776
377e53bb
JL		 1777// 1111 1011 0100 1001 Rn Rn IMM8; asr IMM8,Rn
17788.0xfb+8.0x49+4.RM2,4.RN0=RM2+8.IMM8:D2a:::asr
1779"asr"
1780*am33
0f7d7385 1781{
377e53bb
JL		 1782 int dstreg;
1783 long temp;
1784 int c, z, n;
0f7d7385
JL		 1785
1786 PC = cia;
9c55817e 1787 dstreg = translate_rreg (SD_, RN0);
0f7d7385 1788
377e53bb
JL		 1789 temp = State.regs[dstreg];
1790 c = temp & 1;
1791 temp >>= (IMM8 & 0xff);
1792 State.regs[dstreg] = temp;
1793 z = (State.regs[dstreg] == 0);
1794 n = (State.regs[dstreg] & 0x80000000) != 0;
1795 PSW &= ~(PSW_Z | PSW_N | PSW_C);
1796 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
0f7d7385
JL		 1797}
1798
377e53bb
JL		 1799// 1111 1011 0101 1001 Rn Rn IMM8; lsr IMM8,Rn
18008.0xfb+8.0x59+4.RM2,4.RN0=RM2+8.IMM8:D2a:::lsr
1801"lsr"
1802*am33
1803{
1804 int dstreg;
1805 int z, n, c;
1806
1807 PC = cia;
9c55817e 1808 dstreg = translate_rreg (SD_, RN0);
377e53bb
JL		 1809
1810 c = State.regs[dstreg] & 1;
1811 State.regs[dstreg] >>= (IMM8 & 0xff);
1812 z = (State.regs[dstreg] == 0);
1813 n = (State.regs[dstreg] & 0x80000000) != 0;
1814 PSW &= ~(PSW_Z | PSW_N | PSW_C);
1815 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
1816}
1817
1818// 1111 1011 0110 1001 Rn Rn IMM8; asl IMM8,Rn
18198.0xfb+8.0x69+4.RM2,4.RN0=RM2+8.IMM8:D2a:::asl
1820"asl"
1821*am33
1822{
1823 int srcreg, dstreg;
1824 int z, n;
1825
1826 PC = cia;
9c55817e 1827 dstreg = translate_rreg (SD_, RN0);
377e53bb
JL		 1828
1829 State.regs[dstreg] <<= (IMM8 & 0xff);
1830 z = (State.regs[dstreg] == 0);
1831 n = (State.regs[dstreg] & 0x80000000) != 0;
1832 PSW &= ~(PSW_Z | PSW_N);
1833 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
1834}
1835
1836// 1111 1011 1010 1001 Rn Rn IMM8; mul IMM8,Rn
18378.0xfb+8.0xa9+4.RM2,4.RN0=RM2+8.IMM8:D2a:::mul
1838"mul"
1839*am33
1840{
1841 int dstreg;
1842 unsigned long long temp;
1843 int z, n;
1844
1845 PC = cia;
9c55817e 1846 dstreg = translate_rreg (SD_, RN0);
377e53bb
JL		 1847
1848 temp = ((signed64)(signed32)State.regs[dstreg]
1849 * (signed64)(signed32)EXTEND8 (IMM8));
1850 State.regs[dstreg] = temp & 0xffffffff;
1851 State.regs[REG_MDR] = (temp & 0xffffffff00000000LL) >> 32;;
1852 z = (State.regs[dstreg] == 0);
1853 n = (State.regs[dstreg] & 0x80000000) != 0;
1854 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1855 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
1856}
1857
1858// 1111 1011 1011 1001 Rn Rn IMM8; mulu IMM8,Rn
18598.0xfb+8.0xb9+4.RM2,4.RN0=RM2+8.IMM8:D2a:::mulu
1860"mulu"
1861*am33
1862{
1863 int dstreg;
1864 unsigned long long temp;
1865 int z, n;
1866
1867 PC = cia;
9c55817e 1868 dstreg = translate_rreg (SD_, RN0);
377e53bb
JL		 1869
1870 temp = ((unsigned64)State.regs[dstreg]
1871 * (unsigned64)(IMM8 & 0xff));
1872 State.regs[dstreg] = temp & 0xffffffff;
1873 State.regs[REG_MDR] = (temp & 0xffffffff00000000LL) >> 32;
1874 z = (State.regs[dstreg] == 0);
1875 n = (State.regs[dstreg] & 0x80000000) != 0;
1876 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1877 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
1878}
1879
1880// 1111 1011 1110 1001 Rn Rn IMM8; btst imm8,Rn
18818.0xfb+8.0xe9+4.RN2,4.RM0=RN2+8.IMM8:D2l:::btst
1882"btst"
1883*am33
1884{
1885 int srcreg;
1886
1887 PC = cia;
9c55817e 1888 srcreg = translate_rreg (SD_, RM0);
377e53bb 1889 genericBtst(IMM8, State.regs[srcreg]);
377e53bb
JL		 1890}
1891
377e53bb
JL		 1892// 1111 1011 0000 1010 Rn Rm IMM8; mov (d8,Rm),Rn
18938.0xfb+8.0x0a+4.RN2,4.RM0+8.IMM8:D2l:::mov
1894"mov"
1895*am33
1896{
1897 int srcreg, dstreg;
1898
1899 PC = cia;
9c55817e
JL		 1900 srcreg = translate_rreg (SD_, RM0);
1901 dstreg = translate_rreg (SD_, RN2);
377e53bb
JL		 1902 State.regs[dstreg] = load_word (State.regs[srcreg] + EXTEND8 (IMM8));
1903}
1904
1905// 1111 1011 0001 1010 Rn Rm IMM8; mov Rm,(d8,Rn)
19068.0xfb+8.0x1a+4.RM2,4.RN0+8.IMM8:D2m:::mov
1907"mov"
1908{
1909 int srcreg, dstreg;
1910
1911 PC = cia;
9c55817e
JL		 1912 srcreg = translate_rreg (SD_, RM2);
1913 dstreg = translate_rreg (SD_, RN0);
377e53bb
JL		 1914 store_word (State.regs[dstreg] + EXTEND8 (IMM8), State.regs[srcreg]);
1915}
1916
1917// 1111 1011 0010 1010 Rn Rm IMM8; movbu (d8,Rm),Rn
19188.0xfb+8.0x2a+4.RN2,4.RM0+8.IMM8:D2l:::movbu
1919"movbu"
1920{
1921 int srcreg, dstreg;
1922
1923 PC = cia;
9c55817e
JL		 1924 srcreg = translate_rreg (SD_, RM0);
1925 dstreg = translate_rreg (SD_, RN2);
377e53bb
JL		 1926 State.regs[dstreg] = load_byte (State.regs[srcreg] + EXTEND8 (IMM8));
1927}
1928
1929// 1111 1011 0011 1010 Rn Rm IMM8; movbu Rm,(d8,Rn)
19308.0xfb+8.0x3a+4.RM2,4.RN0+8.IMM8:D2m:::movbu
1931"movbu"
1932{
1933 int srcreg, dstreg;
1934
1935 PC = cia;
9c55817e
JL		 1936 srcreg = translate_rreg (SD_, RM2);
1937 dstreg = translate_rreg (SD_, RN0);
377e53bb
JL		 1938 store_byte (State.regs[dstreg] + EXTEND8 (IMM8), State.regs[srcreg]);
1939}
1940
1941// 1111 1011 0100 1010 Rn Rm IMM8; movhu (d8,Rm),Rn
19428.0xfb+8.0x4a+4.RN2,4.RM0+8.IMM8:D2l:::movhu
1943"movhu"
1944{
1945 int srcreg, dstreg;
1946
1947 PC = cia;
9c55817e
JL		 1948 srcreg = translate_rreg (SD_, RM0);
1949 dstreg = translate_rreg (SD_, RN2);
377e53bb
JL		 1950 State.regs[dstreg] = load_half (State.regs[srcreg] + EXTEND8 (IMM8));
1951}
1952
1953// 1111 1011 0101 1010 Rn Rm IMM8; movhu Rm,(d8,Rn)
19548.0xfb+8.0x5a+4.RM2,4.RN0+8.IMM8:D2m:::movhu
1955"movhu"
1956{
1957 int srcreg, dstreg;
1958
1959 PC = cia;
9c55817e
JL		 1960 srcreg = translate_rreg (SD_, RM2);
1961 dstreg = translate_rreg (SD_, RN0);
377e53bb
JL		 1962 store_half (State.regs[dstreg] + EXTEND8 (IMM8), State.regs[srcreg]);
1963}
1964
1965// 1111 1011 0110 1010 Rn Rm IMM8; mov (d8,Rm+),Rn
19668.0xfb+8.0x6a+4.RN2,4.RM0+8.IMM8:D2y:::mov
1967"mov"
1968*am33
1969{
1970 int srcreg, dstreg;
1971
1972 PC = cia;
9c55817e
JL		 1973 srcreg = translate_rreg (SD_, RM0);
1974 dstreg = translate_rreg (SD_, RN2);
377e53bb
JL		 1975 State.regs[dstreg] = load_word (State.regs[srcreg] + EXTEND8 (IMM8));
1976 State.regs[srcreg] += 4;
1977}
1978
1979// 1111 1011 0111 1010 Rn Rm IMM8; mov Rm,(d8,Rn+)
19808.0xfb+8.0x7a+4.RM2,4.RN0+8.IMM8:D2z:::mov
1981"mov"
1982{
1983 int srcreg, dstreg;
1984
1985 PC = cia;
9c55817e
JL		 1986 srcreg = translate_rreg (SD_, RM2);
1987 dstreg = translate_rreg (SD_, RN0);
377e53bb
JL		 1988 store_word (State.regs[dstreg] + EXTEND8 (IMM8), State.regs[srcreg]);
1989 State.regs[dstreg] += 4;
1990}
1991
1992
1993// 1111 1011 1000 1010 Rn 0000 IMM8; mov (d8,sp),Rn
19948.0xfb+8.0x8a+4.RN2,4.0x0+8.IMM8:D2n:::mov
1995"mov"
1996{
1997 int dstreg;
1998
1999 PC = cia;
9c55817e 2000 dstreg = translate_rreg (SD_, RN2);
377e53bb
JL		 2001 State.regs[dstreg] = load_word (State.regs[REG_SP] + EXTEND8 (IMM8));
2002}
2003
2004// 1111 1011 1001 1010 Rm 0000 IMM8; mov Rm,(d8,Rn)
20058.0xfb+8.0x9a+4.RM2,4.0x0+8.IMM8:D2o:::mov
2006"mov"
2007{
2008 int srcreg;
2009
2010 PC = cia;
9c55817e 2011 srcreg = translate_rreg (SD_, RM2);
377e53bb
JL		 2012 store_word (State.regs[REG_SP] + EXTEND8 (IMM8), State.regs[srcreg]);
2013}
2014
2015// 1111 1011 1010 1010 Rn Rm IMM8; movbu (d8,sp),Rn
20168.0xfb+8.0xaa+4.RN2,4.0x0+8.IMM8:D2n:::movbu
2017"movbu"
2018{
2019 int dstreg;
2020
2021 PC = cia;
9c55817e 2022 dstreg = translate_rreg (SD_, RN2);
377e53bb
JL		 2023 State.regs[dstreg] = load_byte (State.regs[REG_SP] + EXTEND8 (IMM8));
2024}
2025
2026// 1111 1011 1011 1010 Rn Rm IMM8; movbu Rm,(sp,Rn)
20278.0xfb+8.0xba+4.RM2,4.0x0+8.IMM8:D2o:::movbu
2028"movbu"
2029{
2030 int srcreg;
2031
2032 PC = cia;
9c55817e 2033 srcreg = translate_rreg (SD_, RM2);
377e53bb
JL		 2034 store_byte (State.regs[REG_SP] + EXTEND8 (IMM8), State.regs[srcreg]);
2035}
2036
2037// 1111 1011 1100 1010 Rn Rm IMM8; movhu (d8,sp),Rn
20388.0xfb+8.0xca+4.RN2,4.0x0+8.IMM8:D2n:::movhu
2039"movhu"
2040{
2041 int dstreg;
2042
2043 PC = cia;
9c55817e 2044 dstreg = translate_rreg (SD_, RN2);
377e53bb
JL		 2045 State.regs[dstreg] = load_half (State.regs[REG_SP] + EXTEND8 (IMM8));
2046}
2047
2048// 1111 1011 1101 1010 Rn Rm IMM8; movhu Rm,(d8,sp)
20498.0xfb+8.0xda+4.RM2,4.0x0+8.IMM8:D2o:::movhu
2050"movhu"
2051{
2052 int srcreg;
2053
2054 PC = cia;
9c55817e 2055 srcreg = translate_rreg (SD_, RM2);
377e53bb
JL		 2056 store_half (State.regs[REG_SP] + EXTEND8 (IMM8), State.regs[srcreg]);
2057}
2058
2059// 1111 1011 1110 1010 Rn Rm IMM8; movhu (d8,Rm+),Rn
20608.0xfb+8.0xea+4.RN2,4.RM0+8.IMM8:D2y:::movhu
2061"movhu"
2062*am33
2063{
2064 int srcreg, dstreg;
2065
2066 PC = cia;
9c55817e
JL		 2067 srcreg = translate_rreg (SD_, RM0);
2068 dstreg = translate_rreg (SD_, RN2);
377e53bb
JL		 2069 State.regs[dstreg] = load_half (State.regs[srcreg] + EXTEND8 (IMM8));
2070 State.regs[srcreg] += 2;
2071}
2072
2073// 1111 1011 1111 1010 Rn Rm IMM8; movhu Rm,(d8,Rn+)
20748.0xfb+8.0xfa+4.RM2,4.RN0+8.IMM8:D2z:::movhu
2075"movhu"
2076{
2077 int srcreg, dstreg;
2078
2079 PC = cia;
9c55817e
JL		 2080 srcreg = translate_rreg (SD_, RM2);
2081 dstreg = translate_rreg (SD_, RN0);
377e53bb
JL		 2082 store_half (State.regs[dstreg] + EXTEND8 (IMM8), State.regs[srcreg]);
2083 State.regs[dstreg] += 2;
2084}
2085
2086
2087// 1111 1011 0000 1011 Rn Rn IMM8; mac imm8,Rn
20888.0xfb+8.0x0b+4.RN2,4.RN0=RN2+8.IMM8:D2:::mac
2089"mac"
2090{
9c55817e 2091 int srcreg;
377e53bb
JL		 2092 long long temp, sum;
2093 int c, v;
2094
2095 PC = cia;
9c55817e 2096 srcreg = translate_rreg (SD_, RN2);
377e53bb 2097
080ee2ba
JL		 2098 temp = ((signed64)(signed32)EXTEND8 (IMM8)
2099 * (signed64)(signed32)State.regs[srcreg]);
377e53bb
JL		 2100 sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
2101 c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
2102 State.regs[REG_MCRL] = sum;
2103 temp >>= 32;
2104 temp &= 0xffffffff;
2105 sum = State.regs[REG_MCRH] + temp + c;
2106 v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
2107 && (temp & 0x80000000) != (sum & 0x80000000));
2108 State.regs[REG_MCRH] = sum;
2109 if (v)
2110 State.regs[REG_MCVF] = 1;
2111}
2112
2113// 1111 1011 0001 1011 Rn Rn IMM8; macu imm8,Rn
21148.0xfb+8.0x1b+4.RN2,4.RN0=RN2+8.IMM8:D2:::macu
2115"macu"
2116{
9c55817e 2117 int srcreg;
377e53bb
JL		 2118 long long temp, sum;
2119 int c, v;
2120
2121 PC = cia;
9c55817e 2122 srcreg = translate_rreg (SD_, RN2);
377e53bb
JL		 2123
2124 temp = ((unsigned64) (IMM8)
9c55817e 2125 * (unsigned64)State.regs[srcreg]);
377e53bb
JL		 2126 sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
2127 c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
2128 State.regs[REG_MCRL] = sum;
2129 temp >>= 32;
2130 temp &= 0xffffffff;
2131 sum = State.regs[REG_MCRH] + temp + c;
2132 v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
2133 && (temp & 0x80000000) != (sum & 0x80000000));
2134 State.regs[REG_MCRH] = sum;
2135 if (v)
2136 State.regs[REG_MCVF] = 1;
2137}
2138
2139// 1111 1011 0010 1011 Rn Rn IMM8; macb imm8,Rn
21408.0xfb+8.0x2b+4.RN2,4.RN0=RN2+8.IMM8:D2:::macb
2141"macb"
2142{
9c55817e 2143 int srcreg;
377e53bb
JL		 2144 long long temp, sum;
2145 int c, v;
2146
2147 PC = cia;
9c55817e 2148 srcreg = translate_rreg (SD_, RN2);
377e53bb 2149
080ee2ba
JL		 2150 temp = ((signed64)(signed8)EXTEND8 (IMM8)
2151 * (signed64)(signed8)State.regs[srcreg] & 0xff);
377e53bb
JL		 2152 sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
2153 c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
2154 State.regs[REG_MCRL] = sum;
2155 temp >>= 32;
2156 temp &= 0xffffffff;
2157 sum = State.regs[REG_MCRH] + temp + c;
2158 v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
2159 && (temp & 0x80000000) != (sum & 0x80000000));
2160 State.regs[REG_MCRH] = sum;
2161 if (v)
2162 State.regs[REG_MCVF] = 1;
2163}
2164
2165// 1111 1011 0011 1011 Rn Rn IMM8; macbu imm8,Rn
21668.0xfb+8.0x3b+4.RN2,4.RN0=RN2+8.IMM8:D2:::macbu
2167"macbu"
2168{
9c55817e 2169 int srcreg;
377e53bb
JL		 2170 long long temp, sum;
2171 int c, v;
2172
2173 PC = cia;
9c55817e 2174 srcreg = translate_rreg (SD_, RN2);
377e53bb
JL		 2175
2176 temp = ((unsigned64) (IMM8)
9c55817e 2177 * (unsigned64)State.regs[srcreg] & 0xff);
377e53bb
JL		 2178 sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
2179 c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
2180 State.regs[REG_MCRL] = sum;
2181 temp >>= 32;
2182 temp &= 0xffffffff;
2183 sum = State.regs[REG_MCRH] + temp + c;
2184 v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
2185 && (temp & 0x80000000) != (sum & 0x80000000));
2186 State.regs[REG_MCRH] = sum;
2187 if (v)
2188 State.regs[REG_MCVF] = 1;
2189}
2190
2191// 1111 1011 0100 1011 Rn Rn IMM8; mach imm8,Rn
21928.0xfb+8.0x4b+4.RN2,4.RN0=RN2+8.IMM8:D2:::mach
2193"mach"
2194{
9c55817e 2195 int srcreg;
377e53bb
JL		 2196 long long temp, sum;
2197 int c, v;
2198
2199 PC = cia;
9c55817e 2200 srcreg = translate_rreg (SD_, RN2);
377e53bb 2201
080ee2ba
JL		 2202 temp = ((signed64)(signed16)EXTEND8 (IMM8)
2203 * (signed64)(signed16)State.regs[srcreg] & 0xffff);
377e53bb
JL		 2204 sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
2205 c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
2206 State.regs[REG_MCRL] = sum;
2207 temp >>= 32;
2208 temp &= 0xffffffff;
2209 sum = State.regs[REG_MCRH] + temp + c;
2210 v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
2211 && (temp & 0x80000000) != (sum & 0x80000000));
2212 State.regs[REG_MCRH] = sum;
2213 if (v)
2214 State.regs[REG_MCVF] = 1;
2215}
2216
2217// 1111 1011 0101 1011 Rn Rn IMM8; machu imm8,Rn
22188.0xfb+8.0x5b+4.RN2,4.RN0=RN2+8.IMM8:D2:::machu
2219"machu"
2220{
9c55817e 2221 int srcreg;
377e53bb
JL		 2222 long long temp, sum;
2223 int c, v;
2224
2225 PC = cia;
9c55817e 2226 srcreg = translate_rreg (SD_, RN2);
377e53bb
JL		 2227
2228 temp = ((unsigned64) (IMM8)
9c55817e 2229 * (unsigned64)State.regs[srcreg] & 0xffff);
377e53bb
JL		 2230 sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
2231 c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
2232 State.regs[REG_MCRL] = sum;
2233 temp >>= 32;
2234 temp &= 0xffffffff;
2235 sum = State.regs[REG_MCRH] + temp + c;
2236 v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
2237 && (temp & 0x80000000) != (sum & 0x80000000));
2238 State.regs[REG_MCRH] = sum;
2239 if (v)
2240 State.regs[REG_MCVF] = 1;
2241}
2242
1f0ba346
JL		 2243// 1111 1011 1011 1011 Rn Rn IMM8; mcste imm8,Rn
22448.0xfb+8.0xbb+4.RN2,4.RN0=RN2+8.IMM8:D2:::mcste
2245"mcste"
2246{
2247 int dstreg;
2248
2249 PC = cia;
2250 dstreg = translate_rreg (SD_, RN0);
2251
2252 PSW &= ~(PSW_V | PSW_C);
2253 PSW |= (State.regs[REG_MCVF] ? PSW_V : 0);
2254
2255 /* 32bit saturation. */
2256 if (IMM8 == 0x20)
2257 {
2258 long long tmp;
2259
2260 tmp = State.regs[REG_MCRH];
2261 tmp <<= 32;
2262 tmp += State.regs[REG_MCRL];
2263
2264 if (tmp > 0x7fffffff)
2265 State.regs[dstreg] = 0x7fffffff;
2266 else if (tmp < 0xffffffff80000000LL)
2267 State.regs[dstreg] = 0x80000000;
2268 else
2269 State.regs[dstreg] = tmp;
2270 }
2271 /* 16bit saturation */
2272 else if (IMM8 == 0x10)
2273 {
2274 long long tmp;
2275
2276 tmp = State.regs[REG_MCRH];
2277 tmp <<= 32;
2278 tmp += State.regs[REG_MCRL];
2279
2280 if (tmp > 0x7fff)
2281 State.regs[dstreg] = 0x7fff;
2282 else if (tmp < 0xffffffffffff8000LL)
2283 State.regs[dstreg] = 0x8000;
2284 else
2285 State.regs[dstreg] = tmp;
2286 }
2287 /* 8 bit saturation */
2288 else if (IMM8 == 0x8)
2289 {
2290 long long tmp;
2291
2292 tmp = State.regs[REG_MCRH];
2293 tmp <<= 32;
2294 tmp += State.regs[REG_MCRL];
2295
2296 if (tmp > 0x7f)
2297 State.regs[dstreg] = 0x7f;
2298 else if (tmp < 0xffffffffffffff80LL)
2299 State.regs[dstreg] = 0x80;
2300 else
2301 State.regs[dstreg] = tmp;
2302 }
2303 /* 9 bit saturation */
2304 else if (IMM8 == 0x9)
2305 {
2306 long long tmp;
2307
2308 tmp = State.regs[REG_MCRH];
2309 tmp <<= 32;
2310 tmp += State.regs[REG_MCRL];
2311
2312 if (tmp > 0x80)
2313 State.regs[dstreg] = 0x80;
2314 else if (tmp < 0xffffffffffffff81LL)
2315 State.regs[dstreg] = 0x81;
2316 else
2317 State.regs[dstreg] = tmp;
2318 }
2319 /* 9 bit saturation */
2320 else if (IMM8 == 0x30)
2321 {
2322 long long tmp;
2323
2324 tmp = State.regs[REG_MCRH];
2325 tmp <<= 32;
2326 tmp += State.regs[REG_MCRL];
2327
2328 if (tmp > 0x7fffffffffffLL)
2329 tmp = 0x7fffffffffffLL;
2330 else if (tmp < 0xffff800000000000LL)
2331 tmp = 0xffff800000000000LL;
2332
2333 tmp >>= 16;
2334 State.regs[dstreg] = tmp;
2335 }
2336}
377e53bb 2337
0f7d7385
JL		 2338// 1111 1011 0111 1100 Rm Rn Rd; add Rm,Rn,Rd
23398.0xfb+8.0x7c+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::add
2340"add"
2341*am33
2342{
ee61616c 2343 int z, c, n, v;
377e53bb
JL		 2344 unsigned long sum, source1, source2;
2345 int srcreg1, srcreg2, dstreg;
2346
2347 PC = cia;
9c55817e
JL		 2348 srcreg1 = translate_rreg (SD_, RM2);
2349 srcreg2 = translate_rreg (SD_, RN0);
2350 dstreg = translate_rreg (SD_, RD0);
377e53bb
JL		 2351
2352 source1 = State.regs[srcreg1];
2353 source2 = State.regs[srcreg2];
2354 sum = source1 + source2;
2355 State.regs[dstreg] = sum;
2356
2357 z = (sum == 0);
2358 n = (sum & 0x80000000);
2359 c = (sum < source1) || (sum < source2);
2360 v = ((source1 & 0x80000000) == (source2 & 0x80000000)
2361 && (source1 & 0x80000000) != (sum & 0x80000000));
2362
2363 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
2364 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
2365 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
2366}
2367
2368// 1111 1011 1000 1100 Rm Rn Rd; addc Rm,Rn,Rd
23698.0xfb+8.0x8c+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::addc
2370"addc"
2371*am33
2372{
2373 int z, c, n, v;
2374 unsigned long sum, source1, source2;
2375 int srcreg1, srcreg2, dstreg;
2376
2377 PC = cia;
9c55817e
JL		 2378 srcreg1 = translate_rreg (SD_, RM2);
2379 srcreg2 = translate_rreg (SD_, RN0);
2380 dstreg = translate_rreg (SD_, RD0);
377e53bb
JL		 2381
2382 source1 = State.regs[srcreg1];
2383 source2 = State.regs[srcreg2];
2384 sum = source1 + source2 + ((PSW & PSW_C) != 0);
2385 State.regs[dstreg] = sum;
2386
080ee2ba 2387 z = ((PSW & PSW_Z) != 0) && (sum == 0);
377e53bb
JL		 2388 n = (sum & 0x80000000);
2389 c = (sum < source1) || (sum < source2);
2390 v = ((source1 & 0x80000000) == (source2 & 0x80000000)
2391 && (source1 & 0x80000000) != (sum & 0x80000000));
2392
2393 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
2394 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
2395 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
2396}
2397
2398// 1111 1011 1001 1100 Rm Rn Rd; sub Rm,Rn,Rd
23998.0xfb+8.0x9c+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::sub
2400"sub"
2401*am33
2402{
2403 int z, c, n, v;
2404 unsigned long difference, source1, source2;
2405 int srcreg1, srcreg2, dstreg;
2406
2407 PC = cia;
9c55817e
JL		 2408 srcreg1 = translate_rreg (SD_, RM2);
2409 srcreg2 = translate_rreg (SD_, RN0);
2410 dstreg = translate_rreg (SD_, RD0);
377e53bb
JL		 2411
2412 source1 = State.regs[srcreg1];
2413 source2 = State.regs[srcreg2];
2414 difference = source2 - source1;
2415 State.regs[dstreg] = difference;
2416
2417 z = (difference == 0);
2418 n = (difference & 0x80000000);
2419 c = (source1 > source1);
2420 v = ((source1 & 0x80000000) == (source2 & 0x80000000)
2421 && (source1 & 0x80000000) != (difference & 0x80000000));
2422
2423 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
2424 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
2425 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
2426}
2427
2428// 1111 1011 1010 1100 Rm Rn Rd; subc Rm,Rn,Rd
24298.0xfb+8.0xac+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::subc
2430"subc"
2431*am33
2432{
2433 int z, c, n, v;
2434 unsigned long difference, source1, source2;
2435 int srcreg1, srcreg2, dstreg;
2436
2437 PC = cia;
9c55817e
JL		 2438 srcreg1 = translate_rreg (SD_, RM2);
2439 srcreg2 = translate_rreg (SD_, RN0);
2440 dstreg = translate_rreg (SD_, RD0);
377e53bb
JL		 2441
2442 source1 = State.regs[srcreg1];
2443 source2 = State.regs[srcreg2];
2444 difference = source2 - source1 - ((PSW & PSW_C) != 0);
2445 State.regs[dstreg] = difference;
2446
080ee2ba 2447 z = ((PSW & PSW_Z) != 0) && (difference == 0);
377e53bb
JL		 2448 n = (difference & 0x80000000);
2449 c = (source1 > source2);
2450 v = ((source1 & 0x80000000) == (source2 & 0x80000000)
2451 && (source1 & 0x80000000) != (difference & 0x80000000));
2452
2453 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
2454 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
2455 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
2456}
2457
2458// 1111 1011 0000 1101 Rm Rn Rd; and Rm,Rn,Rd
24598.0xfb+8.0x0d+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::and
2460"and"
2461*am33
2462{
080ee2ba 2463 int z, n;
377e53bb
JL		 2464 int srcreg1, srcreg2, dstreg;
2465
2466 PC = cia;
9c55817e
JL		 2467 srcreg1 = translate_rreg (SD_, RM2);
2468 srcreg2 = translate_rreg (SD_, RN0);
2469 dstreg = translate_rreg (SD_, RD0);
377e53bb
JL		 2470
2471 State.regs[dstreg] = State.regs[srcreg1] & State.regs[srcreg2];
2472
2473 z = (State.regs[dstreg] == 0);
2474 n = (State.regs[dstreg] & 0x80000000);
2475
2476 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
2477 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0));
2478}
2479
2480// 1111 1011 0001 1101 Rm Rn Rd; or Rm,Rn,Rd
24818.0xfb+8.0x1d+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::or
2482"or"
2483*am33
2484{
080ee2ba 2485 int z, n;
0f7d7385
JL		 2486 int srcreg1, srcreg2, dstreg;
2487
2488 PC = cia;
9c55817e
JL		 2489 srcreg1 = translate_rreg (SD_, RM2);
2490 srcreg2 = translate_rreg (SD_, RN0);
2491 dstreg = translate_rreg (SD_, RD0);
0f7d7385 2492
377e53bb 2493 State.regs[dstreg] = State.regs[srcreg1] | State.regs[srcreg2];
ee61616c 2494
377e53bb
JL		 2495 z = (State.regs[dstreg] == 0);
2496 n = (State.regs[dstreg] & 0x80000000);
ee61616c
JL		 2497
2498 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
377e53bb 2499 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0));
0f7d7385
JL		 2500}
2501
377e53bb
JL		 2502// 1111 1011 0010 1101 Rm Rn Rd; xor Rm,Rn,Rd
25038.0xfb+8.0x2d+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::xor
2504"xor"
0f7d7385
JL		 2505*am33
2506{
080ee2ba 2507 int z, n;
3e75ff7e 2508 int srcreg1, srcreg2, dstreg;
0f7d7385
JL		 2509
2510 PC = cia;
9c55817e
JL		 2511 srcreg1 = translate_rreg (SD_, RM2);
2512 srcreg2 = translate_rreg (SD_, RN0);
2513 dstreg = translate_rreg (SD_, RD0);
3e75ff7e 2514
377e53bb 2515 State.regs[dstreg] = State.regs[srcreg1] ^ State.regs[srcreg2];
3e75ff7e 2516
377e53bb
JL		 2517 z = (State.regs[dstreg] == 0);
2518 n = (State.regs[dstreg] & 0x80000000);
0f7d7385 2519
3e75ff7e 2520 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
377e53bb 2521 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0));
0f7d7385
JL		 2522}
2523
377e53bb
JL		 2524// 1111 1011 0100 1101 Rm Rn Rd; asr Rm,Rn,Rd
25258.0xfb+8.0x4d+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::asr
2526"asr"
0f7d7385
JL		 2527*am33
2528{
080ee2ba 2529 int z, c, n;
377e53bb 2530 long temp;
3e75ff7e 2531 int srcreg1, srcreg2, dstreg;
0f7d7385
JL		 2532
2533 PC = cia;
9c55817e
JL		 2534 srcreg1 = translate_rreg (SD_, RM2);
2535 srcreg2 = translate_rreg (SD_, RN0);
2536 dstreg = translate_rreg (SD_, RD0);
3e75ff7e 2537
377e53bb
JL		 2538 temp = State.regs[srcreg2];
2539 c = temp & 1;
2540 temp >>= State.regs[srcreg1];
2541 State.regs[dstreg] = temp;
3e75ff7e 2542
377e53bb
JL		 2543 z = (State.regs[dstreg] == 0);
2544 n = (State.regs[dstreg] & 0x80000000);
3e75ff7e 2545
377e53bb
JL		 2546 PSW &= ~(PSW_Z | PSW_N | PSW_C);
2547 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0));
0f7d7385
JL		 2548}
2549
377e53bb
JL		 2550// 1111 1011 0101 1101 Rm Rn Rd; lsr Rm,Rn,Rd
25518.0xfb+8.0x5d+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::lsr
2552"lsr"
2553*am33
2554{
080ee2ba 2555 int z, c, n;
377e53bb
JL		 2556 int srcreg1, srcreg2, dstreg;
2557
2558 PC = cia;
9c55817e
JL		 2559 srcreg1 = translate_rreg (SD_, RM2);
2560 srcreg2 = translate_rreg (SD_, RN0);
2561 dstreg = translate_rreg (SD_, RD0);
377e53bb
JL		 2562
2563 c = State.regs[srcreg2] & 1;
2564 State.regs[dstreg] = State.regs[srcreg2] >> State.regs[srcreg1];
2565
2566 z = (State.regs[dstreg] == 0);
2567 n = (State.regs[dstreg] & 0x80000000);
2568
2569 PSW &= ~(PSW_Z | PSW_N | PSW_C);
2570 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0));
2571}
2572
2573// 1111 1011 0110 1101 Rm Rn Rd; asl Rm,Rn,Rd
25748.0xfb+8.0x6d+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::asl
2575"asl"
2576*am33
2577{
080ee2ba 2578 int z, n;
377e53bb
JL		 2579 int srcreg1, srcreg2, dstreg;
2580
2581 PC = cia;
9c55817e
JL		 2582 srcreg1 = translate_rreg (SD_, RM2);
2583 srcreg2 = translate_rreg (SD_, RN0);
2584 dstreg = translate_rreg (SD_, RD0);
377e53bb
JL		 2585
2586 State.regs[dstreg] = State.regs[srcreg2] << State.regs[srcreg1];;
2587
2588 z = (State.regs[dstreg] == 0);
2589 n = (State.regs[dstreg] & 0x80000000);
2590
2591 PSW &= ~(PSW_Z | PSW_N | PSW_C);
2592 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0));
2593}
2594
2595// 1111 1011 1010 1101 Rm Rn Rd1 Rd2; mul Rm,Rn,Rd1,Rd2
25968.0xfb+8.0xad+4.RM2,4.RN0+4.RD0,4.RD2:D2c:::mul
2597"mul"
2598*am33
2599{
2600 int srcreg1, srcreg2, dstreg1, dstreg2;
2601 signed long long temp;
2602
2603 PC = cia;
9c55817e
JL		 2604 srcreg1 = translate_rreg (SD_, RM2);
2605 srcreg2 = translate_rreg (SD_, RN0);
2606 dstreg1 = translate_rreg (SD_, RD0);
2607 dstreg2 = translate_rreg (SD_, RD2);
377e53bb
JL		 2608
2609 temp = ((signed64)(signed32)State.regs[srcreg1]
2610 * (signed64)(signed32)State.regs[srcreg2]);
2611 State.regs[dstreg1] = temp & 0xffffffff;
2612 State.regs[dstreg2] = (temp & 0xffffffff00000000LL) >> 32;;
2613}
2614
2615// 1111 1011 1011 1101 Rm Rn Rd1 Rd2; mulu Rm,Rn,Rd1,Rd2
26168.0xfb+8.0xbd+4.RM2,4.RN0+4.RD0,4.RD2:D2c:::mulu
2617"mulu"
2618*am33
2619{
2620 int srcreg1, srcreg2, dstreg1, dstreg2;
2621 signed long long temp;
2622
2623 PC = cia;
9c55817e
JL		 2624 srcreg1 = translate_rreg (SD_, RM2);
2625 srcreg2 = translate_rreg (SD_, RN0);
2626 dstreg1 = translate_rreg (SD_, RD0);
2627 dstreg2 = translate_rreg (SD_, RD2);
377e53bb 2628
080ee2ba
JL		 2629 temp = ((unsigned64)State.regs[srcreg1]
2630 * (unsigned64)State.regs[srcreg2]);
377e53bb
JL		 2631 State.regs[dstreg1] = temp & 0xffffffff;
2632 State.regs[dstreg2] = (temp & 0xffffffff00000000LL) >> 32;;
2633}
2634
2635// 1111 1011 0000 1110 Rn 0000 abs8 ; mov (abs8),Rn
26368.0xfb+8.0x0e+4.RN2,4.0x0+8.IMM8:D2p:::mov
2637"mov"
2638*am33
2639{
2640 int dstreg;
2641
2642 PC = cia;
9c55817e 2643 dstreg = translate_rreg (SD_, RN2);
377e53bb
JL		 2644 State.regs[dstreg] = load_word (IMM8);
2645}
2646
2647// 1111 1011 0001 1110 Rm 0000 abs8 ; mov Rn,(abs8)
26488.0xfb+8.0x1e+4.RM2,4.0x0+8.IMM8:D2q:::mov
2649"mov"
2650*am33
2651{
2652 int srcreg;
2653
9c55817e
JL		 2654 PC = cia;
2655 srcreg = translate_rreg (SD_, RM2);
377e53bb
JL		 2656 store_word (IMM8, State.regs[srcreg]);
2657}
2658
2659// 1111 1011 0010 1110 Rn 0000 abs8 ; movbu (abs8),Rn
26608.0xfb+8.0x2e+4.RN2,4.0x0+8.IMM8:D2p:::movbu
2661"movbu"
2662*am33
2663{
2664 int dstreg;
2665
2666 PC = cia;
9c55817e 2667 dstreg = translate_rreg (SD_, RN2);
377e53bb
JL		 2668 State.regs[dstreg] = load_byte (IMM8);
2669}
2670
2671// 1111 1011 0011 1110 Rm 0000 abs8 ; movbu Rn,(abs8)
26728.0xfb+8.0x3e+4.RM2,4.0x0+8.IMM8:D2q:::movbu
2673"movbu"
0f7d7385
JL		 2674*am33
2675{
377e53bb 2676 int srcreg;
0f7d7385
JL		 2677
2678 PC = cia;
9c55817e 2679 srcreg = translate_rreg (SD_, RM2);
377e53bb
JL		 2680 store_byte (IMM8, State.regs[srcreg]);
2681}
0f7d7385 2682
377e53bb
JL		 2683// 1111 1011 0100 1110 Rn 0000 abs8 ; movhu (abs8),Rn
26848.0xfb+8.0x4e+4.RN2,4.0x0+8.IMM8:D2p:::movhu
2685"movhu"
2686*am33
2687{
2688 int dstreg;
2689
2690 PC = cia;
9c55817e 2691 dstreg = translate_rreg (SD_, RN2);
377e53bb
JL		 2692 State.regs[dstreg] = load_half (IMM8);
2693}
3e75ff7e 2694
377e53bb
JL		 2695// 1111 1011 0101 1110 Rm 0000 abs8 ; movhu Rn,(abs8)
26968.0xfb+8.0x5e+4.RM2,4.0x0+8.IMM8:D2q:::movhu
2697"movhu"
2698*am33
2699{
2700 int srcreg;
3e75ff7e 2701
377e53bb 2702 PC = cia;
9c55817e 2703 srcreg = translate_rreg (SD_, RM2);
377e53bb 2704 store_half (IMM8, State.regs[srcreg]);
0f7d7385
JL		 2705}
2706
377e53bb
JL		 2707// 1111 1011 1000 1110 Ri Rm Rn; mov (Ri,Rm),Rn
27088.0xfb+8.0x8e+4.RI0,4.RM0+4.RN0,4.0x0:D2r:::mov
2709"mov"
0f7d7385
JL		 2710*am33
2711{
3e75ff7e 2712 int srcreg1, srcreg2, dstreg;
0f7d7385
JL		 2713
2714 PC = cia;
9c55817e
JL		 2715 srcreg1 = translate_rreg (SD_, RM0);
2716 srcreg1 = translate_rreg (SD_, RI0);
2717 dstreg = translate_rreg (SD_, RN0);
377e53bb 2718 State.regs[dstreg] = load_word (State.regs[srcreg1] + State.regs[srcreg2]);
3e75ff7e
JL		 2719}
2720
377e53bb
JL		 2721// 1111 1011 1001 1110 Ri Rm Rn; mov Rn,(Ri,Rm)
27228.0xfb+8.0x9e+4.RI0,4.RN0+4.RM0,4.0x0:D2s:::mov
2723"mov"
3e75ff7e
JL		 2724*am33
2725{
377e53bb 2726 int srcreg, dstreg1, dstreg2;
3e75ff7e
JL		 2727
2728 PC = cia;
9c55817e
JL		 2729 srcreg = translate_rreg (SD_, RM0);
2730 dstreg1 = translate_rreg (SD_, RI0);
2731 dstreg2 = translate_rreg (SD_, RN0);
377e53bb 2732 store_word (State.regs[dstreg1] + State.regs[dstreg2], State.regs[srcreg]);
3e75ff7e
JL		 2733}
2734
377e53bb
JL		 2735// 1111 1011 1010 1110 Ri Rm Rn; movbu (Ri,Rm),Rn
27368.0xfb+8.0xae+4.RI0,4.RM0+4.RN0,4.0x0:D2r:::movbu
2737"movbu"
3e75ff7e
JL		 2738*am33
2739{
3e75ff7e
JL		 2740 int srcreg1, srcreg2, dstreg;
2741
2742 PC = cia;
9c55817e
JL		 2743 srcreg1 = translate_rreg (SD_, RM0);
2744 srcreg1 = translate_rreg (SD_, RI0);
2745 dstreg = translate_rreg (SD_, RN0);
377e53bb 2746 State.regs[dstreg] = load_byte (State.regs[srcreg1] + State.regs[srcreg2]);
3e75ff7e
JL		 2747}
2748
377e53bb
JL		 2749// 1111 1011 1011 1110 Ri Rm Rn; movbu Rn,(Ri,Rm)
27508.0xfb+8.0xbe+4.RI0,4.RN0+4.RM0,4.0x0:D2s:::movbu
2751"movbu"
3e75ff7e
JL		 2752*am33
2753{
377e53bb 2754 int srcreg, dstreg1, dstreg2;
3e75ff7e
JL		 2755
2756 PC = cia;
9c55817e
JL		 2757 srcreg = translate_rreg (SD_, RM0);
2758 dstreg1 = translate_rreg (SD_, RI0);
2759 dstreg2 = translate_rreg (SD_, RN0);
377e53bb 2760 store_byte (State.regs[dstreg1] + State.regs[dstreg2], State.regs[srcreg]);
3e75ff7e
JL		 2761}
2762
377e53bb
JL		 2763// 1111 1011 1100 1110 Ri Rm Rn; movhu (Ri,Rm),Rn
27648.0xfb+8.0xce+4.RI0,4.RM0+4.RN0,4.0x0:D2r:::movhu
2765"movhu"
3e75ff7e
JL		 2766*am33
2767{
3e75ff7e
JL		 2768 int srcreg1, srcreg2, dstreg;
2769
9c55817e
JL		 2770 PC = cia;
2771 srcreg1 = translate_rreg (SD_, RM0);
2772 srcreg1 = translate_rreg (SD_, RI0);
2773 dstreg = translate_rreg (SD_, RN0);
377e53bb
JL		 2774 State.regs[dstreg] = load_half (State.regs[srcreg1] + State.regs[srcreg2]);
2775}
2776
2777// 1111 1011 1101 1110 Ri Rm Rn; movhu Rn,(Ri,Rm)
27788.0xfb+8.0xde+4.RI0,4.RN0+4.RM0,4.0x0:D2s:::movhu
2779"movhu"
2780*am33
2781{
2782 int srcreg, dstreg1, dstreg2;
2783
2784 PC = cia;
9c55817e
JL		 2785 srcreg = translate_rreg (SD_, RM0);
2786 dstreg1 = translate_rreg (SD_, RI0);
2787 dstreg2 = translate_rreg (SD_, RN0);
377e53bb 2788 store_half (State.regs[dstreg1] + State.regs[dstreg2], State.regs[srcreg]);
3e75ff7e
JL		 2789}
2790
1f0ba346
JL		 2791// 1111 1011 0000 1111 Rm Rn Rd1 Rd2; mac Rm,Rn,Rd1,Rd2
27928.0xfb+8.0x0f+4.RM2,4.RN0+4.RD0,4.RD2:D2c:::mac
2793"mac"
2794*am33
2795{
2796 int srcreg1, srcreg2, dstreg1, dstreg2;
2797 signed long long temp;
2798 unsigned long sum;
2799 int c, v;
2800
2801 PC = cia;
2802 srcreg1 = translate_rreg (SD_, RM2);
2803 srcreg2 = translate_rreg (SD_, RN0);
2804 dstreg1 = translate_rreg (SD_, RD0);
2805 dstreg2 = translate_rreg (SD_, RD2);
2806
2807 temp = ((signed64)(signed32)State.regs[srcreg1]
2808 * (signed64)(signed32)State.regs[srcreg2]);
2809
2810 sum = State.regs[dstreg2] + (temp & 0xffffffff);
2811 c = (sum < State.regs[dstreg2]) || (sum < (temp & 0xffffffff));
2812 State.regs[dstreg2] = sum;
2813 temp >>= 32;
2814 temp &= 0xffffffff;
2815 sum = State.regs[dstreg1] + temp + c;
2816 v = ((State.regs[dstreg1] & 0x80000000) == (temp & 0x80000000)
2817 && (temp & 0x80000000) != (sum & 0x80000000));
2818 State.regs[dstreg1] = sum;
2819 if (v)
2820 State.regs[REG_MCVF] = 1;
2821}
2822
2823// 1111 1011 0001 1111 Rm Rn Rd1 Rd2; macu Rm,Rn,Rd1,Rd2
28248.0xfb+8.0x1f+4.RM2,4.RN0+4.RD0,4.RD2:D2c:::macu
2825"macu"
2826*am33
2827{
2828 int srcreg1, srcreg2, dstreg1, dstreg2;
2829 signed long long temp;
2830 unsigned long sum;
2831 int c, v;
2832
2833 PC = cia;
2834 srcreg1 = translate_rreg (SD_, RM2);
2835 srcreg2 = translate_rreg (SD_, RN0);
2836 dstreg1 = translate_rreg (SD_, RD0);
2837 dstreg2 = translate_rreg (SD_, RD2);
2838
2839 temp = ((unsigned64)State.regs[srcreg1]
2840 * (unsigned64)State.regs[srcreg2]);
2841
2842 sum = State.regs[dstreg2] + (temp & 0xffffffff);
2843 c = (sum < State.regs[dstreg2]) || (sum < (temp & 0xffffffff));
2844 State.regs[dstreg2] = sum;
2845 temp >>= 32;
2846 temp &= 0xffffffff;
2847 sum = State.regs[dstreg1] + temp + c;
2848 v = ((State.regs[dstreg1] & 0x80000000) == (temp & 0x80000000)
2849 && (temp & 0x80000000) != (sum & 0x80000000));
2850 State.regs[dstreg1] = sum;
2851 if (v)
2852 State.regs[REG_MCVF] = 1;
2853}
2854
2855// 1111 1011 0010 1111 Rm Rn Rd1; macb Rm,Rn,Rd1
28568.0xfb+8.0x2f+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::macb
2857"macb"
2858*am33
2859{
2860 int srcreg1, srcreg2, dstreg;
2861 long temp, sum;
2862 int v;
2863
2864 PC = cia;
2865 srcreg1 = translate_rreg (SD_, RM2);
2866 srcreg2 = translate_rreg (SD_, RN0);
2867 dstreg = translate_rreg (SD_, RD0);
2868
2869 temp = ((signed32)(State.regs[srcreg2] & 0xff)
2870 * (signed32)(State.regs[srcreg1] & 0xff));
2871 sum = State.regs[dstreg] + temp;
2872 v = ((State.regs[dstreg] & 0x80000000) == (temp & 0x80000000)
2873 && (temp & 0x80000000) != (sum & 0x80000000));
2874 State.regs[dstreg] = sum;
2875 if (v)
2876 State.regs[REG_MCVF] = 1;
2877}
2878
2879// 1111 1011 0011 1111 Rm Rn Rd1; macbu Rm,Rn,Rd1
28808.0xfb+8.0x3f+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::macbu
2881"macbu"
2882*am33
2883{
2884 int srcreg1, srcreg2, dstreg;
2885 long temp, sum;
2886 int v;
2887
2888 PC = cia;
2889 srcreg1 = translate_rreg (SD_, RM2);
2890 srcreg2 = translate_rreg (SD_, RN0);
2891 dstreg = translate_rreg (SD_, RD0);
2892
2893 temp = ((unsigned32)(State.regs[srcreg2] & 0xff)
2894 * (unsigned32)(State.regs[srcreg1] & 0xff));
2895 sum = State.regs[dstreg] + temp;
2896 v = ((State.regs[dstreg] & 0x80000000) == (temp & 0x80000000)
2897 && (temp & 0x80000000) != (sum & 0x80000000));
2898 State.regs[dstreg] = sum;
2899 if (v)
2900 State.regs[REG_MCVF] = 1;
2901}
2902
2903// 1111 1011 0100 1111 Rm Rn Rd1; mach Rm,Rn,Rd1
29048.0xfb+8.0x4f+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::mach
2905"mach"
2906*am33
2907{
2908 int srcreg1, srcreg2, dstreg;
2909 long temp, sum;
2910 int v;
2911
2912 PC = cia;
2913 srcreg1 = translate_rreg (SD_, RM2);
2914 srcreg2 = translate_rreg (SD_, RN0);
2915 dstreg = translate_rreg (SD_, RD0);
2916
2917 temp = ((signed32)(State.regs[srcreg2] & 0xffff)
2918 * (signed32)(State.regs[srcreg1] & 0xffff));
2919 sum = State.regs[dstreg] + temp;
2920 v = ((State.regs[dstreg] & 0x80000000) == (temp & 0x80000000)
2921 && (temp & 0x80000000) != (sum & 0x80000000));
2922 State.regs[dstreg] = sum;
2923 if (v)
2924 State.regs[REG_MCVF] = 1;
2925}
2926
2927// 1111 1011 0101 1111 Rm Rn Rd1; machu Rm,Rn,Rd1
29288.0xfb+8.0x5f+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::machu
2929"machu"
2930*am33
2931{
2932 int srcreg1, srcreg2, dstreg;
2933 long temp, sum;
2934 int v;
2935
2936 PC = cia;
2937 srcreg1 = translate_rreg (SD_, RM2);
2938 srcreg2 = translate_rreg (SD_, RN0);
2939 dstreg = translate_rreg (SD_, RD0);
2940
2941 temp = ((unsigned32)(State.regs[srcreg2] & 0xffff)
2942 * (unsigned32)(State.regs[srcreg1] & 0xffff));
2943 sum = State.regs[dstreg] + temp;
2944 v = ((State.regs[dstreg] & 0x80000000) == (temp & 0x80000000)
2945 && (temp & 0x80000000) != (sum & 0x80000000));
2946 State.regs[dstreg] = sum;
2947 if (v)
2948 State.regs[REG_MCVF] = 1;
2949}
2950
2951// 1111 1011 0110 1111 Rm Rn Rd1; dmach Rm,Rn,Rd1
29528.0xfb+8.0x6f+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::dmach
2953"dmach"
2954*am33
2955{
2956 int srcreg1, srcreg2, dstreg;
2957 long temp, temp2, sum;
2958 int v;
2959
2960 PC = cia;
2961 srcreg1 = translate_rreg (SD_, RM2);
2962 srcreg2 = translate_rreg (SD_, RN0);
2963 dstreg = translate_rreg (SD_, RD0);
2964
2965 temp = ((signed32)(State.regs[srcreg2] & 0xffff)
2966 * (signed32)(State.regs[srcreg1] & 0xffff));
2967 temp2 = ((signed32)((State.regs[srcreg1] >> 16) & 0xffff)
2968 * (signed32)((State.regs[srcreg2] >> 16) & 0xffff));
2969 sum = temp + temp2 + State.regs[dstreg];
2970 v = ((State.regs[dstreg] & 0x80000000) == (temp & 0x80000000)
2971 && (temp & 0x80000000) != (sum & 0x80000000));
2972 State.regs[dstreg] = sum;
2973 if (v)
2974 State.regs[REG_MCVF] = 1;
2975}
2976
2977// 1111 1011 0111 1111 Rm Rn Rd1; dmachu Rm,Rn,Rd1
29788.0xfb+8.0x7f+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::dmachu
2979"dmachu"
2980*am33
2981{
2982 int srcreg1, srcreg2, dstreg;
2983 long temp, temp2, sum;
2984 int v;
2985
2986 PC = cia;
2987 srcreg1 = translate_rreg (SD_, RM2);
2988 srcreg2 = translate_rreg (SD_, RN0);
2989 dstreg = translate_rreg (SD_, RD0);
2990
2991 temp = ((unsigned32)(State.regs[srcreg2] & 0xffff)
2992 * (unsigned32)(State.regs[srcreg1] & 0xffff));
2993 temp2 = ((unsigned32)((State.regs[srcreg1] >> 16) & 0xffff)
2994 * (unsigned32)((State.regs[srcreg2] >> 16) & 0xffff));
2995 sum = temp + temp2 + State.regs[dstreg];
2996 v = ((State.regs[dstreg] & 0x80000000) == (temp & 0x80000000)
2997 && (temp & 0x80000000) != (sum & 0x80000000));
2998 State.regs[dstreg] = sum;
2999 if (v)
3000 State.regs[REG_MCVF] = 1;
3001}
3002
3003// 1111 1011 1000 1111 Rm Rn Rd1 Rd2; dmulh Rm,Rn,Rd1,Rd2
30048.0xfb+8.0x8f+4.RM2,4.RN0+4.RD0,4.RD2:D2c:::dmulh
3005"dmulh"
3006*am33
3007{
3008 int srcreg1, srcreg2, dstreg1, dstreg2;
3009 signed long long temp;
3010
3011 PC = cia;
3012 srcreg1 = translate_rreg (SD_, RM2);
3013 srcreg2 = translate_rreg (SD_, RN0);
3014 dstreg1 = translate_rreg (SD_, RD0);
3015 dstreg2 = translate_rreg (SD_, RD2);
3016
3017 temp = ((signed32)(State.regs[srcreg1] & 0xffff)
3018 * (signed32)(State.regs[srcreg1] & 0xffff));
3019 State.regs[dstreg2] = temp;
3020 temp = ((signed32)((State.regs[srcreg1] >> 16) & 0xffff)
3021 * (signed32)((State.regs[srcreg1] >>16) & 0xffff));
3022 State.regs[dstreg1] = temp;
3023}
3024
3025// 1111 1011 1001 1111 Rm Rn Rd1 Rd2; dmulhu Rm,Rn,Rd1,Rd2
30268.0xfb+8.0x9f+4.RM2,4.RN0+4.RD0,4.RD2:D2c:::dmulhu
3027"dmulhu"
3028*am33
3029{
3030 int srcreg1, srcreg2, dstreg1, dstreg2;
3031 signed long long temp;
3032
3033 PC = cia;
3034 srcreg1 = translate_rreg (SD_, RM2);
3035 srcreg2 = translate_rreg (SD_, RN0);
3036 dstreg1 = translate_rreg (SD_, RD0);
3037 dstreg2 = translate_rreg (SD_, RD2);
3038
3039 temp = ((unsigned32)(State.regs[srcreg1] & 0xffff)
3040 * (unsigned32)(State.regs[srcreg1] & 0xffff));
3041 State.regs[dstreg2] = temp;
3042 temp = ((unsigned32)((State.regs[srcreg1] >> 16) & 0xffff)
3043 * (unsigned32)((State.regs[srcreg1] >>16) & 0xffff));
3044 State.regs[dstreg1] = temp;
3045}
377e53bb
JL		 3046
3047// 1111 1011 1010 1111 Rm Rn; sat24 Rm,Rn
30488.0xfb+8.0xaf+4.RM2,4.RN0+8.0x0:D2:::sat24
3049"sat24"
3e75ff7e
JL		 3050*am33
3051{
377e53bb
JL		 3052 int srcreg, dstreg;
3053 int value;
3e75ff7e
JL		 3054
3055 PC = cia;
9c55817e
JL		 3056 srcreg = translate_rreg (SD_, RM2);
3057 dstreg = translate_rreg (SD_, RN0);
3e75ff7e 3058
377e53bb 3059 value = State.regs[srcreg];
3e75ff7e 3060
377e53bb
JL		 3061 if (value >= 0x7fffff)
3062 State.regs[dstreg] = 0x7fffff;
3063 else if (value <= 0xff800000)
3064 State.regs[dstreg] = 0xff800000;
3065 else
3066 State.regs[dstreg] = value;
3e75ff7e
JL		 3067}
3068
1f0ba346
JL		 3069// 1111 1011 1111 1111 Rm Rn Rd1; bsch Rm,Rn,Rd1
30708.0xfb+8.0xff+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::bsch
3071"bsch"
3072*am33
3073{
3074 int temp, c, i;
3075 int srcreg1, srcreg2, dstreg;
3076 int start;
3077
3078 PC = cia;
3079 srcreg1 = translate_rreg (SD_, RM2);
3080 srcreg2 = translate_rreg (SD_, RN0);
3081 dstreg = translate_rreg (SD_, RD0);
3082
3083 temp = State.regs[srcreg1];
3084 start = (State.regs[srcreg2] & 0x1f) - 1;
3085 if (start == -1)
3086 start = 31;
3087
3088 for (i = start; i >= 0; i--)
3089 {
3090 if (temp & (1 << i))
3091 {
3092 c = 1;
3093 State.regs[dstreg] = i;
3094 break;
3095 }
3096 }
3097
3098 if (i < 0)
3099 {
3100 c = 0;
3101 State.regs[dstreg] = 0;
3102 }
3103 PSW &= ~(PSW_C);
3104 PSW |= (c ? PSW_C : 0);
3105}
3e75ff7e
JL		 3106
3107// 1111 1101 0000 1000 Rn Rn IMM32; mov imm24,Rn
31088.0xfd+8.0x08+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4t:::mov
3109"mov"
3110*am33
3111{
3112 int dstreg;
3113
3114 PC = cia;
9c55817e 3115 dstreg = translate_rreg (SD_, RN0);
3e75ff7e
JL		 3116 State.regs[dstreg] = EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C));
3117}
3118
3119// 1111 1101 0001 1000 Rn Rn IMM32; movu imm24,Rn
31208.0xfd+8.0x18+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4k:::movu
3121"movu"
3122*am33
3123{
3124 int dstreg;
3125
3126 PC = cia;
9c55817e 3127 dstreg = translate_rreg (SD_, RN0);
3e75ff7e
JL		 3128 State.regs[dstreg] = FETCH24 (IMM24A, IMM24B, IMM24C) & 0xffffff;
3129}
3130
3131// 1111 1101 0111 1000 Rn Rn IMM32; add imm24,Rn
31328.0xfd+8.0x78+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4c:::add
3133"add"
3134*am33
3135{
3136 int dstreg;
3137
3138 PC = cia;
9c55817e 3139 dstreg = translate_rreg (SD_, RN0);
4e86afb8 3140 genericAdd (EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C)), dstreg);
3e75ff7e
JL		 3141}
3142
3143// 1111 1101 1000 1000 Rn Rn IMM32; addc imm24,Rn
31448.0xfd+8.0x88+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::addc
3145"addc"
3146*am33
3147{
3148 int dstreg, z, n, c, v;
3149 unsigned long sum, imm, reg2;
3150
3151 PC = cia;
9c55817e 3152 dstreg = translate_rreg (SD_, RN0);
3e75ff7e
JL		 3153
3154 imm = EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C));
3155 reg2 = State.regs[dstreg];
3156 sum = imm + reg2 + ((PSW & PSW_C) != 0);
3157 State.regs[dstreg] = sum;
3158
080ee2ba 3159 z = ((PSW & PSW_Z) != 0) && (sum == 0);
3e75ff7e
JL		 3160 n = (sum & 0x80000000);
3161 c = (sum < imm) || (sum < reg2);
3162 v = ((reg2 & 0x80000000) == (imm & 0x80000000)
3163 && (reg2 & 0x80000000) != (sum & 0x80000000));
3164
3165 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
3166 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
3167 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
3168}
3169
3170// 1111 1101 1001 1000 Rn Rn IMM32; sub imm24,Rn
31718.0xfd+8.0x98+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::sub
3172"sub"
3173*am33
3174{
3175 int dstreg;
3176
3177 PC = cia;
9c55817e 3178 dstreg = translate_rreg (SD_, RN0);
4e86afb8 3179 genericSub (EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C)), dstreg);
3e75ff7e
JL		 3180}
3181
3182// 1111 1101 1010 1000 Rn Rn IMM32; subc imm24,Rn
31838.0xfd+8.0xa8+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::subc
3184"subc"
3185*am33
3186{
3187 int dstreg, z, n, c, v;
3188 unsigned long difference, imm, reg2;
3189
3190 PC = cia;
9c55817e 3191 dstreg = translate_rreg (SD_, RN0);
3e75ff7e
JL		 3192
3193 imm = EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C));
3194 reg2 = State.regs[dstreg];
3195 difference = reg2 - imm - ((PSW & PSW_C) != 0);
3196 State.regs[dstreg] = difference;
3197
080ee2ba 3198 z = ((PSW & PSW_Z) != 0) && (difference == 0);
3e75ff7e
JL		 3199 n = (difference & 0x80000000);
3200 c = (imm > reg2);
3201 v = ((reg2 & 0x80000000) == (imm & 0x80000000)
3202 && (reg2 & 0x80000000) != (difference & 0x80000000));
3203
3204 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
3205 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
3206 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
3207}
3208
3209// 1111 1101 1101 1000 Rn Rn IMM32; cmp imm24,Rn
32108.0xfd+8.0xd8+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::cmp
3211"cmp"
3212*am33
3213{
3214 int srcreg;
3215
3216 PC = cia;
9c55817e 3217 srcreg = translate_rreg (SD_, RN0);
3e75ff7e
JL		 3218 genericCmp (EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C)), State.regs[srcreg]);
3219}
3220
3221// 1111 1101 1111 1000 XRn XRn IMM32; mov imm24,XRn
32228.0xfd+8.0xf8+4.XRM2,4.XRN0=XRM2+8.IMM24A+8.IMM24B+8.IMM24C:D4o:::mov
3223"mov"
3224*am33
3225{
3e75ff7e
JL		 3226 PC = cia;
3227
3228 if (XRN0 == 0)
3229 {
3230 State.regs[REG_SP] = FETCH24 (IMM24A, IMM24B, IMM24C) & 0xffffff;
3231 }
3232 else
3233 abort ();
3234}
3235
3236// 1111 1101 0000 1001 Rn Rn IMM24; and imm24,Rn
32378.0xfd+8.0x09+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::and
3238"and"
3239*am33
3240{
3241 int dstreg;
3242 int z,n;
3243
3244 PC = cia;
9c55817e 3245 dstreg = translate_rreg (SD_, RN0);
3e75ff7e
JL		 3246
3247 State.regs[dstreg] &= (FETCH24 (IMM24A, IMM24B, IMM24C) & 0xffffff);
3248 z = (State.regs[dstreg] == 0);
3249 n = (State.regs[dstreg] & 0x80000000) != 0;
3250 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
3251 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
3252}
3253
3254// 1111 1101 0001 1001 Rn Rn IMM24; or imm24,Rn
32558.0xfd+8.0x19+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::or
3256"or"
3257*am33
3258{
3259 int dstreg;
3260 int z,n;
3261
3262 PC = cia;
9c55817e 3263 dstreg = translate_rreg (SD_, RN0);
3e75ff7e
JL		 3264
3265 State.regs[dstreg] |= (FETCH24 (IMM24A, IMM24B, IMM24C) & 0xffffff);
3266 z = (State.regs[dstreg] == 0);
3267 n = (State.regs[dstreg] & 0x80000000) != 0;
3268 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
3269 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
3270}
3271
3272// 1111 1101 0010 1001 Rn Rn IMM24; xor imm24,Rn
32738.0xfd+8.0x29+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::xor
3274"xor"
3275*am33
3276{
3277 int dstreg;
3278 int z,n;
3279
3280 PC = cia;
9c55817e 3281 dstreg = translate_rreg (SD_, RN0);
3e75ff7e
JL		 3282
3283 State.regs[dstreg] ^= (FETCH24 (IMM24A, IMM24B, IMM24C) & 0xffffff);
3284 z = (State.regs[dstreg] == 0);
3285 n = (State.regs[dstreg] & 0x80000000) != 0;
3286 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
3287 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
3288}
3289
3290// 1111 1101 0100 1001 Rn Rn IMM24; asr imm24,Rn
32918.0xfd+8.0x49+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::asr
3292"asr"
3293*am33
3294{
3295 int dstreg;
3296 long temp;
3297 int c, z, n;
3298
3299 PC = cia;
9c55817e 3300 dstreg = translate_rreg (SD_, RN0);
3e75ff7e
JL		 3301
3302 temp = State.regs[dstreg];
3303 c = temp & 1;
3304 temp >>= (FETCH24 (IMM24A, IMM24B, IMM24C));
3305 State.regs[dstreg] = temp;
3306 z = (State.regs[dstreg] == 0);
3307 n = (State.regs[dstreg] & 0x80000000) != 0;
3308 PSW &= ~(PSW_Z | PSW_N | PSW_C);
3309 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
3310}
3311
3312
3313// 1111 1101 0101 1001 Rn Rn IMM24; lsr imm24,Rn
33148.0xfd+8.0x59+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::lsr
3315"lsr"
3316*am33
3317{
3318 int dstreg;
3319 int z, n, c;
3320
3321 PC = cia;
9c55817e 3322 dstreg = translate_rreg (SD_, RN0);
3e75ff7e
JL		 3323
3324 c = State.regs[dstreg] & 1;
3325 State.regs[dstreg] >>= (FETCH24 (IMM24A, IMM24B, IMM24C));
3326 z = (State.regs[dstreg] == 0);
3327 n = (State.regs[dstreg] & 0x80000000) != 0;
3328 PSW &= ~(PSW_Z | PSW_N | PSW_C);
3329 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
3330}
3331
3332// 1111 1101 0110 1001 Rn Rn IMM24; asl imm24,Rn
33338.0xfd+8.0x69+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::asl
3334"asl"
3335*am33
3336{
3337 int srcreg, dstreg;
3338 int z, n;
3339
3340 PC = cia;
9c55817e 3341 dstreg = translate_rreg (SD_, RN0);
3e75ff7e
JL		 3342
3343 State.regs[dstreg] <<= (FETCH24 (IMM24A, IMM24B, IMM24C));
3344 z = (State.regs[dstreg] == 0);
3345 n = (State.regs[dstreg] & 0x80000000) != 0;
3346 PSW &= ~(PSW_Z | PSW_N);
3347 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
3348}
3349
1f0ba346
JL		 3350// 1111 1101 1010 1001 Rn Rn IMM24; mul imm24,Rn
33518.0xfd+8.0xa9+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::mul
3352"mul"
3353*am33
3354{
3355 int dstreg;
3356 unsigned long long temp;
3357 int z, n;
3358
3359 PC = cia;
3360 dstreg = translate_rreg (SD_, RN0);
3361
3362 temp = ((signed64)(signed32)State.regs[dstreg]
3363 * (signed64)(signed32)EXTEND8 (FETCH24 (IMM24A, IMM24B, IMM24C)));
3364 State.regs[dstreg] = temp & 0xffffffff;
3365 State.regs[REG_MDR] = (temp & 0xffffffff00000000LL) >> 32;;
3366 z = (State.regs[dstreg] == 0);
3367 n = (State.regs[dstreg] & 0x80000000) != 0;
3368 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
3369 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
3370}
3371
3372// 1111 1101 1011 1001 Rn Rn IMM24; mulu imm24,Rn
33738.0xfd+8.0xb9+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::mulu
3374"mulu"
3375*am33
3376{
3377 int dstreg;
3378 unsigned long long temp;
3379 int z, n;
3380
3381 PC = cia;
3382 dstreg = translate_rreg (SD_, RN0);
3383
3384 temp = ((unsigned64)State.regs[dstreg]
3385 * (unsigned64)EXTEND8 (FETCH24 (IMM24A, IMM24B, IMM24C)));
3386 State.regs[dstreg] = temp & 0xffffffff;
3387 State.regs[REG_MDR] = (temp & 0xffffffff00000000LL) >> 32;;
3388 z = (State.regs[dstreg] == 0);
3389 n = (State.regs[dstreg] & 0x80000000) != 0;
3390 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
3391 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
3392}
3e75ff7e
JL		 3393
3394// 1111 1101 1110 1001 Rn Rn IMM24; btst imm24,,Rn
33958.0xfd+8.0xe9+4.RN2,4.RN0=RN2+8.IMM24A+8.IMM24B+8.IMM24C:D4p:::btst
3396"btst"
3397*am33
3398{
3399 int srcreg;
3400
3401 PC = cia;
9c55817e 3402 srcreg = translate_rreg (SD_, RN0);
3e75ff7e
JL		 3403 genericBtst (FETCH24 (IMM24A, IMM24B, IMM24C), State.regs[srcreg]);
3404}
3405
3406// 1111 1101 0000 1010 Rn Rm IMM24; mov (d24,Rm),Rn
34078.0xfd+8.0x0a+4.RN2,4.RM0+8.IMM24A+8.IMM24B+8.IMM24C:D4p:::mov
3408"mov"
3409*am33
3410{
3411 int srcreg, dstreg;
3412
3413 PC = cia;
9c55817e
JL		 3414 srcreg = translate_rreg (SD_, RM0);
3415 dstreg = translate_rreg (SD_, RN2);
3e75ff7e 3416 State.regs[dstreg] = load_word (State.regs[srcreg]
080ee2ba
JL		 3417 + EXTEND24 (FETCH24 (IMM24A,
3418 IMM24B, IMM24C)));
3e75ff7e
JL		 3419}
3420
3421// 1111 1101 0001 1010 Rm Rn IMM24; mov Rm,(d24,Rn)
34228.0xfd+8.0x1a+4.RM2,4.RN0+8.IMM24A+8.IMM24B+8.IMM24C:D4q:::mov
3423"mov"
3424*am33
3425{
3426 int srcreg, dstreg;
3427
3428 PC = cia;
9c55817e
JL		 3429 srcreg = translate_rreg (SD_, RM2);
3430 dstreg = translate_rreg (SD_, RN0);
080ee2ba 3431 store_word (State.regs[dstreg] + EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C)),
3e75ff7e
JL		 3432 State.regs[srcreg]);
3433}
3434
3435// 1111 1101 0010 1010 Rn Rm IMM24; movbu (d24,Rm),Rn
34368.0xfd+8.0x2a+4.RN2,4.RM0+8.IMM24A+8.IMM24B+8.IMM24C:D4p:::movbu
3437"movbu"
3438*am33
3439{
3440 int srcreg, dstreg;
3441
3442 PC = cia;
9c55817e
JL		 3443 srcreg = translate_rreg (SD_, RM0);
3444 dstreg = translate_rreg (SD_, RN2);
3e75ff7e 3445 State.regs[dstreg] = load_byte (State.regs[srcreg]
080ee2ba
JL		 3446 + EXTEND24 (FETCH24 (IMM24A,
3447 IMM24B, IMM24C)));
3e75ff7e
JL		 3448}
3449
3450// 1111 1101 0011 1010 Rm Rn IMM24; movbu Rm,(d24,Rn)
34518.0xfd+8.0x3a+4.RM2,4.RN0+8.IMM24A+8.IMM24B+8.IMM24C:D4q:::movbu
3452"movbu"
3453*am33
3454{
3455 int srcreg, dstreg;
3456
3457 PC = cia;
9c55817e
JL		 3458 srcreg = translate_rreg (SD_, RM2);
3459 dstreg = translate_rreg (SD_, RN0);
080ee2ba 3460 store_byte (State.regs[dstreg] + EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C)),
3e75ff7e
JL		 3461 State.regs[srcreg]);
3462}
3463
3464// 1111 1101 0100 1010 Rn Rm IMM24; movhu (d24,Rm),Rn
34658.0xfd+8.0x4a+4.RN2,4.RM0+8.IMM24A+8.IMM24B+8.IMM24C:D4p:::movhu
3466"movhu"
3467*am33
3468{
3469 int srcreg, dstreg;
3470
3471 PC = cia;
9c55817e
JL		 3472 srcreg = translate_rreg (SD_, RM0);
3473 dstreg = translate_rreg (SD_, RN2);
3e75ff7e 3474 State.regs[dstreg] = load_half (State.regs[srcreg]
080ee2ba
JL		 3475 + EXTEND24 (FETCH24 (IMM24A,
3476 IMM24B, IMM24C)));
3e75ff7e
JL		 3477}
3478
3479// 1111 1101 0101 1010 Rm Rn IMM24; movhu Rm,(d24,Rn)
34808.0xfd+8.0x5a+4.RM2,4.RN0+8.IMM24A+8.IMM24B+8.IMM24C:D4q:::movhu
3481"movhu"
3482*am33
3483{
3484 int srcreg, dstreg;
3485
3486 PC = cia;
9c55817e
JL		 3487 srcreg = translate_rreg (SD_, RM2);
3488 dstreg = translate_rreg (SD_, RN0);
080ee2ba 3489 store_half (State.regs[dstreg] + EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C)),
3e75ff7e
JL		 3490 State.regs[srcreg]);
3491}
3492
377e53bb
JL		 3493// 1111 1101 0110 1010 Rn Rm IMM24; mov (d24,Rm+),Rn
34948.0xfd+8.0x6a+4.RN2,4.RM0+8.IMM24A+8.IMM24B+8.IMM24C:D4y:::mov
3495"mov"
3496*am33
3497{
3498 int srcreg, dstreg;
3499
3500 PC = cia;
9c55817e
JL		 3501 srcreg = translate_rreg (SD_, RM0);
3502 dstreg = translate_rreg (SD_, RN2);
377e53bb 3503 State.regs[dstreg] = load_word (State.regs[srcreg]
080ee2ba
JL		 3504 + EXTEND24 (FETCH24 (IMM24A,
3505 IMM24B, IMM24C)));
377e53bb
JL		 3506 State.regs[srcreg] += 4;
3507}
3508
3509// 1111 1101 0111 1010 Rm Rn IMM24; mov Rm,(d24,Rn+)
35108.0xfd+8.0x7a+4.RM2,4.RN0+8.IMM24A+8.IMM24B+8.IMM24C:D4z:::mov
3511"mov"
3512*am33
3513{
3514 int srcreg, dstreg;
3515
3516 PC = cia;
9c55817e
JL		 3517 srcreg = translate_rreg (SD_, RM2);
3518 dstreg = translate_rreg (SD_, RN0);
080ee2ba 3519 store_word (State.regs[dstreg] + EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C)),
377e53bb
JL		 3520 State.regs[srcreg]);
3521 State.regs[dstreg] += 4;
3522}
3523
3e75ff7e
JL		 3524
3525// 1111 1101 1000 1010 Rn 0000 IMM24; mov (d24,sp),Rn
35268.0xfd+8.0x8a+4.RN2,4.0x0+IMM24A+8.IMM24B+8.IMM24C:D4r:::mov
3527"mov"
3528*am33
3529{
3530 int dstreg;
3531
3532 PC = cia;
9c55817e 3533 dstreg = translate_rreg (SD_, RN2);
3e75ff7e 3534 State.regs[dstreg] = load_word (State.regs[REG_SP]
080ee2ba
JL		 3535 + EXTEND24 (FETCH24 (IMM24A,
3536 IMM24B, IMM24C)));
3e75ff7e
JL		 3537}
3538
3539// 1111 1101 1001 1010 Rm 0000 IMM24; mov Rm,(d24,sp)
35408.0xfd+8.0x9a+4.RM2,4.0x0+8.IMM24A+8.IMM24B+8.IMM24C:D4s:::mov
3541"mov"
3542*am33
3543{
3544 int srcreg;
3545
3546 PC = cia;
9c55817e 3547 srcreg = translate_rreg (SD_, RM2);
080ee2ba 3548 store_word (State.regs[REG_SP] + EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C)),
3e75ff7e
JL		 3549 State.regs[srcreg]);
3550}
3551
3552// 1111 1101 1010 1010 Rn 0000 IMM24; movbu (d24,Rm),Rn
35538.0xfd+8.0xaa+4.RN2,4.0x0+8.IMM24A+8.IMM24B+8.IMM24C:D4r:::movbu
3554"movbu"
3555*am33
3556{
3557 int dstreg;
3558
3559 PC = cia;
9c55817e 3560 dstreg = translate_rreg (SD_, RN2);
3e75ff7e 3561 State.regs[dstreg] = load_byte (State.regs[REG_SP]
080ee2ba
JL		 3562 + EXTEND24 (FETCH24 (IMM24A,
3563 IMM24B, IMM24C)));
3e75ff7e
JL		 3564}
3565
3566// 1111 1101 1011 1010 Rm 0000 IMM24; movbu Rm,(d24,sp)
35678.0xfd+8.0xba+4.RM2,4.0x0+8.IMM24A+8.IMM24B+8.IMM24C:D4s:::movbu
3568"movbu"
3569*am33
3570{
3571 int srcreg;
3572
3573 PC = cia;
9c55817e 3574 srcreg = translate_rreg (SD_, RM2);
080ee2ba 3575 store_byte (State.regs[REG_SP] + EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C)),
3e75ff7e
JL		 3576 State.regs[srcreg]);
3577}
3578
3579// 1111 1101 1100 1010 Rn 0000 IMM24; movhu (d24,sp),Rn
35808.0xfd+8.0xca+4.RN2,4.0x0+8.IMM24A+8.IMM24B+8.IMM24C:D4r:::movhu
3581"movhu"
3582*am33
3583{
3584 int dstreg;
3585
3586 PC = cia;
9c55817e 3587 dstreg = translate_rreg (SD_, RN2);
3e75ff7e 3588 State.regs[dstreg] = load_half (State.regs[REG_SP]
080ee2ba
JL		 3589 + EXTEND24 (FETCH24 (IMM24A,
3590 IMM24B, IMM24C)));
3e75ff7e
JL		 3591}
3592
3593// 1111 1101 1101 1010 Rm Rn IMM24; movhu Rm,(d24,sp)
35948.0xfd+8.0xda+4.RM2,4.RN0+8.IMM24A+8.IMM24B+8.IMM24C:D4s:::movhu
3595"movhu"
3596*am33
3597{
3598 int srcreg;
3599
3600 PC = cia;
9c55817e 3601 srcreg = translate_rreg (SD_, RM2);
080ee2ba 3602 store_half (State.regs[REG_SP] + EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C)),
3e75ff7e
JL		 3603 State.regs[srcreg]);
3604}
3605
377e53bb
JL		 3606// 1111 1101 1110 1010 Rn Rm IMM24; movhu (d24,Rm+),Rn
36078.0xfd+8.0xea+4.RN2,4.RM0+8.IMM24A+8.IMM24B+8.IMM24C:D4y:::movhu
3608"movhu"
3609*am33
3610{
3611 int srcreg, dstreg;
3612
3613 PC = cia;
9c55817e
JL		 3614 srcreg = translate_rreg (SD_, RM0);
3615 dstreg = translate_rreg (SD_, RN2);
377e53bb 3616 State.regs[dstreg] = load_half (State.regs[srcreg]
080ee2ba
JL		 3617 + EXTEND24 (FETCH24 (IMM24A,
3618 IMM24B, IMM24C)));
377e53bb
JL		 3619 State.regs[dstreg] += 2;
3620}
3621
3622// 1111 1101 1111 1010 Rm Rn IMM24; movhu Rm,(d24,Rn+)
36238.0xfd+8.0xfa+4.RM2,4.RN0+8.IMM24A+8.IMM24B+8.IMM24C:D4z:::movhu
3624"movhu"
3625*am33
3626{
3627 int srcreg, dstreg;
3628
3629 PC = cia;
9c55817e
JL		 3630 srcreg = translate_rreg (SD_, RM2);
3631 dstreg = translate_rreg (SD_, RN0);
080ee2ba 3632 store_half (State.regs[dstreg] + EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C)),
377e53bb
JL		 3633 State.regs[srcreg]);
3634 State.regs[srcreg] += 2;
3635}
3636
1f0ba346
JL		 3637// 1111 1101 0000 1011 Rn IMM24; mac imm24,Rn
36388.0xfd+8.0x0b+4.RN2,4.RN0=RN2+8.IMM24A+8.IMM24B+8.IMM24C:D4z:::mac
3639"mac"
3640*am33
3641{
3642 int srcreg;
3643 long long temp, sum;
3644 int c, v;
3645
3646 PC = cia;
3647 srcreg = translate_rreg (SD_, RN2);
3648
3649 temp = ((signed64)EXTEND8 (FETCH24 (IMM24A, IMM24B, IMM24C))
3650 * (signed64)State.regs[srcreg]);
3651 sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
3652 c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
3653 State.regs[REG_MCRL] = sum;
3654 temp >>= 32;
3655 temp &= 0xffffffff;
3656 sum = State.regs[REG_MCRH] + temp + c;
3657 v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
3658 && (temp & 0x80000000) != (sum & 0x80000000));
3659 State.regs[REG_MCRH] = sum;
3660 if (v)
3661 State.regs[REG_MCVF] = 1;
3662}
3663
3664// 1111 1101 0001 1011 Rn IMM24; macu imm24,Rn
36658.0xfd+8.0x1b+4.RN2,4.RN0=RN2+8.IMM24A+8.IMM24B+8.IMM24C:D4z:::macu
3666"macu"
3667*am33
3668{
3669 int srcreg;
3670 long long temp, sum;
3671 int c, v;
3672
3673 PC = cia;
3674 srcreg = translate_rreg (SD_, RN2);
3675
3676 temp = ((unsigned64) (FETCH24 (IMM24A, IMM24B, IMM24C))
3677 * (unsigned64)State.regs[srcreg]);
3678 sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
3679 c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
3680 State.regs[REG_MCRL] = sum;
3681 temp >>= 32;
3682 temp &= 0xffffffff;
3683 sum = State.regs[REG_MCRH] + temp + c;
3684 v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
3685 && (temp & 0x80000000) != (sum & 0x80000000));
3686 State.regs[REG_MCRH] = sum;
3687 if (v)
3688 State.regs[REG_MCVF] = 1;
3689}
3690
3691// 1111 1101 0010 1011 Rn IMM24; macb imm24,Rn
36928.0xfd+8.0x2b+4.RN2,4.RN0=RN2+8.IMM24A+8.IMM24B+8.IMM24C:D4z:::macb
3693"macb"
3694*am33
3695{
3696 int srcreg;
3697 long long temp, sum;
3698 int c, v;
3699
3700 PC = cia;
3701 srcreg = translate_rreg (SD_, RN2);
3702
3703 temp = ((signed64)EXTEND8 (FETCH24 (IMM24A, IMM24B, IMM24C))
3704 * (signed64)State.regs[srcreg] & 0xff);
3705 sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
3706 c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
3707 State.regs[REG_MCRL] = sum;
3708 temp >>= 32;
3709 temp &= 0xffffffff;
3710 sum = State.regs[REG_MCRH] + temp + c;
3711 v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
3712 && (temp & 0x80000000) != (sum & 0x80000000));
3713 State.regs[REG_MCRH] = sum;
3714 if (v)
3715 State.regs[REG_MCVF] = 1;
3716}
3717
3718// 1111 1101 0011 1011 Rn IMM24; macbu imm24,Rn
37198.0xfd+8.0x3b+4.RN2,4.RN0=RN2+8.IMM24A+8.IMM24B+8.IMM24C:D4z:::macbu
3720"macbu"
3721*am33
3722{
3723 int srcreg;
3724 long long temp, sum;
3725 int c, v;
3726
3727 PC = cia;
3728 srcreg = translate_rreg (SD_, RN2);
3729
3730 temp = ((unsigned64) (FETCH24 (IMM24A, IMM24B, IMM24C))
3731 * (unsigned64)State.regs[srcreg] & 0xff);
3732 sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
3733 c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
3734 State.regs[REG_MCRL] = sum;
3735 temp >>= 32;
3736 temp &= 0xffffffff;
3737 sum = State.regs[REG_MCRH] + temp + c;
3738 v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
3739 && (temp & 0x80000000) != (sum & 0x80000000));
3740 State.regs[REG_MCRH] = sum;
3741 if (v)
3742 State.regs[REG_MCVF] = 1;
3743}
3744
3745// 1111 1101 0100 1011 Rn IMM24; mach imm24,Rn
37468.0xfd+8.0x4b+4.RN2,4.RN0=RN2+8.IMM24A+8.IMM24B+8.IMM24C:D4z:::mach
3747"mach"
3748*am33
3749{
3750 int srcreg;
3751 long long temp, sum;
3752 int c, v;
3753
3754 PC = cia;
3755 srcreg = translate_rreg (SD_, RN2);
3756
3757 temp = ((signed64)EXTEND16 (FETCH24 (IMM24A, IMM24B, IMM24C))
3758 * (signed64)State.regs[srcreg] & 0xffff);
3759 sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
3760 c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
3761 State.regs[REG_MCRL] = sum;
3762 temp >>= 32;
3763 temp &= 0xffffffff;
3764 sum = State.regs[REG_MCRH] + temp + c;
3765 v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
3766 && (temp & 0x80000000) != (sum & 0x80000000));
3767 State.regs[REG_MCRH] = sum;
3768 if (v)
3769 State.regs[REG_MCVF] = 1;
3770}
3771
3772// 1111 1101 0101 1011 Rn IMM24; machu imm24,Rn
37738.0xfd+8.0x5b+4.RN2,4.RN0=RN2+8.IMM24A+8.IMM24B+8.IMM24C:D4z:::machu
3774"machu"
3775*am33
3776{
3777 int srcreg;
3778 long long temp, sum;
3779 int c, v;
3780
3781 PC = cia;
3782 srcreg = translate_rreg (SD_, RN2);
3783
3784 temp = ((unsigned64) (FETCH24 (IMM24A, IMM24B, IMM24C) & 0xffff)
3785 * (unsigned64)State.regs[srcreg] & 0xffff);
3786 sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
3787 c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
3788 State.regs[REG_MCRL] = sum;
3789 temp >>= 32;
3790 temp &= 0xffffffff;
3791 sum = State.regs[REG_MCRH] + temp + c;
3792 v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
3793 && (temp & 0x80000000) != (sum & 0x80000000));
3794 State.regs[REG_MCRH] = sum;
3795 if (v)
3796 State.regs[REG_MCVF] = 1;
3797}
3e75ff7e
JL		 3798
3799// 1111 1101 0000 1110 Rn 0000 ABS24; mov (abs24),Rn
38008.0xfd+8.0x0e+4.RN2,4.0x0+8.IMM24A+8.IMM24B+8.IMM24C:D4u:::mov
3801"mov"
3802*am33
3803{
3804 int dstreg;
3805
3806 PC = cia;
9c55817e 3807 dstreg = translate_rreg (SD_, RN2);
3e75ff7e
JL		 3808 State.regs[dstreg] = load_word (FETCH24 (IMM24A, IMM24B, IMM24C));
3809}
3810
3811// 1111 1101 0001 1110 Rm 0000 ABS24; mov Rm,(abs24)
38128.0xfd+8.0x1e+4.RM2,4.0x0+8.IMM24A+8.IMM24B+8.IMM24C:D4v:::mov
3813"mov"
3814*am33
3815{
3816 int srcreg;
3817
3818 PC = cia;
9c55817e 3819 srcreg = translate_rreg (SD_, RM2);
3e75ff7e
JL		 3820 store_word (FETCH24 (IMM24A, IMM24B, IMM24C), State.regs[srcreg]);
3821}
3822
3823
3824// 1111 1101 0010 1110 Rn 0000 ABS24; movbu (abs24),Rn
38258.0xfd+8.0x2e+4.RN2,4.0x0+8.IMM24A+8.IMM24B+8.IMM24C:D4t:::movbu
3826"movbu"
3827*am33
3828{
3829 int dstreg;
3830
3831 PC = cia;
9c55817e 3832 dstreg = translate_rreg (SD_, RN2);
3e75ff7e
JL		 3833 State.regs[dstreg] = load_byte (FETCH24 (IMM24A, IMM24B, IMM24C));
3834}
3835
3836// 1111 1101 0011 1110 Rm 0000 ABS24; movbu Rm,(abs24)
38378.0xfd+8.0x3e+4.RM2,4.0x0+8.IMM24A+8.IMM24B+8.IMM24C:D4u:::movbu
3838"movbu"
3839*am33
3840{
3841 int srcreg;
3842
3843 PC = cia;
9c55817e 3844 srcreg = translate_rreg (SD_, RM2);
3e75ff7e
JL		 3845 store_byte (FETCH24 (IMM24A, IMM24B, IMM24C), State.regs[srcreg]);
3846}
3847
3848
3849// 1111 1101 0100 1110 Rn 0000 ABS24; movhu (abs24),Rn
38508.0xfd+8.0x4e+4.RN2,4.0x0+8.IMM24A+8.IMM24B+8.IMM24C:D4t:::movhu
3851"movhu"
3852*am33
3853{
3854 int dstreg;
3855
3856 PC = cia;
9c55817e 3857 dstreg = translate_rreg (SD_, RN2);
3e75ff7e
JL		 3858 State.regs[dstreg] = load_half (FETCH24 (IMM24A, IMM24B, IMM24C));
3859}
3860
3861// 1111 1101 0101 1110 Rm 0000 ABS24; movhu Rm,(abs24)
38628.0xfd+8.0x5e+4.RM2,4.0x0+8.IMM24A+8.IMM24B+8.IMM24C:D4u:::movhu
3863"movhu"
3864*am33
3865{
3866 int srcreg;
3867
3868 PC = cia;
9c55817e 3869 srcreg = translate_rreg (SD_, RM2);
3e75ff7e
JL		 3870 store_half (FETCH24 (IMM24A, IMM24B, IMM24C), State.regs[srcreg]);
3871}
3872
3873
3874// 1111 1110 0000 1000 Rn Rn IMM32; mov imm32,Rn
38758.0xfe+8.0x08+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::mov
3876"mov"
3877*am33
3878{
3879 int dstreg;
3880
3881 PC = cia;
9c55817e 3882 dstreg = translate_rreg (SD_, RN0);
3e75ff7e
JL		 3883 State.regs[dstreg] = FETCH32(IMM32A, IMM32B, IMM32C, IMM32D);
3884}
3885
3886// 1111 1110 0001 1000 Rn Rn IMM32; movu imm32,Rn
38878.0xfe+8.0x18+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::movu
3888"movu"
3889*am33
3890{
3891 int dstreg;
3892
3893 PC = cia;
9c55817e 3894 dstreg = translate_rreg (SD_, RN0);
3e75ff7e
JL		 3895 State.regs[dstreg] = FETCH32(IMM32A, IMM32B, IMM32C, IMM32D);
3896}
3897
3898// 1111 1110 0111 1000 Rn Rn IMM32; add imm32,Rn
38998.0xfe+8.0x78+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::add
3900"add"
3901*am33
3902{
3903 int dstreg;
3904
3905 PC = cia;
9c55817e 3906 dstreg = translate_rreg (SD_, RN0);
3e75ff7e
JL		 3907 genericAdd (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D), dstreg);
3908}
3909
3910// 1111 1110 1000 1000 Rn Rn IMM32; addc imm32,Rn
39118.0xfe+8.0x88+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::addc
3912"addc"
3913*am33
3914{
3915 int dstreg;
3916 unsigned int imm, reg2, sum;
3917 int z, n, c, v;
3918
3919 PC = cia;
9c55817e 3920 dstreg = translate_rreg (SD_, RN0);
3e75ff7e
JL		 3921
3922 imm = FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);
3923 reg2 = State.regs[dstreg];
3924 sum = imm + reg2 + ((PSW & PSW_C) != 0);
3925 State.regs[dstreg] = sum;
3926
080ee2ba 3927 z = ((PSW & PSW_Z) != 0) && (sum == 0);
3e75ff7e
JL		 3928 n = (sum & 0x80000000);
3929 c = (sum < imm) || (sum < reg2);
3930 v = ((reg2 & 0x80000000) == (imm & 0x80000000)
3931 && (reg2 & 0x80000000) != (sum & 0x80000000));
3932
3933 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
3934 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
3935 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
3936}
3937
3938// 1111 1110 1001 1000 Rn Rn IMM32; sub imm32,Rn
39398.0xfe+8.0x98+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::sub
3940"sub"
3941*am33
3942{
3943 int dstreg;
3944
3945 PC = cia;
9c55817e 3946 dstreg = translate_rreg (SD_, RN0);
3e75ff7e
JL		 3947 genericSub (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D), dstreg);
3948}
3949
3950// 1111 1110 1010 1000 Rn Rn IMM32; subc imm32,Rn
39518.0xfe+8.0xa8+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::subc
3952"subc"
3953*am33
3954{
3955 int dstreg;
3956 unsigned int imm, reg2, difference;
3957 int z, n, c, v;
3958
3959 PC = cia;
9c55817e 3960 dstreg = translate_rreg (SD_, RN0);
3e75ff7e
JL		 3961
3962 imm = FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);
3963 reg2 = State.regs[dstreg];
3964 difference = reg2 - imm - ((PSW & PSW_C) != 0);
3965 State.regs[dstreg] = difference;
3966
080ee2ba 3967 z = ((PSW & PSW_Z) != 0) && (difference == 0);
3e75ff7e
JL		 3968 n = (difference & 0x80000000);
3969 c = (imm > reg2);
3970 v = ((reg2 & 0x80000000) == (imm & 0x80000000)
3971 && (reg2 & 0x80000000) != (difference & 0x80000000));
3972
3973 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
3974 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
3975 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
3976}
3977
3978// 1111 1110 0111 1000 Rn Rn IMM32; cmp imm32,Rn
39798.0xfe+8.0xd8+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::cmp
3980"cmp"
3981*am33
3982{
3983 int srcreg;
3984
3985 PC = cia;
9c55817e 3986 srcreg = translate_rreg (SD_, RN0);
3e75ff7e
JL		 3987 genericCmp (FETCH32(IMM32A, IMM32B, IMM32C, IMM32D), State.regs[srcreg]);
3988}
3989
3990// 1111 1110 1111 1000 XRn XRn IMM32; mov imm32,XRn
39918.0xfe+8.0xf8+4.XRM2,4.XRN0=XRM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5b:::mov
3992"mov"
3993*am33
3994{
3e75ff7e
JL		 3995 PC = cia;
3996
3997 if (XRN0 == 0)
3998 State.regs[REG_SP] = FETCH32(IMM32A, IMM32B, IMM32C, IMM32D);
3999 else
4000 abort ();
4001}
4002
4003// 1111 1110 0000 1001 Rn Rn IMM32; and imm32,Rn
40048.0xfe+8.0x09+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::and
4005"and"
4006*am33
4007{
4008 int dstreg;
4009 int z,n;
4010
4011 PC = cia;
9c55817e 4012 dstreg = translate_rreg (SD_, RN0);
3e75ff7e
JL		 4013
4014 State.regs[dstreg] &= (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
4015 z = (State.regs[dstreg] == 0);
4016 n = (State.regs[dstreg] & 0x80000000) != 0;
4017 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
4018 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
4019}
4020
4021// 1111 1110 0001 1001 Rn Rn IMM32; or imm32,Rn
40228.0xfe+8.0x19+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::or
4023"or"
4024*am33
4025{
4026 int dstreg;
4027 int z,n;
4028
4029 PC = cia;
9c55817e 4030 dstreg = translate_rreg (SD_, RN0);
3e75ff7e
JL		 4031
4032 State.regs[dstreg] |= (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
4033 z = (State.regs[dstreg] == 0);
4034 n = (State.regs[dstreg] & 0x80000000) != 0;
4035 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
4036 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
4037}
4038
4039// 1111 1110 0010 1001 Rn Rn IMM32; xor imm32,Rn
40408.0xfe+8.0x29+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::xor
4041"xor"
4042*am33
4043{
4044 int dstreg;
4045 int z,n;
4046
4047 PC = cia;
9c55817e 4048 dstreg = translate_rreg (SD_, RN0);
3e75ff7e
JL		 4049
4050 State.regs[dstreg] ^= (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
4051 z = (State.regs[dstreg] == 0);
4052 n = (State.regs[dstreg] & 0x80000000) != 0;
4053 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
4054 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
4055}
4056
4057// 1111 1110 0100 1001 Rn Rn IMM32; asr imm32,Rn
40588.0xfe+8.0x49+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::asr
4059"asr"
4060*am33
4061{
4062 int dstreg;
4063 long temp;
4064 int c, z, n;
4065
4066 PC = cia;
9c55817e 4067 dstreg = translate_rreg (SD_, RN0);
3e75ff7e
JL		 4068
4069 temp = State.regs[dstreg];
4070 c = temp & 1;
4071 temp >>= (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
4072 State.regs[dstreg] = temp;
4073 z = (State.regs[dstreg] == 0);
4074 n = (State.regs[dstreg] & 0x80000000) != 0;
4075 PSW &= ~(PSW_Z | PSW_N | PSW_C);
4076 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
4077}
4078
4079// 1111 1110 0101 1001 Rn Rn IMM32; lsr imm32,Rn
40808.0xfe+8.0x59+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::lsr
4081"lsr"
4082*am33
4083{
4084 int dstreg;
4085 int z, n, c;
4086
4087 PC = cia;
9c55817e 4088 dstreg = translate_rreg (SD_, RN0);
3e75ff7e
JL		 4089
4090 c = State.regs[dstreg] & 1;
4091 State.regs[dstreg] >>= (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
4092 z = (State.regs[dstreg] == 0);
4093 n = (State.regs[dstreg] & 0x80000000) != 0;
4094 PSW &= ~(PSW_Z | PSW_N | PSW_C);
4095 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
4096}
4097
4098// 1111 1110 0110 1001 Rn Rn IMM32; asl imm32,Rn
40998.0xfe+8.0x69+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::asl
4100"asl"
4101*am33
4102{
4103 int srcreg, dstreg;
4104 int z, n;
4105
4106 PC = cia;
9c55817e 4107 dstreg = translate_rreg (SD_, RN0);
3e75ff7e
JL		 4108
4109 State.regs[dstreg] <<= (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
4110 z = (State.regs[dstreg] == 0);
4111 n = (State.regs[dstreg] & 0x80000000) != 0;
4112 PSW &= ~(PSW_Z | PSW_N);
4113 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
4114}
4115
377e53bb
JL		 4116// ??? mul
4117// ??? mulu
3e75ff7e
JL		 4118
4119// 1111 1110 1110 1001 Rn Rn IMM32; btst imm32,Rn
41208.0xfe+8.0xe9+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5a:::btst
4121"btst"
4122*am33
4123{
4124 int srcreg;
4125
4126 PC = cia;
9c55817e 4127 srcreg = translate_rreg (SD_, RN0);
3e75ff7e
JL		 4128 genericBtst (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D), State.regs[srcreg]);
4129}
4130
4131// 1111 1110 0000 1010 Rn Rm IMM32; mov (d32,Rm),Rn
41328.0xfe+8.0x0a+4.RN2,4.RM0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5f:::mov
4133"mov"
4134*am33
4135{
4136 int srcreg, dstreg;
4137
4138 PC = cia;
9c55817e
JL		 4139 srcreg = translate_rreg (SD_, RM0);
4140 dstreg = translate_rreg (SD_, RN2);
3e75ff7e
JL		 4141 State.regs[dstreg] = load_word (State.regs[srcreg]
4142 + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
4143}
4144
4145// 1111 1110 0001 1010 Rm Rn IMM32; mov Rm,(d32,Rn)
41468.0xfe+8.0x1a+4.RM2,4.RN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5g:::mov
4147"mov"
4148*am33
4149{
4150 int srcreg, dstreg;
4151
4152 PC = cia;
9c55817e
JL		 4153 srcreg = translate_rreg (SD_, RM2);
4154 dstreg = translate_rreg (SD_, RN0);
3e75ff7e
JL		 4155 store_word (State.regs[dstreg] + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D),
4156 State.regs[srcreg]);
4157}
4158
4159// 1111 1110 0010 1010 Rn Rm IMM32; movbu (d32,Rm),Rn
41608.0xfe+8.0x2a+4.RN2,4.RM0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::movbu
4161"movbu"
4162*am33
4163{
4164 int srcreg, dstreg;
4165
4166 PC = cia;
9c55817e
JL		 4167 srcreg = translate_rreg (SD_, RM0);
4168 dstreg = translate_rreg (SD_, RN2);
3e75ff7e
JL		 4169 State.regs[dstreg] = load_byte (State.regs[srcreg]
4170 + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
4171}
4172
4173// 1111 1110 0011 1010 Rm Rn IMM32; movbu Rm,(d32,Rn)
41748.0xfe+8.0x3a+4.RM2,4.RN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5b:::movbu
4175"movbu"
4176*am33
4177{
4178 int srcreg, dstreg;
4179
4180 PC = cia;
9c55817e
JL		 4181 srcreg = translate_rreg (SD_, RM2);
4182 dstreg = translate_rreg (SD_, RN0);
3e75ff7e
JL		 4183 store_byte (State.regs[dstreg] + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D),
4184 State.regs[srcreg]);
0f7d7385
JL		 4185}
4186
3e75ff7e
JL		 4187// 1111 1110 0100 1010 Rn Rm IMM32; movhu (d32,Rm),Rn
41888.0xfe+8.0x4a+4.RN2,4.RM0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::movhu
4189"movhu"
0f7d7385
JL		 4190*am33
4191{
3e75ff7e
JL		 4192 int srcreg, dstreg;
4193
4194 PC = cia;
9c55817e
JL		 4195 srcreg = translate_rreg (SD_, RM0);
4196 dstreg = translate_rreg (SD_, RN2);
3e75ff7e
JL		 4197 State.regs[dstreg] = load_half (State.regs[srcreg]
4198 + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
4199}
4200
4201// 1111 1110 0101 1010 Rm Rn IMM32; movhu Rm,(d32,Rn)
42028.0xfe+8.0x5a+4.RM2,4.RN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5b:::movhu
4203"movhu"
4204*am33
4205{
4206 int srcreg, dstreg;
0f7d7385
JL		 4207
4208 PC = cia;
9c55817e
JL		 4209 srcreg = translate_rreg (SD_, RM2);
4210 dstreg = translate_rreg (SD_, RN0);
3e75ff7e
JL		 4211 store_half (State.regs[dstreg] + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D),
4212 State.regs[srcreg]);
4213}
4214
377e53bb
JL		 4215// 1111 1110 0110 1010 Rn Rm IMM32; mov (d32,Rm+),Rn
42168.0xfe+8.0x6a+4.RN2,4.RM0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5y:::mov
4217"mov"
4218*am33
4219{
4220 int srcreg, dstreg;
4221
4222 PC = cia;
9c55817e
JL		 4223 srcreg = translate_rreg (SD_, RM0);
4224 dstreg = translate_rreg (SD_, RN2);
377e53bb
JL		 4225 State.regs[dstreg] = load_word (State.regs[srcreg]
4226 + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
4227 State.regs[srcreg] += 4;
4228}
4229
4230// 1111 1110 0111 1010 Rm Rn IMM32; mov Rm,(d32,Rn+)
42318.0xfe+8.0x7a+4.RM2,4.RN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5z:::mov
4232"mov"
4233*am33
4234{
4235 int srcreg, dstreg;
4236
4237 PC = cia;
9c55817e
JL		 4238 srcreg = translate_rreg (SD_, RM2);
4239 dstreg = translate_rreg (SD_, RN0);
377e53bb
JL		 4240 store_word (State.regs[dstreg] + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D),
4241 State.regs[srcreg]);
4242 State.regs[dstreg] += 4;
4243}
4244
3e75ff7e
JL		 4245
4246// 1111 1110 1000 1010 Rn 0000 IMM32; mov (d32,sp),Rn
42478.0xfe+8.0x8a+4.RN2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5c:::mov
4248"mov"
4249*am33
4250{
4251 int dstreg;
4252
4253 PC = cia;
9c55817e 4254 dstreg = translate_rreg (SD_, RN2);
3e75ff7e
JL		 4255 State.regs[dstreg] = load_word (State.regs[REG_SP]
4256 + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
4257}
4258
4259// 1111 1110 1001 1010 Rm 0000 IMM32; mov Rm,(d32,sp)
42608.0xfe+8.0x9a+4.RM2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5d:::mov
4261"mov"
4262*am33
4263{
4264 int srcreg;
4265
4266 PC = cia;
9c55817e 4267 srcreg = translate_rreg (SD_, RM2);
3e75ff7e
JL		 4268 store_word (State.regs[REG_SP] + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D),
4269 State.regs[srcreg]);
4270}
4271
4272// 1111 1110 1010 1010 Rn 0000 IMM32; movbu (d32,sp),Rn
42738.0xfe+8.0xaa+4.RN2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5c:::movbu
4274"movbu"
4275*am33
4276{
4277 int dstreg;
4278
4279 PC = cia;
9c55817e 4280 dstreg = translate_rreg (SD_, RN2);
3e75ff7e
JL		 4281 State.regs[dstreg] = load_byte (State.regs[REG_SP]
4282 + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
4283}
4284
4285// 1111 1110 1011 1010 Rm 0000 IMM32; movbu Rm,(d32,sp)
42868.0xfe+8.0xba+4.RM2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5d:::movbu
4287"movbu"
4288*am33
4289{
4290 int srcreg;
4291
4292 PC = cia;
9c55817e 4293 srcreg = translate_rreg (SD_, RM2);
3e75ff7e
JL		 4294 store_byte (State.regs[REG_SP] + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D),
4295 State.regs[srcreg]);
4296}
4297
4298// 1111 1110 1100 1010 Rn 0000 IMM32; movhu (d32,sp),Rn
42998.0xfe+8.0xca+4.RN2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5c:::movhu
4300"movhu"
4301*am33
4302{
4303 int dstreg;
4304
4305 PC = cia;
9c55817e 4306 dstreg = translate_rreg (SD_, RN2);
3e75ff7e
JL		 4307 State.regs[dstreg] = load_half (State.regs[REG_SP]
4308 + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
4309}
4310
4311// 1111 1110 1101 1010 Rm 0000 IMM32; movhu Rm,(d32,sp)
43128.0xfe+8.0xda+4.RM2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5d:::movhu
4313"movhu"
4314*am33
4315{
4316 int srcreg;
4317
4318 PC = cia;
9c55817e 4319 srcreg = translate_rreg (SD_, RM2);
3e75ff7e
JL		 4320 store_half (State.regs[REG_SP] + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D),
4321 State.regs[srcreg]);
4322}
4323
4324
377e53bb
JL		 4325// 1111 1110 1110 1010 Rn Rm IMM32; movhu (d32,Rm+),Rn
43268.0xfe+8.0xea+4.RN2,4.RM0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5y:::movhu
4327"movhu"
4328*am33
4329{
4330 int srcreg, dstreg;
4331
4332 PC = cia;
9c55817e
JL		 4333 srcreg = translate_rreg (SD_, RM0);
4334 dstreg = translate_rreg (SD_, RN2);
377e53bb
JL		 4335 State.regs[dstreg] = load_half (State.regs[srcreg]
4336 + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
4337 State.regs[srcreg] += 2;
4338}
4339
4340// 1111 1110 1111 1010 Rm Rn IMM32; movhu Rm,(d32,Rn+)
43418.0xfe+8.0xfa+4.RM2,4.RN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5f:::movhu
4342"movhu"
4343*am33
4344{
4345 int srcreg, dstreg;
4346
4347 PC = cia;
9c55817e
JL		 4348 srcreg = translate_rreg (SD_, RM2);
4349 dstreg = translate_rreg (SD_, RN0);
377e53bb
JL		 4350 store_half (State.regs[dstreg] + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D),
4351 State.regs[srcreg]);
4352 State.regs[dstreg] += 2;
4353}
4354
3e75ff7e 4355
377e53bb
JL		 4356// ??? mac
4357// ??? macu
4358// ??? macb
4359// ??? macbu
4360// ??? mach
4361// ??? machu
4362// ??? dmach
4363// ??? dmachu
4364// ??? dmulh
4365// ??? dmulhu
3e75ff7e
JL		 4366
4367// 1111 1110 0000 1110 Rn 0000 IMM32; mov (abs32),Rn
43688.0xfe+8.0x0e+4.RN2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5h:::mov
4369"mov"
4370*am33
4371{
4372 int dstreg;
4373
4374 PC = cia;
9c55817e 4375 dstreg = translate_rreg (SD_, RN2);
3e75ff7e
JL		 4376 State.regs[dstreg] = load_word (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
4377}
4378
4379// 1111 1110 0001 1110 Rm 0000 IMM32; mov Rn,(abs32)
43808.0xfe+8.0x1e+4.RM2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5e:::mov
4381"mov"
4382*am33
4383{
4384 int srcreg;
4385
4386 PC = cia;
9c55817e 4387 srcreg = translate_rreg (SD_, RM2);
3e75ff7e
JL		 4388 store_word (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D), State.regs[srcreg]);
4389}
4390
4391// 1111 1110 0020 1110 Rn 0000 IMM32; movbu (abs32),Rn
43928.0xfe+8.0x2e+4.RN2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5i:::movbu
4393"movbu"
4394*am33
4395{
4396 int dstreg;
4397
4398 PC = cia;
9c55817e 4399 dstreg = translate_rreg (SD_, RN2);
3e75ff7e
JL		 4400 State.regs[dstreg] = load_byte (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
4401}
4402
4403// 1111 1110 0011 1110 Rm 0000 IMM32; movbu Rn,(abs32)
44048.0xfe+8.0x3e+4.RM2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5e:::movbu
4405"movbu"
4406*am33
4407{
4408 int srcreg;
4409
4410 PC = cia;
9c55817e 4411 srcreg = translate_rreg (SD_, RM2);
3e75ff7e
JL		 4412 store_byte (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D), State.regs[srcreg]);
4413}
4414
4415// 1111 1110 0100 1110 Rn 0000 IMM32; movhu (abs32),Rn
44168.0xfe+8.0x4e+4.RN2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5j:::movhu
4417"movhu"
4418*am33
4419{
4420 int dstreg;
4421
4422 PC = cia;
9c55817e 4423 dstreg = translate_rreg (SD_, RN2);
3e75ff7e
JL		 4424 State.regs[dstreg] = load_half (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
4425}
4426
4427// 1111 1110 0101 1110 Rm 0000 IMM32; movhu Rn,(abs32)
44288.0xfe+8.0x5e+4.RM2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5e:::movhu
4429"movhu"
4430*am33
4431{
4432 int srcreg;
4433
4434 PC = cia;
9c55817e 4435 srcreg = translate_rreg (SD_, RM2);
3e75ff7e 4436 store_half (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D), State.regs[srcreg]);
0f7d7385
JL		 4437}
4438
9c55817e 4439// ??? DSP
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