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Commit | Line | Data |
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c906108c | 1 | #include "sim-main.h" |
61a0c964 | 2 | #include "sim-syscall.h" |
c906108c SS |
3 | #include "targ-vals.h" |
4 | ||
c906108c | 5 | #include <time.h> |
c906108c SS |
6 | #ifdef HAVE_UNISTD_H |
7 | #include <unistd.h> | |
8 | #endif | |
c906108c | 9 | #include <string.h> |
c906108c | 10 | #include <sys/stat.h> |
c906108c SS |
11 | #include <sys/time.h> |
12 | ||
13 | ||
14 | ||
15 | #define REG0(X) ((X) & 0x3) | |
16 | #define REG1(X) (((X) & 0xc) >> 2) | |
17 | #define REG0_4(X) (((X) & 0x30) >> 4) | |
18 | #define REG0_8(X) (((X) & 0x300) >> 8) | |
19 | #define REG1_8(X) (((X) & 0xc00) >> 10) | |
20 | #define REG0_16(X) (((X) & 0x30000) >> 16) | |
21 | #define REG1_16(X) (((X) & 0xc0000) >> 18) | |
22 | ||
23 | ||
24 | INLINE_SIM_MAIN (void) | |
24a39d88 | 25 | genericAdd(unsigned32 source, unsigned32 destReg) |
c906108c SS |
26 | { |
27 | int z, c, n, v; | |
24a39d88 | 28 | unsigned32 dest, sum; |
c906108c SS |
29 | |
30 | dest = State.regs[destReg]; | |
31 | sum = source + dest; | |
32 | State.regs[destReg] = sum; | |
33 | ||
34 | z = (sum == 0); | |
35 | n = (sum & 0x80000000); | |
36 | c = (sum < source) || (sum < dest); | |
37 | v = ((dest & 0x80000000) == (source & 0x80000000) | |
38 | && (dest & 0x80000000) != (sum & 0x80000000)); | |
39 | ||
40 | PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); | |
41 | PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0) | |
42 | | (c ? PSW_C : 0) | (v ? PSW_V : 0)); | |
43 | } | |
44 | ||
45 | ||
46 | ||
47 | ||
48 | INLINE_SIM_MAIN (void) | |
24a39d88 | 49 | genericSub(unsigned32 source, unsigned32 destReg) |
c906108c SS |
50 | { |
51 | int z, c, n, v; | |
24a39d88 | 52 | unsigned32 dest, difference; |
c906108c SS |
53 | |
54 | dest = State.regs[destReg]; | |
55 | difference = dest - source; | |
56 | State.regs[destReg] = difference; | |
57 | ||
58 | z = (difference == 0); | |
59 | n = (difference & 0x80000000); | |
60 | c = (source > dest); | |
61 | v = ((dest & 0x80000000) != (source & 0x80000000) | |
62 | && (dest & 0x80000000) != (difference & 0x80000000)); | |
63 | ||
64 | PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); | |
65 | PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0) | |
66 | | (c ? PSW_C : 0) | (v ? PSW_V : 0)); | |
67 | } | |
68 | ||
69 | INLINE_SIM_MAIN (void) | |
24a39d88 | 70 | genericCmp(unsigned32 leftOpnd, unsigned32 rightOpnd) |
c906108c SS |
71 | { |
72 | int z, c, n, v; | |
24a39d88 | 73 | unsigned32 value; |
c906108c SS |
74 | |
75 | value = rightOpnd - leftOpnd; | |
76 | ||
77 | z = (value == 0); | |
78 | n = (value & 0x80000000); | |
79 | c = (leftOpnd > rightOpnd); | |
80 | v = ((rightOpnd & 0x80000000) != (leftOpnd & 0x80000000) | |
81 | && (rightOpnd & 0x80000000) != (value & 0x80000000)); | |
82 | ||
83 | PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); | |
84 | PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0) | |
85 | | (c ? PSW_C : 0) | (v ? PSW_V : 0)); | |
86 | } | |
87 | ||
88 | ||
89 | INLINE_SIM_MAIN (void) | |
24a39d88 | 90 | genericOr(unsigned32 source, unsigned32 destReg) |
c906108c SS |
91 | { |
92 | int n, z; | |
93 | ||
94 | State.regs[destReg] |= source; | |
95 | z = (State.regs[destReg] == 0); | |
96 | n = (State.regs[destReg] & 0x80000000) != 0; | |
97 | PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); | |
98 | PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0)); | |
99 | } | |
100 | ||
101 | ||
102 | INLINE_SIM_MAIN (void) | |
24a39d88 | 103 | genericXor(unsigned32 source, unsigned32 destReg) |
c906108c SS |
104 | { |
105 | int n, z; | |
106 | ||
107 | State.regs[destReg] ^= source; | |
108 | z = (State.regs[destReg] == 0); | |
109 | n = (State.regs[destReg] & 0x80000000) != 0; | |
110 | PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); | |
111 | PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0)); | |
112 | } | |
113 | ||
114 | ||
115 | INLINE_SIM_MAIN (void) | |
24a39d88 | 116 | genericBtst(unsigned32 leftOpnd, unsigned32 rightOpnd) |
c906108c | 117 | { |
24a39d88 | 118 | unsigned32 temp; |
c906108c SS |
119 | int z, n; |
120 | ||
121 | temp = rightOpnd; | |
122 | temp &= leftOpnd; | |
123 | n = (temp & 0x80000000) != 0; | |
124 | z = (temp == 0); | |
125 | PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V); | |
126 | PSW |= (z ? PSW_Z : 0) | (n ? PSW_N : 0); | |
127 | } | |
128 | ||
c906108c SS |
129 | /* syscall */ |
130 | INLINE_SIM_MAIN (void) | |
489503ee | 131 | do_syscall (void) |
c906108c | 132 | { |
7d5c6c43 MF |
133 | /* Registers passed to trap 0. */ |
134 | ||
135 | /* Function number. */ | |
136 | reg_t func = State.regs[0]; | |
137 | /* Parameters. */ | |
138 | reg_t parm1 = State.regs[1]; | |
139 | reg_t parm2 = load_word (State.regs[REG_SP] + 12); | |
140 | reg_t parm3 = load_word (State.regs[REG_SP] + 16); | |
141 | reg_t parm4 = load_word (State.regs[REG_SP] + 20); | |
c906108c SS |
142 | |
143 | /* We use this for simulated system calls; we may need to change | |
144 | it to a reserved instruction if we conflict with uses at | |
145 | Matsushita. */ | |
146 | int save_errno = errno; | |
147 | errno = 0; | |
148 | ||
7d5c6c43 | 149 | if (func == TARGET_SYS_exit) |
c906108c | 150 | { |
7d5c6c43 | 151 | /* EXIT - caller can look in parm1 to work out the reason */ |
96eaf29e | 152 | sim_engine_halt (simulator, STATE_CPU (simulator, 0), NULL, PC, |
7d5c6c43 | 153 | (parm1 == 0xdead ? SIM_SIGABRT : sim_exited), parm1); |
c906108c SS |
154 | } |
155 | else | |
156 | { | |
7d5c6c43 MF |
157 | long result, result2; |
158 | int errcode; | |
c906108c | 159 | |
7d5c6c43 MF |
160 | sim_syscall_multi (STATE_CPU (simulator, 0), func, parm1, parm2, |
161 | parm3, parm4, &result, &result2, &errcode); | |
162 | ||
163 | /* Registers set by trap 0. */ | |
164 | State.regs[0] = errcode; | |
165 | State.regs[1] = result; | |
166 | } | |
c906108c SS |
167 | |
168 | errno = save_errno; | |
169 | } |