]> git.ipfire.org Git - thirdparty/binutils-gdb.git/blame - sim/mn10300/simops.c
projects / thirdparty / binutils-gdb.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
* add valops.c to list of files to be sanitized for d10v
[thirdparty/binutils-gdb.git] / sim / mn10300 / simops.c
CommitLineData
05ccbdfd
JL		 1#include "config.h"
2
3#include <signal.h>
4#ifdef HAVE_UNISTD_H
5#include <unistd.h>
6#endif
7#include "mn10300_sim.h"
8#include "simops.h"
9#include "sys/syscall.h"
10#include "bfd.h"
11#include <errno.h>
12#include <sys/stat.h>
13#include <sys/times.h>
14#include <sys/time.h>
15
16enum op_types {
17 OP_UNKNOWN,
18};
19
20#ifdef DEBUG
21static void trace_input PARAMS ((char *name, enum op_types type, int size));
22static void trace_output PARAMS ((enum op_types result));
23static int init_text_p = 0;
24static asection *text;
25static bfd_vma text_start;
26static bfd_vma text_end;
27extern bfd *exec_bfd;
28
29#ifndef SIZE_INSTRUCTION
30#define SIZE_INSTRUCTION 6
31#endif
32
33#ifndef SIZE_OPERANDS
34#define SIZE_OPERANDS 16
35#endif
36
37#ifndef SIZE_VALUES
38#define SIZE_VALUES 11
39#endif
40
41#ifndef SIZE_LOCATION
42#define SIZE_LOCATION 40
43#endif
44
45static void
46trace_input (name, type, size)
47 char *name;
48 enum op_types type;
49 int size;
50{
51}
52
53static void
54trace_output (result)
55 enum op_types result;
56{
57}
58
59#else
60#define trace_input(NAME, IN1, IN2)
61#define trace_output(RESULT)
62#endif
63
64\f
707641f6 65/* mov imm8, dn */
05ccbdfd
JL		 66void OP_8000 ()
67{
707641f6 68 State.regs[REG_D0 + ((insn & 0x300) >> 8)] = SEXT8 (insn & 0xff);
05ccbdfd
JL		 69}
70
707641f6 71/* mov dm, dn */
05ccbdfd
JL		 72void OP_80 ()
73{
707641f6 74 State.regs[REG_D0 + (insn & 0x3)] = State.regs[REG_D0 + ((insn & 0xc) >> 2)];
05ccbdfd
JL		 75}
76
707641f6 77/* mov dm, an */
05ccbdfd
JL		 78void OP_F1E0 ()
79{
af388638 80 State.regs[REG_A0 + (insn & 0x3)] = State.regs[REG_D0 + ((insn & 0xc) >> 2)];
05ccbdfd
JL		 81}
82
707641f6 83/* mov am, dn */
05ccbdfd
JL		 84void OP_F1D0 ()
85{
707641f6 86 State.regs[REG_D0 + (insn & 0x3)] = State.regs[REG_A0 + ((insn & 0xc) >> 2)];
05ccbdfd
JL		 87}
88
707641f6 89/* mov imm8, an */
05ccbdfd
JL		 90void OP_9000 ()
91{
fcfaf40d 92 State.regs[REG_A0 + ((insn & 0x300) >> 8)] = insn & 0xff;
05ccbdfd
JL		 93}
94
707641f6 95/* mov am, an */
05ccbdfd
JL		 96void OP_90 ()
97{
707641f6 98 State.regs[REG_A0 + (insn & 0x3)] = State.regs[REG_A0 + ((insn & 0xc) >> 2)];
05ccbdfd
JL		 99}
100
1f3bea21 101/* mov sp, an */
05ccbdfd
JL		 102void OP_3C ()
103{
92284aaa 104 State.regs[REG_A0 + (insn & 0x3)] = State.regs[REG_SP];
05ccbdfd
JL		 105}
106
1f3bea21 107/* mov am, sp */
05ccbdfd
JL		 108void OP_F2F0 ()
109{
92284aaa 110 State.regs[REG_SP] = State.regs[REG_A0 + ((insn & 0xc) >> 2)];
05ccbdfd
JL		 111}
112
707641f6 113/* mov psw, dn */
05ccbdfd
JL		 114void OP_F2E4 ()
115{
707641f6 116 State.regs[REG_D0 + (insn & 0x3)] = PSW;
05ccbdfd
JL		 117}
118
707641f6 119/* mov dm, psw */
05ccbdfd
JL		 120void OP_F2F3 ()
121{
707641f6 122 PSW = State.regs[REG_D0 + ((insn & 0xc) >> 2)];
05ccbdfd
JL		 123}
124
707641f6 125/* mov mdr, dn */
05ccbdfd
JL		 126void OP_F2E0 ()
127{
707641f6 128 State.regs[REG_D0 + (insn & 0x3)] = State.regs[REG_MDR];
05ccbdfd
JL		 129}
130
707641f6 131/* mov dm, mdr */
05ccbdfd
JL		 132void OP_F2F2 ()
133{
707641f6 134 State.regs[REG_MDR] = State.regs[REG_D0 + ((insn & 0xc) >> 2)];
05ccbdfd
JL		 135}
136
2e35551c 137/* mov (am), dn */
05ccbdfd
JL		 138void OP_70 ()
139{
707641f6
JL		 140 State.regs[REG_D0 + ((insn & 0xc) >> 2)]
141 = load_mem (State.regs[REG_A0 + (insn & 0x3)], 4);
05ccbdfd
JL		 142}
143
2e35551c 144/* mov (d8,am), dn */
05ccbdfd
JL		 145void OP_F80000 ()
146{
2e35551c
JL		 147 State.regs[REG_D0 + ((insn & 0xc00) >> 10)]
148 = load_mem ((State.regs[REG_A0 + ((insn & 0x300) >> 8)]
149 + SEXT8 (insn & 0xff)), 4);
05ccbdfd
JL		 150}
151
ecb4b5a3 152/* mov (d16,am), dn */
05ccbdfd
JL		 153void OP_FA000000 ()
154{
ecb4b5a3
JL		 155 State.regs[REG_D0 + ((insn & 0xc0000) >> 18)]
156 = load_mem ((State.regs[REG_A0 + ((insn & 0x30000) >> 16)]
157 + SEXT16 (insn & 0xffff)), 4);
05ccbdfd
JL		 158}
159
de0dce7c 160/* mov (d32,am), dn */
05ccbdfd
JL		 161void OP_FC000000 ()
162{
de0dce7c
JL		 163 State.regs[REG_D0 + ((insn & 0xc0000) >> 18)]
164 = load_mem ((State.regs[REG_A0 + ((insn & 0x30000) >> 16)]
165 + ((insn & 0xffff) << 16) | extension), 4);
05ccbdfd
JL		 166}
167
707641f6 168/* mov (d8,sp), dn */
05ccbdfd
JL		 169void OP_5800 ()
170{
707641f6 171 State.regs[REG_D0 + ((insn & 0x300) >> 8)]
ecb4b5a3 172 = load_mem (State.regs[REG_SP] + (insn & 0xff), 4);
05ccbdfd
JL		 173}
174
ecb4b5a3 175/* mov (d16,sp), dn */
05ccbdfd
JL		 176void OP_FAB40000 ()
177{
ecb4b5a3
JL		 178 State.regs[REG_D0 + ((insn & 0x30000) >> 16)]
179 = load_mem (State.regs[REG_SP] + (insn & 0xffff), 4);
05ccbdfd
JL		 180}
181
de0dce7c 182/* mov (d32,sp), dn */
05ccbdfd
JL		 183void OP_FCB40000 ()
184{
de0dce7c
JL		 185 State.regs[REG_D0 + ((insn & 0x30000) >> 16)]
186 = load_mem (State.regs[REG_SP] + (((insn & 0xffff) << 16) + extension), 4);
05ccbdfd
JL		 187}
188
f5f13c1d 189/* mov (di,am), dn */
05ccbdfd
JL		 190void OP_F300 ()
191{
2e35551c 192 State.regs[REG_D0 + ((insn & 0x300) >> 8)]
f5f13c1d
JL		 193 = load_mem ((State.regs[REG_A0 + (insn & 0x3)]
194 + State.regs[REG_D0 + ((insn & 0xc) >> 2)]), 4);
05ccbdfd
JL		 195}
196
707641f6 197/* mov (abs16), dn */
05ccbdfd
JL		 198void OP_300000 ()
199{
ecb4b5a3 200 State.regs[REG_D0 + ((insn & 0x30000) >> 16)] = load_mem ((insn & 0xffff), 4);
05ccbdfd
JL		 201}
202
de0dce7c 203/* mov (abs32), dn */
05ccbdfd
JL		 204void OP_FCA40000 ()
205{
de0dce7c
JL		 206 State.regs[REG_D0 + ((insn & 0x30000) >> 16)]
207 = load_mem ((((insn & 0xffff) << 16) + extension), 4);
05ccbdfd
JL		 208}
209
707641f6 210/* mov (am), an */
05ccbdfd
JL		 211void OP_F000 ()
212{
707641f6
JL		 213 State.regs[REG_A0 + ((insn & 0xc) >> 2)]
214 = load_mem (State.regs[REG_A0 + (insn & 0x3)], 4);
05ccbdfd
JL		 215}
216
2e35551c 217/* mov (d8,am), an */
05ccbdfd
JL		 218void OP_F82000 ()
219{
2e35551c
JL		 220 State.regs[REG_A0 + ((insn & 0xc00) >> 10)]
221 = load_mem ((State.regs[REG_A0 + ((insn & 0x300) >> 8)]
222 + SEXT8 (insn & 0xff)), 4);
05ccbdfd
JL		 223}
224
ecb4b5a3 225/* mov (d16,am), an */
05ccbdfd
JL		 226void OP_FA200000 ()
227{
ecb4b5a3
JL		 228 State.regs[REG_A0 + ((insn & 0xc0000) >> 18)]
229 = load_mem ((State.regs[REG_A0 + ((insn & 0x30000) >> 16)]
230 + SEXT16 (insn & 0xffff)), 4);
05ccbdfd
JL		 231}
232
de0dce7c 233/* mov (d32,am), an */
05ccbdfd
JL		 234void OP_FC200000 ()
235{
de0dce7c
JL		 236 State.regs[REG_A0 + ((insn & 0xc0000) >> 18)]
237 = load_mem ((State.regs[REG_A0 + ((insn & 0x30000) >> 16)]
238 + ((insn & 0xffff) << 16) + extension), 4);
05ccbdfd
JL		 239}
240
707641f6 241/* mov (d8,sp), an */
05ccbdfd
JL		 242void OP_5C00 ()
243{
707641f6 244 State.regs[REG_A0 + ((insn & 0x300) >> 8)]
ecb4b5a3 245 = load_mem (State.regs[REG_SP] + (insn & 0xff), 4);
05ccbdfd
JL		 246}
247
ecb4b5a3 248/* mov (d16,sp), an */
05ccbdfd
JL		 249void OP_FAB00000 ()
250{
ecb4b5a3
JL		 251 State.regs[REG_A0 + ((insn & 0x30000) >> 16)]
252 = load_mem (State.regs[REG_SP] + (insn & 0xffff), 4);
05ccbdfd
JL		 253}
254
de0dce7c 255/* mov (d32,sp), an */
05ccbdfd
JL		 256void OP_FCB00000 ()
257{
de0dce7c
JL		 258 State.regs[REG_A0 + ((insn & 0x30000) >> 16)]
259 = load_mem (State.regs[REG_SP] + (((insn & 0xffff) << 16) + extension), 4);
05ccbdfd
JL		 260}
261
de0dce7c 262/* mov (di,am), an */
05ccbdfd
JL		 263void OP_F380 ()
264{
2e35551c 265 State.regs[REG_A0 + ((insn & 0x300) >> 8)]
f5f13c1d
JL		 266 = load_mem ((State.regs[REG_A0 + (insn & 0x3)]
267 + State.regs[REG_D0 + ((insn & 0xc) >> 2)]), 4);
05ccbdfd
JL		 268}
269
ecb4b5a3 270/* mov (abs16), an */
05ccbdfd
JL		 271void OP_FAA00000 ()
272{
ecb4b5a3 273 State.regs[REG_A0 + ((insn & 0x30000) >> 16)] = load_mem ((insn & 0xffff), 4);
05ccbdfd
JL		 274}
275
de0dce7c 276/* mov (abs32), an */
05ccbdfd
JL		 277void OP_FCA00000 ()
278{
de0dce7c
JL		 279 State.regs[REG_A0 + ((insn & 0x30000) >> 16)]
280 = load_mem ((((insn & 0xffff) << 16) + extension), 4);
05ccbdfd
JL		 281}
282
2e35551c 283/* mov (d8,am), sp */
05ccbdfd
JL		 284void OP_F8F000 ()
285{
2e35551c
JL		 286 State.regs[REG_SP]
287 = load_mem ((State.regs[REG_A0 + ((insn & 0x300) >> 8)]
288 + SEXT8 (insn & 0xff)), 4);
05ccbdfd
JL		 289}
290
707641f6 291/* mov dm, (an) */
05ccbdfd
JL		 292void OP_60 ()
293{
707641f6
JL		 294 store_mem (State.regs[REG_A0 + (insn & 0x3)], 4,
295 State.regs[REG_D0 + ((insn & 0xc) >> 2)]);
05ccbdfd
JL		 296}
297
2e35551c 298/* mov dm, (d8,an) */
05ccbdfd
JL		 299void OP_F81000 ()
300{
2e35551c
JL		 301 store_mem ((State.regs[REG_A0 + ((insn & 0x300) >> 8)]
302 + SEXT8 (insn & 0xff)), 4,
303 State.regs[REG_D0 + ((insn & 0xc00) >> 10)]);
05ccbdfd
JL		 304}
305
ecb4b5a3 306/* mov dm (d16,an) */
05ccbdfd
JL		 307void OP_FA100000 ()
308{
ecb4b5a3
JL		 309 store_mem ((State.regs[REG_A0 + ((insn & 0x30000) >> 16)]
310 + SEXT16 (insn & 0xffff)), 4,
311 State.regs[REG_D0 + ((insn & 0xc0000) >> 18)]);
05ccbdfd
JL		 312}
313
de0dce7c 314/* mov dm (d32,an) */
05ccbdfd
JL		 315void OP_FC100000 ()
316{
de0dce7c
JL		 317 store_mem ((State.regs[REG_A0 + ((insn & 0x30000) >> 16)]
318 + ((insn & 0xffff) << 16) + extension), 4,
319 State.regs[REG_D0 + ((insn & 0xc0000) >> 18)]);
05ccbdfd
JL		 320}
321
707641f6 322/* mov dm, (d8,sp) */
05ccbdfd
JL		 323void OP_4200 ()
324{
ecb4b5a3 325 store_mem (State.regs[REG_SP] + (insn & 0xff), 4,
707641f6 326 State.regs[REG_D0 + ((insn & 0xc00) >> 10)]);
05ccbdfd
JL		 327}
328
ecb4b5a3 329/* mov dm, (d16,sp) */
05ccbdfd
JL		 330void OP_FA910000 ()
331{
ecb4b5a3
JL		 332 store_mem (State.regs[REG_SP] + (insn & 0xffff), 4,
333 State.regs[REG_D0 + ((insn & 0xc0000) >> 18)]);
05ccbdfd
JL		 334}
335
de0dce7c 336/* mov dm, (d32,sp) */
05ccbdfd
JL		 337void OP_FC910000 ()
338{
de0dce7c
JL		 339 store_mem (State.regs[REG_SP] + (((insn & 0xffff) << 16) + extension), 4,
340 State.regs[REG_D0 + ((insn & 0xc0000) >> 18)]);
05ccbdfd
JL		 341}
342
f5f13c1d 343/* mov dm, (di,an) */
05ccbdfd
JL		 344void OP_F340 ()
345{
f5f13c1d
JL		 346 store_mem ((State.regs[REG_A0 + (insn & 0x3)]
347 + State.regs[REG_D0 + ((insn & 0xc) >> 2)]), 4,
2e35551c 348 State.regs[REG_D0 + ((insn & 0x300) >> 8)]);
05ccbdfd
JL		 349}
350
707641f6 351/* mov dm, (abs16) */
05ccbdfd
JL		 352void OP_10000 ()
353{
707641f6 354 store_mem ((insn & 0xffff), 4, State.regs[REG_D0 + ((insn & 0xc0000) >> 18)]);
05ccbdfd
JL		 355}
356
de0dce7c 357/* mov dm, (abs32) */
05ccbdfd
JL		 358void OP_FC810000 ()
359{
de0dce7c 360 store_mem ((((insn & 0xffff) << 16) + extension), 4, State.regs[REG_D0 + ((insn & 0xc0000) >> 18)]);
05ccbdfd
JL		 361}
362
707641f6 363/* mov am, (an) */
05ccbdfd
JL		 364void OP_F010 ()
365{
707641f6
JL		 366 store_mem (State.regs[REG_A0 + (insn & 0x3)], 4,
367 State.regs[REG_A0 + ((insn & 0xc) >> 2)]);
05ccbdfd
JL		 368}
369
2e35551c 370/* mov am, (d8,an) */
05ccbdfd
JL		 371void OP_F83000 ()
372{
2e35551c
JL		 373 store_mem ((State.regs[REG_A0 + ((insn & 0x300) >> 8)]
374 + SEXT8 (insn & 0xff)), 4,
375 State.regs[REG_A0 + ((insn & 0xc00) >> 10)]);
05ccbdfd
JL		 376}
377
de0dce7c 378/* mov am, (d16,an) */
05ccbdfd
JL		 379void OP_FA300000 ()
380{
e5a7a537 381 store_mem ((State.regs[REG_A0 + ((insn & 0x30000) >> 16)]
ecb4b5a3
JL		 382 + SEXT16 (insn & 0xffff)), 4,
383 State.regs[REG_A0 + ((insn & 0xc0000) >> 18)]);
05ccbdfd
JL		 384}
385
de0dce7c 386/* mov am, (d32,an) */
05ccbdfd
JL		 387void OP_FC300000 ()
388{
e5a7a537 389 store_mem ((State.regs[REG_A0 + ((insn & 0x30000) >> 16)]
de0dce7c
JL		 390 + ((insn & 0xffff) << 16) + extension), 4,
391 State.regs[REG_A0 + ((insn & 0xc0000) >> 18)]);
05ccbdfd
JL		 392}
393
707641f6 394/* mov am, (d8,sp) */
05ccbdfd
JL		 395void OP_4300 ()
396{
ecb4b5a3 397 store_mem (State.regs[REG_SP] + (insn & 0xff), 4,
707641f6 398 State.regs[REG_A0 + ((insn & 0xc00) >> 10)]);
05ccbdfd
JL		 399}
400
ecb4b5a3 401/* mov am, (d16,sp) */
05ccbdfd
JL		 402void OP_FA900000 ()
403{
ecb4b5a3
JL		 404 store_mem (State.regs[REG_SP] + (insn & 0xffff), 4,
405 State.regs[REG_A0 + ((insn & 0xc0000) >> 18)]);
05ccbdfd
JL		 406}
407
de0dce7c 408/* mov am, (d32,sp) */
05ccbdfd
JL		 409void OP_FC900000 ()
410{
de0dce7c
JL		 411 store_mem (State.regs[REG_SP] + (((insn & 0xffff) << 16) + extension), 4,
412 State.regs[REG_A0 + ((insn & 0xc0000) >> 18)]);
05ccbdfd
JL		 413}
414
f5f13c1d 415/* mov am, (di,an) */
05ccbdfd
JL		 416void OP_F3C0 ()
417{
f5f13c1d
JL		 418 store_mem ((State.regs[REG_A0 + (insn & 0x3)]
419 + State.regs[REG_D0 + ((insn & 0xc) >> 2)]), 4,
2e35551c 420 State.regs[REG_A0 + ((insn & 0x300) >> 8)]);
05ccbdfd
JL		 421}
422
ecb4b5a3 423/* mov am, (abs16) */
05ccbdfd
JL		 424void OP_FA800000 ()
425{
ecb4b5a3 426 store_mem ((insn & 0xffff), 4, State.regs[REG_A0 + ((insn & 0xc0000) >> 18)]);
05ccbdfd
JL		 427}
428
de0dce7c 429/* mov am, (abs32) */
05ccbdfd
JL		 430void OP_FC800000 ()
431{
de0dce7c 432 store_mem ((((insn & 0xffff) << 16) + extension), 4, State.regs[REG_A0 + ((insn & 0xc0000) >> 18)]);
05ccbdfd
JL		 433}
434
2e35551c 435/* mov sp, (d8,an) */
05ccbdfd
JL		 436void OP_F8F400 ()
437{
2e35551c
JL		 438 store_mem (State.regs[REG_A0 + ((insn & 0x300) >> 8)] + SEXT8 (insn & 0xff),
439 4, State.regs[REG_SP]);
05ccbdfd
JL		 440}
441
707641f6 442/* mov imm16, dn */
05ccbdfd
JL		 443void OP_2C0000 ()
444{
707641f6
JL		 445 unsigned long value;
446
447 value = SEXT16 (insn & 0xffff);
fcfaf40d 448 State.regs[REG_D0 + ((insn & 0x30000) >> 16)] = value;
05ccbdfd
JL		 449}
450
de0dce7c 451/* mov imm32,dn */
05ccbdfd
JL		 452void OP_FCCC0000 ()
453{
de0dce7c
JL		 454 unsigned long value;
455
456 value = (insn & 0xffff) << 16 | extension;
457 State.regs[REG_D0 + ((insn & 0x30000) >> 16)] = value;
05ccbdfd
JL		 458}
459
707641f6 460/* mov imm16, an */
05ccbdfd
JL		 461void OP_240000 ()
462{
707641f6
JL		 463 unsigned long value;
464
465 value = insn & 0xffff;
466 State.regs[REG_A0 + ((insn & 0x30000) >> 16)] = value;
05ccbdfd
JL		 467}
468
de0dce7c 469/* mov imm32, an */
05ccbdfd
JL		 470void OP_FCDC0000 ()
471{
73e65298
JL		 472 unsigned long value;
473
474 value = (insn & 0xffff) << 16 | extension;
475 State.regs[REG_A0 + ((insn & 0x30000) >> 16)] = value;
05ccbdfd
JL		 476}
477
707641f6 478/* movbu (am), dn */
05ccbdfd
JL		 479void OP_F040 ()
480{
707641f6
JL		 481 State.regs[REG_D0 + ((insn & 0xc) >> 2)]
482 = load_mem (State.regs[REG_A0 + (insn & 0x3)], 1);
05ccbdfd
JL		 483}
484
2e35551c 485/* movbu (d8,am), dn */
05ccbdfd
JL		 486void OP_F84000 ()
487{
2e35551c
JL		 488 State.regs[REG_D0 + ((insn & 0xc00) >> 10)]
489 = load_mem ((State.regs[REG_A0 + ((insn & 0x300) >> 8)]
490 + SEXT8 (insn & 0xff)), 1);
05ccbdfd
JL		 491}
492
ecb4b5a3 493/* movbu (d16,am), dn */
05ccbdfd
JL		 494void OP_FA400000 ()
495{
ecb4b5a3
JL		 496 State.regs[REG_D0 + ((insn & 0xc0000) >> 18)]
497 = load_mem ((State.regs[REG_A0 + ((insn & 0x30000) >> 16)]
498 + SEXT16 (insn & 0xffff)), 1);
05ccbdfd
JL		 499}
500
de0dce7c 501/* movbu (d32,am), dn */
05ccbdfd
JL		 502void OP_FC400000 ()
503{
de0dce7c
JL		 504 State.regs[REG_D0 + ((insn & 0xc0000) >> 18)]
505 = load_mem ((State.regs[REG_A0 + ((insn & 0x30000) >> 16)]
506 + ((insn & 0xffff) << 16) + extension), 1);
05ccbdfd
JL		 507}
508
2e35551c 509/* movbu (d8,sp), dn */
05ccbdfd
JL		 510void OP_F8B800 ()
511{
2e35551c 512 State.regs[REG_D0 + ((insn & 0x300) >> 8)]
ecb4b5a3 513 = load_mem ((State.regs[REG_SP] + (insn & 0xff)), 1);
05ccbdfd
JL		 514}
515
ecb4b5a3 516/* movbu (d16,sp), dn */
05ccbdfd
JL		 517void OP_FAB80000 ()
518{
ecb4b5a3
JL		 519 State.regs[REG_D0 + ((insn & 0x30000) >> 16)]
520 = load_mem ((State.regs[REG_SP] + (insn & 0xffff)), 1);
05ccbdfd
JL		 521}
522
de0dce7c 523/* movbu (d32,sp), dn */
05ccbdfd
JL		 524void OP_FCB80000 ()
525{
de0dce7c
JL		 526 State.regs[REG_D0 + ((insn & 0x30000) >> 16)]
527 = load_mem (State.regs[REG_SP] + (((insn & 0xffff) << 16) + extension), 1);
05ccbdfd
JL		 528}
529
f5f13c1d 530/* movbu (di,am), dn */
05ccbdfd
JL		 531void OP_F400 ()
532{
2e35551c 533 State.regs[REG_D0 + ((insn & 0x300) >> 8)]
f5f13c1d
JL		 534 = load_mem ((State.regs[REG_A0 + (insn & 0x3)]
535 + State.regs[REG_D0 + ((insn & 0xc) >> 2)]), 1);
05ccbdfd
JL		 536}
537
707641f6 538/* movbu (abs16), dn */
05ccbdfd
JL		 539void OP_340000 ()
540{
ecb4b5a3 541 State.regs[REG_D0 + ((insn & 0x30000) >> 16)] = load_mem ((insn & 0xffff), 1);
05ccbdfd
JL		 542}
543
de0dce7c 544/* movbu (abs32), dn */
05ccbdfd
JL		 545void OP_FCA80000 ()
546{
de0dce7c
JL		 547 State.regs[REG_D0 + ((insn & 0x30000) >> 16)]
548 = load_mem ((((insn & 0xffff) << 16) + extension), 1);
05ccbdfd
JL		 549}
550
707641f6 551/* movbu dm, (an) */
05ccbdfd
JL		 552void OP_F050 ()
553{
af388638
JL		 554 store_mem (State.regs[REG_A0 + (insn & 0x3)], 1,
555 State.regs[REG_D0 + ((insn & 0xc) >> 2)]);
05ccbdfd
JL		 556}
557
2e35551c 558/* movbu dm, (d8,an) */
05ccbdfd
JL		 559void OP_F85000 ()
560{
2e35551c
JL		 561 store_mem ((State.regs[REG_A0 + ((insn & 0x300) >> 8)]
562 + SEXT8 (insn & 0xff)), 1,
563 State.regs[REG_D0 + ((insn & 0xc00) >> 10)]);
05ccbdfd
JL		 564}
565
ecb4b5a3 566/* movbu dm, (d16,an) */
05ccbdfd
JL		 567void OP_FA500000 ()
568{
ecb4b5a3 569 store_mem ((State.regs[REG_A0 + ((insn & 0x30000) >> 16)]
de0dce7c 570 + SEXT16 (insn & 0xffff)), 1,
ecb4b5a3 571 State.regs[REG_D0 + ((insn & 0xc0000) >> 18)]);
05ccbdfd
JL		 572}
573
de0dce7c 574/* movbu dm, (d32,an) */
05ccbdfd
JL		 575void OP_FC500000 ()
576{
de0dce7c
JL		 577 store_mem ((State.regs[REG_A0 + ((insn & 0x30000) >> 16)]
578 + ((insn & 0xffff) << 16) + extension), 1,
579 State.regs[REG_D0 + ((insn & 0xc0000) >> 18)]);
05ccbdfd
JL		 580}
581
2e35551c 582/* movbu dm, (d8,sp) */
05ccbdfd
JL		 583void OP_F89200 ()
584{
ecb4b5a3 585 store_mem (State.regs[REG_SP] + (insn & 0xff), 1,
2e35551c 586 State.regs[REG_D0 + ((insn & 0xc00) >> 10)]);
05ccbdfd
JL		 587}
588
ecb4b5a3 589/* movbu dm, (d16,sp) */
05ccbdfd
JL		 590void OP_FA920000 ()
591{
ecb4b5a3
JL		 592 store_mem (State.regs[REG_SP] + (insn & 0xffff), 2,
593 State.regs[REG_D0 + ((insn & 0xc00) >> 10)]);
05ccbdfd
JL		 594}
595
de0dce7c 596/* movbu dm (d32,sp) */
05ccbdfd
JL		 597void OP_FC920000 ()
598{
de0dce7c
JL		 599 store_mem (State.regs[REG_SP] + (((insn & 0xffff) << 16) + extension), 2,
600 State.regs[REG_D0 + ((insn & 0xc00) >> 10)]);
05ccbdfd
JL		 601}
602
f5f13c1d 603/* movbu dm, (di,an) */
05ccbdfd
JL		 604void OP_F440 ()
605{
f5f13c1d
JL		 606 store_mem ((State.regs[REG_A0 + (insn & 0x3)]
607 + State.regs[REG_D0 + ((insn & 0xc) >> 2)]), 1,
2e35551c 608 State.regs[REG_D0 + ((insn & 0x300) >> 8)]);
05ccbdfd
JL		 609}
610
707641f6 611/* movbu dm, (abs16) */
05ccbdfd
JL		 612void OP_20000 ()
613{
707641f6 614 store_mem ((insn & 0xffff), 1, State.regs[REG_D0 + ((insn & 0xc0000) >> 18)]);
05ccbdfd
JL		 615}
616
de0dce7c 617/* movbu dm, (abs32) */
05ccbdfd
JL		 618void OP_FC820000 ()
619{
de0dce7c 620 store_mem ((((insn & 0xffff) << 16) + extension), 1, State.regs[REG_D0 + ((insn & 0xc0000) >> 18)]);
05ccbdfd
JL		 621}
622
707641f6 623/* movhu (am), dn */
05ccbdfd
JL		 624void OP_F060 ()
625{
707641f6
JL		 626 State.regs[REG_D0 + ((insn & 0xc) >> 2)]
627 = load_mem (State.regs[REG_A0 + (insn & 0x3)], 2);
05ccbdfd
JL		 628}
629
2e35551c 630/* movhu (d8,am), dn */
05ccbdfd
JL		 631void OP_F86000 ()
632{
2e35551c
JL		 633 State.regs[REG_D0 + ((insn & 0xc00) >> 10)]
634 = load_mem ((State.regs[REG_A0 + ((insn & 0x300) >> 8)]
635 + SEXT8 (insn & 0xff)), 2);
05ccbdfd
JL		 636}
637
ecb4b5a3 638/* movhu (d16,am), dn */
05ccbdfd
JL		 639void OP_FA600000 ()
640{
ecb4b5a3
JL		 641 State.regs[REG_D0 + ((insn & 0xc0000) >> 18)]
642 = load_mem ((State.regs[REG_A0 + ((insn & 0x30000) >> 16)]
643 + SEXT16 (insn & 0xffff)), 2);
05ccbdfd
JL		 644}
645
de0dce7c 646/* movhu (d32,am), dn */
05ccbdfd
JL		 647void OP_FC600000 ()
648{
de0dce7c
JL		 649 State.regs[REG_D0 + ((insn & 0xc0000) >> 18)]
650 = load_mem ((State.regs[REG_A0 + ((insn & 0x30000) >> 16)]
651 + ((insn & 0xffff) << 16) + extension), 2);
05ccbdfd
JL		 652}
653
2e35551c 654/* movhu (d8,sp) dn */
05ccbdfd
JL		 655void OP_F8BC00 ()
656{
2e35551c 657 State.regs[REG_D0 + ((insn & 0x300) >> 8)]
ecb4b5a3 658 = load_mem ((State.regs[REG_SP] + (insn & 0xff)), 2);
05ccbdfd
JL		 659}
660
ecb4b5a3 661/* movhu (d16,sp), dn */
05ccbdfd
JL		 662void OP_FABC0000 ()
663{
ecb4b5a3
JL		 664 State.regs[REG_D0 + ((insn & 0x30000) >> 16)]
665 = load_mem ((State.regs[REG_SP] + (insn & 0xffff)), 2);
05ccbdfd
JL		 666}
667
de0dce7c 668/* movhu (d32,sp), dn */
05ccbdfd
JL		 669void OP_FCBC0000 ()
670{
de0dce7c
JL		 671 State.regs[REG_D0 + ((insn & 0x30000) >> 16)]
672 = load_mem (State.regs[REG_SP] + (((insn & 0xffff) << 16) + extension), 2);
05ccbdfd
JL		 673}
674
f5f13c1d 675/* movhu (di,am), dn */
05ccbdfd
JL		 676void OP_F480 ()
677{
2e35551c 678 State.regs[REG_D0 + ((insn & 0x300) >> 8)]
f5f13c1d
JL		 679 = load_mem ((State.regs[REG_A0 + (insn & 0x3)]
680 + State.regs[REG_D0 + ((insn & 0xc) >> 2)]), 2);
05ccbdfd
JL		 681}
682
707641f6 683/* movhu (abs16), dn */
05ccbdfd
JL		 684void OP_380000 ()
685{
ecb4b5a3 686 State.regs[REG_D0 + ((insn & 0x30000) >> 16)] = load_mem ((insn & 0xffff), 2);
05ccbdfd
JL		 687}
688
de0dce7c 689/* movhu (abs32), dn */
05ccbdfd
JL		 690void OP_FCAC0000 ()
691{
de0dce7c
JL		 692 State.regs[REG_D0 + ((insn & 0x30000) >> 16)]
693 = load_mem ((((insn & 0xffff) << 16) + extension), 2);
05ccbdfd
JL		 694}
695
707641f6 696/* movhu dm, (an) */
05ccbdfd
JL		 697void OP_F070 ()
698{
af388638
JL		 699 store_mem (State.regs[REG_A0 + (insn & 0x3)], 2,
700 State.regs[REG_D0 + ((insn & 0xc) >> 2)]);
05ccbdfd
JL		 701}
702
2e35551c 703/* movhu dm, (d8,an) */
05ccbdfd
JL		 704void OP_F87000 ()
705{
2e35551c
JL		 706 store_mem ((State.regs[REG_A0 + ((insn & 0x300) >> 8)]
707 + SEXT8 (insn & 0xff)), 2,
708 State.regs[REG_D0 + ((insn & 0xc00) >> 10)]);
05ccbdfd
JL		 709}
710
ecb4b5a3 711/* movhu dm, (d16,an) */
05ccbdfd
JL		 712void OP_FA700000 ()
713{
ecb4b5a3
JL		 714 store_mem ((State.regs[REG_A0 + ((insn & 0x30000) >> 16)]
715 + SEXT16 (insn & 0xffff)), 2,
716 State.regs[REG_D0 + ((insn & 0xc0000) >> 18)]);
05ccbdfd
JL		 717}
718
de0dce7c 719/* movhu dm, (d32,an) */
05ccbdfd
JL		 720void OP_FC700000 ()
721{
de0dce7c
JL		 722 store_mem ((State.regs[REG_A0 + ((insn & 0x30000) >> 16)]
723 + ((insn & 0xffff) << 16) + extension), 2,
724 State.regs[REG_D0 + ((insn & 0xc0000) >> 18)]);
05ccbdfd
JL		 725}
726
2e35551c 727/* movhu dm,(d8,sp) */
05ccbdfd
JL		 728void OP_F89300 ()
729{
ecb4b5a3 730 store_mem (State.regs[REG_SP] + (insn & 0xff), 2,
2e35551c 731 State.regs[REG_D0 + ((insn & 0xc00) >> 10)]);
05ccbdfd
JL		 732}
733
ecb4b5a3 734/* movhu dm,(d16,sp) */
05ccbdfd
JL		 735void OP_FA930000 ()
736{
ecb4b5a3
JL		 737 store_mem (State.regs[REG_SP] + (insn & 0xffff), 2,
738 State.regs[REG_D0 + ((insn & 0xc0000) >> 18)]);
05ccbdfd
JL		 739}
740
de0dce7c 741/* movhu dm,(d32,sp) */
05ccbdfd
JL		 742void OP_FC930000 ()
743{
de0dce7c
JL		 744 store_mem (State.regs[REG_SP] + (((insn & 0xffff) << 16) + extension), 2,
745 State.regs[REG_D0 + ((insn & 0xc0000) >> 18)]);
05ccbdfd
JL		 746}
747
f5f13c1d 748/* movhu dm, (di,an) */
05ccbdfd
JL		 749void OP_F4C0 ()
750{
f5f13c1d
JL		 751 store_mem ((State.regs[REG_A0 + (insn & 0x3)]
752 + State.regs[REG_D0 + ((insn & 0xc) >> 2)]), 2,
2e35551c 753 State.regs[REG_D0 + ((insn & 0x300) >> 8)]);
05ccbdfd
JL		 754}
755
707641f6 756/* movhu dm, (abs16) */
05ccbdfd
JL		 757void OP_30000 ()
758{
707641f6 759 store_mem ((insn & 0xffff), 2, State.regs[REG_D0 + ((insn & 0xc0000) >> 18)]);
05ccbdfd
JL		 760}
761
de0dce7c 762/* movhu dm, (abs32) */
05ccbdfd
JL		 763void OP_FC830000 ()
764{
de0dce7c 765 store_mem ((((insn & 0xffff) << 16) + extension), 2, State.regs[REG_D0 + ((insn & 0xc0000) >> 18)]);
05ccbdfd
JL		 766}
767
707641f6 768/* ext dn */
05ccbdfd
JL		 769void OP_F2D0 ()
770{
707641f6
JL		 771 if (State.regs[REG_D0 + (insn & 0x3)] & 0x80000000)
772 State.regs[REG_MDR] = -1;
773 else
774 State.regs[REG_MDR] = 0;
05ccbdfd
JL		 775}
776
707641f6 777/* extb dn */
05ccbdfd
JL		 778void OP_10 ()
779{
707641f6 780 State.regs[REG_D0 + (insn & 0x3)] = SEXT8 (State.regs[REG_D0 + (insn & 0x3)]);
05ccbdfd
JL		 781}
782
707641f6 783/* extbu dn */
05ccbdfd
JL		 784void OP_14 ()
785{
707641f6 786 State.regs[REG_D0 + (insn & 0x3)] &= 0xff;
05ccbdfd
JL		 787}
788
707641f6 789/* exth dn */
05ccbdfd
JL		 790void OP_18 ()
791{
707641f6
JL		 792 State.regs[REG_D0 + (insn & 0x3)]
793 = SEXT16 (State.regs[REG_D0 + (insn & 0x3)]);
05ccbdfd
JL		 794}
795
707641f6 796/* exthu dn */
05ccbdfd
JL		 797void OP_1C ()
798{
707641f6 799 State.regs[REG_D0 + (insn & 0x3)] &= 0xffff;
05ccbdfd
JL		 800}
801
1f3bea21 802/* movm (sp), reg_list */
05ccbdfd
JL		 803void OP_CE00 ()
804{
1f3bea21
JL		 805 unsigned long sp = State.regs[REG_SP];
806 unsigned long mask;
807
808 mask = insn & 0xff;
809
810 if (mask & 0x8)
811 {
812 sp += 4;
813 State.regs[REG_LAR] = load_mem (sp, 4);
814 sp += 4;
815 State.regs[REG_LIR] = load_mem (sp, 4);
816 sp += 4;
817 State.regs[REG_MDR] = load_mem (sp, 4);
818 sp += 4;
819 State.regs[REG_A0 + 1] = load_mem (sp, 4);
820 sp += 4;
821 State.regs[REG_A0] = load_mem (sp, 4);
822 sp += 4;
823 State.regs[REG_D0 + 1] = load_mem (sp, 4);
824 sp += 4;
825 State.regs[REG_D0] = load_mem (sp, 4);
826 sp += 4;
827 }
828
829 if (mask & 0x10)
830 {
831 State.regs[REG_A0 + 3] = load_mem (sp, 4);
832 sp += 4;
833 }
834
835 if (mask & 0x20)
836 {
837 State.regs[REG_A0 + 2] = load_mem (sp, 4);
838 sp += 4;
839 }
840
841 if (mask & 0x40)
842 {
843 State.regs[REG_D0 + 3] = load_mem (sp, 4);
844 sp += 4;
845 }
846
847 if (mask & 0x80)
848 {
849 State.regs[REG_D0 + 2] = load_mem (sp, 4);
850 sp += 4;
851 }
852
853 /* And make sure to update the stack pointer. */
854 State.regs[REG_SP] = sp;
855}
856
857/* movm reg_list, (sp) */
05ccbdfd
JL		 858void OP_CF00 ()
859{
1f3bea21
JL		 860 unsigned long sp = State.regs[REG_SP];
861 unsigned long mask;
862
863 mask = insn & 0xff;
864
865 if (mask & 0x80)
866 {
867 sp -= 4;
6e7a01c1 868 store_mem (sp, 4, State.regs[REG_D0 + 2]);
1f3bea21
JL		 869 }
870
871 if (mask & 0x40)
872 {
873 sp -= 4;
6e7a01c1 874 store_mem (sp, 4, State.regs[REG_D0 + 3]);
1f3bea21
JL		 875 }
876
877 if (mask & 0x20)
878 {
879 sp -= 4;
6e7a01c1 880 store_mem (sp, 4, State.regs[REG_A0 + 2]);
1f3bea21
JL		 881 }
882
883 if (mask & 0x10)
884 {
885 sp -= 4;
6e7a01c1 886 store_mem (sp, 4, State.regs[REG_A0 + 3]);
1f3bea21
JL		 887 }
888
889 if (mask & 0x8)
890 {
891 sp -= 4;
6e7a01c1 892 store_mem (sp, 4, State.regs[REG_D0]);
1f3bea21 893 sp -= 4;
6e7a01c1 894 store_mem (sp, 4, State.regs[REG_D0 + 1]);
1f3bea21 895 sp -= 4;
6e7a01c1 896 store_mem (sp, 4, State.regs[REG_A0]);
1f3bea21 897 sp -= 4;
6e7a01c1 898 store_mem (sp, 4, State.regs[REG_A0 + 1]);
1f3bea21 899 sp -= 4;
6e7a01c1 900 store_mem (sp, 4, State.regs[REG_MDR]);
1f3bea21 901 sp -= 4;
6e7a01c1 902 store_mem (sp, 4, State.regs[REG_LIR]);
1f3bea21 903 sp -= 4;
6e7a01c1 904 store_mem (sp, 4, State.regs[REG_LAR]);
1f3bea21
JL		 905 sp -= 4;
906 }
907
908 /* And make sure to update the stack pointer. */
909 State.regs[REG_SP] = sp;
05ccbdfd
JL		 910}
911
73e65298 912/* clr dn */
05ccbdfd
JL		 913void OP_0 ()
914{
73e65298
JL		 915 State.regs[REG_D0 + ((insn & 0xc) >> 2)] = 0;
916
917 PSW |= PSW_Z;
918 PSW &= ~(PSW_V | PSW_C | PSW_N);
05ccbdfd
JL		 919}
920
de0dce7c 921/* add dm,dn */
05ccbdfd
JL		 922void OP_E0 ()
923{
73e65298
JL		 924 int z, c, n, v;
925 unsigned long reg1, reg2, value;
926
927 reg1 = State.regs[REG_D0 + ((insn & 0xc) >> 2)];
928 reg2 = State.regs[REG_D0 + (insn & 0x3)];
929 value = reg1 + reg2;
930 State.regs[REG_D0 + (insn & 0x3)] = value;
931
932 z = (value == 0);
933 n = (value & 0x80000000);
934 c = (reg1 < reg2);
b7b89deb
JL		 935 v = ((reg2 & 0x80000000) != (reg1 & 0x80000000)
936 && (reg2 & 0x80000000) != (value & 0x80000000));
73e65298
JL		 937
938 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
939 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
940 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
05ccbdfd
JL		 941}
942
73e65298 943/* add dm, an */
05ccbdfd
JL		 944void OP_F160 ()
945{
73e65298
JL		 946 int z, c, n, v;
947 unsigned long reg1, reg2, value;
948
949 reg1 = State.regs[REG_D0 + ((insn & 0xc) >> 2)];
950 reg2 = State.regs[REG_A0 + (insn & 0x3)];
951 value = reg1 + reg2;
952 State.regs[REG_A0 + (insn & 0x3)] = value;
953
954 z = (value == 0);
955 n = (value & 0x80000000);
956 c = (reg1 < reg2);
b7b89deb
JL		 957 v = ((reg2 & 0x80000000) != (reg1 & 0x80000000)
958 && (reg2 & 0x80000000) != (value & 0x80000000));
73e65298
JL		 959
960 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
961 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
962 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
05ccbdfd
JL		 963}
964
de0dce7c 965/* add am, dn */
05ccbdfd
JL		 966void OP_F150 ()
967{
73e65298
JL		 968 int z, c, n, v;
969 unsigned long reg1, reg2, value;
970
971 reg1 = State.regs[REG_A0 + ((insn & 0xc) >> 2)];
972 reg2 = State.regs[REG_D0 + (insn & 0x3)];
973 value = reg1 + reg2;
974 State.regs[REG_D0 + (insn & 0x3)] = value;
975
976 z = (value == 0);
977 n = (value & 0x80000000);
978 c = (reg1 < reg2);
b7b89deb
JL		 979 v = ((reg2 & 0x80000000) != (reg1 & 0x80000000)
980 && (reg2 & 0x80000000) != (value & 0x80000000));
73e65298
JL		 981
982 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
983 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
984 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
05ccbdfd
JL		 985}
986
73e65298 987/* add am,an */
05ccbdfd
JL		 988void OP_F170 ()
989{
73e65298
JL		 990 int z, c, n, v;
991 unsigned long reg1, reg2, value;
992
993 reg1 = State.regs[REG_A0 + ((insn & 0xc) >> 2)];
994 reg2 = State.regs[REG_A0 + (insn & 0x3)];
995 value = reg1 + reg2;
996 State.regs[REG_A0 + (insn & 0x3)] = value;
997
998 z = (value == 0);
999 n = (value & 0x80000000);
1000 c = (reg1 < reg2);
b7b89deb
JL		 1001 v = ((reg2 & 0x80000000) != (reg1 & 0x80000000)
1002 && (reg2 & 0x80000000) != (value & 0x80000000));
73e65298
JL		 1003
1004 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1005 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1006 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
05ccbdfd
JL		 1007}
1008
73e65298 1009/* add imm8, dn */
05ccbdfd
JL		 1010void OP_2800 ()
1011{
73e65298
JL		 1012 int z, c, n, v;
1013 unsigned long reg1, imm, value;
1014
6e7a01c1 1015 reg1 = State.regs[REG_D0 + ((insn & 0x300) >> 8)];
73e65298
JL		 1016 imm = SEXT8 (insn & 0xff);
1017 value = reg1 + imm;
6e7a01c1 1018 State.regs[REG_D0 + ((insn & 0x300) >> 8)] = value;
73e65298
JL		 1019
1020 z = (value == 0);
1021 n = (value & 0x80000000);
1022 c = (reg1 < imm);
b7b89deb
JL		 1023 v = ((reg1 & 0x80000000) != (imm & 0x80000000)
1024 && (reg1 & 0x80000000) != (value & 0x80000000));
73e65298
JL		 1025
1026 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1027 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1028 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
05ccbdfd
JL		 1029}
1030
73e65298 1031/* add imm16, dn */
05ccbdfd
JL		 1032void OP_FAC00000 ()
1033{
73e65298
JL		 1034 int z, c, n, v;
1035 unsigned long reg1, imm, value;
1036
6db7fc49 1037 reg1 = State.regs[REG_D0 + ((insn & 0x30000) >> 16)];
73e65298
JL		 1038 imm = SEXT16 (insn & 0xffff);
1039 value = reg1 + imm;
6db7fc49 1040 State.regs[REG_D0 + ((insn & 0x30000) >> 16)] = value;
73e65298
JL		 1041
1042 z = (value == 0);
1043 n = (value & 0x80000000);
1044 c = (reg1 < imm);
b7b89deb
JL		 1045 v = ((reg1 & 0x80000000) != (imm & 0x80000000)
1046 && (reg1 & 0x80000000) != (value & 0x80000000));
73e65298
JL		 1047
1048 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1049 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1050 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
05ccbdfd
JL		 1051}
1052
73e65298 1053/* add imm32,dn */
05ccbdfd
JL		 1054void OP_FCC00000 ()
1055{
73e65298
JL		 1056 int z, c, n, v;
1057 unsigned long reg1, imm, value;
1058
6db7fc49 1059 reg1 = State.regs[REG_D0 + ((insn & 0x30000) >> 16)];
73e65298
JL		 1060 imm = ((insn & 0xffff) << 16) | extension;
1061 value = reg1 + imm;
6db7fc49 1062 State.regs[REG_D0 + ((insn & 0x30000) >> 16)] = value;
73e65298
JL		 1063
1064 z = (value == 0);
1065 n = (value & 0x80000000);
1066 c = (reg1 < imm);
b7b89deb
JL		 1067 v = ((reg1 & 0x80000000) != (imm & 0x80000000)
1068 && (reg1 & 0x80000000) != (value & 0x80000000));
73e65298
JL		 1069
1070 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1071 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1072 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
05ccbdfd
JL		 1073}
1074
73e65298 1075/* add imm8, an */
05ccbdfd
JL		 1076void OP_2000 ()
1077{
73e65298
JL		 1078 int z, c, n, v;
1079 unsigned long reg1, imm, value;
1080
6e7a01c1
JL		 1081 reg1 = State.regs[REG_A0 + ((insn & 0x300) >> 8)];
1082 imm = SEXT8 (insn & 0xff);
73e65298 1083 value = reg1 + imm;
6e7a01c1 1084 State.regs[REG_A0 + ((insn & 0x300) >> 8)] = value;
73e65298
JL		 1085
1086 z = (value == 0);
1087 n = (value & 0x80000000);
1088 c = (reg1 < imm);
b7b89deb
JL		 1089 v = ((reg1 & 0x80000000) != (imm & 0x80000000)
1090 && (reg1 & 0x80000000) != (value & 0x80000000));
73e65298
JL		 1091
1092 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1093 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1094 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
05ccbdfd
JL		 1095}
1096
73e65298 1097/* add imm16, an */
05ccbdfd
JL		 1098void OP_FAD00000 ()
1099{
73e65298
JL		 1100 int z, c, n, v;
1101 unsigned long reg1, imm, value;
1102
6db7fc49 1103 reg1 = State.regs[REG_A0 + ((insn & 0x30000) >> 16)];
6e7a01c1 1104 imm = SEXT16 (insn & 0xffff);
73e65298 1105 value = reg1 + imm;
6db7fc49 1106 State.regs[REG_A0 + ((insn & 0x30000) >> 16)] = value;
73e65298
JL		 1107
1108 z = (value == 0);
1109 n = (value & 0x80000000);
1110 c = (reg1 < imm);
b7b89deb
JL		 1111 v = ((reg1 & 0x80000000) != (imm & 0x80000000)
1112 && (reg1 & 0x80000000) != (value & 0x80000000));
73e65298
JL		 1113
1114 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1115 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1116 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
05ccbdfd
JL		 1117}
1118
73e65298 1119/* add imm32, an */
05ccbdfd
JL		 1120void OP_FCD00000 ()
1121{
73e65298
JL		 1122 int z, c, n, v;
1123 unsigned long reg1, imm, value;
1124
6db7fc49 1125 reg1 = State.regs[REG_A0 + ((insn & 0x30000) >> 16)];
73e65298
JL		 1126 imm = ((insn & 0xffff) << 16) | extension;
1127 value = reg1 + imm;
6db7fc49 1128 State.regs[REG_A0 + ((insn & 0x30000) >> 16)] = value;
73e65298
JL		 1129
1130 z = (value == 0);
1131 n = (value & 0x80000000);
1132 c = (reg1 < imm);
b7b89deb
JL		 1133 v = ((reg1 & 0x80000000) != (imm & 0x80000000)
1134 && (reg1 & 0x80000000) != (value & 0x80000000));
73e65298
JL		 1135
1136 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1137 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1138 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
05ccbdfd
JL		 1139}
1140
de0dce7c 1141/* add imm8, sp */
05ccbdfd
JL		 1142void OP_F8FE00 ()
1143{
73e65298
JL		 1144 int z, c, n, v;
1145 unsigned long reg1, imm, value;
1146
1147 reg1 = State.regs[REG_SP];
1148 imm = SEXT8 (insn & 0xff);
1149 value = reg1 + imm;
1150 State.regs[REG_SP] = value;
05ccbdfd
JL		 1151}
1152
73e65298 1153/* add imm16,sp */
05ccbdfd
JL		 1154void OP_FAFE0000 ()
1155{
73e65298
JL		 1156 int z, c, n, v;
1157 unsigned long reg1, imm, value;
1158
1159 reg1 = State.regs[REG_SP];
1160 imm = SEXT16 (insn & 0xffff);
1161 value = reg1 + imm;
1162 State.regs[REG_SP] = value;
05ccbdfd
JL		 1163}
1164
de0dce7c 1165/* add imm32, sp */
05ccbdfd
JL		 1166void OP_FCFE0000 ()
1167{
73e65298
JL		 1168 int z, c, n, v;
1169 unsigned long reg1, imm, value;
1170
1171 reg1 = State.regs[REG_SP];
1172 imm = ((insn & 0xffff) << 16) | extension;
1173 value = reg1 + imm;
1174 State.regs[REG_SP] = value;
05ccbdfd
JL		 1175}
1176
de0dce7c 1177/* addc dm,dn */
05ccbdfd
JL		 1178void OP_F140 ()
1179{
73e65298
JL		 1180 int z, c, n, v;
1181 unsigned long reg1, reg2, value;
1182
1183 reg1 = State.regs[REG_D0 + ((insn & 0xc) >> 2)];
1184 reg2 = State.regs[REG_D0 + (insn & 0x3)];
1185 value = reg1 + reg2 + ((PSW & PSW_C) != 0);
1186 State.regs[REG_D0 + (insn & 0x3)] = value;
1187
1188 z = (value == 0);
1189 n = (value & 0x80000000);
1190 c = (reg1 < reg2);
b7b89deb
JL		 1191 v = ((reg2 & 0x80000000) != (reg1 & 0x80000000)
1192 && (reg2 & 0x80000000) != (value & 0x80000000));
73e65298
JL		 1193
1194 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1195 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1196 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
05ccbdfd
JL		 1197}
1198
707641f6 1199/* sub dm, dn */
05ccbdfd
JL		 1200void OP_F100 ()
1201{
707641f6
JL		 1202 int z, c, n, v;
1203 unsigned long reg1, reg2, value;
1204
1205 reg1 = State.regs[REG_D0 + ((insn & 0xc) >> 2)];
1206 reg2 = State.regs[REG_D0 + (insn & 0x3)];
1207 value = reg2 - reg1;
1208
1209 z = (value == 0);
1210 n = (value & 0x80000000);
216e6557 1211 c = (reg1 > reg2);
b7b89deb
JL		 1212 v = ((reg2 & 0x80000000) != (reg1 & 0x80000000)
1213 && (reg2 & 0x80000000) != (value & 0x80000000));
707641f6
JL		 1214
1215 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1216 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1217 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1218 State.regs[REG_D0 + (insn & 0x3)] = value;
05ccbdfd
JL		 1219}
1220
707641f6 1221/* sub dm, an */
05ccbdfd
JL		 1222void OP_F120 ()
1223{
707641f6
JL		 1224 int z, c, n, v;
1225 unsigned long reg1, reg2, value;
1226
1227 reg1 = State.regs[REG_D0 + ((insn & 0xc) >> 2)];
1228 reg2 = State.regs[REG_A0 + (insn & 0x3)];
1229 value = reg2 - reg1;
1230
1231 z = (value == 0);
1232 n = (value & 0x80000000);
216e6557 1233 c = (reg1 > reg2);
b7b89deb
JL		 1234 v = ((reg2 & 0x80000000) != (reg1 & 0x80000000)
1235 && (reg2 & 0x80000000) != (value & 0x80000000));
707641f6
JL		 1236
1237 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1238 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1239 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1240 State.regs[REG_A0 + (insn & 0x3)] = value;
05ccbdfd
JL		 1241}
1242
707641f6 1243/* sub am, dn */
05ccbdfd
JL		 1244void OP_F110 ()
1245{
707641f6
JL		 1246 int z, c, n, v;
1247 unsigned long reg1, reg2, value;
1248
1249 reg1 = State.regs[REG_A0 + ((insn & 0xc) >> 2)];
1250 reg2 = State.regs[REG_D0 + (insn & 0x3)];
1251 value = reg2 - reg1;
1252
1253 z = (value == 0);
1254 n = (value & 0x80000000);
216e6557 1255 c = (reg1 > reg2);
b7b89deb
JL		 1256 v = ((reg2 & 0x80000000) != (reg1 & 0x80000000)
1257 && (reg2 & 0x80000000) != (value & 0x80000000));
707641f6
JL		 1258
1259 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1260 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1261 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1262 State.regs[REG_D0 + (insn & 0x3)] = value;
05ccbdfd
JL		 1263}
1264
707641f6 1265/* sub am, an */
05ccbdfd
JL		 1266void OP_F130 ()
1267{
707641f6
JL		 1268 int z, c, n, v;
1269 unsigned long reg1, reg2, value;
1270
1271 reg1 = State.regs[REG_A0 + ((insn & 0xc) >> 2)];
1272 reg2 = State.regs[REG_A0 + (insn & 0x3)];
1273 value = reg2 - reg1;
1274
1275 z = (value == 0);
1276 n = (value & 0x80000000);
216e6557 1277 c = (reg1 > reg2);
b7b89deb
JL		 1278 v = ((reg2 & 0x80000000) != (reg1 & 0x80000000)
1279 && (reg2 & 0x80000000) != (value & 0x80000000));
707641f6
JL		 1280
1281 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1282 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1283 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1284 State.regs[REG_A0 + (insn & 0x3)] = value;
05ccbdfd
JL		 1285}
1286
de0dce7c 1287/* sub imm32, dn */
05ccbdfd
JL		 1288void OP_FCC40000 ()
1289{
707641f6
JL		 1290 int z, c, n, v;
1291 unsigned long reg1, imm, value;
1292
20e1ab85 1293 reg1 = State.regs[REG_D0 + ((insn & 0x30000) >> 16)];
707641f6
JL		 1294 imm = ((insn & 0xffff) << 16) | extension;
1295 value = reg1 - imm;
1296
1297 z = (value == 0);
1298 n = (value & 0x80000000);
1299 c = (reg1 < imm);
b7b89deb
JL		 1300 v = ((reg1 & 0x80000000) != (imm & 0x80000000)
1301 && (reg1 & 0x80000000) != (value & 0x80000000));
707641f6
JL		 1302
1303 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1304 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1305 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
20e1ab85 1306 State.regs[REG_D0 + ((insn & 0x30000) >> 16)] = value;
05ccbdfd
JL		 1307}
1308
de0dce7c 1309/* sub imm32, an */
05ccbdfd
JL		 1310void OP_FCD40000 ()
1311{
707641f6
JL		 1312 int z, c, n, v;
1313 unsigned long reg1, imm, value;
1314
20e1ab85 1315 reg1 = State.regs[REG_A0 + ((insn & 0x30000) >> 16)];
707641f6
JL		 1316 imm = ((insn & 0xffff) << 16) | extension;
1317 value = reg1 - imm;
1318
1319 z = (value == 0);
1320 n = (value & 0x80000000);
1321 c = (reg1 < imm);
b7b89deb
JL		 1322 v = ((reg1 & 0x80000000) != (imm & 0x80000000)
1323 && (reg1 & 0x80000000) != (value & 0x80000000));
707641f6
JL		 1324
1325 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1326 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1327 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
20e1ab85 1328 State.regs[REG_A0 + ((insn & 0x30000) >> 16)] = value;
05ccbdfd
JL		 1329}
1330
de0dce7c 1331/* subc dm, dn */
05ccbdfd
JL		 1332void OP_F180 ()
1333{
707641f6
JL		 1334 int z, c, n, v;
1335 unsigned long reg1, reg2, value;
1336
1337 reg1 = State.regs[REG_D0 + ((insn & 0xc) >> 2)];
1338 reg2 = State.regs[REG_D0 + (insn & 0x3)];
1339 value = reg2 - reg1 - ((PSW & PSW_C) != 0);
1340
1341 z = (value == 0);
1342 n = (value & 0x80000000);
216e6557 1343 c = (reg1 > reg2);
b7b89deb
JL		 1344 v = ((reg2 & 0x80000000) != (reg1 & 0x80000000)
1345 && (reg2 & 0x80000000) != (value & 0x80000000));
707641f6
JL		 1346
1347 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1348 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1349 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1350 State.regs[REG_D0 + (insn & 0x3)] = value;
05ccbdfd
JL		 1351}
1352
de0dce7c 1353/* mul dm, dn */
05ccbdfd
JL		 1354void OP_F240 ()
1355{
707641f6
JL		 1356 unsigned long long temp;
1357 int n, z;
1358
1359 temp = (State.regs[REG_D0 + (insn & 0x3)]
1360 * State.regs[REG_D0 + ((insn & 0xc) >> 2)]);
1361 State.regs[REG_D0 + (insn & 0x3)] = temp & 0xffffffff;
1362 State.regs[REG_MDR] = temp & 0xffffffff00000000LL;
1363 z = (State.regs[REG_D0 + (insn & 0x3)] == 0);
b7b89deb 1364 n = (State.regs[REG_D0 + (insn & 0x3)] & 0x80000000) != 0;
707641f6
JL		 1365 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1366 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
05ccbdfd
JL		 1367}
1368
de0dce7c 1369/* mulu dm, dn */
05ccbdfd
JL		 1370void OP_F250 ()
1371{
707641f6
JL		 1372 unsigned long long temp;
1373 int n, z;
1374
1375 temp = (State.regs[REG_D0 + (insn & 0x3)]
1376 * State.regs[REG_D0 + ((insn & 0xc) >> 2)]);
1377 State.regs[REG_D0 + (insn & 0x3)] = temp & 0xffffffff;
1378 State.regs[REG_MDR] = temp & 0xffffffff00000000LL;
1379 z = (State.regs[REG_D0 + (insn & 0x3)] == 0);
b7b89deb 1380 n = (State.regs[REG_D0 + (insn & 0x3)] & 0x80000000) != 0;
707641f6
JL		 1381 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1382 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
05ccbdfd
JL		 1383}
1384
de0dce7c 1385/* div dm, dn */
05ccbdfd
JL		 1386void OP_F260 ()
1387{
707641f6
JL		 1388 long long temp;
1389 int n, z;
1390
1391 temp = State.regs[REG_MDR];
1392 temp <<= 32;
1393 temp |= State.regs[REG_D0 + (insn & 0x3)];
e4e13022
JL		 1394 State.regs[REG_MDR] = temp % (long)State.regs[REG_D0 + ((insn & 0xc) >> 2)];
1395 temp /= (long)State.regs[REG_D0 + ((insn & 0xc) >> 2)];
707641f6
JL		 1396 State.regs[REG_D0 + (insn & 0x3)] = temp & 0xffffffff;
1397 State.regs[REG_MDR] = temp & 0xffffffff00000000LL;
1398 z = (State.regs[REG_D0 + (insn & 0x3)] == 0);
b7b89deb 1399 n = (State.regs[REG_D0 + (insn & 0x3)] & 0x80000000) != 0;
707641f6
JL		 1400 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1401 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
05ccbdfd
JL		 1402}
1403
de0dce7c 1404/* divu dm, dn */
05ccbdfd
JL		 1405void OP_F270 ()
1406{
707641f6
JL		 1407 unsigned long long temp;
1408 int n, z;
1409
1410 temp = State.regs[REG_MDR];
1411 temp <<= 32;
1412 temp |= State.regs[REG_D0 + (insn & 0x3)];
1413 State.regs[REG_MDR] = temp % State.regs[REG_D0 + ((insn & 0xc) >> 2)];
1414 temp /= State.regs[REG_D0 + ((insn & 0xc) >> 2)];
707641f6
JL		 1415 State.regs[REG_D0 + (insn & 0x3)] = temp & 0xffffffff;
1416 State.regs[REG_MDR] = temp & 0xffffffff00000000LL;
1417 z = (State.regs[REG_D0 + (insn & 0x3)] == 0);
b7b89deb 1418 n = (State.regs[REG_D0 + (insn & 0x3)] & 0x80000000) != 0;
707641f6
JL		 1419 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1420 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
05ccbdfd
JL		 1421}
1422
73e65298 1423/* inc dn */
05ccbdfd
JL		 1424void OP_40 ()
1425{
61ecca95 1426 int z,n,c,v;
4d8ced6c 1427 unsigned int value, imm, reg1;
61ecca95 1428
4d8ced6c
JL		 1429 reg1 = State.regs[REG_D0 + ((insn & 0xc) >> 2)];
1430 imm = 1;
1431 value = reg1 + imm;
61ecca95
JL		 1432 State.regs[REG_D0 + ((insn & 0xc) >> 2)] = value;
1433
1434 z = (value == 0);
1435 n = (value & 0x80000000);
4d8ced6c
JL		 1436 c = (reg1 < imm);
1437 v = ((reg1 & 0x80000000) != (imm & 0x80000000)
1438 && (reg1 & 0x80000000) != (value & 0x80000000));
61ecca95
JL		 1439
1440 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1441 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1442 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
05ccbdfd
JL		 1443}
1444
73e65298 1445/* inc an */
05ccbdfd
JL		 1446void OP_41 ()
1447{
73e65298 1448 State.regs[REG_A0 + ((insn & 0xc) >> 2)] += 1;
05ccbdfd
JL		 1449}
1450
92284aaa 1451/* inc4 an */
05ccbdfd
JL		 1452void OP_50 ()
1453{
73e65298 1454 State.regs[REG_A0 + (insn & 0x3)] += 4;
05ccbdfd
JL		 1455}
1456
92284aaa 1457/* cmp imm8, dn */
05ccbdfd
JL		 1458void OP_A000 ()
1459{
92284aaa
JL		 1460 int z, c, n, v;
1461 unsigned long reg1, imm, value;
1462
1463 reg1 = State.regs[REG_D0 + ((insn & 0x300) >> 8)];
1464 imm = SEXT8 (insn & 0xff);
1465 value = reg1 - imm;
1466
1467 z = (value == 0);
1468 n = (value & 0x80000000);
1469 c = (reg1 < imm);
b7b89deb
JL		 1470 v = ((reg1 & 0x80000000) != (imm & 0x80000000)
1471 && (reg1 & 0x80000000) != (value & 0x80000000));
92284aaa
JL		 1472
1473 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1474 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1475 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
05ccbdfd
JL		 1476}
1477
92284aaa 1478/* cmp dm, dn */
05ccbdfd
JL		 1479void OP_A0 ()
1480{
92284aaa
JL		 1481 int z, c, n, v;
1482 unsigned long reg1, reg2, value;
1483
1484 reg1 = State.regs[REG_D0 + ((insn & 0xc) >> 2)];
1485 reg2 = State.regs[REG_D0 + (insn & 0x3)];
707641f6 1486 value = reg2 - reg1;
92284aaa
JL		 1487
1488 z = (value == 0);
1489 n = (value & 0x80000000);
216e6557 1490 c = (reg1 > reg2);
b7b89deb
JL		 1491 v = ((reg2 & 0x80000000) != (reg1 & 0x80000000)
1492 && (reg2 & 0x80000000) != (value & 0x80000000));
92284aaa
JL		 1493
1494 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1495 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1496 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
05ccbdfd
JL		 1497}
1498
92284aaa 1499/* cmp dm, an */
05ccbdfd
JL		 1500void OP_F1A0 ()
1501{
92284aaa
JL		 1502 int z, c, n, v;
1503 unsigned long reg1, reg2, value;
1504
1505 reg1 = State.regs[REG_D0 + ((insn & 0xc) >> 2)];
1506 reg2 = State.regs[REG_A0 + (insn & 0x3)];
707641f6 1507 value = reg2 - reg1;
92284aaa
JL		 1508
1509 z = (value == 0);
1510 n = (value & 0x80000000);
216e6557 1511 c = (reg1 > reg2);
b7b89deb
JL		 1512 v = ((reg2 & 0x80000000) != (reg1 & 0x80000000)
1513 && (reg2 & 0x80000000) != (value & 0x80000000));
92284aaa
JL		 1514
1515 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1516 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1517 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
05ccbdfd
JL		 1518}
1519
92284aaa 1520/* cmp am, dn */
05ccbdfd
JL		 1521void OP_F190 ()
1522{
92284aaa
JL		 1523 int z, c, n, v;
1524 unsigned long reg1, reg2, value;
1525
1526 reg1 = State.regs[REG_A0 + ((insn & 0xc) >> 2)];
1527 reg2 = State.regs[REG_D0 + (insn & 0x3)];
707641f6 1528 value = reg2 - reg1;
92284aaa
JL		 1529
1530 z = (value == 0);
1531 n = (value & 0x80000000);
216e6557 1532 c = (reg1 > reg2);
b7b89deb
JL		 1533 v = ((reg2 & 0x80000000) != (reg1 & 0x80000000)
1534 && (reg2 & 0x80000000) != (value & 0x80000000));
92284aaa
JL		 1535
1536 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1537 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1538 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
05ccbdfd
JL		 1539}
1540
92284aaa 1541/* cmp imm8, an */
05ccbdfd
JL		 1542void OP_B000 ()
1543{
92284aaa
JL		 1544 int z, c, n, v;
1545 unsigned long reg1, imm, value;
1546
1547 reg1 = State.regs[REG_A0 + ((insn & 0x300) >> 8)];
1548 imm = insn & 0xff;
1549 value = reg1 - imm;
1550
1551 z = (value == 0);
1552 n = (value & 0x80000000);
1553 c = (reg1 < imm);
b7b89deb
JL		 1554 v = ((reg1 & 0x80000000) != (imm & 0x80000000)
1555 && (reg1 & 0x80000000) != (value & 0x80000000));
92284aaa
JL		 1556
1557 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1558 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1559 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
05ccbdfd
JL		 1560}
1561
707641f6 1562/* cmp am, an */
05ccbdfd
JL		 1563void OP_B0 ()
1564{
73e65298
JL		 1565 int z, c, n, v;
1566 unsigned long reg1, reg2, value;
1567
1568 reg1 = State.regs[REG_A0 + ((insn & 0xc) >> 2)];
1569 reg2 = State.regs[REG_A0 + (insn & 0x3)];
707641f6 1570 value = reg2 - reg1;
73e65298
JL		 1571
1572 z = (value == 0);
1573 n = (value & 0x80000000);
216e6557 1574 c = (reg1 > reg2);
b7b89deb
JL		 1575 v = ((reg2 & 0x80000000) != (reg1 & 0x80000000)
1576 && (reg2 & 0x80000000) != (value & 0x80000000));
73e65298
JL		 1577
1578 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1579 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1580 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
05ccbdfd
JL		 1581}
1582
707641f6 1583/* cmp imm16, dn */
05ccbdfd
JL		 1584void OP_FAC80000 ()
1585{
92284aaa
JL		 1586 int z, c, n, v;
1587 unsigned long reg1, imm, value;
1588
20e1ab85 1589 reg1 = State.regs[REG_D0 + ((insn & 0x30000) >> 16)];
92284aaa
JL		 1590 imm = SEXT16 (insn & 0xffff);
1591 value = reg1 - imm;
1592
1593 z = (value == 0);
1594 n = (value & 0x80000000);
1595 c = (reg1 < imm);
b7b89deb
JL		 1596 v = ((reg1 & 0x80000000) != (imm & 0x80000000)
1597 && (reg1 & 0x80000000) != (value & 0x80000000));
92284aaa
JL		 1598
1599 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1600 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1601 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
05ccbdfd
JL		 1602}
1603
707641f6 1604/* cmp imm32, dn */
05ccbdfd
JL		 1605void OP_FCC80000 ()
1606{
92284aaa
JL		 1607 int z, c, n, v;
1608 unsigned long reg1, imm, value;
1609
20e1ab85 1610 reg1 = State.regs[REG_D0 + ((insn & 0x30000) >> 16)];
92284aaa
JL		 1611 imm = ((insn & 0xffff) << 16) | extension;
1612 value = reg1 - imm;
1613
1614 z = (value == 0);
1615 n = (value & 0x80000000);
1616 c = (reg1 < imm);
b7b89deb
JL		 1617 v = ((reg1 & 0x80000000) != (imm & 0x80000000)
1618 && (reg1 & 0x80000000) != (value & 0x80000000));
92284aaa
JL		 1619
1620 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1621 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1622 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
05ccbdfd
JL		 1623}
1624
707641f6 1625/* cmp imm16, an */
05ccbdfd
JL		 1626void OP_FAD80000 ()
1627{
92284aaa
JL		 1628 int z, c, n, v;
1629 unsigned long reg1, imm, value;
1630
20e1ab85 1631 reg1 = State.regs[REG_A0 + ((insn & 0x30000) >> 16)];
92284aaa
JL		 1632 imm = insn & 0xffff;
1633 value = reg1 - imm;
1634
1635 z = (value == 0);
1636 n = (value & 0x80000000);
1637 c = (reg1 < imm);
b7b89deb
JL		 1638 v = ((reg1 & 0x80000000) != (imm & 0x80000000)
1639 && (reg1 & 0x80000000) != (value & 0x80000000));
92284aaa
JL		 1640
1641 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1642 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1643 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
05ccbdfd
JL		 1644}
1645
707641f6 1646/* cmp imm32, an */
05ccbdfd
JL		 1647void OP_FCD80000 ()
1648{
92284aaa
JL		 1649 int z, c, n, v;
1650 unsigned long reg1, imm, value;
1651
20e1ab85 1652 reg1 = State.regs[REG_A0 + ((insn & 0x30000) >> 16)];
92284aaa
JL		 1653 imm = ((insn & 0xffff) << 16) | extension;
1654 value = reg1 - imm;
1655
1656 z = (value == 0);
1657 n = (value & 0x80000000);
1658 c = (reg1 < imm);
b7b89deb
JL		 1659 v = ((reg1 & 0x80000000) != (imm & 0x80000000)
1660 && (reg1 & 0x80000000) != (value & 0x80000000));
92284aaa
JL		 1661
1662 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1663 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1664 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
05ccbdfd
JL		 1665}
1666
707641f6 1667/* and dm, dn */
05ccbdfd
JL		 1668void OP_F200 ()
1669{
707641f6
JL		 1670 int n, z;
1671
1672 State.regs[REG_D0 + (insn & 0x3)] &= State.regs[REG_D0 + ((insn & 0xc) >> 2)];
1673 z = (State.regs[REG_D0 + (insn & 0x3)] == 0);
b7b89deb 1674 n = (State.regs[REG_D0 + (insn & 0x3)] & 0x80000000) != 0;
707641f6
JL		 1675 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1676 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
05ccbdfd
JL		 1677}
1678
2e35551c 1679/* and imm8, dn */
05ccbdfd
JL		 1680void OP_F8E000 ()
1681{
2e35551c
JL		 1682 int n, z;
1683
1684 State.regs[REG_D0 + ((insn & 0x300) >> 8)] &= (insn & 0xff);
1685 z = (State.regs[REG_D0 + ((insn & 0x300) >> 8)] == 0);
b7b89deb 1686 n = (State.regs[REG_D0 + ((insn & 0x300) >> 8)] & 0x80000000) != 0;
2e35551c
JL		 1687 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1688 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
05ccbdfd
JL		 1689}
1690
ecb4b5a3 1691/* and imm16, dn */
05ccbdfd
JL		 1692void OP_FAE00000 ()
1693{
ecb4b5a3
JL		 1694 int n, z;
1695
1696 State.regs[REG_D0 + ((insn & 0x30000) >> 16)] &= (insn & 0xffff);
1697 z = (State.regs[REG_D0 + ((insn & 0x30000) >> 16)] == 0);
b7b89deb 1698 n = (State.regs[REG_D0 + ((insn & 0x30000) >> 16)] & 0x80000000) != 0;
ecb4b5a3
JL		 1699 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1700 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
05ccbdfd
JL		 1701}
1702
de0dce7c 1703/* and imm32, dn */
05ccbdfd
JL		 1704void OP_FCE00000 ()
1705{
de0dce7c
JL		 1706 int n, z;
1707
1708 State.regs[REG_D0 + ((insn & 0x30000) >> 16)]
1709 &= ((insn & 0xffff) << 16 | extension);
1710 z = (State.regs[REG_D0 + ((insn & 0x30000) >> 16)] == 0);
b7b89deb 1711 n = (State.regs[REG_D0 + ((insn & 0x30000) >> 16)] & 0x80000000) != 0;
de0dce7c
JL		 1712 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1713 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
05ccbdfd
JL		 1714}
1715
ecb4b5a3 1716/* and imm16, psw */
05ccbdfd
JL		 1717void OP_FAFC0000 ()
1718{
ecb4b5a3 1719 PSW &= (insn & 0xffff);
05ccbdfd
JL		 1720}
1721
707641f6 1722/* or dm, dn*/
05ccbdfd
JL		 1723void OP_F210 ()
1724{
707641f6
JL		 1725 int n, z;
1726
1727 State.regs[REG_D0 + (insn & 0x3)] |= State.regs[REG_D0 + ((insn & 0xc) >> 2)];
1728 z = (State.regs[REG_D0 + (insn & 0x3)] == 0);
b7b89deb 1729 n = (State.regs[REG_D0 + (insn & 0x3)] & 0x80000000) != 0;
707641f6
JL		 1730 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1731 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
05ccbdfd
JL		 1732}
1733
2e35551c 1734/* or imm8, dn */
05ccbdfd
JL		 1735void OP_F8E400 ()
1736{
2e35551c
JL		 1737 int n, z;
1738
1739 State.regs[REG_D0 + ((insn & 0x300) >> 8)] |= insn & 0xff;
1740 z = (State.regs[REG_D0 + ((insn & 0x300) >> 8)] == 0);
b7b89deb 1741 n = (State.regs[REG_D0 + ((insn & 0x300) >> 8)] & 0x80000000) != 0;
2e35551c
JL		 1742 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1743 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
05ccbdfd
JL		 1744}
1745
ecb4b5a3 1746/* or imm16, dn*/
05ccbdfd
JL		 1747void OP_FAE40000 ()
1748{
ecb4b5a3
JL		 1749 int n, z;
1750
1751 State.regs[REG_D0 + ((insn & 0x30000) >> 16)] |= insn & 0xffff;
1752 z = (State.regs[REG_D0 + ((insn & 0x30000) >> 16)] == 0);
b7b89deb 1753 n = (State.regs[REG_D0 + ((insn & 0x30000) >> 16)] & 0x80000000) != 0;
ecb4b5a3
JL		 1754 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1755 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
05ccbdfd
JL		 1756}
1757
de0dce7c 1758/* or imm32, dn */
05ccbdfd
JL		 1759void OP_FCE40000 ()
1760{
de0dce7c
JL		 1761 int n, z;
1762
1763 State.regs[REG_D0 + ((insn & 0x30000) >> 16)]
1764 |= ((insn & 0xffff) << 16 | extension);
1765 z = (State.regs[REG_D0 + ((insn & 0x30000) >> 16)] == 0);
b7b89deb 1766 n = (State.regs[REG_D0 + ((insn & 0x30000) >> 16)] & 0x80000000) != 0;
de0dce7c
JL		 1767 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1768 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
05ccbdfd
JL		 1769}
1770
ecb4b5a3 1771/* or imm16,psw */
05ccbdfd
JL		 1772void OP_FAFD0000 ()
1773{
ecb4b5a3 1774 PSW |= (insn & 0xffff);
05ccbdfd
JL		 1775}
1776
707641f6 1777/* xor dm, dn*/
05ccbdfd
JL		 1778void OP_F220 ()
1779{
707641f6
JL		 1780 int n, z;
1781
1782 State.regs[REG_D0 + (insn & 0x3)] ^= State.regs[REG_D0 + ((insn & 0xc) >> 2)];
1783 z = (State.regs[REG_D0 + (insn & 0x3)] == 0);
b7b89deb 1784 n = (State.regs[REG_D0 + (insn & 0x3)] & 0x80000000) != 0;
707641f6
JL		 1785 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1786 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
05ccbdfd
JL		 1787}
1788
ecb4b5a3 1789/* xor imm16, dn */
05ccbdfd
JL		 1790void OP_FAE80000 ()
1791{
ecb4b5a3
JL		 1792 int n, z;
1793
1794 State.regs[REG_D0 + ((insn & 0x30000) >> 16)] ^= insn & 0xffff;
1795 z = (State.regs[REG_D0 + ((insn & 0x30000) >> 16)] == 0);
b7b89deb 1796 n = (State.regs[REG_D0 + ((insn & 0x30000) >> 16)] & 0x80000000) != 0;
ecb4b5a3
JL		 1797 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1798 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
05ccbdfd
JL		 1799}
1800
de0dce7c 1801/* xor imm32, dn */
05ccbdfd
JL		 1802void OP_FCE80000 ()
1803{
de0dce7c
JL		 1804 int n, z;
1805
1806 State.regs[REG_D0 + ((insn & 0x30000) >> 16)]
1807 ^= ((insn & 0xffff) << 16 | extension);
1808 z = (State.regs[REG_D0 + ((insn & 0x30000) >> 16)] == 0);
b7b89deb 1809 n = (State.regs[REG_D0 + ((insn & 0x30000) >> 16)] & 0x80000000) != 0;
de0dce7c
JL		 1810 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1811 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
05ccbdfd
JL		 1812}
1813
de0dce7c 1814/* not dn */
05ccbdfd
JL		 1815void OP_F230 ()
1816{
707641f6
JL		 1817 int n, z;
1818
1819 State.regs[REG_D0 + (insn & 0x3)] = ~State.regs[REG_D0 + (insn & 0x3)];
1820 z = (State.regs[REG_D0 + (insn & 0x3)] == 0);
b7b89deb 1821 n = (State.regs[REG_D0 + (insn & 0x3)] & 0x80000000) != 0;
707641f6
JL		 1822 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1823 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
05ccbdfd
JL		 1824}
1825
2e35551c 1826/* btst imm8, dn */
05ccbdfd
JL		 1827void OP_F8EC00 ()
1828{
2e35551c
JL		 1829 unsigned long temp;
1830 int z, n;
1831
1832 temp = State.regs[REG_D0 + ((insn & 0x300) >> 8)];
1833 temp &= (insn & 0xff);
1834 n = (temp & 0x80000000) != 0;
1835 z = (temp == 0);
1836 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1837 PSW |= (z ? PSW_Z : 0) | (n ? PSW_N : 0);
05ccbdfd
JL		 1838}
1839
ecb4b5a3 1840/* btst imm16, dn */
05ccbdfd
JL		 1841void OP_FAEC0000 ()
1842{
ecb4b5a3
JL		 1843 unsigned long temp;
1844 int z, n;
1845
1846 temp = State.regs[REG_D0 + ((insn & 0x30000) >> 16)];
1847 temp &= (insn & 0xffff);
1848 n = (temp & 0x80000000) != 0;
1849 z = (temp == 0);
1850 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1851 PSW |= (z ? PSW_Z : 0) | (n ? PSW_N : 0);
05ccbdfd
JL		 1852}
1853
de0dce7c 1854/* btst imm32, dn */
05ccbdfd
JL		 1855void OP_FCEC0000 ()
1856{
de0dce7c
JL		 1857 unsigned long temp;
1858 int z, n;
1859
1860 temp = State.regs[REG_D0 + ((insn & 0x30000) >> 16)];
1861 temp &= ((insn & 0xffff) << 16 | extension);
1862 n = (temp & 0x80000000) != 0;
1863 z = (temp == 0);
1864 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1865 PSW |= (z ? PSW_Z : 0) | (n ? PSW_N : 0);
05ccbdfd
JL		 1866}
1867
de0dce7c 1868/* btst imm8,(abs32) */
05ccbdfd
JL		 1869void OP_FE020000 ()
1870{
de0dce7c
JL		 1871 unsigned long temp;
1872 int n, z;
1873
1874 temp = load_mem (((insn & 0xffff) << 16) | (extension >> 8), 1);
1875 temp &= (extension & 0xff);
1876 n = (temp & 0x80000000) != 0;
1877 z = (temp == 0);
1878 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1879 PSW |= (z ? PSW_Z : 0) | (n ? PSW_N : 0);
05ccbdfd
JL		 1880}
1881
ecb4b5a3 1882/* btst imm8,(d8,an) */
05ccbdfd
JL		 1883void OP_FAF80000 ()
1884{
ecb4b5a3
JL		 1885 unsigned long temp;
1886 int n, z;
1887
1888 temp = load_mem ((State.regs[REG_A0 + ((insn & 0x30000) >> 16)]
1889 + SEXT8 ((insn & 0xff00) >> 8)), 1);
1890 temp &= (insn & 0xff);
1891 n = (temp & 0x80000000) != 0;
1892 z = (temp == 0);
1893 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1894 PSW |= (z ? PSW_Z : 0) | (n ? PSW_N : 0);
05ccbdfd
JL		 1895}
1896
707641f6 1897/* bset dm, (an) */
05ccbdfd
JL		 1898void OP_F080 ()
1899{
707641f6
JL		 1900 unsigned long temp;
1901 int z;
1902
1903 temp = load_mem (State.regs[REG_A0 + (insn & 3)], 1);
1904 z = (temp & State.regs[REG_D0 + ((insn & 0xc) >> 2)]) == 0;
1905 temp |= State.regs[REG_D0 + ((insn & 0xc) >> 2)];
1906 store_mem (State.regs[REG_A0 + (insn & 3)], 1, temp);
1907 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1908 PSW |= (z ? PSW_Z : 0);
05ccbdfd
JL		 1909}
1910
de0dce7c 1911/* bset imm8, (abs32) */
05ccbdfd
JL		 1912void OP_FE000000 ()
1913{
de0dce7c
JL		 1914 unsigned long temp;
1915 int z;
1916
1917 temp = load_mem (((insn & 0xffff) << 16 | (extension >> 8)), 1);
1918 z = (temp & (extension & 0xff)) == 0;
1919 temp |= (extension & 0xff);
1920 store_mem ((((insn & 0xffff) << 16) | (extension >> 8)), 1, temp);
1921 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1922 PSW |= (z ? PSW_Z : 0);
05ccbdfd
JL		 1923}
1924
ecb4b5a3 1925/* bset imm8,(d8,an) */
05ccbdfd
JL		 1926void OP_FAF00000 ()
1927{
ecb4b5a3
JL		 1928 unsigned long temp;
1929 int z;
1930
1931 temp = load_mem ((State.regs[REG_A0 + ((insn & 0x30000) >> 16)]
1932 + SEXT8 ((insn & 0xff00) >> 8)), 1);
1933 z = (temp & (insn & 0xff)) == 0;
1934 temp |= (insn & 0xff);
1935 store_mem (State.regs[REG_A0 + ((insn & 30000)>> 16)], 1, temp);
1936 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1937 PSW |= (z ? PSW_Z : 0);
05ccbdfd
JL		 1938}
1939
707641f6 1940/* bclr dm, (an) */
05ccbdfd
JL		 1941void OP_F090 ()
1942{
707641f6
JL		 1943 unsigned long temp;
1944 int z;
1945
1946 temp = load_mem (State.regs[REG_A0 + (insn & 3)], 1);
1947 z = (temp & State.regs[REG_D0 + ((insn & 0xc) >> 2)]) == 0;
1948 temp = ~temp & State.regs[REG_D0 + ((insn & 0xc) >> 2)];
1949 store_mem (State.regs[REG_A0 + (insn & 3)], 1, temp);
1950 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1951 PSW |= (z ? PSW_Z : 0);
05ccbdfd
JL		 1952}
1953
de0dce7c 1954/* bclr imm8, (abs32) */
05ccbdfd
JL		 1955void OP_FE010000 ()
1956{
de0dce7c
JL		 1957 unsigned long temp;
1958 int z;
1959
1960 temp = load_mem (((insn & 0xffff) << 16) | (extension >> 8), 1);
1961 z = (temp & (extension & 0xff)) == 0;
1962 temp = ~temp & (extension & 0xff);
1963 store_mem (((insn & 0xffff) << 16) | (extension >> 8), 1, temp);
1964 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1965 PSW |= (z ? PSW_Z : 0);
05ccbdfd
JL		 1966}
1967
ecb4b5a3 1968/* bclr imm8,(d8,an) */
05ccbdfd
JL		 1969void OP_FAF40000 ()
1970{
ecb4b5a3
JL		 1971 unsigned long temp;
1972 int z;
1973
1974 temp = load_mem ((State.regs[REG_A0 + ((insn & 0x30000) >> 16)]
1975 + SEXT8 ((insn & 0xff00) >> 8)), 1);
1976 z = (temp & (insn & 0xff)) == 0;
1977 temp = ~temp & (insn & 0xff);
1978 store_mem (State.regs[REG_A0 + ((insn & 30000)>> 16)], 1, temp);
1979 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1980 PSW |= (z ? PSW_Z : 0);
05ccbdfd
JL		 1981}
1982
2e35551c 1983/* asr dm, dn */
05ccbdfd
JL		 1984void OP_F2B0 ()
1985{
707641f6
JL		 1986 long temp;
1987 int z, n, c;
1988
1989 temp = State.regs[REG_D0 + (insn & 0x3)];
1990 c = temp & 1;
1991 temp >>= State.regs[REG_D0 + ((insn & 0xc) >> 2)];
1992 State.regs[REG_D0 + (insn & 0x3)] = temp;
1993 z = (State.regs[REG_D0 + (insn & 0x3)] == 0);
b7b89deb 1994 n = (State.regs[REG_D0 + (insn & 0x3)] & 0x80000000) != 0;
707641f6
JL		 1995 PSW &= ~(PSW_Z | PSW_N | PSW_C);
1996 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
05ccbdfd
JL		 1997}
1998
2e35551c 1999/* asr imm8, dn */
05ccbdfd
JL		 2000void OP_F8C800 ()
2001{
2e35551c
JL		 2002 long temp;
2003 int z, n, c;
2004
2005 temp = State.regs[REG_D0 + ((insn & 0x300) >> 8)];
2006 c = temp & 1;
2007 temp >>= (insn & 0xff);
2008 State.regs[REG_D0 + ((insn & 0x300) >> 8)] = temp;
2009 z = (State.regs[REG_D0 + ((insn & 0x300) >> 8)] == 0);
b7b89deb 2010 n = (State.regs[REG_D0 + ((insn & 0x300) >> 8)] & 0x80000000) != 0;
2e35551c
JL		 2011 PSW &= ~(PSW_Z | PSW_N | PSW_C);
2012 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
05ccbdfd
JL		 2013}
2014
2e35551c 2015/* lsr dm, dn */
05ccbdfd
JL		 2016void OP_F2A0 ()
2017{
707641f6
JL		 2018 int z, n, c;
2019
2020 c = State.regs[REG_D0 + (insn & 0x3)] & 1;
2021 State.regs[REG_D0 + (insn & 0x3)]
2022 >>= State.regs[REG_D0 + ((insn & 0xc) >> 2)];
2023 z = (State.regs[REG_D0 + (insn & 0x3)] == 0);
b7b89deb 2024 n = (State.regs[REG_D0 + (insn & 0x3)] & 0x80000000) != 0;
707641f6
JL		 2025 PSW &= ~(PSW_Z | PSW_N | PSW_C);
2026 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
05ccbdfd
JL		 2027}
2028
2e35551c 2029/* lsr dm, dn */
05ccbdfd
JL		 2030void OP_F8C400 ()
2031{
2e35551c
JL		 2032 int z, n, c;
2033
2034 c = State.regs[REG_D0 + ((insn & 0x300) >> 8)] & 1;
2035 State.regs[REG_D0 + ((insn & 0x300) >> 8)] >>= (insn & 0xff);
2036 z = (State.regs[REG_D0 + ((insn & 0x3) >> 8)] == 0);
b7b89deb 2037 n = (State.regs[REG_D0 + ((insn & 0x3) >> 8)] & 0x80000000) != 0;
2e35551c
JL		 2038 PSW &= ~(PSW_Z | PSW_N | PSW_C);
2039 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
05ccbdfd
JL		 2040}
2041
2e35551c 2042/* asl dm, dn */
05ccbdfd
JL		 2043void OP_F290 ()
2044{
707641f6
JL		 2045 int n, z;
2046
2047 State.regs[REG_D0 + (insn & 0x3)]
2048 <<= State.regs[REG_D0 + ((insn & 0xc) >> 2)];
2049 z = (State.regs[REG_D0 + (insn & 0x3)] == 0);
b7b89deb 2050 n = (State.regs[REG_D0 + (insn & 0x3)] & 0x80000000) != 0;
707641f6
JL		 2051 PSW &= ~(PSW_Z | PSW_N);
2052 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
05ccbdfd
JL		 2053}
2054
2e35551c 2055/* asl imm8, dn */
05ccbdfd
JL		 2056void OP_F8C000 ()
2057{
2e35551c
JL		 2058 int n, z;
2059
2060 State.regs[REG_D0 + ((insn & 0x300) >> 8)] <<= (insn & 0xff);
2061 z = (State.regs[REG_D0 + ((insn & 0x300) >> 8)] == 0);
b7b89deb 2062 n = (State.regs[REG_D0 + ((insn & 0x300) >> 8)] & 0x80000000) != 0;
2e35551c
JL		 2063 PSW &= ~(PSW_Z | PSW_N);
2064 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
05ccbdfd
JL		 2065}
2066
707641f6 2067/* asl2 dn */
05ccbdfd
JL		 2068void OP_54 ()
2069{
707641f6
JL		 2070 int n, z;
2071
2072 State.regs[REG_D0 + (insn & 0x3)] <<= 2;
2073 z = (State.regs[REG_D0 + (insn & 0x3)] == 0);
b7b89deb 2074 n = (State.regs[REG_D0 + (insn & 0x3)] & 0x80000000) != 0;
707641f6
JL		 2075 PSW &= ~(PSW_Z | PSW_N);
2076 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
05ccbdfd
JL		 2077}
2078
707641f6 2079/* ror dn */
05ccbdfd
JL		 2080void OP_F284 ()
2081{
707641f6
JL		 2082 unsigned long value;
2083 int c,n,z;
2084
2085 value = State.regs[REG_D0 + (insn & 0x3)];
2086 if (value & 0x1)
2087 c = 1;
2088
2089 value >>= 1;
2090 value |= ((PSW & PSW_C) != 0) ? 0x80000000 : 0;
2091 State.regs[REG_D0 + (insn & 0x3)] = value;
2092 z = (value == 0);
b7b89deb 2093 n = (value & 0x80000000) != 0;
707641f6
JL		 2094 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
2095 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
05ccbdfd
JL		 2096}
2097
707641f6 2098/* rol dn */
05ccbdfd
JL		 2099void OP_F280 ()
2100{
707641f6
JL		 2101 unsigned long value;
2102 int c,n,z;
2103
2104 value = State.regs[REG_D0 + (insn & 0x3)];
2105 if (value & 0x80000000)
2106 c = 1;
2107
2108 value <<= 1;
2109 value |= ((PSW & PSW_C) != 0);
2110 State.regs[REG_D0 + (insn & 0x3)] = value;
2111 z = (value == 0);
b7b89deb 2112 n = (value & 0x80000000) != 0;
707641f6
JL		 2113 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
2114 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
05ccbdfd
JL		 2115}
2116
f5f13c1d 2117/* beq label:8 */
05ccbdfd
JL		 2118void OP_C800 ()
2119{
73e65298
JL		 2120 /* The dispatching code will add 2 after we return, so
2121 we subtract two here to make things right. */
2122 if (PSW & PSW_Z)
2123 State.pc += SEXT8 (insn & 0xff) - 2;
05ccbdfd
JL		 2124}
2125
f5f13c1d 2126/* bne label:8 */
05ccbdfd
JL		 2127void OP_C900 ()
2128{
73e65298
JL		 2129 /* The dispatching code will add 2 after we return, so
2130 we subtract two here to make things right. */
2131 if (!(PSW & PSW_Z))
2132 State.pc += SEXT8 (insn & 0xff) - 2;
05ccbdfd
JL		 2133}
2134
f5f13c1d 2135/* bgt label:8 */
05ccbdfd
JL		 2136void OP_C100 ()
2137{
f5f13c1d
JL		 2138 /* The dispatching code will add 2 after we return, so
2139 we subtract two here to make things right. */
2140 if (!((PSW & PSW_Z)
2141 || (((PSW & PSW_N) != 0) ^ (PSW & PSW_V) != 0)))
2142 State.pc += SEXT8 (insn & 0xff) - 2;
05ccbdfd
JL		 2143}
2144
f5f13c1d 2145/* bge label:8 */
05ccbdfd
JL		 2146void OP_C200 ()
2147{
f5f13c1d
JL		 2148 /* The dispatching code will add 2 after we return, so
2149 we subtract two here to make things right. */
2150 if (!(((PSW & PSW_N) != 0) ^ (PSW & PSW_V) != 0))
2151 State.pc += SEXT8 (insn & 0xff) - 2;
05ccbdfd
JL		 2152}
2153
f5f13c1d 2154/* ble label:8 */
05ccbdfd
JL		 2155void OP_C300 ()
2156{
f5f13c1d
JL		 2157 /* The dispatching code will add 2 after we return, so
2158 we subtract two here to make things right. */
2159 if ((PSW & PSW_Z)
2160 || (((PSW & PSW_N) != 0) ^ (PSW & PSW_V) != 0))
2161 State.pc += SEXT8 (insn & 0xff) - 2;
05ccbdfd
JL		 2162}
2163
f5f13c1d 2164/* blt label:8 */
05ccbdfd
JL		 2165void OP_C000 ()
2166{
f5f13c1d
JL		 2167 /* The dispatching code will add 2 after we return, so
2168 we subtract two here to make things right. */
2169 if (((PSW & PSW_N) != 0) ^ (PSW & PSW_V) != 0)
2170 State.pc += SEXT8 (insn & 0xff) - 2;
05ccbdfd
JL		 2171}
2172
f5f13c1d 2173/* bhi label:8 */
05ccbdfd
JL		 2174void OP_C500 ()
2175{
f5f13c1d
JL		 2176 /* The dispatching code will add 2 after we return, so
2177 we subtract two here to make things right. */
2178 if (!(((PSW & PSW_C) != 0) || (PSW & PSW_Z) != 0))
2179 State.pc += SEXT8 (insn & 0xff) - 2;
05ccbdfd
JL		 2180}
2181
f5f13c1d 2182/* bcc label:8 */
05ccbdfd
JL		 2183void OP_C600 ()
2184{
f5f13c1d
JL		 2185 /* The dispatching code will add 2 after we return, so
2186 we subtract two here to make things right. */
2187 if (!(PSW & PSW_C))
2188 State.pc += SEXT8 (insn & 0xff) - 2;
05ccbdfd
JL		 2189}
2190
f5f13c1d 2191/* bls label:8 */
05ccbdfd
JL		 2192void OP_C700 ()
2193{
f5f13c1d
JL		 2194 /* The dispatching code will add 2 after we return, so
2195 we subtract two here to make things right. */
2196 if (((PSW & PSW_C) != 0) || (PSW & PSW_Z) != 0)
2197 State.pc += SEXT8 (insn & 0xff) - 2;
05ccbdfd
JL		 2198}
2199
f5f13c1d 2200/* bcs label:8 */
05ccbdfd
JL		 2201void OP_C400 ()
2202{
f5f13c1d
JL		 2203 /* The dispatching code will add 2 after we return, so
2204 we subtract two here to make things right. */
2205 if (PSW & PSW_C)
2206 State.pc += SEXT8 (insn & 0xff) - 2;
05ccbdfd
JL		 2207}
2208
f5f13c1d 2209/* bvc label:8 */
05ccbdfd
JL		 2210void OP_F8E800 ()
2211{
f5f13c1d
JL		 2212 /* The dispatching code will add 3 after we return, so
2213 we subtract two here to make things right. */
2214 if (!(PSW & PSW_V))
2215 State.pc += SEXT8 (insn & 0xff) - 3;
05ccbdfd
JL		 2216}
2217
f5f13c1d 2218/* bvs label:8 */
05ccbdfd
JL		 2219void OP_F8E900 ()
2220{
f5f13c1d
JL		 2221 /* The dispatching code will add 3 after we return, so
2222 we subtract two here to make things right. */
2223 if (PSW & PSW_V)
2224 State.pc += SEXT8 (insn & 0xff) - 3;
05ccbdfd
JL		 2225}
2226
f5f13c1d 2227/* bnc label:8 */
05ccbdfd
JL		 2228void OP_F8EA00 ()
2229{
f5f13c1d
JL		 2230 /* The dispatching code will add 3 after we return, so
2231 we subtract two here to make things right. */
2232 if (!(PSW & PSW_N))
2233 State.pc += SEXT8 (insn & 0xff) - 3;
05ccbdfd
JL		 2234}
2235
f5f13c1d 2236/* bns label:8 */
05ccbdfd
JL		 2237void OP_F8EB00 ()
2238{
f5f13c1d
JL		 2239 /* The dispatching code will add 3 after we return, so
2240 we subtract two here to make things right. */
2241 if (PSW & PSW_N)
2242 State.pc += SEXT8 (insn & 0xff) - 3;
05ccbdfd
JL		 2243}
2244
f5f13c1d 2245/* bra label:8 */
05ccbdfd
JL		 2246void OP_CA00 ()
2247{
f5f13c1d
JL		 2248 /* The dispatching code will add 2 after we return, so
2249 we subtract two here to make things right. */
2250 State.pc += SEXT8 (insn & 0xff) - 2;
05ccbdfd
JL		 2251}
2252
2253/* leq */
2254void OP_D8 ()
2255{
f5f13c1d 2256 abort ();
05ccbdfd
JL		 2257}
2258
2259/* lne */
2260void OP_D9 ()
2261{
f5f13c1d 2262 abort ();
05ccbdfd
JL		 2263}
2264
2265/* lgt */
2266void OP_D1 ()
2267{
f5f13c1d 2268 abort ();
05ccbdfd
JL		 2269}
2270
2271/* lge */
2272void OP_D2 ()
2273{
f5f13c1d 2274 abort ();
05ccbdfd
JL		 2275}
2276
2277/* lle */
2278void OP_D3 ()
2279{
f5f13c1d 2280 abort ();
05ccbdfd
JL		 2281}
2282
2283/* llt */
2284void OP_D0 ()
2285{
f5f13c1d 2286 abort ();
05ccbdfd
JL		 2287}
2288
2289/* lhi */
2290void OP_D5 ()
2291{
f5f13c1d 2292 abort ();
05ccbdfd
JL		 2293}
2294
2295/* lcc */
2296void OP_D6 ()
2297{
f5f13c1d 2298 abort ();
05ccbdfd
JL		 2299}
2300
2301/* lls */
2302void OP_D7 ()
2303{
f5f13c1d 2304 abort ();
05ccbdfd
JL		 2305}
2306
2307/* lcs */
2308void OP_D4 ()
2309{
f5f13c1d 2310 abort ();
05ccbdfd
JL		 2311}
2312
2313/* lra */
2314void OP_DA ()
2315{
f5f13c1d 2316 abort ();
05ccbdfd
JL		 2317}
2318
2319/* setlb */
2320void OP_DB ()
2321{
f5f13c1d 2322 abort ();
05ccbdfd
JL		 2323}
2324
707641f6 2325/* jmp (an) */
05ccbdfd
JL		 2326void OP_F0F4 ()
2327{
92284aaa 2328 State.pc = State.regs[REG_A0 + (insn & 0x3)] - 2;
05ccbdfd
JL		 2329}
2330
707641f6 2331/* jmp label:16 */
05ccbdfd
JL		 2332void OP_CC0000 ()
2333{
92284aaa 2334 State.pc += SEXT16 (insn & 0xffff) - 3;
05ccbdfd
JL		 2335}
2336
707641f6 2337/* jmp label:32 */
05ccbdfd
JL		 2338void OP_DC000000 ()
2339{
92284aaa 2340 State.pc += (((insn & 0xffffff) << 8) | extension) - 5;
05ccbdfd
JL		 2341}
2342
707641f6 2343/* call label:16,reg_list,imm8 */
05ccbdfd
JL		 2344void OP_CD000000 ()
2345{
707641f6
JL		 2346 unsigned int next_pc, sp, adjust;
2347 unsigned long mask;
2348
2349 sp = State.regs[REG_SP];
2350 next_pc = State.pc + 2;
2351 State.mem[sp] = next_pc & 0xff;
3bb3fe44
JL		 2352 State.mem[sp+1] = (next_pc & 0xff00) >> 8;
2353 State.mem[sp+2] = (next_pc & 0xff0000) >> 16;
2354 State.mem[sp+3] = (next_pc & 0xff000000) >> 24;
707641f6
JL		 2355
2356 mask = insn & 0xff;
2357
2358 adjust = 0;
2359 if (mask & 0x80)
2360 {
2361 adjust -= 4;
2362 State.regs[REG_D0 + 2] = load_mem (sp + adjust, 4);
2363 }
2364
2365 if (mask & 0x40)
2366 {
2367 adjust -= 4;
2368 State.regs[REG_D0 + 3] = load_mem (sp + adjust, 4);
2369 }
2370
2371 if (mask & 0x20)
2372 {
2373 adjust -= 4;
2374 State.regs[REG_A0 + 2] = load_mem (sp + adjust, 4);
2375 }
2376
2377 if (mask & 0x10)
2378 {
2379 adjust -= 4;
2380 State.regs[REG_A0 + 3] = load_mem (sp + adjust, 4);
2381 }
2382
2383 if (mask & 0x8)
2384 {
2385 adjust -= 4;
2386 State.regs[REG_D0] = load_mem (sp + adjust, 4);
2387 adjust -= 4;
2388 State.regs[REG_D0 + 1] = load_mem (sp + adjust, 4);
2389 adjust -= 4;
2390 State.regs[REG_A0] = load_mem (sp + adjust, 4);
2391 adjust -= 4;
2392 State.regs[REG_A0 + 1] = load_mem (sp + adjust, 4);
2393 adjust -= 4;
2394 State.regs[REG_MDR] = load_mem (sp + adjust, 4);
2395 adjust -= 4;
2396 State.regs[REG_LIR] = load_mem (sp + adjust, 4);
2397 adjust -= 4;
2398 State.regs[REG_LAR] = load_mem (sp + adjust, 4);
2399 adjust -= 4;
2400 }
2401
2402 /* And make sure to update the stack pointer. */
2403 State.regs[REG_SP] -= extension;
2404 State.regs[REG_MDR] = next_pc;
2405 State.pc += SEXT16 ((insn & 0xffff00) >> 8) - 5;
05ccbdfd
JL		 2406}
2407
707641f6 2408/* call label:32,reg_list,imm8*/
05ccbdfd
JL		 2409void OP_DD000000 ()
2410{
707641f6
JL		 2411 unsigned int next_pc, sp, adjust;
2412 unsigned long mask;
2413
2414 sp = State.regs[REG_SP];
2415 next_pc = State.pc + 2;
2416 State.mem[sp] = next_pc & 0xff;
3bb3fe44
JL		 2417 State.mem[sp+1] = (next_pc & 0xff00) >> 8;
2418 State.mem[sp+2] = (next_pc & 0xff0000) >> 16;
2419 State.mem[sp+3] = (next_pc & 0xff000000) >> 24;
707641f6
JL		 2420
2421 mask = (extension & 0xff00) >> 8;
2422
2423 adjust = 0;
2424 if (mask & 0x80)
2425 {
2426 adjust -= 4;
2427 State.regs[REG_D0 + 2] = load_mem (sp + adjust, 4);
2428 }
2429
2430 if (mask & 0x40)
2431 {
2432 adjust -= 4;
2433 State.regs[REG_D0 + 3] = load_mem (sp + adjust, 4);
2434 }
2435
2436 if (mask & 0x20)
2437 {
2438 adjust -= 4;
2439 State.regs[REG_A0 + 2] = load_mem (sp + adjust, 4);
2440 }
2441
2442 if (mask & 0x10)
2443 {
2444 adjust -= 4;
2445 State.regs[REG_A0 + 3] = load_mem (sp + adjust, 4);
2446 }
2447
2448 if (mask & 0x8)
2449 {
2450 adjust -= 4;
2451 State.regs[REG_D0] = load_mem (sp + adjust, 4);
2452 adjust -= 4;
2453 State.regs[REG_D0 + 1] = load_mem (sp + adjust, 4);
2454 adjust -= 4;
2455 State.regs[REG_A0] = load_mem (sp + adjust, 4);
2456 adjust -= 4;
2457 State.regs[REG_A0 + 1] = load_mem (sp + adjust, 4);
2458 adjust -= 4;
2459 State.regs[REG_MDR] = load_mem (sp + adjust, 4);
2460 adjust -= 4;
2461 State.regs[REG_LIR] = load_mem (sp + adjust, 4);
2462 adjust -= 4;
2463 State.regs[REG_LAR] = load_mem (sp + adjust, 4);
2464 adjust -= 4;
2465 }
2466
2467 /* And make sure to update the stack pointer. */
2468 State.regs[REG_SP] -= (extension & 0xff);
2469 State.regs[REG_MDR] = next_pc;
2470 State.pc += (((insn & 0xffffff) << 8) | ((extension & 0xff0000) >> 16)) - 7;
05ccbdfd
JL		 2471}
2472
707641f6 2473/* calls (an) */
05ccbdfd
JL		 2474void OP_F0F0 ()
2475{
92284aaa
JL		 2476 unsigned int next_pc, sp;
2477
2478 sp = State.regs[REG_SP];
2479 next_pc = State.pc + 2;
2480 State.mem[sp] = next_pc & 0xff;
3bb3fe44
JL		 2481 State.mem[sp+1] = (next_pc & 0xff00) >> 8;
2482 State.mem[sp+2] = (next_pc & 0xff0000) >> 16;
2483 State.mem[sp+3] = (next_pc & 0xff000000) >> 24;
92284aaa
JL		 2484 State.regs[REG_MDR] = next_pc;
2485 State.pc = State.regs[REG_A0 + (insn & 0x3)] - 2;
05ccbdfd
JL		 2486}
2487
707641f6 2488/* calls label:16 */
05ccbdfd
JL		 2489void OP_FAFF0000 ()
2490{
92284aaa
JL		 2491 unsigned int next_pc, sp;
2492
2493 sp = State.regs[REG_SP];
2494 next_pc = State.pc + 4;
2495 State.mem[sp] = next_pc & 0xff;
3bb3fe44
JL		 2496 State.mem[sp+1] = (next_pc & 0xff00) >> 8;
2497 State.mem[sp+2] = (next_pc & 0xff0000) >> 16;
2498 State.mem[sp+3] = (next_pc & 0xff000000) >> 24;
92284aaa
JL		 2499 State.regs[REG_MDR] = next_pc;
2500 State.pc += SEXT16 (insn & 0xffff) - 4;
05ccbdfd
JL		 2501}
2502
707641f6 2503/* calls label:32 */
05ccbdfd
JL		 2504void OP_FCFF0000 ()
2505{
92284aaa
JL		 2506 unsigned int next_pc, sp;
2507
2508 sp = State.regs[REG_SP];
2509 next_pc = State.pc + 6;
2510 State.mem[sp] = next_pc & 0xff;
3bb3fe44
JL		 2511 State.mem[sp+1] = (next_pc & 0xff00) >> 8;
2512 State.mem[sp+2] = (next_pc & 0xff0000) >> 16;
2513 State.mem[sp+3] = (next_pc & 0xff000000) >> 24;
92284aaa
JL		 2514 State.regs[REG_MDR] = next_pc;
2515 State.pc += (((insn & 0xffff) << 16) | extension) - 6;
05ccbdfd
JL		 2516}
2517
de0dce7c 2518/* ret reg_list, imm8 */
05ccbdfd
JL		 2519void OP_DF0000 ()
2520{
707641f6
JL		 2521 unsigned int sp;
2522 unsigned long mask;
2523
2524 State.regs[REG_SP] += insn & 0xff;
2525 State.pc = State.regs[REG_MDR] - 3;
2526 sp = State.regs[REG_SP];
2527
2528 mask = (insn & 0xff00) >> 8;
2529
2530 if (mask & 0x8)
2531 {
2532 sp += 4;
2533 State.regs[REG_LAR] = load_mem (sp, 4);
2534 sp += 4;
2535 State.regs[REG_LIR] = load_mem (sp, 4);
2536 sp += 4;
2537 State.regs[REG_MDR] = load_mem (sp, 4);
2538 sp += 4;
2539 State.regs[REG_A0 + 1] = load_mem (sp, 4);
2540 sp += 4;
2541 State.regs[REG_A0] = load_mem (sp, 4);
2542 sp += 4;
2543 State.regs[REG_D0 + 1] = load_mem (sp, 4);
2544 sp += 4;
2545 State.regs[REG_D0] = load_mem (sp, 4);
2546 sp += 4;
2547 }
2548
2549 if (mask & 0x10)
2550 {
2551 State.regs[REG_A0 + 3] = load_mem (sp, 4);
2552 sp += 4;
2553 }
2554
2555 if (mask & 0x20)
2556 {
2557 State.regs[REG_A0 + 2] = load_mem (sp, 4);
2558 sp += 4;
2559 }
2560
2561 if (mask & 0x40)
2562 {
2563 State.regs[REG_D0 + 3] = load_mem (sp, 4);
2564 sp += 4;
2565 }
2566
2567 if (mask & 0x80)
2568 {
2569 State.regs[REG_D0 + 2] = load_mem (sp, 4);
2570 sp += 4;
2571 }
05ccbdfd
JL		 2572}
2573
707641f6 2574/* retf reg_list,imm8 */
05ccbdfd
JL		 2575void OP_DE0000 ()
2576{
707641f6
JL		 2577 unsigned int sp;
2578 unsigned long mask;
2579
2580 State.regs[REG_SP] += insn & 0xff;
2581 State.pc = (State.mem[sp] | (State.mem[sp+1] << 8)
2582 | (State.mem[sp+2] << 16) | (State.mem[sp+3] << 24));
2583 State.pc -= 3;
2584
2585 sp = State.regs[REG_SP];
2586
2587 mask = (insn & 0xff00) >> 8;
2588
2589 if (mask & 0x8)
2590 {
2591 sp += 4;
2592 State.regs[REG_LAR] = load_mem (sp, 4);
2593 sp += 4;
2594 State.regs[REG_LIR] = load_mem (sp, 4);
2595 sp += 4;
2596 State.regs[REG_MDR] = load_mem (sp, 4);
2597 sp += 4;
2598 State.regs[REG_A0 + 1] = load_mem (sp, 4);
2599 sp += 4;
2600 State.regs[REG_A0] = load_mem (sp, 4);
2601 sp += 4;
2602 State.regs[REG_D0 + 1] = load_mem (sp, 4);
2603 sp += 4;
2604 State.regs[REG_D0] = load_mem (sp, 4);
2605 sp += 4;
2606 }
2607
2608 if (mask & 0x10)
2609 {
2610 State.regs[REG_A0 + 3] = load_mem (sp, 4);
2611 sp += 4;
2612 }
2613
2614 if (mask & 0x20)
2615 {
2616 State.regs[REG_A0 + 2] = load_mem (sp, 4);
2617 sp += 4;
2618 }
2619
2620 if (mask & 0x40)
2621 {
2622 State.regs[REG_D0 + 3] = load_mem (sp, 4);
2623 sp += 4;
2624 }
2625
2626 if (mask & 0x80)
2627 {
2628 State.regs[REG_D0 + 2] = load_mem (sp, 4);
2629 sp += 4;
2630 }
05ccbdfd
JL		 2631}
2632
2633/* rets */
2634void OP_F0FC ()
2635{
92284aaa
JL		 2636 unsigned int sp;
2637
2638 sp = State.regs[REG_SP];
2639 State.pc = (State.mem[sp] | (State.mem[sp+1] << 8)
2640 | (State.mem[sp+2] << 16) | (State.mem[sp+3] << 24));
2641 State.pc -= 2;
05ccbdfd
JL		 2642}
2643
2644/* rti */
2645void OP_F0FD ()
2646{
f5f13c1d 2647 abort ();
05ccbdfd
JL		 2648}
2649
2650/* trap */
2651void OP_F0FE ()
2652{
3bb3fe44
JL		 2653 /* We use this for simulated system calls; we may need to change
2654 it to a reserved instruction if we conflict with uses at
2655 Matsushita. */
2656 int save_errno = errno;
2657 errno = 0;
2658
2659/* Registers passed to trap 0 */
2660
2661/* Function number. */
2662#define FUNC (load_mem (State.regs[REG_SP] + 4, 4))
2663
2664/* Parameters. */
2665#define PARM1 (load_mem (State.regs[REG_SP] + 8, 4))
2666#define PARM2 (load_mem (State.regs[REG_SP] + 12, 4))
2667#define PARM3 (load_mem (State.regs[REG_SP] + 16, 4))
2668
2669/* Registers set by trap 0 */
2670
2671#define RETVAL State.regs[0] /* return value */
2672#define RETERR State.regs[1] /* return error code */
2673
2674/* Turn a pointer in a register into a pointer into real memory. */
2675
2676#define MEMPTR(x) (State.mem + x)
2677
2678 switch (FUNC)
2679 {
2680#if !defined(__GO32__) && !defined(_WIN32)
2681 case SYS_fork:
2682 RETVAL = fork ();
2683 break;
2684 case SYS_execve:
2685 RETVAL = execve (MEMPTR (PARM1), (char **) MEMPTR (PARM2),
2686 (char **)MEMPTR (PARM3));
2687 break;
2688 case SYS_execv:
2689 RETVAL = execve (MEMPTR (PARM1), (char **) MEMPTR (PARM2), NULL);
2690 break;
2691#endif
2692
2693 case SYS_read:
2694 RETVAL = mn10300_callback->read (mn10300_callback, PARM1,
2695 MEMPTR (PARM2), PARM3);
2696 break;
2697 case SYS_write:
2698 if (PARM1 == 1)
2699 RETVAL = (int)mn10300_callback->write_stdout (mn10300_callback,
2700 MEMPTR (PARM2), PARM3);
2701 else
2702 RETVAL = (int)mn10300_callback->write (mn10300_callback, PARM1,
2703 MEMPTR (PARM2), PARM3);
2704 break;
2705 case SYS_lseek:
2706 RETVAL = mn10300_callback->lseek (mn10300_callback, PARM1, PARM2, PARM3);
2707 break;
2708 case SYS_close:
2709 RETVAL = mn10300_callback->close (mn10300_callback, PARM1);
2710 break;
2711 case SYS_open:
2712 RETVAL = mn10300_callback->open (mn10300_callback, MEMPTR (PARM1), PARM2);
2713 break;
2714 case SYS_exit:
2715 /* EXIT - caller can look in PARM1 to work out the
2716 reason */
2717 if (PARM1 == 0xdead || PARM1 == 0x1)
2718 State.exception = SIGABRT;
2719 else
2720 State.exception = SIGQUIT;
2721 break;
2722
2723 case SYS_stat: /* added at hmsi */
2724 /* stat system call */
2725 {
2726 struct stat host_stat;
2727 reg_t buf;
2728
2729 RETVAL = stat (MEMPTR (PARM1), &host_stat);
2730
2731 buf = PARM2;
2732
2733 /* Just wild-assed guesses. */
2734 store_mem (buf, 2, host_stat.st_dev);
2735 store_mem (buf + 2, 2, host_stat.st_ino);
2736 store_mem (buf + 4, 4, host_stat.st_mode);
2737 store_mem (buf + 8, 2, host_stat.st_nlink);
2738 store_mem (buf + 10, 2, host_stat.st_uid);
2739 store_mem (buf + 12, 2, host_stat.st_gid);
2740 store_mem (buf + 14, 2, host_stat.st_rdev);
2741 store_mem (buf + 16, 4, host_stat.st_size);
2742 store_mem (buf + 20, 4, host_stat.st_atime);
2743 store_mem (buf + 28, 4, host_stat.st_mtime);
2744 store_mem (buf + 36, 4, host_stat.st_ctime);
2745 }
2746 break;
2747
2748 case SYS_chown:
2749 RETVAL = chown (MEMPTR (PARM1), PARM2, PARM3);
2750 break;
2751 case SYS_chmod:
2752 RETVAL = chmod (MEMPTR (PARM1), PARM2);
2753 break;
2754 case SYS_time:
2755 RETVAL = time (MEMPTR (PARM1));
2756 break;
2757 case SYS_times:
2758 {
2759 struct tms tms;
2760 RETVAL = times (&tms);
2761 store_mem (PARM1, 4, tms.tms_utime);
2762 store_mem (PARM1 + 4, 4, tms.tms_stime);
2763 store_mem (PARM1 + 8, 4, tms.tms_cutime);
2764 store_mem (PARM1 + 12, 4, tms.tms_cstime);
2765 break;
2766 }
2767 case SYS_gettimeofday:
2768 {
2769 struct timeval t;
2770 struct timezone tz;
2771 RETVAL = gettimeofday (&t, &tz);
2772 store_mem (PARM1, 4, t.tv_sec);
2773 store_mem (PARM1 + 4, 4, t.tv_usec);
2774 store_mem (PARM2, 4, tz.tz_minuteswest);
2775 store_mem (PARM2 + 4, 4, tz.tz_dsttime);
2776 break;
2777 }
2778 case SYS_utime:
2779 /* Cast the second argument to void *, to avoid type mismatch
2780 if a prototype is present. */
2781 RETVAL = utime (MEMPTR (PARM1), (void *) MEMPTR (PARM2));
2782 break;
2783 default:
2784 abort ();
2785 }
2786 RETERR = errno;
2787 errno = save_errno;
05ccbdfd
JL		 2788}
2789
2790/* rtm */
2791void OP_F0FF ()
2792{
f5f13c1d 2793 abort ();
05ccbdfd
JL		 2794}
2795
2796/* nop */
2797void OP_CB ()
2798{
2799}
2800
2801/* putx */
2802void OP_F500 ()
2803{
2804}
2805
2806/* getx */
2807void OP_F6F0 ()
2808{
2809}
2810
2811/* mulq */
2812void OP_F600 ()
2813{
2814}
2815
2816/* mulq */
2817void OP_F90000 ()
2818{
2819}
2820
2821/* mulq */
2822void OP_FB000000 ()
2823{
2824}
2825
2826/* mulq */
2827void OP_FD000000 ()
2828{
2829}
2830
2831/* mulqu */
2832void OP_F610 ()
2833{
2834}
2835
2836/* mulqu */
2837void OP_F91400 ()
2838{
2839}
2840
2841/* mulqu */
2842void OP_FB140000 ()
2843{
2844}
2845
2846/* mulqu */
2847void OP_FD140000 ()
2848{
2849}
2850
2851/* sat16 */
2852void OP_F640 ()
2853{
2854}
2855
2856/* sat24 */
2857void OP_F650 ()
2858{
2859}
2860
2861/* bsch */
2862void OP_F670 ()
2863{
2864}
A mirror of the official binutils-gdb repository