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Introduce common-debug.h
[thirdparty/binutils-gdb.git] / sim / msp430 / msp430-sim.c
CommitLineData
3346cfda
NC		 1/* Simulator for TI MSP430 and MSP430X
2
ecd75fc8 3 Copyright (C) 2013-2014 Free Software Foundation, Inc.
3346cfda
NC		 4 Contributed by Red Hat.
5 Based on sim/bfin/bfin-sim.c which was contributed by Analog Devices, Inc.
6
7 This file is part of simulators.
8
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 3 of the License, or
12 (at your option) any later version.
13
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
18
19 You should have received a copy of the GNU General Public License
20 along with this program. If not, see <http://www.gnu.org/licenses/>. */
21
22#include "config.h"
23#include <stdio.h>
24#include <stdlib.h>
25#include <string.h>
26#include <inttypes.h>
27#include <assert.h>
28#include "bfd.h"
29#include "opcode/msp430-decode.h"
30#include "sim-main.h"
31#include "dis-asm.h"
32#include "targ-vals.h"
33
34static int
35loader_write_mem (SIM_DESC sd,
36 SIM_ADDR taddr,
37 const unsigned char *buf,
38 int bytes)
39{
40 SIM_CPU *cpu = MSP430_CPU (sd);
41 return sim_core_write_buffer (sd, cpu, write_map, buf, taddr, bytes);
42}
43
44static sim_cia
45msp430_pc_fetch (SIM_CPU *cpu)
46{
47 return cpu->state.regs[0];
48}
49
50static void
51msp430_pc_store (SIM_CPU *cpu, sim_cia newpc)
52{
53 cpu->state.regs[0] = newpc;
54}
55
56static long
57lookup_symbol (SIM_DESC sd, const char *name)
58{
59 struct bfd *abfd = STATE_PROG_BFD (sd);
60 asymbol **symbol_table = STATE_SYMBOL_TABLE (sd);
61 long number_of_symbols = STATE_NUM_SYMBOLS (sd);
62 long i;
63
64 if (symbol_table == NULL)
65 {
66 long storage_needed;
67
68 storage_needed = bfd_get_symtab_upper_bound (abfd);
69 if (storage_needed <= 0)
70 return -1;
71
72 STATE_SYMBOL_TABLE (sd) = symbol_table = xmalloc (storage_needed);
73 STATE_NUM_SYMBOLS (sd) = number_of_symbols =
74 bfd_canonicalize_symtab (abfd, symbol_table);
75 }
76
77 for (i = 0; i < number_of_symbols; i++)
78 if (strcmp (symbol_table[i]->name, name) == 0)
79 {
80 long val = symbol_table[i]->section->vma + symbol_table[i]->value;
81 return val;
82 }
83 return -1;
84}
85
86static int
87msp430_reg_fetch (SIM_CPU *cpu, int regno, unsigned char *buf, int len)
88{
89 if (0 <= regno && regno < 16)
90 {
91 if (len == 2)
92 {
93 int val = cpu->state.regs[regno];
94 buf[0] = val & 0xff;
95 buf[1] = (val >> 8) & 0xff;
96 return 0;
97 }
98 else if (len == 4)
99 {
100 int val = cpu->state.regs[regno];
101 buf[0] = val & 0xff;
102 buf[1] = (val >> 8) & 0xff;
103 buf[2] = (val >> 16) & 0x0f; /* Registers are only 20 bits wide. */
104 buf[3] = 0;
105 return 0;
106 }
107 else
108 return -1;
109 }
110 else
111 return -1;
112}
113
114static int
115msp430_reg_store (SIM_CPU *cpu, int regno, unsigned char *buf, int len)
116{
117 if (0 <= regno && regno < 16)
118 {
119 if (len == 2)
120 {
121 cpu->state.regs[regno] = (buf[1] << 8) | buf[0];
122 return len;
123 }
124
125 if (len == 4)
126 {
127 cpu->state.regs[regno] = ((buf[2] << 16) & 0xf0000)
128 | (buf[1] << 8) | buf[0];
129 return len;
130 }
131 }
132
133 return -1;
134}
135
136static inline void
137msp430_initialize_cpu (SIM_DESC sd, SIM_CPU *cpu)
138{
139 memset (&cpu->state, 0, sizeof (cpu->state));
140}
141
142SIM_DESC
143sim_open (SIM_OPEN_KIND kind,
144 struct host_callback_struct *callback,
145 struct bfd *abfd,
146 char **argv)
147{
148 SIM_DESC sd = sim_state_alloc (kind, callback);
149 char c;
150 struct bfd *prog_bfd;
151
152 /* Initialise the simulator. */
153
154 if (sim_cpu_alloc_all (sd, 1, /*cgen_cpu_max_extra_bytes ()*/0) != SIM_RC_OK)
155 {
156 sim_state_free (sd);
157 return 0;
158 }
159
160 if (sim_pre_argv_init (sd, argv[0]) != SIM_RC_OK)
161 {
162 sim_state_free (sd);
163 return 0;
164 }
165
166 if (sim_parse_args (sd, argv) != SIM_RC_OK)
167 {
168 sim_state_free (sd);
169 return 0;
170 }
171
172 CPU_PC_FETCH (MSP430_CPU (sd)) = msp430_pc_fetch;
173 CPU_PC_STORE (MSP430_CPU (sd)) = msp430_pc_store;
174 CPU_REG_FETCH (MSP430_CPU (sd)) = msp430_reg_fetch;
175 CPU_REG_STORE (MSP430_CPU (sd)) = msp430_reg_store;
176
177 /* Allocate memory if none specified by user. */
8969934d
NC		 178 if (sim_core_read_buffer (sd, MSP430_CPU (sd), read_map, &c, 0x130, 1) == 0)
179 sim_do_commandf (sd, "memory-region 0,0x20");
3346cfda 180 if (sim_core_read_buffer (sd, MSP430_CPU (sd), read_map, &c, 0x200, 1) == 0)
8969934d 181 sim_do_commandf (sd, "memory-region 0x200,0xffe00");
3346cfda
NC		 182 if (sim_core_read_buffer (sd, MSP430_CPU (sd), read_map, &c, 0xfffe, 1) == 0)
183 sim_do_commandf (sd, "memory-region 0xfffe,2");
184 if (sim_core_read_buffer (sd, MSP430_CPU (sd), read_map, &c, 0x10000, 1) == 0)
185 sim_do_commandf (sd, "memory-region 0x10000,0x100000");
186
187 /* Check for/establish the a reference program image. */
188 if (sim_analyze_program (sd,
189 (STATE_PROG_ARGV (sd) != NULL
190 ? *STATE_PROG_ARGV (sd)
191 : NULL), abfd) != SIM_RC_OK)
192 {
193 sim_state_free (sd);
194 return 0;
195 }
196
197 prog_bfd = sim_load_file (sd, argv[0], callback,
198 "the program",
199 STATE_PROG_BFD (sd),
200 0 /* verbose */,
201 1 /* use LMA instead of VMA */,
202 loader_write_mem);
203 if (prog_bfd == NULL)
204 {
205 sim_state_free (sd);
206 return 0;
207 }
208
209 /* Establish any remaining configuration options. */
210 if (sim_config (sd) != SIM_RC_OK)
211 {
212 sim_state_free (sd);
213 return 0;
214 }
215
216 if (sim_post_argv_init (sd) != SIM_RC_OK)
217 {
218 sim_state_free (sd);
219 return 0;
220 }
221
222 /* CPU specific initialization. */
223 assert (MAX_NR_PROCESSORS == 1);
224 msp430_initialize_cpu (sd, MSP430_CPU (sd));
225
226 msp430_trace_init (STATE_PROG_BFD (sd));
227
228 MSP430_CPU (sd)->state.cio_breakpoint = lookup_symbol (sd, "C$$IO$$");
229 MSP430_CPU (sd)->state.cio_buffer = lookup_symbol (sd, "__CIOBUF__");
230 if (MSP430_CPU (sd)->state.cio_buffer == -1)
231 MSP430_CPU (sd)->state.cio_buffer = lookup_symbol (sd, "_CIOBUF_");
232
233 return sd;
234}
235
236void
237sim_close (SIM_DESC sd,
238 int quitting)
239{
240 free (STATE_SYMBOL_TABLE (sd));
241 sim_state_free (sd);
242}
243
244SIM_RC
245sim_create_inferior (SIM_DESC sd,
246 struct bfd *abfd,
247 char **argv,
248 char **env)
249{
250 unsigned char resetv[2];
251 int c;
252 int new_pc;
253
7b0278dc 254 /* Set the PC to the default reset vector if available. */
3346cfda 255 c = sim_core_read_buffer (sd, MSP430_CPU (sd), read_map, resetv, 0xfffe, 2);
3346cfda 256 new_pc = resetv[0] + 256 * resetv[1];
7b0278dc
MF		 257
258 /* If the reset vector isn't initialized, then use the ELF entry. */
259 if (abfd != NULL && !new_pc)
260 new_pc = bfd_get_start_address (abfd);
261
3346cfda
NC		 262 sim_pc_set (MSP430_CPU (sd), new_pc);
263 msp430_pc_store (MSP430_CPU (sd), new_pc);
264
265 return SIM_RC_OK;
266}
267
268typedef struct
269{
270 SIM_DESC sd;
271 int gb_addr;
272} Get_Byte_Local_Data;
273
274static int
275msp430_getbyte (void *vld)
276{
277 Get_Byte_Local_Data *ld = (Get_Byte_Local_Data *)vld;
278 char buf[1];
279 SIM_DESC sd = ld->sd;
280
281 sim_core_read_buffer (sd, MSP430_CPU (sd), read_map, buf, ld->gb_addr, 1);
282 ld->gb_addr ++;
283 return buf[0];
284}
285
286#define REG(N) MSP430_CPU (sd)->state.regs[(N)]
287#define PC REG(MSR_PC)
288#define SP REG(MSR_SP)
289#define SR REG(MSR_SR)
290
291static const char *
292register_names[] =
293{
294 "PC", "SP", "SR", "CG", "R4", "R5", "R6", "R7", "R8",
295 "R9", "R10", "R11", "R12", "R13", "R14", "R15"
296};
297
298static void
299trace_reg_put (SIM_DESC sd, int n, unsigned int v)
300{
301 if (TRACE_VPU_P (MSP430_CPU (sd)))
302 trace_generic (sd, MSP430_CPU (sd), TRACE_VPU_IDX,
303 "PUT: %#x -> %s", v, register_names [n]);
304 REG (n) = v;
305}
306
307static unsigned int
308trace_reg_get (SIM_DESC sd, int n)
309{
310 if (TRACE_VPU_P (MSP430_CPU (sd)))
311 trace_generic (sd, MSP430_CPU (sd), TRACE_VPU_IDX,
312 "GET: %s -> %#x", register_names [n], REG (n));
313 return REG (n);
314}
315
316#define REG_PUT(N,V) trace_reg_put (sd, N, V)
317#define REG_GET(N) trace_reg_get (sd, N)
318
8969934d
NC		 319/* Hardware multiply (and accumulate) support. */
320static enum { UNSIGN_32, SIGN_32, UNSIGN_MAC_32, SIGN_MAC_32 } hwmult_type;
321static unsigned32 hwmult_op1;
322static unsigned32 hwmult_op2;
323static unsigned32 hwmult_result;
324static signed32 hwmult_signed_result;
325static unsigned32 hwmult_accumulator;
326static signed32 hwmult_signed_accumulator;
327
328static enum { UNSIGN_64, SIGN_64 } hw32mult_type;
329static unsigned64 hw32mult_op1;
330static unsigned64 hw32mult_op2;
331static unsigned64 hw32mult_result;
332
333static unsigned int
334zero_ext (unsigned int v, unsigned int bits)
335{
336 v &= ((1 << bits) - 1);
337 return v;
338}
339
a7da346e
DD		 340static signed long long
341sign_ext (signed long long v, unsigned int bits)
8969934d 342{
a7da346e
DD		 343 signed long long sb = 1LL << (bits-1); /* Sign bit. */
344 signed long long mb = (1LL << (bits-1)) - 1LL; /* Mantissa bits. */
8969934d
NC		 345
346 if (v & sb)
347 v = v | ~mb;
348 else
349 v = v & mb;
350 return v;
351}
352
3346cfda
NC		 353static int
354get_op (SIM_DESC sd, MSP430_Opcode_Decoded *opc, int n)
355{
356 MSP430_Opcode_Operand *op = opc->op + n;
357 int rv;
358 int addr;
359 unsigned char buf[4];
360 int incval = 0;
361
362 switch (op->type)
363 {
364 case MSP430_Operand_Immediate:
365 rv = op->addend;
366 break;
367 case MSP430_Operand_Register:
368 rv = REG_GET (op->reg);
369 break;
370 case MSP430_Operand_Indirect:
371 case MSP430_Operand_Indirect_Postinc:
372 addr = op->addend;
373 if (op->reg != MSR_None)
374 {
375 int reg;
376 /* Index values are signed, but the sum is limited to 16
377 bits if the register < 64k, for MSP430 compatibility in
378 MSP430X chips. */
379 if (addr & 0x8000)
380 addr |= -1 << 16;
381 reg = REG_GET (op->reg);
382 addr += reg;
383 if (reg < 0x10000 && ! opc->ofs_430x)
384 addr &= 0xffff;
385 }
386 addr &= 0xfffff;
387 switch (opc->size)
388 {
389 case 8:
390 sim_core_read_buffer (sd, MSP430_CPU (sd), read_map, buf, addr, 1);
391 rv = buf[0];
392 break;
393 case 16:
394 sim_core_read_buffer (sd, MSP430_CPU (sd), read_map, buf, addr, 2);
395 rv = buf[0] | (buf[1] << 8);
396 break;
397 case 20:
398 case 32:
399 sim_core_read_buffer (sd, MSP430_CPU (sd), read_map, buf, addr, 4);
400 rv = buf[0] | (buf[1] << 8) | (buf[2] << 16) | (buf[3] << 24);
401 break;
402 default:
403 assert (! opc->size);
404 break;
405 }
406#if 0
407 /* Hack - MSP430X5438 serial port status register. */
408 if (addr == 0x5dd)
409 rv = 2;
410#endif
8969934d
NC		 411 if (addr >= 0x130 && addr <= 0x15B)
412 {
413 switch (addr)
414 {
415 case 0x13A:
aef392c4
NC		 416 switch (hwmult_type)
417 {
418 case UNSIGN_MAC_32:
419 case UNSIGN_32: rv = zero_ext (hwmult_result, 16); break;
420 case SIGN_MAC_32:
421 case SIGN_32: rv = sign_ext (hwmult_signed_result, 16); break;
422 }
8969934d
NC		 423 break;
424
425 case 0x13C:
426 switch (hwmult_type)
427 {
aef392c4 428 case UNSIGN_MAC_32:
8969934d
NC		 429 case UNSIGN_32:
430 rv = zero_ext (hwmult_result >> 16, 16);
431 break;
432
aef392c4 433 case SIGN_MAC_32:
8969934d
NC		 434 case SIGN_32:
435 rv = sign_ext (hwmult_signed_result >> 16, 16);
436 break;
437 }
438 break;
439
440 case 0x13E:
441 switch (hwmult_type)
442 {
443 case UNSIGN_32:
444 rv = 0;
445 break;
446 case SIGN_32:
447 rv = hwmult_signed_result < 0 ? -1 : 0;
448 break;
449 case UNSIGN_MAC_32:
450 rv = 0; /* FIXME: Should be carry of last accumulate. */
451 break;
452 case SIGN_MAC_32:
453 rv = hwmult_signed_accumulator < 0 ? -1 : 0;
454 break;
455 }
456 break;
457
458 case 0x154:
459 rv = zero_ext (hw32mult_result, 16);
460 break;
461
462 case 0x156:
463 rv = zero_ext (hw32mult_result >> 16, 16);
464 break;
465
466 case 0x158:
467 rv = zero_ext (hw32mult_result >> 32, 16);
468 break;
469
470 case 0x15A:
471 switch (hw32mult_type)
472 {
473 case UNSIGN_64: rv = zero_ext (hw32mult_result >> 48, 16); break;
474 case SIGN_64: rv = sign_ext (hw32mult_result >> 48, 16); break;
475 }
476 break;
477
478 default:
479 fprintf (stderr, "unimplemented HW MULT read!\n");
480 break;
481 }
482 }
483
3346cfda
NC		 484 if (TRACE_MEMORY_P (MSP430_CPU (sd)))
485 trace_generic (sd, MSP430_CPU (sd), TRACE_MEMORY_IDX,
486 "GET: [%#x].%d -> %#x", addr, opc->size, rv);
487 break;
488 default:
489 fprintf (stderr, "invalid operand %d type %d\n", n, op->type);
490 abort ();
491 }
492
493 switch (opc->size)
494 {
495 case 8:
496 rv &= 0xff;
497 incval = 1;
498 break;
499 case 16:
500 rv &= 0xffff;
501 incval = 2;
502 break;
503 case 20:
504 rv &= 0xfffff;
505 incval = 4;
506 break;
507 case 32:
508 rv &= 0xffffffff;
509 incval = 4;
510 break;
511 }
512
513 if (op->type == MSP430_Operand_Indirect_Postinc)
514 REG_PUT (op->reg, REG_GET (op->reg) + incval);
515
516 return rv;
517}
518
519static int
520put_op (SIM_DESC sd, MSP430_Opcode_Decoded *opc, int n, int val)
521{
522 MSP430_Opcode_Operand *op = opc->op + n;
523 int rv;
524 int addr;
525 unsigned char buf[4];
526 int incval = 0;
527
528 switch (opc->size)
529 {
530 case 8:
531 val &= 0xff;
532 break;
533 case 16:
534 val &= 0xffff;
535 break;
536 case 20:
537 val &= 0xfffff;
538 break;
539 case 32:
540 val &= 0xffffffff;
541 break;
542 }
543
544 switch (op->type)
545 {
546 case MSP430_Operand_Register:
547 REG (op->reg) = val;
548 REG_PUT (op->reg, val);
549 break;
550 case MSP430_Operand_Indirect:
551 case MSP430_Operand_Indirect_Postinc:
552 addr = op->addend;
553 if (op->reg != MSR_None)
554 {
555 int reg;
556 /* Index values are signed, but the sum is limited to 16
557 bits if the register < 64k, for MSP430 compatibility in
558 MSP430X chips. */
559 if (addr & 0x8000)
560 addr |= -1 << 16;
561 reg = REG_GET (op->reg);
562 addr += reg;
563 if (reg < 0x10000)
564 addr &= 0xffff;
565 }
566 addr &= 0xfffff;
567
568 if (TRACE_MEMORY_P (MSP430_CPU (sd)))
569 trace_generic (sd, MSP430_CPU (sd), TRACE_MEMORY_IDX,
570 "PUT: [%#x].%d <- %#x", addr, opc->size, val);
571#if 0
572 /* Hack - MSP430X5438 serial port transmit register. */
573 if (addr == 0x5ce)
574 putchar (val);
575#endif
8969934d
NC		 576 if (addr >= 0x130 && addr <= 0x15B)
577 {
578 signed int a,b;
579
580 /* Hardware Multiply emulation. */
581 assert (opc->size == 16);
582
583 switch (addr)
584 {
585 case 0x130: hwmult_op1 = val; hwmult_type = UNSIGN_32; break;
586 case 0x132: hwmult_op1 = val; hwmult_type = SIGN_32; break;
587 case 0x134: hwmult_op1 = val; hwmult_type = UNSIGN_MAC_32; break;
588 case 0x136: hwmult_op1 = val; hwmult_type = SIGN_MAC_32; break;
589
590 case 0x138: hwmult_op2 = val;
591 switch (hwmult_type)
592 {
593 case UNSIGN_32:
594 hwmult_result = hwmult_op1 * hwmult_op2;
595 hwmult_signed_result = (signed) hwmult_result;
596 hwmult_accumulator = hwmult_signed_accumulator = 0;
597 break;
598
599 case SIGN_32:
600 a = sign_ext (hwmult_op1, 16);
601 b = sign_ext (hwmult_op2, 16);
602 hwmult_signed_result = a * b;
603 hwmult_result = (unsigned) hwmult_signed_result;
604 hwmult_accumulator = hwmult_signed_accumulator = 0;
605 break;
606
607 case UNSIGN_MAC_32:
608 hwmult_accumulator += hwmult_op1 * hwmult_op2;
609 hwmult_signed_accumulator += hwmult_op1 * hwmult_op2;
aef392c4
NC		 610 hwmult_result = hwmult_accumulator;
611 hwmult_signed_result = hwmult_signed_accumulator;
8969934d
NC		 612 break;
613
614 case SIGN_MAC_32:
615 a = sign_ext (hwmult_op1, 16);
616 b = sign_ext (hwmult_op2, 16);
617 hwmult_accumulator += a * b;
618 hwmult_signed_accumulator += a * b;
aef392c4
NC		 619 hwmult_result = hwmult_accumulator;
620 hwmult_signed_result = hwmult_signed_accumulator;
8969934d
NC		 621 break;
622 }
623 break;
624
aef392c4
NC		 625 case 0x13a:
626 /* Copy into LOW result... */
627 switch (hwmult_type)
628 {
629 case UNSIGN_MAC_32:
630 case UNSIGN_32:
631 hwmult_accumulator = hwmult_result = zero_ext (val, 16);
632 hwmult_signed_accumulator = sign_ext (val, 16);
633 break;
634 case SIGN_MAC_32:
635 case SIGN_32:
636 hwmult_signed_accumulator = hwmult_result = sign_ext (val, 16);
637 hwmult_accumulator = zero_ext (val, 16);
638 break;
639 }
640 break;
641
8969934d
NC		 642 case 0x140: hw32mult_op1 = val; hw32mult_type = UNSIGN_64; break;
643 case 0x142: hw32mult_op1 = (hw32mult_op1 & 0xFFFF) | (val << 16); break;
644 case 0x144: hw32mult_op1 = val; hw32mult_type = SIGN_64; break;
645 case 0x146: hw32mult_op1 = (hw32mult_op1 & 0xFFFF) | (val << 16); break;
646 case 0x150: hw32mult_op2 = val; break;
647
648 case 0x152: hw32mult_op2 = (hw32mult_op2 & 0xFFFF) | (val << 16);
649 switch (hw32mult_type)
650 {
651 case UNSIGN_64:
652 hw32mult_result = hw32mult_op1 * hw32mult_op2;
653 break;
654 case SIGN_64:
655 hw32mult_result = sign_ext (hw32mult_op1, 32) * sign_ext (hw32mult_op2, 32);
656 break;
657 }
658 break;
659
660 default:
661 fprintf (stderr, "unimplemented HW MULT write to %x!\n", addr);
662 break;
663 }
664 }
665
3346cfda
NC		 666 switch (opc->size)
667 {
668 case 8:
669 buf[0] = val;
670 sim_core_write_buffer (sd, MSP430_CPU (sd), write_map, buf, addr, 1);
671 break;
672 case 16:
673 buf[0] = val;
674 buf[1] = val >> 8;
675 sim_core_write_buffer (sd, MSP430_CPU (sd), write_map, buf, addr, 2);
676 break;
677 case 20:
678 case 32:
679 buf[0] = val;
680 buf[1] = val >> 8;
681 buf[2] = val >> 16;
682 buf[3] = val >> 24;
683 sim_core_write_buffer (sd, MSP430_CPU (sd), write_map, buf, addr, 4);
684 break;
685 default:
686 assert (! opc->size);
687 break;
688 }
689 break;
690 default:
691 fprintf (stderr, "invalid operand %d type %d\n", n, op->type);
692 abort ();
693 }
694
695 switch (opc->size)
696 {
697 case 8:
698 rv &= 0xff;
699 incval = 1;
700 break;
701 case 16:
702 rv &= 0xffff;
703 incval = 2;
704 break;
705 case 20:
706 rv &= 0xfffff;
707 incval = 4;
708 break;
709 case 32:
710 rv &= 0xffffffff;
711 incval = 4;
712 break;
713 }
714
715 if (op->type == MSP430_Operand_Indirect_Postinc)
716 {
717 int new_val = REG_GET (op->reg) + incval;
718 /* SP is always word-aligned. */
719 if (op->reg == MSR_SP && (new_val & 1))
720 new_val ++;
721 REG_PUT (op->reg, new_val);
722 }
723
724 return rv;
725}
726
727static void
728mem_put_val (SIM_DESC sd, int addr, int val, int bits)
729{
730 MSP430_Opcode_Decoded opc;
731
732 opc.size = bits;
733 opc.op[0].type = MSP430_Operand_Indirect;
734 opc.op[0].addend = addr;
735 opc.op[0].reg = MSR_None;
736 put_op (sd, &opc, 0, val);
737}
738
739static int
740mem_get_val (SIM_DESC sd, int addr, int bits)
741{
742 MSP430_Opcode_Decoded opc;
743
744 opc.size = bits;
745 opc.op[0].type = MSP430_Operand_Indirect;
746 opc.op[0].addend = addr;
747 opc.op[0].reg = MSR_None;
748 return get_op (sd, &opc, 0);
749}
750
751#define CIO_OPEN (0xF0)
752#define CIO_CLOSE (0xF1)
753#define CIO_READ (0xF2)
754#define CIO_WRITE (0xF3)
755#define CIO_LSEEK (0xF4)
756#define CIO_UNLINK (0xF5)
757#define CIO_GETENV (0xF6)
758#define CIO_RENAME (0xF7)
759#define CIO_GETTIME (0xF8)
760#define CIO_GETCLK (0xF9)
761#define CIO_SYNC (0xFF)
762
763#define CIO_I(n) (parms[(n)] + parms[(n)+1] * 256)
764#define CIO_L(n) (parms[(n)] + parms[(n)+1] * 256 \
765 + parms[(n)+2] * 65536 + parms[(n)+3] * 16777216)
766
767static void
768msp430_cio (SIM_DESC sd)
769{
770 /* A block of data at __CIOBUF__ describes the I/O operation to
771 perform. */
772
773 unsigned char raw_parms[13];
774 unsigned char parms[8];
775 long length;
776 int command;
777 unsigned char buffer[512];
778 long ret_buflen = 0;
779 long fd, addr, len, rv;
780
781 sim_core_read_buffer (sd, MSP430_CPU (sd), 0, parms,
782 MSP430_CPU (sd)->state.cio_buffer, 5);
783 length = CIO_I (0);
784 command = parms[2];
785
786 sim_core_read_buffer (sd, MSP430_CPU (sd), 0, parms,
787 MSP430_CPU (sd)->state.cio_buffer + 3, 8);
788
789 sim_core_read_buffer (sd, MSP430_CPU (sd), 0, buffer,
790 MSP430_CPU (sd)->state.cio_buffer + 11, length);
791
792 switch (command)
793 {
794 case CIO_WRITE:
795 fd = CIO_I (0);
796 len = CIO_I (2);
797
798 rv = write (fd, buffer, len);
799 parms[0] = rv & 0xff;
800 parms[1] = rv >> 8;
801
802 break;
803 }
804
805 sim_core_write_buffer (sd, MSP430_CPU (sd), 0, parms,
806 MSP430_CPU (sd)->state.cio_buffer + 4, 8);
807 if (ret_buflen)
808 sim_core_write_buffer (sd, MSP430_CPU (sd), 0, buffer,
809 MSP430_CPU (sd)->state.cio_buffer + 12, ret_buflen);
810}
811
812#define SRC get_op (sd, opcode, 1)
813#define DSRC get_op (sd, opcode, 0)
814#define DEST(V) put_op (sd, opcode, 0, (V))
815
816static int
817msp430_dis_read (bfd_vma memaddr,
818 bfd_byte *myaddr,
819 unsigned int length,
820 struct disassemble_info *dinfo)
821{
822 SIM_DESC sd = dinfo->private_data;
823 sim_core_read_buffer (sd, MSP430_CPU (sd), 0, myaddr, memaddr, length);
824 return 0;
825}
826
827#define DO_ALU(OP,SOP,MORE) \
828 { \
829 int s1 = DSRC; \
830 int s2 = SRC; \
831 int result = s1 OP s2 MORE; \
832 if (TRACE_ALU_P (MSP430_CPU (sd))) \
833 trace_generic (sd, MSP430_CPU (sd), TRACE_ALU_IDX, \
834 "ALU: %#x %s %#x %s = %#x", s1, SOP, s2, #MORE, result); \
835 DEST (result); \
836 }
837
838#define SIGN (1 << (opcode->size - 1))
839#define POS(x) (((x) & SIGN) ? 0 : 1)
840#define NEG(x) (((x) & SIGN) ? 1 : 0)
841
3346cfda
NC		 842#define SX(v) sign_ext (v, opcode->size)
843#define ZX(v) zero_ext (v, opcode->size)
844
845static char *
846flags2string (int f)
847{
848 static char buf[2][6];
849 static int bi = 0;
850 char *bp = buf[bi];
851
852 bi = (bi + 1) % 2;
853
854 bp[0] = f & MSP430_FLAG_V ? 'V' : '-';
855 bp[1] = f & MSP430_FLAG_N ? 'N' : '-';
856 bp[2] = f & MSP430_FLAG_Z ? 'Z' : '-';
857 bp[3] = f & MSP430_FLAG_C ? 'C' : '-';
858 bp[4] = 0;
859 return bp;
860}
861
862/* Random number that won't show up in our usual logic. */
863#define MAGIC_OVERFLOW 0x55000F
864
865static void
866do_flags (SIM_DESC sd,
867 MSP430_Opcode_Decoded *opcode,
868 int vnz_val, /* Signed result. */
869 int carry,
870 int overflow)
871{
872 int f = SR;
873 int new_f = 0;
874 int signbit = 1 << (opcode->size - 1);
875
876 f &= ~opcode->flags_0;
877 f &= ~opcode->flags_set;
878 f |= opcode->flags_1;
879
880 if (vnz_val & signbit)
881 new_f |= MSP430_FLAG_N;
882 if (! (vnz_val & ((signbit << 1) - 1)))
883 new_f |= MSP430_FLAG_Z;
884 if (overflow == MAGIC_OVERFLOW)
885 {
886 if (vnz_val != SX (vnz_val))
887 new_f |= MSP430_FLAG_V;
888 }
889 else
890 if (overflow)
891 new_f |= MSP430_FLAG_V;
892 if (carry)
893 new_f |= MSP430_FLAG_C;
894
895 new_f = f | (new_f & opcode->flags_set);
896 if (TRACE_ALU_P (MSP430_CPU (sd)))
897 {
898 if (SR != new_f)
899 trace_generic (sd, MSP430_CPU (sd), TRACE_ALU_IDX,
900 "FLAGS: %s -> %s", flags2string (SR),
901 flags2string (new_f));
902 else
903 trace_generic (sd, MSP430_CPU (sd), TRACE_ALU_IDX,
904 "FLAGS: %s", flags2string (new_f));
905 }
906 SR = new_f;
907}
908
909#define FLAGS(vnz,c) do_flags (sd, opcode, vnz, c, MAGIC_OVERFLOW)
910#define FLAGSV(vnz,c,v) do_flags (sd, opcode, vnz, c, v)
911
912/* These two assume unsigned 16-bit (four digit) words.
913 Mask off unwanted bits for byte operations. */
914
915static int
916bcd_to_binary (int v)
917{
918 int r = ( ((v >> 0) & 0xf) * 1
919 + ((v >> 4) & 0xf) * 10
920 + ((v >> 8) & 0xf) * 100
921 + ((v >> 12) & 0xf) * 1000);
922 return r;
923}
924
925static int
926binary_to_bcd (int v)
927{
928 int r = ( ((v / 1) % 10) << 0
929 | ((v / 10) % 10) << 4
930 | ((v / 100) % 10) << 8
931 | ((v / 1000) % 10) << 12);
932 return r;
933}
934
935static int
936syscall_read_mem (host_callback *cb, struct cb_syscall *sc,
937 unsigned long taddr, char *buf, int bytes)
938{
939 SIM_DESC sd = (SIM_DESC) sc->p1;
940 SIM_CPU *cpu = (SIM_CPU *) sc->p2;
941
942 return sim_core_read_buffer (sd, cpu, read_map, buf, taddr, bytes);
943}
944
945static int
946syscall_write_mem (host_callback *cb, struct cb_syscall *sc,
947 unsigned long taddr, const char *buf, int bytes)
948{
949 SIM_DESC sd = (SIM_DESC) sc->p1;
950 SIM_CPU *cpu = (SIM_CPU *) sc->p2;
951
952 return sim_core_write_buffer (sd, cpu, write_map, buf, taddr, bytes);
953}
954
955static const char *
956cond_string (int cond)
957{
958 switch (cond)
959 {
960 case MSC_nz:
961 return "NZ";
962 case MSC_z:
963 return "Z";
964 case MSC_nc:
965 return "NC";
966 case MSC_c:
967 return "C";
968 case MSC_n:
969 return "N";
970 case MSC_ge:
971 return "GE";
972 case MSC_l:
973 return "L";
974 case MSC_true:
975 return "MP";
976 default:
977 return "??";
978 }
979}
980
981/* Checks a CALL to address CALL_ADDR. If this is a special
982 syscall address then the call is simulated and non-zero is
983 returned. Otherwise 0 is returned. */
984
985static int
986maybe_perform_syscall (SIM_DESC sd, int call_addr)
987{
988 if (call_addr == 0x00160)
989 {
990 int i;
991
992 for (i = 0; i < 16; i++)
993 {
994 if (i % 4 == 0)
995 fprintf (stderr, "\t");
996 fprintf (stderr, "R%-2d %05x ", i, MSP430_CPU (sd)->state.regs[i]);
997 if (i % 4 == 3)
998 {
999 int sp = SP + (3 - (i / 4)) * 2;
1000 unsigned char buf[2];
1001
1002 sim_core_read_buffer (sd, MSP430_CPU (sd), read_map, buf, sp, 2);
1003
1004 fprintf (stderr, "\tSP%+d: %04x", sp - SP,
1005 buf[0] + buf[1] * 256);
1006
1007 if (i / 4 == 0)
1008 {
1009 int flags = SR;
1010
1011 fprintf (stderr, flags & 0x100 ? " V" : " -");
1012 fprintf (stderr, flags & 0x004 ? "N" : "-");
1013 fprintf (stderr, flags & 0x002 ? "Z" : "-");
1014 fprintf (stderr, flags & 0x001 ? "C" : "-");
1015 }
1016
1017 fprintf (stderr, "\n");
1018 }
1019 }
1020 return 1;
1021 }
1022
1023 if ((call_addr & ~0x3f) == 0x00180)
1024 {
1025 /* Syscall! */
1026 int syscall_num = call_addr & 0x3f;
1027 host_callback *cb = STATE_CALLBACK (sd);
1028 CB_SYSCALL sc;
1029
1030 CB_SYSCALL_INIT (&sc);
1031
1032 sc.func = syscall_num;
1033 sc.arg1 = MSP430_CPU (sd)->state.regs[12];
1034 sc.arg2 = MSP430_CPU (sd)->state.regs[13];
1035 sc.arg3 = MSP430_CPU (sd)->state.regs[14];
1036 sc.arg4 = MSP430_CPU (sd)->state.regs[15];
1037
1038 if (TRACE_SYSCALL_P (MSP430_CPU (sd)))
1039 {
1040 const char *syscall_name = "*unknown*";
1041
1042 switch (syscall_num)
1043 {
1044 case TARGET_SYS_exit:
1045 syscall_name = "exit(%d)";
1046 break;
1047 case TARGET_SYS_open:
1048 syscall_name = "open(%#x,%#x)";
1049 break;
1050 case TARGET_SYS_close:
1051 syscall_name = "close(%d)";
1052 break;
1053 case TARGET_SYS_read:
1054 syscall_name = "read(%d,%#x,%d)";
1055 break;
1056 case TARGET_SYS_write:
1057 syscall_name = "write(%d,%#x,%d)";
1058 break;
1059 }
1060 trace_generic (sd, MSP430_CPU (sd), TRACE_SYSCALL_IDX,
1061 syscall_name, sc.arg1, sc.arg2, sc.arg3, sc.arg4);
1062 }
1063
1064 /* Handle SYS_exit here. */
1065 if (syscall_num == 1)
1066 {
1067 sim_engine_halt (sd, MSP430_CPU (sd), NULL,
1068 MSP430_CPU (sd)->state.regs[0],
1069 sim_exited, sc.arg1);
1070 return 1;
1071 }
1072
1073 sc.p1 = sd;
1074 sc.p2 = MSP430_CPU (sd);
1075 sc.read_mem = syscall_read_mem;
1076 sc.write_mem = syscall_write_mem;
1077
1078 cb_syscall (cb, &sc);
1079
1080 if (TRACE_SYSCALL_P (MSP430_CPU (sd)))
1081 trace_generic (sd, MSP430_CPU (sd), TRACE_SYSCALL_IDX,
a3271a3e 1082 "returns %ld", sc.result);
3346cfda
NC		 1083
1084 MSP430_CPU (sd)->state.regs[12] = sc.result;
1085 return 1;
1086 }
1087
1088 return 0;
1089}
1090
1091static void
1092msp430_step_once (SIM_DESC sd)
1093{
1094 Get_Byte_Local_Data ld;
1095 unsigned char buf[100];
1096 int i;
1097 int opsize;
1098 unsigned int opcode_pc;
1099 MSP430_Opcode_Decoded opcode_buf;
1100 MSP430_Opcode_Decoded *opcode = &opcode_buf;
1101 int s1, s2, result;
1102 int u1, u2, uresult;
1103 int c, reg;
1104 int sp;
1105 int carry_to_use;
1106 int n_repeats;
1107 int rept;
1108 int op_bytes, op_bits;
1109
1110 PC &= 0xfffff;
1111 opcode_pc = PC;
1112
1113 if (opcode_pc < 0x10)
1114 {
1115 fprintf (stderr, "Fault: PC(%#x) is less than 0x10\n", opcode_pc);
1116 sim_engine_halt (sd, MSP430_CPU (sd), NULL,
1117 MSP430_CPU (sd)->state.regs[0],
1118 sim_exited, -1);
1119 return;
1120 }
1121
1122 if (PC == MSP430_CPU (sd)->state.cio_breakpoint
1123 && STATE_OPEN_KIND (sd) != SIM_OPEN_DEBUG)
1124 msp430_cio (sd);
1125
1126 ld.sd = sd;
1127 ld.gb_addr = PC;
1128 opsize = msp430_decode_opcode (MSP430_CPU (sd)->state.regs[0],
1129 opcode, msp430_getbyte, &ld);
1130 PC += opsize;
1131 if (opsize <= 0)
1132 {
1133 fprintf (stderr, "Fault: undecodable opcode at %#x\n", opcode_pc);
1134 sim_engine_halt (sd, MSP430_CPU (sd), NULL,
1135 MSP430_CPU (sd)->state.regs[0],
1136 sim_exited, -1);
1137 return;
1138 }
1139
1140 if (opcode->repeat_reg)
1141 n_repeats = (MSP430_CPU (sd)->state.regs[opcode->repeats] & 0x000f) + 1;
1142 else
1143 n_repeats = opcode->repeats + 1;
1144
1145 op_bits = opcode->size;
1146 switch (op_bits)
1147 {
1148 case 8:
1149 op_bytes = 1;
1150 break;
1151 case 16:
1152 op_bytes = 2;
1153 break;
1154 case 20:
1155 case 32:
1156 op_bytes = 4;
1157 break;
1158 }
1159
1160 if (TRACE_INSN_P (MSP430_CPU (sd)))
1161 {
1162 disassemble_info info;
1163 unsigned char b[10];
1164
1165 msp430_trace_one (opcode_pc);
1166
1167 sim_core_read_buffer (sd, MSP430_CPU (sd), 0, b, opcode_pc, opsize);
1168
a3271a3e 1169 init_disassemble_info (&info, stderr, (fprintf_ftype) fprintf);
3346cfda
NC		 1170 info.private_data = sd;
1171 info.read_memory_func = msp430_dis_read;
1172 fprintf (stderr, "%#8x ", opcode_pc);
1173 for (i = 0; i < opsize; i += 2)
1174 fprintf (stderr, " %02x%02x", b[i+1], b[i]);
1175 for (; i < 6; i += 2)
1176 fprintf (stderr, " ");
1177 fprintf (stderr, " ");
1178 print_insn_msp430 (opcode_pc, &info);
1179 fprintf (stderr, "\n");
1180 fflush (stdout);
1181 }
1182
1183 if (TRACE_ANY_P (MSP430_CPU (sd)))
1184 trace_prefix (sd, MSP430_CPU (sd), NULL_CIA, opcode_pc,
1185 TRACE_LINENUM_P (MSP430_CPU (sd)), NULL, 0, "");
1186
1187 carry_to_use = 0;
1188 switch (opcode->id)
1189 {
1190 case MSO_unknown:
1191 break;
1192
1193 /* Double-operand instructions. */
1194 case MSO_mov:
1195 if (opcode->n_bytes == 2
1196 && opcode->op[0].type == MSP430_Operand_Register
1197 && opcode->op[0].reg == MSR_CG
1198 && opcode->op[1].type == MSP430_Operand_Immediate
1199 && opcode->op[1].addend == 0
1200 /* A 16-bit write of #0 is a NOP; an 8-bit write is a BRK. */
1201 && opcode->size == 8)
1202 {
1203 /* This is the designated software breakpoint instruction. */
1204 PC -= opsize;
1205 sim_engine_halt (sd, MSP430_CPU (sd), NULL,
1206 MSP430_CPU (sd)->state.regs[0],
1207 sim_stopped, SIM_SIGTRAP);
1208
1209 }
1210 else
1211 {
1212 /* Otherwise, do the move. */
1213 for (rept = 0; rept < n_repeats; rept ++)
1214 {
1215 DEST (SRC);
1216 }
1217 }
1218 break;
1219
1220 case MSO_addc:
1221 for (rept = 0; rept < n_repeats; rept ++)
1222 {
1223 carry_to_use = (SR & MSP430_FLAG_C) ? 1 : 0;
1224 u1 = DSRC;
1225 u2 = SRC;
1226 s1 = SX (u1);
1227 s2 = SX (u2);
1228 uresult = u1 + u2 + carry_to_use;
1229 result = s1 + s2 + carry_to_use;
1230 if (TRACE_ALU_P (MSP430_CPU (sd)))
1231 trace_generic (sd, MSP430_CPU (sd), TRACE_ALU_IDX,
1232 "ADDC: %#x + %#x + %d = %#x",
1233 u1, u2, carry_to_use, uresult);
1234 DEST (result);
1235 FLAGS (result, uresult != ZX (uresult));
1236 }
1237 break;
1238
1239 case MSO_add:
1240 for (rept = 0; rept < n_repeats; rept ++)
1241 {
1242 u1 = DSRC;
1243 u2 = SRC;
1244 s1 = SX (u1);
1245 s2 = SX (u2);
1246 uresult = u1 + u2;
1247 result = s1 + s2;
1248 if (TRACE_ALU_P (MSP430_CPU (sd)))
1249 trace_generic (sd, MSP430_CPU (sd), TRACE_ALU_IDX,
1250 "ADD: %#x + %#x = %#x",
1251 u1, u2, uresult);
1252 DEST (result);
1253 FLAGS (result, uresult != ZX (uresult));
1254 }
1255 break;
1256
1257 case MSO_subc:
1258 for (rept = 0; rept < n_repeats; rept ++)
1259 {
1260 carry_to_use = (SR & MSP430_FLAG_C) ? 1 : 0;
1261 u1 = DSRC;
1262 u2 = SRC;
1263 s1 = SX (u1);
1264 s2 = SX (u2);
1265 uresult = ZX (~u2) + u1 + carry_to_use;
1266 result = s1 - s2 + (carry_to_use - 1);
1267 if (TRACE_ALU_P (MSP430_CPU (sd)))
1268 trace_generic (sd, MSP430_CPU (sd), TRACE_ALU_IDX,
1269 "SUBC: %#x - %#x + %d = %#x",
1270 u1, u2, carry_to_use, uresult);
1271 DEST (result);
1272 FLAGS (result, uresult != ZX (uresult));
1273 }
1274 break;
1275
1276 case MSO_sub:
1277 for (rept = 0; rept < n_repeats; rept ++)
1278 {
1279 u1 = DSRC;
1280 u2 = SRC;
1281 s1 = SX (u1);
1282 s2 = SX (u2);
1283 uresult = ZX (~u2) + u1 + 1;
1284 result = SX (uresult);
1285 if (TRACE_ALU_P (MSP430_CPU (sd)))
1286 trace_generic (sd, MSP430_CPU (sd), TRACE_ALU_IDX,
1287 "SUB: %#x - %#x = %#x",
1288 u1, u2, uresult);
1289 DEST (result);
1290 FLAGS (result, uresult != ZX (uresult));
1291 }
1292 break;
1293
1294 case MSO_cmp:
1295 for (rept = 0; rept < n_repeats; rept ++)
1296 {
1297 u1 = DSRC;
1298 u2 = SRC;
1299 s1 = SX (u1);
1300 s2 = SX (u2);
1301 uresult = ZX (~u2) + u1 + 1;
1302 result = s1 - s2;
1303 if (TRACE_ALU_P (MSP430_CPU (sd)))
1304 trace_generic (sd, MSP430_CPU (sd), TRACE_ALU_IDX,
1305 "CMP: %#x - %#x = %x",
1306 u1, u2, uresult);
1307 FLAGS (result, uresult != ZX (uresult));
1308 }
1309 break;
1310
1311 case MSO_dadd:
1312 for (rept = 0; rept < n_repeats; rept ++)
1313 {
1314 carry_to_use = (SR & MSP430_FLAG_C) ? 1 : 0;
1315 u1 = DSRC;
1316 u2 = SRC;
1317 uresult = bcd_to_binary (u1) + bcd_to_binary (u2) + carry_to_use;
1318 result = binary_to_bcd (uresult);
1319 if (TRACE_ALU_P (MSP430_CPU (sd)))
1320 trace_generic (sd, MSP430_CPU (sd), TRACE_ALU_IDX,
1321 "DADD: %#x + %#x + %d = %#x",
1322 u1, u2, carry_to_use, result);
1323 DEST (result);
1324 FLAGS (result, uresult > ((opcode->size == 8) ? 99 : 9999));
1325 }
1326 break;
1327
1328 case MSO_and:
1329 for (rept = 0; rept < n_repeats; rept ++)
1330 {
1331 u1 = DSRC;
1332 u2 = SRC;
1333 uresult = u1 & u2;
1334 if (TRACE_ALU_P (MSP430_CPU (sd)))
1335 trace_generic (sd, MSP430_CPU (sd), TRACE_ALU_IDX,
1336 "AND: %#x & %#x = %#x",
1337 u1, u2, uresult);
1338 DEST (uresult);
1339 FLAGS (uresult, uresult != 0);
1340 }
1341 break;
1342
1343 case MSO_bit:
1344 for (rept = 0; rept < n_repeats; rept ++)
1345 {
1346 u1 = DSRC;
1347 u2 = SRC;
1348 uresult = u1 & u2;
1349 if (TRACE_ALU_P (MSP430_CPU (sd)))
1350 trace_generic (sd, MSP430_CPU (sd), TRACE_ALU_IDX,
1351 "BIT: %#x & %#x -> %#x",
1352 u1, u2, uresult);
1353 FLAGS (uresult, uresult != 0);
1354 }
1355 break;
1356
1357 case MSO_bic:
1358 for (rept = 0; rept < n_repeats; rept ++)
1359 {
1360 u1 = DSRC;
1361 u2 = SRC;
1362 uresult = u1 & ~ u2;
1363 if (TRACE_ALU_P (MSP430_CPU (sd)))
1364 trace_generic (sd, MSP430_CPU (sd), TRACE_ALU_IDX,
1365 "BIC: %#x & ~ %#x = %#x",
1366 u1, u2, uresult);
1367 DEST (uresult);
1368 }
1369 break;
1370
1371 case MSO_bis:
1372 for (rept = 0; rept < n_repeats; rept ++)
1373 {
1374 u1 = DSRC;
1375 u2 = SRC;
1376 uresult = u1 | u2;
1377 if (TRACE_ALU_P (MSP430_CPU (sd)))
1378 trace_generic (sd, MSP430_CPU (sd), TRACE_ALU_IDX,
1379 "BIS: %#x | %#x = %#x",
1380 u1, u2, uresult);
1381 DEST (uresult);
1382 }
1383 break;
1384
1385 case MSO_xor:
1386 for (rept = 0; rept < n_repeats; rept ++)
1387 {
1388 s1 = 1 << (opcode->size - 1);
1389 u1 = DSRC;
1390 u2 = SRC;
1391 uresult = u1 ^ u2;
1392 if (TRACE_ALU_P (MSP430_CPU (sd)))
1393 trace_generic (sd, MSP430_CPU (sd), TRACE_ALU_IDX,
1394 "XOR: %#x & %#x = %#x",
1395 u1, u2, uresult);
1396 DEST (uresult);
1397 FLAGSV (uresult, uresult != 0, (u1 & s1) && (u2 & s1));
1398 }
1399 break;
1400
1401 /* Single-operand instructions. Note: the decoder puts the same
1402 operand in SRC as in DEST, for our convenience. */
1403
1404 case MSO_rrc:
1405 for (rept = 0; rept < n_repeats; rept ++)
1406 {
1407 u1 = SRC;
1408 carry_to_use = u1 & 1;
1409 uresult = u1 >> 1;
1410 if (SR & MSP430_FLAG_C)
1411 uresult |= (1 << (opcode->size - 1));
1412 if (TRACE_ALU_P (MSP430_CPU (sd)))
1413 trace_generic (sd, MSP430_CPU (sd), TRACE_ALU_IDX,
1414 "RRC: %#x >>= %#x",
1415 u1, uresult);
1416 DEST (uresult);
1417 FLAGS (uresult, carry_to_use);
1418 }
1419 break;
1420
1421 case MSO_swpb:
1422 for (rept = 0; rept < n_repeats; rept ++)
1423 {
1424 u1 = SRC;
1425 uresult = ((u1 >> 8) & 0x00ff) | ((u1 << 8) & 0xff00);
1426 if (TRACE_ALU_P (MSP430_CPU (sd)))
1427 trace_generic (sd, MSP430_CPU (sd), TRACE_ALU_IDX,
1428 "SWPB: %#x -> %#x",
1429 u1, uresult);
1430 DEST (uresult);
1431 }
1432 break;
1433
1434 case MSO_rra:
1435 for (rept = 0; rept < n_repeats; rept ++)
1436 {
1437 u1 = SRC;
1438 c = u1 & 1;
1439 s1 = 1 << (opcode->size - 1);
1440 uresult = (u1 >> 1) | (u1 & s1);
1441 if (TRACE_ALU_P (MSP430_CPU (sd)))
1442 trace_generic (sd, MSP430_CPU (sd), TRACE_ALU_IDX,
1443 "RRA: %#x >>= %#x",
1444 u1, uresult);
1445 DEST (uresult);
1446 FLAGS (uresult, c);
1447 }
1448 break;
1449
1450 case MSO_rru:
1451 for (rept = 0; rept < n_repeats; rept ++)
1452 {
1453 u1 = SRC;
1454 c = u1 & 1;
1455 uresult = (u1 >> 1);
1456 if (TRACE_ALU_P (MSP430_CPU (sd)))
1457 trace_generic (sd, MSP430_CPU (sd), TRACE_ALU_IDX,
1458 "RRU: %#x >>= %#x",
1459 u1, uresult);
1460 DEST (uresult);
1461 FLAGS (uresult, c);
1462 }
1463 break;
1464
1465 case MSO_sxt:
1466 for (rept = 0; rept < n_repeats; rept ++)
1467 {
1468 u1 = SRC;
1469 if (u1 & 0x80)
1470 uresult = u1 | 0xfff00;
1471 else
1472 uresult = u1 & 0x000ff;
1473 if (TRACE_ALU_P (MSP430_CPU (sd)))
1474 trace_generic (sd, MSP430_CPU (sd), TRACE_ALU_IDX,
1475 "SXT: %#x -> %#x",
1476 u1, uresult);
1477 DEST (uresult);
1478 FLAGS (uresult, c);
1479 }
1480 break;
1481
1482 case MSO_push:
1483 for (rept = 0; rept < n_repeats; rept ++)
1484 {
1485 int new_sp;
1486
1487 new_sp = REG_GET (MSR_SP) - op_bytes;
1488 /* SP is always word-aligned. */
1489 if (new_sp & 1)
1490 new_sp --;
1491 REG_PUT (MSR_SP, new_sp);
1492 u1 = SRC;
1493 mem_put_val (sd, SP, u1, op_bits);
1494 if (opcode->op[1].type == MSP430_Operand_Register)
1495 opcode->op[1].reg --;
1496 }
1497 break;
1498
1499 case MSO_pop:
1500 for (rept = 0; rept < n_repeats; rept ++)
1501 {
1502 int new_sp;
1503
1504 u1 = mem_get_val (sd, SP, op_bits);
1505 DEST (u1);
1506 if (opcode->op[0].type == MSP430_Operand_Register)
1507 opcode->op[0].reg ++;
1508 new_sp = REG_GET (MSR_SP) + op_bytes;
1509 /* SP is always word-aligned. */
1510 if (new_sp & 1)
1511 new_sp ++;
1512 REG_PUT (MSR_SP, new_sp);
1513 }
1514 break;
1515
1516 case MSO_call:
1517 u1 = SRC;
1518
1519 if (maybe_perform_syscall (sd, u1))
1520 break;
1521
1522 REG_PUT (MSR_SP, REG_GET (MSR_SP) - op_bytes);
1523 mem_put_val (sd, SP, PC, op_bits);
1524 if (TRACE_ALU_P (MSP430_CPU (sd)))
1525 trace_generic (sd, MSP430_CPU (sd), TRACE_ALU_IDX,
1526 "CALL: func %#x ret %#x, sp %#x",
1527 u1, PC, SP);
1528 REG_PUT (MSR_PC, u1);
1529 break;
1530
1531 case MSO_reti:
8969934d
NC		 1532 u1 = mem_get_val (sd, SP, 16);
1533 SR = u1 & 0xFF;
3346cfda 1534 SP += 2;
8969934d 1535 PC = mem_get_val (sd, SP, 16);
3346cfda 1536 SP += 2;
8969934d
NC		 1537 /* Emulate the RETI action of the 20-bit CPUX architecure.
1538 This is safe for 16-bit CPU architectures as well, since the top
1539 8-bits of SR will have been written to the stack here, and will
1540 have been read as 0. */
1541 PC |= (u1 & 0xF000) << 4;
3346cfda
NC		 1542 if (TRACE_ALU_P (MSP430_CPU (sd)))
1543 trace_generic (sd, MSP430_CPU (sd), TRACE_ALU_IDX,
1544 "RETI: pc %#x sr %#x",
1545 PC, SR);
1546 break;
1547
1548 /* Jumps. */
1549
1550 case MSO_jmp:
1551 i = SRC;
1552 switch (opcode->cond)
1553 {
1554 case MSC_nz:
1555 u1 = (SR & MSP430_FLAG_Z) ? 0 : 1;
1556 break;
1557 case MSC_z:
1558 u1 = (SR & MSP430_FLAG_Z) ? 1 : 0;
1559 break;
1560 case MSC_nc:
1561 u1 = (SR & MSP430_FLAG_C) ? 0 : 1;
1562 break;
1563 case MSC_c:
1564 u1 = (SR & MSP430_FLAG_C) ? 1 : 0;
1565 break;
1566 case MSC_n:
1567 u1 = (SR & MSP430_FLAG_N) ? 1 : 0;
1568 break;
1569 case MSC_ge:
1570 u1 = (!!(SR & MSP430_FLAG_N) == !!(SR & MSP430_FLAG_V)) ? 1 : 0;
1571 break;
1572 case MSC_l:
1573 u1 = (!!(SR & MSP430_FLAG_N) == !!(SR & MSP430_FLAG_V)) ? 0 : 1;
1574 break;
1575 case MSC_true:
1576 u1 = 1;
1577 break;
1578 }
1579
1580 if (u1)
1581 {
1582 if (TRACE_BRANCH_P (MSP430_CPU (sd)))
1583 trace_generic (sd, MSP430_CPU (sd), TRACE_BRANCH_IDX,
1584 "J%s: pc %#x -> %#x sr %#x, taken",
1585 cond_string (opcode->cond), PC, i, SR);
1586 PC = i;
1587 if (PC == opcode_pc)
1588 exit (0);
1589 }
1590 else
1591 if (TRACE_BRANCH_P (MSP430_CPU (sd)))
1592 trace_generic (sd, MSP430_CPU (sd), TRACE_BRANCH_IDX,
1593 "J%s: pc %#x to %#x sr %#x, not taken",
1594 cond_string (opcode->cond), PC, i, SR);
1595 break;
1596
1597 default:
1598 fprintf (stderr, "error: unexpected opcode id %d\n", opcode->id);
1599 exit (1);
1600 }
1601}
1602
1603void
1604sim_engine_run (SIM_DESC sd,
1605 int next_cpu_nr,
1606 int nr_cpus,
1607 int siggnal)
1608{
1609 while (1)
1610 {
1611 msp430_step_once (sd);
1612 if (sim_events_tick (sd))
1613 sim_events_process (sd);
1614 }
1615}
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