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8e20a3ac MM |
1 | /* This file is part of the program psim. |
2 | ||
3 | Copyright (C) 1994-1995, Andrew Cagney <cagney@highland.com.au> | |
4 | ||
5 | This program is free software; you can redistribute it and/or modify | |
6 | it under the terms of the GNU General Public License as published by | |
7 | the Free Software Foundation; either version 2 of the License, or | |
8 | (at your option) any later version. | |
9 | ||
10 | This program is distributed in the hope that it will be useful, | |
11 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | GNU General Public License for more details. | |
14 | ||
15 | You should have received a copy of the GNU General Public License | |
16 | along with this program; if not, write to the Free Software | |
17 | Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. | |
18 | ||
19 | */ | |
20 | ||
21 | ||
22 | #ifndef _CONFIG_H_ | |
23 | #define _CONFIG_H_ | |
24 | ||
25 | ||
26 | /* endianness of the host/target: | |
27 | ||
28 | If the build process is aware (at compile time) of the endianness | |
29 | of the host/target it is able to eliminate slower generic endian | |
30 | handling code. | |
31 | ||
5b4d72dd | 32 | Possible values are 0 (unknown), LITTLE_ENDIAN, BIG_ENDIAN */ |
8e20a3ac | 33 | |
5b4d72dd | 34 | #ifndef WITH_HOST_BYTE_ORDER |
8e20a3ac | 35 | #define WITH_HOST_BYTE_ORDER 0 /*unknown*/ |
5b4d72dd MM |
36 | #endif |
37 | ||
38 | #ifndef WITH_TARGET_BYTE_ORDER | |
8e20a3ac | 39 | #define WITH_TARGET_BYTE_ORDER 0 /*unknown*/ |
5b4d72dd | 40 | #endif |
8e20a3ac MM |
41 | |
42 | extern int current_host_byte_order; | |
8e20a3ac MM |
43 | #define CURRENT_HOST_BYTE_ORDER (WITH_HOST_BYTE_ORDER \ |
44 | ? WITH_HOST_BYTE_ORDER \ | |
45 | : current_host_byte_order) | |
5b4d72dd | 46 | extern int current_target_byte_order; |
8e20a3ac MM |
47 | #define CURRENT_TARGET_BYTE_ORDER (WITH_TARGET_BYTE_ORDER \ |
48 | ? WITH_TARGET_BYTE_ORDER \ | |
49 | : current_target_byte_order) | |
50 | ||
51 | ||
5b4d72dd MM |
52 | /* Intel host BSWAP support: |
53 | ||
54 | Whether to use bswap on the 486 and pentiums rather than the 386 | |
55 | sequence that uses xchgb/rorl/xchgb */ | |
56 | #ifndef WITH_BSWAP | |
57 | #define WITH_BSWAP 0 | |
58 | #endif | |
59 | ||
60 | ||
8e20a3ac MM |
61 | /* SMP support: |
62 | ||
63 | Sets a limit on the number of processors that can be simulated. If | |
64 | WITH_SMP is set to zero (0), the simulator is restricted to | |
65 | suporting only on processor (and as a consequence leaves the SMP | |
5b4d72dd MM |
66 | code out of the build process). |
67 | ||
68 | The actual number of processors is taken from the device | |
69 | /options/smp@<nr-cpu> */ | |
8e20a3ac MM |
70 | |
71 | #ifndef WITH_SMP | |
5b4d72dd MM |
72 | #define WITH_SMP 2 |
73 | #endif | |
74 | #if WITH_SMP | |
75 | #define MAX_NR_PROCESSORS WITH_SMP | |
76 | #else | |
77 | #define MAX_NR_PROCESSORS 1 | |
8e20a3ac MM |
78 | #endif |
79 | ||
80 | ||
81 | /* Word size of host/target: | |
82 | ||
83 | Set these according to your host and target requirements. At this | |
84 | point in time, I've only compiled (not run) for a 64bit and never | |
85 | built for a 64bit host. This will always remain a compile time | |
86 | option */ | |
87 | ||
88 | #ifndef WITH_TARGET_WORD_BITSIZE | |
89 | #define WITH_TARGET_WORD_BITSIZE 32 /* compiled only */ | |
90 | #endif | |
5b4d72dd | 91 | |
8e20a3ac MM |
92 | #ifndef WITH_HOST_WORD_BITSIZE |
93 | #define WITH_HOST_WORD_BITSIZE 32 /* 64bit ready? */ | |
94 | #endif | |
95 | ||
96 | ||
97 | /* Program environment: | |
98 | ||
a983c8f0 MM |
99 | Three environments are available - UEA (user), VEA (virtual) and |
100 | OEA (perating). The former two are environment that users would | |
101 | expect to see (VEA includes things like coherency and the time | |
102 | base) while OEA is what an operating system expects to see. By | |
8e20a3ac MM |
103 | setting these to specific values, the build process is able to |
104 | eliminate non relevent environment code | |
105 | ||
106 | CURRENT_ENVIRONMENT specifies which of vea or oea is required for | |
107 | the current runtime. */ | |
108 | ||
a983c8f0 MM |
109 | #define USER_ENVIRONMENT 1 |
110 | #define VIRTUAL_ENVIRONMENT 2 | |
111 | #define OPERATING_ENVIRONMENT 3 | |
8e20a3ac | 112 | |
5b4d72dd MM |
113 | #ifndef WITH_ENVIRONMENT |
114 | #define WITH_ENVIRONMENT 0 | |
115 | #endif | |
116 | ||
8e20a3ac MM |
117 | extern int current_environment; |
118 | #define CURRENT_ENVIRONMENT (WITH_ENVIRONMENT \ | |
119 | ? WITH_ENVIRONMENT \ | |
120 | : current_environment) | |
121 | ||
122 | ||
123 | /* Optional VEA/OEA code: | |
124 | ||
125 | The below, required for the OEA model may also be included in the | |
126 | VEA model however, as far as I can tell only make things | |
127 | slower... */ | |
128 | ||
129 | ||
130 | /* Events. Devices modeling real H/W need to be able to efficiently | |
131 | schedule things to do at known times in the future. The event | |
132 | queue implements this. Unfortunatly this adds the need to check | |
133 | for any events once each full instruction cycle. */ | |
134 | ||
a983c8f0 | 135 | #define WITH_EVENTS (WITH_ENVIRONMENT != USER_ENVIRONMENT) |
8e20a3ac MM |
136 | |
137 | ||
138 | /* Time base: | |
139 | ||
140 | The PowerPC architecture includes the addition of both a time base | |
141 | register and a decrement timer. Like events adds to the overhead | |
142 | of of some instruction cycles. */ | |
143 | ||
144 | #ifndef WITH_TIME_BASE | |
a983c8f0 | 145 | #define WITH_TIME_BASE (WITH_ENVIRONMENT != USER_ENVIRONMENT) |
8e20a3ac MM |
146 | #endif |
147 | ||
148 | ||
149 | /* Callback/Default Memory. | |
150 | ||
151 | Core includes a builtin memory type (raw_memory) that is | |
152 | implemented using an array. raw_memory does not require any | |
153 | additional functions etc. | |
154 | ||
155 | Callback memory is where the core calls a core device for the data | |
156 | it requires. | |
157 | ||
158 | Default memory is an extenstion of this where for addresses that do | |
159 | not map into either a callback or core memory range a default map | |
160 | can be used. | |
161 | ||
162 | The OEA model uses callback memory for devices and default memory | |
163 | for buses. | |
164 | ||
165 | The VEA model uses callback memory to capture `page faults'. | |
166 | ||
167 | While it may be possible to eliminate callback/default memory (and | |
168 | hence also eliminate an additional test per memory fetch) it | |
169 | probably is not worth the effort. | |
170 | ||
171 | BTW, while raw_memory could have been implemented as a callback, | |
172 | profiling has shown that there is a biger win (at least for the | |
173 | x86) in eliminating a function call for the most common | |
174 | (raw_memory) case. */ | |
175 | ||
176 | #define WITH_CALLBACK_MEMORY 1 | |
177 | ||
178 | ||
179 | /* Alignment: | |
180 | ||
181 | The PowerPC may or may not handle miss aligned transfers. An | |
182 | implementation normally handles miss aligned transfers in big | |
183 | endian mode but generates an exception in little endian mode. | |
184 | ||
185 | This model. Instead allows both little and big endian modes to | |
186 | either take exceptions or handle miss aligned transfers. | |
187 | ||
188 | If 0 is specified then for big-endian mode miss alligned accesses | |
189 | are permitted (NONSTRICT_ALIGNMENT) while in little-endian mode the | |
190 | processor will fault on them (STRICT_ALIGNMENT). */ | |
191 | ||
192 | #define NONSTRICT_ALIGNMENT 1 | |
193 | #define STRICT_ALIGNMENT 2 | |
194 | ||
195 | #ifndef WITH_ALIGNMENT | |
196 | #define WITH_ALIGNMENT 0 | |
197 | #endif | |
5b4d72dd | 198 | |
8e20a3ac MM |
199 | extern int current_alignment; |
200 | #define CURRENT_ALIGNMENT (WITH_ALIGNMENT \ | |
201 | ? WITH_ALIGNMENT \ | |
202 | : current_alignment) | |
203 | ||
204 | ||
205 | /* Floating point suport: | |
206 | ||
207 | Still under development. */ | |
208 | ||
209 | #define SOFT_FLOATING_POINT 1 | |
210 | #define HARD_FLOATING_POINT 2 | |
211 | ||
212 | #ifndef WITH_FLOATING_POINT | |
213 | #define WITH_FLOATING_POINT HARD_FLOATING_POINT | |
214 | #endif | |
215 | extern int current_floating_point; | |
216 | #define CURRENT_FLOATING_POINT (WITH_FLOATING_POINT \ | |
217 | ? WITH_FLOATING_POINT \ | |
218 | : current_floating_point) | |
219 | ||
220 | ||
221 | /* Debugging: | |
222 | ||
223 | Control the inclusion of debugging code. */ | |
224 | ||
225 | /* Include the tracing code. Disabling this eliminates all tracing | |
226 | code */ | |
227 | ||
228 | #ifndef WITH_TRACE | |
229 | #define WITH_TRACE 1 | |
230 | #endif | |
231 | ||
232 | /* include code that checks assertions scattered through out the | |
233 | program */ | |
234 | ||
235 | #ifndef WITH_ASSERT | |
236 | #define WITH_ASSERT 1 | |
237 | #endif | |
238 | ||
5b4d72dd | 239 | /* include monitoring code */ |
8e20a3ac | 240 | |
5b4d72dd MM |
241 | #define MONITOR_INSTRUCTION_ISSUE 1 |
242 | #define MONITOR_LOAD_STORE_UNIT 2 | |
243 | #ifndef WITH_MON | |
244 | #define WITH_MON (MONITOR_LOAD_STORE_UNIT \ | |
245 | | MONITOR_INSTRUCTION_ISSUE) | |
8e20a3ac MM |
246 | #endif |
247 | ||
248 | ||
8e20a3ac MM |
249 | |
250 | /* INLINE CODE SELECTION: | |
251 | ||
252 | GCC -O3 attempts to inline any function or procedure in scope. The | |
253 | options below facilitate fine grained control over what is and what | |
254 | isn't made inline. For instance it can control things down to a | |
255 | specific modules static routines. This control is implemented in | |
256 | two parts. Doing this allows the compiler to both eliminate the | |
257 | overhead of function calls and (as a consequence) also eliminate | |
258 | further dead code. | |
259 | ||
260 | Experementing with CISC (x86) I've found that I can achieve an | |
261 | order of magintude speed improvement (x3-x5). In the case of RISC | |
262 | (sparc) while the performance gain isn't as great it is still | |
263 | significant. | |
264 | ||
265 | Part One - Static functions: It is possible to control how static | |
266 | functions within each module are to be compiled. On a per module | |
267 | or global basis, it is possible to specify that a modules static | |
268 | functions should be compiled inline. This is controled by the the | |
269 | macro's STATIC_INLINE and INLINE_STATIC_<module>. | |
270 | ||
271 | Part Two - External functions: Again it is possible to allow the | |
272 | inlining of calls to external functions. This is far more | |
273 | complicated and much heaver on the compiler. In this case, it is | |
274 | controled by the <module>_INLINE macro's. Where each can have a | |
275 | value: | |
276 | ||
5b4d72dd | 277 | 0 Make a normal external call to functions in the module. |
8e20a3ac | 278 | |
5b4d72dd MM |
279 | 1 Include the module but to not inline functions within it. |
280 | This allows functions within the module to inline functions | |
281 | from other modules that have been included. | |
8e20a3ac | 282 | |
5b4d72dd MM |
283 | 2 Both include the module and inline functions contained within |
284 | it. | |
8e20a3ac MM |
285 | |
286 | Finally, this is not for the faint harted. I've seen GCC get up to | |
287 | 200mb trying to compile what this can create */ | |
288 | ||
289 | /* Your compilers inline reserved word */ | |
290 | ||
291 | #ifndef INLINE | |
292 | #if defined(__GNUC__) && defined(__OPTIMIZE__) | |
293 | #define INLINE __inline__ | |
294 | #else | |
295 | #define INLINE /*inline*/ | |
296 | #endif | |
297 | #endif | |
298 | ||
299 | /* Default prefix for static functions */ | |
300 | ||
301 | #ifndef STATIC_INLINE | |
302 | #define STATIC_INLINE static INLINE | |
303 | #endif | |
304 | ||
5b4d72dd | 305 | /* Default macro to simplify control several of key the inlines */ |
8e20a3ac MM |
306 | |
307 | #ifndef DEFAULT_INLINE | |
308 | #define DEFAULT_INLINE 0 | |
309 | #endif | |
310 | ||
5b4d72dd MM |
311 | /* Code that converts between hosts and target byte order. Used on |
312 | every memory access (instruction and data). (See ppc-endian.h for | |
313 | additional byte swapping configuration information) */ | |
8e20a3ac MM |
314 | |
315 | #ifndef ENDIAN_INLINE | |
316 | #define ENDIAN_INLINE DEFAULT_INLINE | |
317 | #endif | |
318 | ||
5b4d72dd MM |
319 | /* Code that gives access to various CPU internals such as registers. |
320 | Used every time an instruction is executed */ | |
8e20a3ac | 321 | |
5b4d72dd MM |
322 | #ifndef CPU_INLINE |
323 | #define CPU_INLINE DEFAULT_INLINE | |
8e20a3ac MM |
324 | #endif |
325 | ||
5b4d72dd MM |
326 | /* Code that translates between an effective and real address. Used |
327 | by every load or store. */ | |
8e20a3ac MM |
328 | |
329 | #ifndef VM_INLINE | |
330 | #define VM_INLINE DEFAULT_INLINE | |
331 | #endif | |
332 | ||
5b4d72dd MM |
333 | /* Code that loads/stores data to/from the memory data structure. |
334 | Used by every load or store */ | |
8e20a3ac | 335 | |
5b4d72dd MM |
336 | #ifndef CORE_INLINE |
337 | #define CORE_INLINE DEFAULT_INLINE | |
8e20a3ac MM |
338 | #endif |
339 | ||
5b4d72dd MM |
340 | /* Code to check for and process any events scheduled in the future. |
341 | Called once per instruction cycle */ | |
8e20a3ac MM |
342 | |
343 | #ifndef EVENTS_INLINE | |
344 | #define EVENTS_INLINE DEFAULT_INLINE | |
345 | #endif | |
346 | ||
5b4d72dd MM |
347 | /* Code monotoring the processors performance. It counts events on |
348 | every instruction cycle */ | |
8e20a3ac | 349 | |
5b4d72dd MM |
350 | #ifndef MON_INLINE |
351 | #define MON_INLINE DEFAULT_INLINE | |
8e20a3ac MM |
352 | #endif |
353 | ||
5b4d72dd | 354 | /* Code called on the rare occasions that an interrupt occures. */ |
8e20a3ac MM |
355 | |
356 | #ifndef INTERRUPTS_INLINE | |
5b4d72dd MM |
357 | #define INTERRUPTS_INLINE 0 |
358 | #endif | |
359 | ||
360 | /* Code called on the rare occasion that either gdb or the device tree | |
361 | need to manipulate a register within a processor */ | |
362 | ||
363 | #ifndef REGISTERS_INLINE | |
364 | #define REGISTERS_INLINE 0 | |
8e20a3ac MM |
365 | #endif |
366 | ||
5b4d72dd MM |
367 | /* Code called on the rare occasion that a processor is manipulating |
368 | real hardware instead of RAM. | |
369 | ||
370 | Also, most of the functions in devices.c are always called through | |
371 | a jump table. | |
8e20a3ac MM |
372 | |
373 | There seems to be some problem with making either device_tree or | |
5b4d72dd MM |
374 | devices inline. It reports the message: device_tree_find_node() |
375 | not a leaf */ | |
8e20a3ac MM |
376 | |
377 | #ifndef DEVICE_TREE_INLINE | |
a983c8f0 | 378 | #define DEVICE_TREE_INLINE 0 |
8e20a3ac MM |
379 | #endif |
380 | ||
381 | #ifndef DEVICES_INLINE | |
382 | #define DEVICES_INLINE 0 | |
383 | #endif | |
384 | ||
5b4d72dd MM |
385 | /* Code called whenever information on a Special Purpose Register is |
386 | required. Called by the mflr/mtlr pseudo instructions */ | |
8e20a3ac MM |
387 | |
388 | #ifndef SPREG_INLINE | |
389 | #define SPREG_INLINE DEFAULT_INLINE | |
390 | #endif | |
391 | ||
392 | /* Functions modeling the semantics of each instruction. Two cases to | |
393 | consider, firstly of idecode is implemented with a switch then this | |
394 | allows the idecode function to inline each semantic function | |
395 | (avoiding a call). The second case is when idecode is using a | |
396 | table, even then while the semantic functions can't be inlined, | |
397 | setting it to one still enables each semantic function to inline | |
398 | anything they call (if that code is marked for being inlined). | |
399 | ||
400 | WARNING: you need lots (like 200mb of swap) of swap. Setting this | |
401 | to 1 is useful when using a table as it enables the sematic code to | |
402 | inline all of their called functions */ | |
403 | ||
404 | #ifndef SEMANTICS_INLINE | |
5b4d72dd | 405 | #define SEMANTICS_INLINE (DEFAULT_INLINE ? 1 : 0) |
8e20a3ac MM |
406 | #endif |
407 | ||
5b4d72dd MM |
408 | /* Code to decode an instruction. Normally called on every instruction |
409 | cycle */ | |
8e20a3ac MM |
410 | |
411 | #ifndef IDECODE_INLINE | |
412 | #define IDECODE_INLINE DEFAULT_INLINE | |
413 | #endif | |
414 | ||
8e20a3ac | 415 | #endif /* _CONFIG_H */ |