[thirdparty/binutils-gdb.git] / sim / sh64 / sh-desc.h

/* CPU data header for sh.

THIS FILE IS MACHINE GENERATED WITH CGEN.

Copyright (C) 1996, 1997, 1998, 1999, 2000 Free Software Foundation, Inc.

This file is part of the GNU Binutils and/or GDB, the GNU debugger.

This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2, or (at your option)
any later version.

This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
GNU General Public License for more details.

You should have received a copy of the GNU General Public License along
with this program; if not, write to the Free Software Foundation, Inc.,
59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.

*/

#ifndef SH_CPU_H
#define SH_CPU_H

#define CGEN_ARCH sh

/* Given symbol S, return sh_cgen_<S>.  */
#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
#define CGEN_SYM(s) sh##_cgen_##s
#else
#define CGEN_SYM(s) sh/**/_cgen_/**/s
#endif


/* Selected cpu families.  */
#define HAVE_CPU_SH64

#define CGEN_INSN_LSB0_P 1

/* Minimum size of any insn (in bytes).  */
#define CGEN_MIN_INSN_SIZE 2

/* Maximum size of any insn (in bytes).  */
#define CGEN_MAX_INSN_SIZE 4

#define CGEN_INT_INSN_P 1

/* Maximum nymber of syntax bytes in an instruction.  */
#define CGEN_ACTUAL_MAX_SYNTAX_BYTES 22

/* CGEN_MNEMONIC_OPERANDS is defined if mnemonics have operands.
   e.g. In "b,a foo" the ",a" is an operand.  If mnemonics have operands
   we can't hash on everything up to the space.  */
#define CGEN_MNEMONIC_OPERANDS

/* Maximum number of fields in an instruction.  */
#define CGEN_ACTUAL_MAX_IFMT_OPERANDS 8

/* Enums.  */

/* Enum declaration for .  */
typedef enum frc_names {
  H_FRC_FR0, H_FRC_FR1, H_FRC_FR2, H_FRC_FR3
 , H_FRC_FR4, H_FRC_FR5, H_FRC_FR6, H_FRC_FR7
 , H_FRC_FR8, H_FRC_FR9, H_FRC_FR10, H_FRC_FR11
 , H_FRC_FR12, H_FRC_FR13, H_FRC_FR14, H_FRC_FR15
} FRC_NAMES;

/* Enum declaration for .  */
typedef enum drc_names {
  H_DRC_DR0 = 0, H_DRC_DR2 = 2, H_DRC_DR4 = 4, H_DRC_DR6 = 6
 , H_DRC_DR8 = 8, H_DRC_DR10 = 10, H_DRC_DR12 = 12, H_DRC_DR14 = 14
} DRC_NAMES;

/* Enum declaration for .  */
typedef enum xf_names {
  H_XF_XF0, H_XF_XF1, H_XF_XF2, H_XF_XF3
 , H_XF_XF4, H_XF_XF5, H_XF_XF6, H_XF_XF7
 , H_XF_XF8, H_XF_XF9, H_XF_XF10, H_XF_XF11
 , H_XF_XF12, H_XF_XF13, H_XF_XF14, H_XF_XF15
} XF_NAMES;

/* Attributes.  */

/* Enum declaration for machine type selection.  */
typedef enum mach_attr {
  MACH_BASE, MACH_SH2, MACH_SH3, MACH_SH3E
 , MACH_SH4, MACH_SH5, MACH_MAX
} MACH_ATTR;

/* Enum declaration for instruction set selection.  */
typedef enum isa_attr {
  ISA_COMPACT, ISA_MEDIA, ISA_MAX
} ISA_ATTR;

/* Number of architecture variants.  */
#define MAX_ISAS  ((int) ISA_MAX)
#define MAX_MACHS ((int) MACH_MAX)

/* Ifield attribute indices.  */

/* Enum declaration for cgen_ifld attrs.  */
typedef enum cgen_ifld_attr {
  CGEN_IFLD_VIRTUAL, CGEN_IFLD_PCREL_ADDR, CGEN_IFLD_ABS_ADDR, CGEN_IFLD_RESERVED
 , CGEN_IFLD_SIGN_OPT, CGEN_IFLD_SIGNED, CGEN_IFLD_END_BOOLS, CGEN_IFLD_START_NBOOLS = 31
 , CGEN_IFLD_MACH, CGEN_IFLD_ISA, CGEN_IFLD_END_NBOOLS
} CGEN_IFLD_ATTR;

/* Number of non-boolean elements in cgen_ifld_attr.  */
#define CGEN_IFLD_NBOOL_ATTRS (CGEN_IFLD_END_NBOOLS - CGEN_IFLD_START_NBOOLS - 1)

/* Enum declaration for sh ifield types.  */
typedef enum ifield_type {
  SH_F_NIL, SH_F_ANYOF, SH_F_OP4, SH_F_OP8
 , SH_F_OP16, SH_F_SUB4, SH_F_SUB8, SH_F_SUB10
 , SH_F_RN, SH_F_RM, SH_F_8_1, SH_F_DISP8
 , SH_F_DISP12, SH_F_IMM8, SH_F_IMM4, SH_F_IMM4X2
 , SH_F_IMM4X4, SH_F_IMM8X2, SH_F_IMM8X4, SH_F_DN
 , SH_F_DM, SH_F_VN, SH_F_VM, SH_F_XN
 , SH_F_XM, SH_F_OP, SH_F_EXT, SH_F_RSVD
 , SH_F_LEFT, SH_F_RIGHT, SH_F_DEST, SH_F_LEFT_RIGHT
 , SH_F_TRA, SH_F_TRB, SH_F_LIKELY, SH_F_25
 , SH_F_8_2, SH_F_IMM6, SH_F_IMM10, SH_F_IMM16
 , SH_F_UIMM6, SH_F_UIMM16, SH_F_DISP6, SH_F_DISP6X32
 , SH_F_DISP10, SH_F_DISP10X8, SH_F_DISP10X4, SH_F_DISP10X2
 , SH_F_DISP16, SH_F_MAX
} IFIELD_TYPE;

#define MAX_IFLD ((int) SH_F_MAX)

/* Hardware attribute indices.  */

/* Enum declaration for cgen_hw attrs.  */
typedef enum cgen_hw_attr {
  CGEN_HW_VIRTUAL, CGEN_HW_CACHE_ADDR, CGEN_HW_PC, CGEN_HW_PROFILE
 , CGEN_HW_END_BOOLS, CGEN_HW_START_NBOOLS = 31, CGEN_HW_MACH, CGEN_HW_END_NBOOLS
} CGEN_HW_ATTR;

/* Number of non-boolean elements in cgen_hw_attr.  */
#define CGEN_HW_NBOOL_ATTRS (CGEN_HW_END_NBOOLS - CGEN_HW_START_NBOOLS - 1)

/* Enum declaration for sh hardware types.  */
typedef enum cgen_hw_type {
  HW_H_MEMORY, HW_H_SINT, HW_H_UINT, HW_H_ADDR
 , HW_H_IADDR, HW_H_PC, HW_H_GR, HW_H_GRC
 , HW_H_CR, HW_H_SR, HW_H_FPSCR, HW_H_FRBIT
 , HW_H_SZBIT, HW_H_PRBIT, HW_H_SBIT, HW_H_MBIT
 , HW_H_QBIT, HW_H_FR, HW_H_FP, HW_H_FV
 , HW_H_FMTX, HW_H_DR, HW_H_TR, HW_H_ENDIAN
 , HW_H_ISM, HW_H_FRC, HW_H_DRC, HW_H_XF
 , HW_H_XD, HW_H_FVC, HW_H_FPCCR, HW_H_GBR
 , HW_H_PR, HW_H_MACL, HW_H_MACH, HW_H_TBIT
 , HW_MAX
} CGEN_HW_TYPE;

#define MAX_HW ((int) HW_MAX)

/* Operand attribute indices.  */

/* Enum declaration for cgen_operand attrs.  */
typedef enum cgen_operand_attr {
  CGEN_OPERAND_VIRTUAL, CGEN_OPERAND_PCREL_ADDR, CGEN_OPERAND_ABS_ADDR, CGEN_OPERAND_SIGN_OPT
 , CGEN_OPERAND_SIGNED, CGEN_OPERAND_NEGATIVE, CGEN_OPERAND_RELAX, CGEN_OPERAND_SEM_ONLY
 , CGEN_OPERAND_END_BOOLS, CGEN_OPERAND_START_NBOOLS = 31, CGEN_OPERAND_MACH, CGEN_OPERAND_ISA
 , CGEN_OPERAND_END_NBOOLS
} CGEN_OPERAND_ATTR;

/* Number of non-boolean elements in cgen_operand_attr.  */
#define CGEN_OPERAND_NBOOL_ATTRS (CGEN_OPERAND_END_NBOOLS - CGEN_OPERAND_START_NBOOLS - 1)

/* Enum declaration for sh operand types.  */
typedef enum cgen_operand_type {
  SH_OPERAND_PC, SH_OPERAND_ENDIAN, SH_OPERAND_ISM, SH_OPERAND_RM
 , SH_OPERAND_RN, SH_OPERAND_R0, SH_OPERAND_FRN, SH_OPERAND_FRM
 , SH_OPERAND_FVN, SH_OPERAND_FVM, SH_OPERAND_DRN, SH_OPERAND_DRM
 , SH_OPERAND_IMM4, SH_OPERAND_IMM8, SH_OPERAND_UIMM8, SH_OPERAND_IMM4X2
 , SH_OPERAND_IMM4X4, SH_OPERAND_IMM8X2, SH_OPERAND_IMM8X4, SH_OPERAND_DISP8
 , SH_OPERAND_DISP12, SH_OPERAND_RM64, SH_OPERAND_RN64, SH_OPERAND_GBR
 , SH_OPERAND_PR, SH_OPERAND_FPSCR, SH_OPERAND_TBIT, SH_OPERAND_SBIT
 , SH_OPERAND_MBIT, SH_OPERAND_QBIT, SH_OPERAND_FPUL, SH_OPERAND_FRBIT
 , SH_OPERAND_SZBIT, SH_OPERAND_PRBIT, SH_OPERAND_MACL, SH_OPERAND_MACH
 , SH_OPERAND_FSDM, SH_OPERAND_FSDN, SH_OPERAND_RD, SH_OPERAND_FRG
 , SH_OPERAND_FRH, SH_OPERAND_FRF, SH_OPERAND_FRGH, SH_OPERAND_FPF
 , SH_OPERAND_FVG, SH_OPERAND_FVH, SH_OPERAND_FVF, SH_OPERAND_MTRXG
 , SH_OPERAND_DRG, SH_OPERAND_DRH, SH_OPERAND_DRF, SH_OPERAND_DRGH
 , SH_OPERAND_CRJ, SH_OPERAND_CRK, SH_OPERAND_TRA, SH_OPERAND_TRB
 , SH_OPERAND_DISP6, SH_OPERAND_DISP6X32, SH_OPERAND_DISP10, SH_OPERAND_DISP10X2
 , SH_OPERAND_DISP10X4, SH_OPERAND_DISP10X8, SH_OPERAND_DISP16, SH_OPERAND_IMM6
 , SH_OPERAND_IMM10, SH_OPERAND_IMM16, SH_OPERAND_UIMM6, SH_OPERAND_UIMM16
 , SH_OPERAND_LIKELY, SH_OPERAND_MAX
} CGEN_OPERAND_TYPE;

/* Number of operands types.  */
#define MAX_OPERANDS 72

/* Maximum number of operands referenced by any insn.  */
#define MAX_OPERAND_INSTANCES 8

/* Insn attribute indices.  */

/* Enum declaration for cgen_insn attrs.  */
typedef enum cgen_insn_attr {
  CGEN_INSN_ALIAS, CGEN_INSN_VIRTUAL, CGEN_INSN_UNCOND_CTI, CGEN_INSN_COND_CTI
 , CGEN_INSN_SKIP_CTI, CGEN_INSN_DELAY_SLOT, CGEN_INSN_RELAXABLE, CGEN_INSN_RELAX
 , CGEN_INSN_NO_DIS, CGEN_INSN_PBB, CGEN_INSN_ILLSLOT, CGEN_INSN_FP_INSN
 , CGEN_INSN_END_BOOLS, CGEN_INSN_START_NBOOLS = 31, CGEN_INSN_MACH, CGEN_INSN_ISA
 , CGEN_INSN_END_NBOOLS
} CGEN_INSN_ATTR;

/* Number of non-boolean elements in cgen_insn_attr.  */
#define CGEN_INSN_NBOOL_ATTRS (CGEN_INSN_END_NBOOLS - CGEN_INSN_START_NBOOLS - 1)

/* cgen.h uses things we just defined.  */
#include "opcode/cgen.h"

/* Attributes.  */
extern const CGEN_ATTR_TABLE sh_cgen_hardware_attr_table[];
extern const CGEN_ATTR_TABLE sh_cgen_ifield_attr_table[];
extern const CGEN_ATTR_TABLE sh_cgen_operand_attr_table[];
extern const CGEN_ATTR_TABLE sh_cgen_insn_attr_table[];

/* Hardware decls.  */

extern CGEN_KEYWORD sh_cgen_opval_h_gr;
extern CGEN_KEYWORD sh_cgen_opval_h_grc;
extern CGEN_KEYWORD sh_cgen_opval_h_cr;
extern CGEN_KEYWORD sh_cgen_opval_h_fr;
extern CGEN_KEYWORD sh_cgen_opval_h_fp;
extern CGEN_KEYWORD sh_cgen_opval_h_fv;
extern CGEN_KEYWORD sh_cgen_opval_h_fmtx;
extern CGEN_KEYWORD sh_cgen_opval_h_dr;
extern CGEN_KEYWORD sh_cgen_opval_h_tr;
extern CGEN_KEYWORD sh_cgen_opval_frc_names;
extern CGEN_KEYWORD sh_cgen_opval_drc_names;
extern CGEN_KEYWORD sh_cgen_opval_xf_names;
extern CGEN_KEYWORD sh_cgen_opval_frc_names;
extern CGEN_KEYWORD sh_cgen_opval_h_fvc;

/* Ifield support.  */

extern const struct cgen_ifld sh_cgen_ifld_table[];


#endif /* SH_CPU_H */
Commit	Line	Data
cbb38b47 BE	1	/* CPU data header for sh.
	2
	3	THIS FILE IS MACHINE GENERATED WITH CGEN.
	4
	5	Copyright (C) 1996, 1997, 1998, 1999, 2000 Free Software Foundation, Inc.
	6
	7	This file is part of the GNU Binutils and/or GDB, the GNU debugger.
	8
	9	This program is free software; you can redistribute it and/or modify
	10	it under the terms of the GNU General Public License as published by
	11	the Free Software Foundation; either version 2, or (at your option)
	12	any later version.
	13
	14	This program is distributed in the hope that it will be useful,
	15	but WITHOUT ANY WARRANTY; without even the implied warranty of
	16	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	17	GNU General Public License for more details.
	18
	19	You should have received a copy of the GNU General Public License along
	20	with this program; if not, write to the Free Software Foundation, Inc.,
	21	59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
	22
	23	*/
	24
	25	#ifndef SH_CPU_H
	26	#define SH_CPU_H
	27
	28	#define CGEN_ARCH sh
	29
	30	/* Given symbol S, return sh_cgen_<S>. */
	31	#if defined (__STDC__) \|\| defined (ALMOST_STDC) \|\| defined (HAVE_STRINGIZE)
	32	#define CGEN_SYM(s) sh##_cgen_##s
	33	#else
	34	#define CGEN_SYM(s) sh//_cgen_//s
	35	#endif
	36
	37
	38	/* Selected cpu families. */
	39	#define HAVE_CPU_SH64
	40
	41	#define CGEN_INSN_LSB0_P 1
	42
	43	/* Minimum size of any insn (in bytes). */
	44	#define CGEN_MIN_INSN_SIZE 2
	45
	46	/* Maximum size of any insn (in bytes). */
	47	#define CGEN_MAX_INSN_SIZE 4
	48
	49	#define CGEN_INT_INSN_P 1
	50
	51	/* Maximum nymber of syntax bytes in an instruction. */
	52	#define CGEN_ACTUAL_MAX_SYNTAX_BYTES 22
	53
	54	/* CGEN_MNEMONIC_OPERANDS is defined if mnemonics have operands.
	55	e.g. In "b,a foo" the ",a" is an operand. If mnemonics have operands
	56	we can't hash on everything up to the space. */
	57	#define CGEN_MNEMONIC_OPERANDS
	58
	59	/* Maximum number of fields in an instruction. */
	60	#define CGEN_ACTUAL_MAX_IFMT_OPERANDS 8
	61
	62	/* Enums. */
	63
	64	/* Enum declaration for . */
65	typedef enum frc_names {
66	H_FRC_FR0, H_FRC_FR1, H_FRC_FR2, H_FRC_FR3
67	, H_FRC_FR4, H_FRC_FR5, H_FRC_FR6, H_FRC_FR7
68	, H_FRC_FR8, H_FRC_FR9, H_FRC_FR10, H_FRC_FR11
69	, H_FRC_FR12, H_FRC_FR13, H_FRC_FR14, H_FRC_FR15
70	} FRC_NAMES;
71
72	/* Enum declaration for . */
73	typedef enum drc_names {
74	H_DRC_DR0 = 0, H_DRC_DR2 = 2, H_DRC_DR4 = 4, H_DRC_DR6 = 6
75	, H_DRC_DR8 = 8, H_DRC_DR10 = 10, H_DRC_DR12 = 12, H_DRC_DR14 = 14
76	} DRC_NAMES;
77
78	/* Enum declaration for . */
79	typedef enum xf_names {
80	H_XF_XF0, H_XF_XF1, H_XF_XF2, H_XF_XF3
81	, H_XF_XF4, H_XF_XF5, H_XF_XF6, H_XF_XF7
82	, H_XF_XF8, H_XF_XF9, H_XF_XF10, H_XF_XF11
83	, H_XF_XF12, H_XF_XF13, H_XF_XF14, H_XF_XF15
84	} XF_NAMES;
85
86	/* Attributes. */
87
88	/* Enum declaration for machine type selection. */
89	typedef enum mach_attr {
90	MACH_BASE, MACH_SH2, MACH_SH3, MACH_SH3E
91	, MACH_SH4, MACH_SH5, MACH_MAX
92	} MACH_ATTR;
93
94	/* Enum declaration for instruction set selection. */
95	typedef enum isa_attr {
96	ISA_COMPACT, ISA_MEDIA, ISA_MAX
97	} ISA_ATTR;
98
99	/* Number of architecture variants. */
100	#define MAX_ISAS ((int) ISA_MAX)
101	#define MAX_MACHS ((int) MACH_MAX)
102
cbb38b47 BE	103	/* Ifield attribute indices. */
	104
	105	/* Enum declaration for cgen_ifld attrs. */
	106	typedef enum cgen_ifld_attr {
	107	CGEN_IFLD_VIRTUAL, CGEN_IFLD_PCREL_ADDR, CGEN_IFLD_ABS_ADDR, CGEN_IFLD_RESERVED
	108	, CGEN_IFLD_SIGN_OPT, CGEN_IFLD_SIGNED, CGEN_IFLD_END_BOOLS, CGEN_IFLD_START_NBOOLS = 31
	109	, CGEN_IFLD_MACH, CGEN_IFLD_ISA, CGEN_IFLD_END_NBOOLS
	110	} CGEN_IFLD_ATTR;
	111
	112	/* Number of non-boolean elements in cgen_ifld_attr. */
	113	#define CGEN_IFLD_NBOOL_ATTRS (CGEN_IFLD_END_NBOOLS - CGEN_IFLD_START_NBOOLS - 1)
	114
	115	/* Enum declaration for sh ifield types. */
	116	typedef enum ifield_type {
	117	SH_F_NIL, SH_F_ANYOF, SH_F_OP4, SH_F_OP8
	118	, SH_F_OP16, SH_F_SUB4, SH_F_SUB8, SH_F_SUB10
	119	, SH_F_RN, SH_F_RM, SH_F_8_1, SH_F_DISP8
	120	, SH_F_DISP12, SH_F_IMM8, SH_F_IMM4, SH_F_IMM4X2
	121	, SH_F_IMM4X4, SH_F_IMM8X2, SH_F_IMM8X4, SH_F_DN
	122	, SH_F_DM, SH_F_VN, SH_F_VM, SH_F_XN
	123	, SH_F_XM, SH_F_OP, SH_F_EXT, SH_F_RSVD
	124	, SH_F_LEFT, SH_F_RIGHT, SH_F_DEST, SH_F_LEFT_RIGHT
	125	, SH_F_TRA, SH_F_TRB, SH_F_LIKELY, SH_F_25
	126	, SH_F_8_2, SH_F_IMM6, SH_F_IMM10, SH_F_IMM16
	127	, SH_F_UIMM6, SH_F_UIMM16, SH_F_DISP6, SH_F_DISP6X32
	128	, SH_F_DISP10, SH_F_DISP10X8, SH_F_DISP10X4, SH_F_DISP10X2
	129	, SH_F_DISP16, SH_F_MAX
	130	} IFIELD_TYPE;
	131
	132	#define MAX_IFLD ((int) SH_F_MAX)
	133
	134	/* Hardware attribute indices. */
	135
	136	/* Enum declaration for cgen_hw attrs. */
	137	typedef enum cgen_hw_attr {
	138	CGEN_HW_VIRTUAL, CGEN_HW_CACHE_ADDR, CGEN_HW_PC, CGEN_HW_PROFILE
	139	, CGEN_HW_END_BOOLS, CGEN_HW_START_NBOOLS = 31, CGEN_HW_MACH, CGEN_HW_END_NBOOLS
	140	} CGEN_HW_ATTR;
	141
	142	/* Number of non-boolean elements in cgen_hw_attr. */
	143	#define CGEN_HW_NBOOL_ATTRS (CGEN_HW_END_NBOOLS - CGEN_HW_START_NBOOLS - 1)
	144
	145	/* Enum declaration for sh hardware types. */
	146	typedef enum cgen_hw_type {
	147	HW_H_MEMORY, HW_H_SINT, HW_H_UINT, HW_H_ADDR
	148	, HW_H_IADDR, HW_H_PC, HW_H_GR, HW_H_GRC
	149	, HW_H_CR, HW_H_SR, HW_H_FPSCR, HW_H_FRBIT
	150	, HW_H_SZBIT, HW_H_PRBIT, HW_H_SBIT, HW_H_MBIT
	151	, HW_H_QBIT, HW_H_FR, HW_H_FP, HW_H_FV
	152	, HW_H_FMTX, HW_H_DR, HW_H_TR, HW_H_ENDIAN
	153	, HW_H_ISM, HW_H_FRC, HW_H_DRC, HW_H_XF
	154	, HW_H_XD, HW_H_FVC, HW_H_FPCCR, HW_H_GBR
	155	, HW_H_PR, HW_H_MACL, HW_H_MACH, HW_H_TBIT
	156	, HW_MAX
	157	} CGEN_HW_TYPE;
	158
	159	#define MAX_HW ((int) HW_MAX)
	160
	161	/* Operand attribute indices. */
	162
	163	/* Enum declaration for cgen_operand attrs. */
	164	typedef enum cgen_operand_attr {
	165	CGEN_OPERAND_VIRTUAL, CGEN_OPERAND_PCREL_ADDR, CGEN_OPERAND_ABS_ADDR, CGEN_OPERAND_SIGN_OPT
	166	, CGEN_OPERAND_SIGNED, CGEN_OPERAND_NEGATIVE, CGEN_OPERAND_RELAX, CGEN_OPERAND_SEM_ONLY
167	, CGEN_OPERAND_END_BOOLS, CGEN_OPERAND_START_NBOOLS = 31, CGEN_OPERAND_MACH, CGEN_OPERAND_ISA
168	, CGEN_OPERAND_END_NBOOLS
169	} CGEN_OPERAND_ATTR;
170
171	/* Number of non-boolean elements in cgen_operand_attr. */
172	#define CGEN_OPERAND_NBOOL_ATTRS (CGEN_OPERAND_END_NBOOLS - CGEN_OPERAND_START_NBOOLS - 1)
173
174	/* Enum declaration for sh operand types. */
175	typedef enum cgen_operand_type {
176	SH_OPERAND_PC, SH_OPERAND_ENDIAN, SH_OPERAND_ISM, SH_OPERAND_RM
177	, SH_OPERAND_RN, SH_OPERAND_R0, SH_OPERAND_FRN, SH_OPERAND_FRM
178	, SH_OPERAND_FVN, SH_OPERAND_FVM, SH_OPERAND_DRN, SH_OPERAND_DRM
179	, SH_OPERAND_IMM4, SH_OPERAND_IMM8, SH_OPERAND_UIMM8, SH_OPERAND_IMM4X2
180	, SH_OPERAND_IMM4X4, SH_OPERAND_IMM8X2, SH_OPERAND_IMM8X4, SH_OPERAND_DISP8
181	, SH_OPERAND_DISP12, SH_OPERAND_RM64, SH_OPERAND_RN64, SH_OPERAND_GBR
182	, SH_OPERAND_PR, SH_OPERAND_FPSCR, SH_OPERAND_TBIT, SH_OPERAND_SBIT
183	, SH_OPERAND_MBIT, SH_OPERAND_QBIT, SH_OPERAND_FPUL, SH_OPERAND_FRBIT
184	, SH_OPERAND_SZBIT, SH_OPERAND_PRBIT, SH_OPERAND_MACL, SH_OPERAND_MACH
185	, SH_OPERAND_FSDM, SH_OPERAND_FSDN, SH_OPERAND_RD, SH_OPERAND_FRG
186	, SH_OPERAND_FRH, SH_OPERAND_FRF, SH_OPERAND_FRGH, SH_OPERAND_FPF
187	, SH_OPERAND_FVG, SH_OPERAND_FVH, SH_OPERAND_FVF, SH_OPERAND_MTRXG
188	, SH_OPERAND_DRG, SH_OPERAND_DRH, SH_OPERAND_DRF, SH_OPERAND_DRGH
189	, SH_OPERAND_CRJ, SH_OPERAND_CRK, SH_OPERAND_TRA, SH_OPERAND_TRB
190	, SH_OPERAND_DISP6, SH_OPERAND_DISP6X32, SH_OPERAND_DISP10, SH_OPERAND_DISP10X2
191	, SH_OPERAND_DISP10X4, SH_OPERAND_DISP10X8, SH_OPERAND_DISP16, SH_OPERAND_IMM6
192	, SH_OPERAND_IMM10, SH_OPERAND_IMM16, SH_OPERAND_UIMM6, SH_OPERAND_UIMM16
193	, SH_OPERAND_LIKELY, SH_OPERAND_MAX
194	} CGEN_OPERAND_TYPE;
195
196	/* Number of operands types. */
197	#define MAX_OPERANDS 72
198
199	/* Maximum number of operands referenced by any insn. */
200	#define MAX_OPERAND_INSTANCES 8
201
202	/* Insn attribute indices. */
203
204	/* Enum declaration for cgen_insn attrs. */
205	typedef enum cgen_insn_attr {
206	CGEN_INSN_ALIAS, CGEN_INSN_VIRTUAL, CGEN_INSN_UNCOND_CTI, CGEN_INSN_COND_CTI
207	, CGEN_INSN_SKIP_CTI, CGEN_INSN_DELAY_SLOT, CGEN_INSN_RELAXABLE, CGEN_INSN_RELAX
208	, CGEN_INSN_NO_DIS, CGEN_INSN_PBB, CGEN_INSN_ILLSLOT, CGEN_INSN_FP_INSN
209	, CGEN_INSN_END_BOOLS, CGEN_INSN_START_NBOOLS = 31, CGEN_INSN_MACH, CGEN_INSN_ISA
210	, CGEN_INSN_END_NBOOLS
211	} CGEN_INSN_ATTR;
212
213	/* Number of non-boolean elements in cgen_insn_attr. */
214	#define CGEN_INSN_NBOOL_ATTRS (CGEN_INSN_END_NBOOLS - CGEN_INSN_START_NBOOLS - 1)
215
216	/* cgen.h uses things we just defined. */
217	#include "opcode/cgen.h"
218
219	/* Attributes. */
220	extern const CGEN_ATTR_TABLE sh_cgen_hardware_attr_table[];
221	extern const CGEN_ATTR_TABLE sh_cgen_ifield_attr_table[];
222	extern const CGEN_ATTR_TABLE sh_cgen_operand_attr_table[];
223	extern const CGEN_ATTR_TABLE sh_cgen_insn_attr_table[];
224
225	/* Hardware decls. */
226
227	extern CGEN_KEYWORD sh_cgen_opval_h_gr;
228	extern CGEN_KEYWORD sh_cgen_opval_h_grc;
229	extern CGEN_KEYWORD sh_cgen_opval_h_cr;
230	extern CGEN_KEYWORD sh_cgen_opval_h_fr;
231	extern CGEN_KEYWORD sh_cgen_opval_h_fp;
232	extern CGEN_KEYWORD sh_cgen_opval_h_fv;
233	extern CGEN_KEYWORD sh_cgen_opval_h_fmtx;
234	extern CGEN_KEYWORD sh_cgen_opval_h_dr;
235	extern CGEN_KEYWORD sh_cgen_opval_h_tr;
236	extern CGEN_KEYWORD sh_cgen_opval_frc_names;
237	extern CGEN_KEYWORD sh_cgen_opval_drc_names;
238	extern CGEN_KEYWORD sh_cgen_opval_xf_names;
239	extern CGEN_KEYWORD sh_cgen_opval_frc_names;
240	extern CGEN_KEYWORD sh_cgen_opval_h_fvc;
241
4839e910 CV	242	/* Ifield support. */
	243
	244	extern const struct cgen_ifld sh_cgen_ifld_table[];
	245
cbb38b47 BE	246
	247
	248
	249	#endif /* SH_CPU_H */