]> git.ipfire.org Git - thirdparty/binutils-gdb.git/blame - sim/v850/ChangeLog
Cleanups to compile under FreeBSD
[thirdparty/binutils-gdb.git] / sim / v850 / ChangeLog
CommitLineData
87e43259
AC
1Wed Apr 16 19:53:55 1997 Andrew Cagney <cagney@b1.cygnus.com>
2
3 * simops.c (OP_10007E0): Only provide system calls SYS_execv,
4 SYS_wait, SYS_wait, SYS_utime, SYS_time if defined by the host.
5
6Mon Apr 7 15:45:02 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
7
8 * configure: Regenerated to track ../common/aclocal.m4 changes.
9 * config.in: Ditto.
10
fbda74b1
DE
11Wed Apr 2 15:06:28 1997 Doug Evans <dje@canuck.cygnus.com>
12
8a7c3105
DE
13 * interp.c (sim_open): New arg `kind'.
14
fbda74b1
DE
15 * configure: Regenerated to track ../common/aclocal.m4 changes.
16
a35e91c3
AC
17Wed Apr 2 14:34:19 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
18
19 * configure: Regenerated to track ../common/aclocal.m4 changes.
20
21Wed Mar 19 01:14:00 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
22
23 * configure: Regenerated to track ../common/aclocal.m4 changes.
24
a77aa7ec
AC
25Mon Mar 17 15:10:07 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
26
27 * configure: Re-generate.
28
601fb8ae
MM
29Fri Mar 14 10:34:11 1997 Michael Meissner <meissner@cygnus.com>
30
31 * configure: Regenerate to track ../common/aclocal.m4 changes.
32
0b0cc453
DE
33Thu Mar 13 13:00:54 1997 Doug Evans <dje@canuck.cygnus.com>
34
35 * interp.c (sim_open): New SIM_DESC result. Argument is now
36 in argv form.
37 (other sim_*): New SIM_DESC argument.
38
39Tue Feb 4 13:33:30 1997 Doug Evans <dje@canuck.cygnus.com>
40
41 * Makefile.in (@COMMON_MAKEFILE_FRAG): Use
42 COMMON_{PRE,POST}_CONFIG_FRAG instead.
43 * configure.in: sinclude ../common/aclocal.m4.
44 * configure: Regenerated.
45
295dbbe4
SG
46Thu Jan 23 11:46:23 1997 Stu Grossman (grossman@critters.cygnus.com)
47
48 * configure configure.in Makefile.in: Update to new configure
49 scheme which is more compatible with WinGDB builds.
50 * configure.in: Improve comment on how to run autoconf.
51 * configure: Re-run autoconf to get new ../common/aclocal.m4.
52 * Makefile.in: Use autoconf substitution to install common
53 makefile fragment.
54
5a8023e5
MM
55Mon Jan 20 16:05:34 1997 Michael Meissner <meissner@tiktok.cygnus.com>
56
57 * simops.c (OP_{E0,2E0,6E0}): The multiply operations sign extend,
58 not zero extend.
59
60Tue Jan 14 17:06:03 1997 Stu Grossman (grossman@critters.cygnus.com)
61
62 * simops.c: Put ifdefs around things to make MSVC happy. Get rid
63 of unistd.h. Disable SYS_stat, SYS_chown, SYS_time, SYS_times,
64 SYS_gettimeofday and SYS_utime from MSVC.
65
6ec96a02
MM
66Tue Dec 31 18:11:13 1996 Michael Meissner <meissner@tiktok.cygnus.com>
67
68 * simops.c (OP_10007E0): Know that kill encodes the signal number
69 via: 0xdead0000 | signal and turn it back into a signal.
70
ee3f2d4f
MM
71Fri Dec 27 14:44:06 1996 Michael Meissner <meissner@tiktok.cygnus.com>
72
73 * v850_sim.h (SIG_V850_EXIT): Define as -1.
74
75 * interp.c (sim_open): Cast calloc function.
76 (sim_stop_reason): If signal is SIG_V850_EXIT, inform gdb the
77 program exited with the appropriate exit code.
78 (sim_set_interrupt): Declare buildargv.
79
80 * simops.c (OP_10007E0): Make exit signal normal exit. Make time
81 type correct and work on big endian systems.
82
83Wed Nov 20 02:18:44 1996 Doug Evans <dje@canuck.cygnus.com>
84
85 * Makefile.in: Delete stuff moved to ../common/Make-common.in.
86 (SIM_OBJS,SIM_EXTRA_CFLAGS,SIM_EXTRA_CLEAN): Define.
87 * configure.in: Simplify using macros in ../common/aclocal.m4.
88 Call AC_CHECK_HEADERS(unistd.h).
89 * configure: Regenerated.
90 * config.in: New file.
91 * simops.c: #include "config.h". #include <unistd.h> if present.
92
93Sun Nov 3 23:02:54 1996 Stan Shebs <shebs@andros.cygnus.com>
94
95 * v850_sim.h (State): New slots dummy_mem, pending_nmi.
96 (EIPC, etc): New macros for system registers.
97 * simops.c, interp.c: Use everywhere.
98
99 * interp.c: Add support for interrupts issued by interrupt
100 generators, either PC- or time-based. Controlled by simulator
101 command "sim interrupt".
102
103 * interp.c: Add support for variable-size allocation of memory,
104 via simulator command "sim memory-map".
105 (map): Issue SIGSEGV for references to invalid memory regions.
106
7fc45edb
GRK
107Thu Oct 31 14:44:10 1996 Gavin Koch <gavin@cygnus.com>
108
109 * simops.c: Include <sys/time.h> for struct timeval and
110 struct timezone.
111
6803f89b
JL
112Wed Oct 30 08:49:10 1996 Jeffrey A Law (law@cygnus.com)
113
8824fb45
JL
114 * simops.c (OP_10007E0): Handle SYS_times and SYS_gettimeofday.
115
6803f89b
JL
116 * simops.c (OP_10007E0): Handle SYS_time.
117
c500c074
JL
118Tue Oct 29 14:22:55 1996 Jeffrey A Law (law@cygnus.com)
119
120 * simops.c: Include <sys/stat.h>.
121 (OP_10007E0): Handle SYS_stat.
122
0a89af6e
JL
123Thu Oct 24 12:26:35 1996 Jeffrey A Law (law@cygnus.com)
124
c500c074
JL
125 * simops.c (OP_10007E0): Don't declare errno.
126
f0099789
JL
127 * simops.c (OP_500): Mask off low bit in displacement
128 for sld.w.
129 (OP_501): Similarly.
130
85c09b05
JL
131 * simops.c (OP_500): Fix displacement handling for sld.w.
132 (OP_501): Similarly for sst.w.
133
0a89af6e
JL
134 * simops.c (trace_input): Remove all references to SEXT7.
135 (OP_300, OP_400, OP_500, OP_380, OP_480, OP_501): Displacement
136 is zero extended for sst/sld instructions.
137 * v850_sim.h (SEX7): Delete. It's no longer needed (and it
138 was incorrect anyway).
139
96851909
SG
140Thu Oct 24 10:33:33 1996 Stu Grossman (grossman@critters.cygnus.com)
141
142 * Makefile.in: Get rid of srcroot. Set all INSTALL macros via
143 autoconf.
144 * gencode.c (write_opcodes): Pad operands field to account for
145 MSVC braindamage.
146 * simops.c: Include errno.h. Exclude SYS_chown, since MSVC
147 doesn't support it. (Why is this here in the first place?!?)
148 * v850_sim.h: Get rid of 64 bit defs. Also, get rid of #elif's.
149 Change number of operands in struct simops from 9 to 6. Define
150 SIGTRAP and SIGQUIT for MSVC.
151
254ef340
SG
152Tue Oct 15 16:19:51 1996 Stu Grossman (grossman@critters.cygnus.com)
153
154 * interp.c (MEM_SIZE): It's now bytes, not a power of 2.
155 * (map): Add support for external mem in the 1->2 meg range.
156 Also, abort() when memory access is way out of bounds. (Better to
157 die than to give wrong result. (This will be fixed later.))
158 * (sim_size): MEM_SIZE is now bytes, not shift factor.
159
160Tue Oct 1 15:53:24 1996 Gavin Koch <gavin@cygnus.com>
161
162 * simops.c (trace_input): Swapped order of operands for output
163 output of OP_IMM_REG. Changed the fetching of the operands for
164 OP_LOAD32, and OP_STORE32 to work like op-function.
165
166Mon Sep 30 15:46:33 1996 Stu Grossman (grossman@critters.cygnus.com)
167
168 * interp.c: Move includes of remote-sim.h and callback.h to
169 v850-sim.h.
170 * (lookup_hash): Add PC to report of hash failure.
171 * (map load_mem store_mem): New memory subsystem. Models V851
172 memory system.
173 * (sim_write sim_read): Use new memory subsystem.
174 * (sim_resume): Don't load and save PC into EIPC anymore. Needed
175 to make user-defined traps work right.
176 * simops.c (OP_*): Use new memory subsystem.
177 * (OP_14007E0 (reti)): Implement reti.
178 * (OP_14996E0 (trap)): Implement user-defined traps. Move I/O to
179 trap 31. Use new memory subsystem.
180 * v850_sim.h: Prototypes for load_mem, store_mem and map. Use
181 load_mem in RLW macro.
182
88777ce2
SG
183Fri Sep 27 18:34:09 1996 Stu Grossman (grossman@critters.cygnus.com)
184
185 * gencode.c (write_opcodes): Output hex values for opcode mask
186 and patterns.
187 * interp.c (sim_resume): Save and restore PC from the appropriate
188 register.
189 * (sim_fetch_register sim_store_register): Fix byte-order problem
190 with reading and writing registers.
191 * simops.c (OP_FFFF): Implement pseudo-breakpoint insn.
192
da86a4fa
JL
193Fri Sep 27 17:42:37 1996 Jeffrey A Law (law@cygnus.com)
194
195 * simops.c (trace_input): Fix thinko.
196
197Wed Sep 18 09:54:12 1996 Michael Meissner <meissner@tiktok.cygnus.com>
198
199 * simops.c (exec_bfd): Rename from sim_bfd.
200 (trace_input): Ditto.
201
1d00ce83
MM
202Thu Sep 12 12:03:05 1996 Michael Meissner <meissner@tiktok.cygnus.com>
203
204 * simops.c (trace_input): Use find_nearest_line to print line
205 number, function name or file name of PC.
206
ead4a3f1
MM
207Wed Sep 11 16:44:37 1996 Michael Meissner <meissner@tiktok.cygnus.com>
208
209 * simops.c: Add tracing support. Use SEXTxx macros instead of
210 doing hardwired shifts.
211
212 * configure.in (--enable-sim-cflags): Add switch to add additional
213 flags to simulator buld. If --enable-sim-cflags=trace, turn on
214 tracing.
215 * configure: Regenerate.
216
217 * Makefile.in: Don't require a VPATH capable make if configuring
218 in the same directory. Don't use CFLAGS for configuration flags.
219 Add flags from --enable-sim-cflags. Support canadian cross
220 builds. Rebuild whole simulator if include files change.
221
222 * interp.c (v850_debug): New global for debugging.
223 (lookup_hash,sim_size,sim_set_profile): Use
224 printf_filtered callback, instead of calling printf directly.
225 (sim_{open,trace}): Enable tracing if -t and compiled for tracing.
226
227 * v850_sim.h: Use limits.h to set the various sized types.
228 (SEXT{5,7,16,22}): New macros.
229
9909e232
JL
230Mon Sep 9 20:50:46 1996 Jeffrey A Law (law@cygnus.com)
231
232 * interp.c (hash): Make this an inline function
233 when compiling with GCC. Simplify.
234 * simpos.c: Explicitly include "sys/syscall.h". Remove
235 some #if 0'd code. Enable more emulated syscalls.
236
237Wed Sep 4 01:48:55 1996 Jeffrey A Law (law@cygnus.com)
238
239 * interp.c: Fix sign bit handling for add and sub instructions.
240
d81352b8
JL
241Tue Sep 3 10:20:30 1996 Jeffrey A Law (law@cygnus.com)
242
9fca2fd3
JL
243 * gencode.c: Fix various indention & style problems.
244 Remove test code. Remove #if 0 code.
245 * interp.c: Provide prototypes for all static functions.
246 Fix minor indention problems.
247 (sim_open, sim_resume): Remove unused variables.
248 (sim_read): Return type is "int".
249 * simops.c: Remove unused variables.
250 (divh): Make result of divide-by-zero zero.
251 (setf): Initialize result to keep compiler quiet.
252 (sar instructions): These just clear the overflow bit.
253 * v850_sim.h: Provide prototypes for put_byte, put_half
254 and put_word.
255
d81352b8
JL
256 * interp.c: OP should be an array of 32bit operands!
257 (v850_callback): Declare.
258 (do_format_5): Fix extraction of OP[0].
259 (sim_size): Remove debugging printf.
260 (sim_set_callbacks): Do something useful.
261 (sim_stop_reason): Gross hacks to get c-torture running.
262 * simops.c: Simplify code for computing targets of bCC
263 insns. Invert 's' bit if 'ov' bit is set for some
264 instructions. Fix 'cy' bit handling for numerous
265 instructions. Make the simulator stop when a halt
266 instruction is encountered. Very crude support for
267 emulated syscalls (trap 0).
268 * v850_sim.h: Include "callback.h" and declare
269 v850_callback. Items in the operand array are 32bits.
270
271Sun Sep 1 22:35:35 1996 Jeffrey A Law (law@cygnus.com)
272
273 * interp.c (sim_resume): Fix code to check for a format 3
274 opcode.
275 * simops.c: bCC insns only argument is a constant, not a
276 register value (duh...)
277
83fc3bac
JL
278Fri Aug 30 10:33:49 1996 Jeffrey A Law (law@cygnus.com)
279
787d66bb
JL
280 * simops.c: Fix "not1" and "set1".
281
3046d879
JL
282 * simops.c: Don't forget to initialize temp for
283 "ld.h" and "ld.w"
284
ba853302
JL
285 * interp.c: Remove various debugging printfs.
286
0e4ccc58
JL
287 * simops.c: Fix satadd, satsub boundary case handling.
288
83fc3bac
JL
289 * interp.c (hash): Fix.
290 * interp.c (do_format_8): Get operands correctly and
291 call the target function.
292 * simops.c: Rough cut at "clr1", "not1", "set1", and "tst1".
293
1fe983dc
JL
294Thu Aug 29 13:53:29 1996 Jeffrey A Law (law@cygnus.com)
295
3cb6bf78
JL
296 * interp.c (do_format_4): Get operands correctly and
297 call the target function.
298 * simops.c: Rough cut at "sld.b", "sld.h", "sld.w", "sst.b",
299 "sst.h", and "sst.w".
300
28647e4c
JL
301 * v850_sim.h: The V850 doesn't have split I&D spaces. Change
302 accordingly. Remove many unused definitions.
303 * interp.c: The V850 doesn't have split I&D spaces. Change
304 accordingly.
305 (get_longlong, get_longword, get_word): Deleted.
306 (write_longlong, write_longword, write_word): Deleted.
307 (get_operands): Deleted.
308 (get_byte, get_half, get_word): New functions.
309 (put_byte, put_half, put_word): New functions.
310 * simops.c: Remove unused functions. Rough cut at
311 "ld.b", "ld.h", "ld.w", "st.b", "st.h", "st.w" insns.
312
614f1c68
JL
313 * v850_sim.h (struct _state): Remove "psw" field. Add
314 "sregs" field.
315 (PSW): Remove bogus definition.
316 * simops.c: Change condition code handling to use the psw
317 register within the sregs array. Handle "ldsr" and "stsr".
318
dca41ba7
JL
319 * simops.c: Handle "satadd", "satsub", "satsubi", "satsubr".
320
e9b6cbac
JL
321 * interp.c (do_format_5): Get operands correctly and
322 call the target function.
323 (sim_resume): Don't do a PC update for format 5 instructions.
324 * simops.c: Handle "jarl" and "jmp" instructions.
325
3095b8df
JL
326 * simops.c: Fix minor typos. Handle "cmp", "setf", "tst"
327 "di", and "ei" instructions correctly.
328
2108e864
JL
329 * interp.c (do_format_3): Get operands correctly and call
330 the target function.
331 * simops.c: Handle bCC instructions.
332
35404c7d
JL
333 * simops.c: Add condition code handling to shift insns.
334 Fix minor typos in condition code handling for other insns.
335
aabce0f4
JL
336 * Makefile.in: Fix typo.
337 * simops.c: Add condition code handling to "sub" "subr" and
338 "divh" instructions.
339
0ef0eba5
JL
340 * interp.c (hash): Update to be more accurate.
341 (lookup_hash): Call hash rather than computing the hash
342 code here.
343 (do_format_1_2): Handle format 1 and format 2 instructions.
344 Get operands correctly and call the target function.
345 (do_format_6): Get operands correctly and call the target
346 function.
347 (do_formats_9_10): Rough cut so shift ops will work.
348 (sim_resume): Tweak to deal with format 1 and format 2
349 handling in a single funtion. Don't update the PC
350 for format 3 insns. Fix typos.
351 * simops.c: Slightly reorganize. Add condition code handling
352 to "add", "addi", "and", "andi", "or", "ori", "xor", "xori"
353 and "not" instructions.
354 * v850_sim.h (reg_t): Registers are 32bits.
355 (_state): The V850 has 32 general registers. Add a 32bit
356 psw and pc register too. Add accessor macros
357
358 * Makefile.in, interp.c, v850_sim.h: Bring over endianness
359 changes from the d10v simulator.
360
77553374
JL
361 * simops.c: Add shift support.
362
e98e3b2c
JL
363 * simops.c: Add multiply & divide support. Abort for system
364 instructions.
365
1fe983dc
JL
366 * simops.c: Add logicals, mov, movhi, movea, add, addi, sub
367 and subr. No condition codes yet.
368
22c1c7dd
JL
369Wed Aug 28 13:53:22 1996 Jeffrey A Law (law@cygnus.com)
370
371 * ChangeLog, Makefile.in, configure, configure.in, v850_sim.h,
372 gencode.c, interp.c, simops.c: Created.
373