[thirdparty/binutils-gdb.git] / sim / v850 / sim-main.h

#ifndef SIM_MAIN_H
#define SIM_MAIN_H

/* General config options */

#define WITH_CORE
#define WITH_MODULO_MEMORY 1
#define WITH_WATCHPOINTS 1


/* The v850 has 32bit words, numbered 31 (MSB) to 0 (LSB) */

#define WITH_TARGET_WORD_MSB 31

#include "config.h"
#include "sim-basics.h"
#include "sim-signal.h"
#include "sim-fpu.h"

typedef address_word sim_cia;

typedef struct _sim_cpu SIM_CPU;

#include "sim-base.h"

#include "simops.h"
#include "bfd.h"


typedef signed8 int8;
typedef unsigned8 uint8;
typedef signed16 int16;
typedef unsigned16 uint16;
typedef signed32 int32;
typedef unsigned32 uint32;
typedef unsigned32 reg_t;
typedef unsigned64 reg64_t;


/* The current state of the processor; registers, memory, etc.  */

typedef struct _v850_regs {
  reg_t regs[32];		/* general-purpose registers */
  reg_t sregs[32];		/* system registers, including psw */
  reg_t pc;
  int dummy_mem;                /* where invalid accesses go */
  reg_t mpu0_sregs[28];         /* mpu0 system registers */
  reg_t mpu1_sregs[28];         /* mpu1 system registers */
  reg_t fpu_sregs[28];          /* fpu system registers */
  reg_t selID_sregs[7][32];	/* system registers, selID 1 thru selID 7 */
  reg64_t vregs[32];		/* vector registers.  */
} v850_regs;

struct _sim_cpu
{
  /* ... simulator specific members ... */
  v850_regs reg;
  reg_t psw_mask;               /* only allow non-reserved bits to be set */
  sim_event *pending_nmi;
  /* ... base type ... */
  sim_cpu_base base;
};

#define CIA_GET(CPU) ((CPU)->reg.pc + 0)
#define CIA_SET(CPU,VAL) ((CPU)->reg.pc = (VAL))

struct sim_state {
  sim_cpu *cpu[MAX_NR_PROCESSORS];
#if (WITH_SMP)
#define STATE_CPU(sd,n) ((sd)->cpu[n])
#else
#define STATE_CPU(sd,n) ((sd)->cpu[0])
#endif
#if 0
  SIM_ADDR rom_size;
  SIM_ADDR low_end;
  SIM_ADDR high_start;
  SIM_ADDR high_base;
  void *mem;
#endif
  sim_state_base base;
};

/* For compatibility, until all functions converted to passing
   SIM_DESC as an argument */
extern SIM_DESC simulator;


#define V850_ROM_SIZE 0x8000
#define V850_LOW_END 0x200000
#define V850_HIGH_START 0xffe000


/* Because we are still using the old semantic table, provide compat
   macro's that store the instruction where the old simops expects
   it. */

extern uint32 OP[4];
#if 0
OP[0] = inst & 0x1f;           /* RRRRR -> reg1 */
OP[1] = (inst >> 11) & 0x1f;   /* rrrrr -> reg2 */
OP[2] = (inst >> 16) & 0xffff; /* wwwww -> reg3 OR imm16 */
OP[3] = inst;
#endif

#define SAVE_1 \
PC = cia; \
OP[0] = instruction_0 & 0x1f; \
OP[1] = (instruction_0 >> 11) & 0x1f; \
OP[2] = 0; \
OP[3] = instruction_0

#define COMPAT_1(CALL) \
SAVE_1; \
PC += (CALL); \
nia = PC

#define SAVE_2 \
PC = cia; \
OP[0] = instruction_0 & 0x1f; \
OP[1] = (instruction_0 >> 11) & 0x1f; \
OP[2] = instruction_1; \
OP[3] = (instruction_1 << 16) | instruction_0

#define COMPAT_2(CALL) \
SAVE_2; \
PC += (CALL); \
nia = PC


/* new */
#define GR  ((CPU)->reg.regs)
#define SR  ((CPU)->reg.sregs)
#define VR  ((CPU)->reg.vregs)
#define MPU0_SR  ((STATE_CPU (sd, 0))->reg.mpu0_sregs)
#define MPU1_SR  ((STATE_CPU (sd, 0))->reg.mpu1_sregs)
#define FPU_SR   ((STATE_CPU (sd, 0))->reg.fpu_sregs)

/* old */
#define State    (STATE_CPU (simulator, 0)->reg)
#define PC	(State.pc)
#define SP_REGNO        3
#define SP      (State.regs[SP_REGNO])
#define EP	(State.regs[30])

#define EIPC  (State.sregs[0])
#define EIPSW (State.sregs[1])
#define FEPC  (State.sregs[2])
#define FEPSW (State.sregs[3])
#define ECR   (State.sregs[4])
#define PSW   (State.sregs[5])
#define PSW_REGNO   5
#define EIIC  (State.sregs[13])
#define FEIC  (State.sregs[14])
#define DBIC  (SR[15])
#define CTPC  (SR[16])
#define CTPSW (SR[17])
#define DBPC  (State.sregs[18])
#define DBPSW (State.sregs[19])
#define CTBP  (State.sregs[20])
#define DIR   (SR[21])
#define EIWR  (SR[28])
#define FEWR  (SR[29])
#define DBWR  (SR[30])
#define BSEL  (SR[31])

#define PSW_US BIT32 (8)
#define PSW_NP 0x80
#define PSW_EP 0x40
#define PSW_ID 0x20
#define PSW_SAT 0x10
#define PSW_CY 0x8
#define PSW_OV 0x4
#define PSW_S 0x2
#define PSW_Z 0x1

#define PSW_NPV	(1<<18)
#define PSW_DMP	(1<<17)
#define PSW_IMP	(1<<16)

#define ECR_EICC 0x0000ffff
#define ECR_FECC 0xffff0000

/* FPU */

#define FPSR  (FPU_SR[6])
#define FPSR_REGNO 6
#define FPEPC (FPU_SR[7])
#define FPST  (FPU_SR[8])
#define FPST_REGNO 8
#define FPCC  (FPU_SR[9])
#define FPCFG (FPU_SR[10])
#define FPCFG_REGNO 10

#define FPSR_DEM  0x00200000
#define FPSR_SEM  0x00100000
#define FPSR_RM   0x000c0000
#define FPSR_RN   0x00000000
#define FPSR_FS   0x00020000
#define FPSR_PR   0x00010000

#define FPSR_XC   0x0000fc00
#define FPSR_XCE  0x00008000
#define FPSR_XCV  0x00004000
#define FPSR_XCZ  0x00002000
#define FPSR_XCO  0x00001000
#define FPSR_XCU  0x00000800
#define FPSR_XCI  0x00000400

#define FPSR_XE   0x000003e0
#define FPSR_XEV  0x00000200
#define FPSR_XEZ  0x00000100
#define FPSR_XEO  0x00000080
#define FPSR_XEU  0x00000040
#define FPSR_XEI  0x00000020

#define FPSR_XP   0x0000001f
#define FPSR_XPV  0x00000010
#define FPSR_XPZ  0x00000008
#define FPSR_XPO  0x00000004
#define FPSR_XPU  0x00000002
#define FPSR_XPI  0x00000001

#define FPST_PR   0x00008000 
#define FPST_XCE  0x00002000 
#define FPST_XCV  0x00001000 
#define FPST_XCZ  0x00000800 
#define FPST_XCO  0x00000400 
#define FPST_XCU  0x00000200 
#define FPST_XCI  0x00000100 

#define FPST_XPV  0x00000010 
#define FPST_XPZ  0x00000008 
#define FPST_XPO  0x00000004 
#define FPST_XPU  0x00000002 
#define FPST_XPI  0x00000001 

#define FPCFG_RM   0x00000180 
#define FPCFG_XEV  0x00000010 
#define FPCFG_XEZ  0x00000008 
#define FPCFG_XEO  0x00000004 
#define FPCFG_XEU  0x00000002 
#define FPCFG_XEI  0x00000001 

#define GET_FPCC()\
 ((FPSR >> 24) &0xf)

#define CLEAR_FPCC(bbb)\
  (FPSR &= ~(1 << (bbb+24)))

#define SET_FPCC(bbb)\
 (FPSR |= 1 << (bbb+24))

#define TEST_FPCC(bbb)\
  ((FPSR & (1 << (bbb+24))) != 0)

#define FPSR_GET_ROUND()					\
  (((FPSR & FPSR_RM) == FPSR_RN) ? sim_fpu_round_near		\
   : ((FPSR & FPSR_RM) == 0x00040000) ? sim_fpu_round_up	\
   : ((FPSR & FPSR_RM) == 0x00080000) ? sim_fpu_round_down	\
   : sim_fpu_round_zero)


enum FPU_COMPARE {
  FPU_CMP_F = 0,
  FPU_CMP_UN,
  FPU_CMP_EQ,
  FPU_CMP_UEQ,
  FPU_CMP_OLT,
  FPU_CMP_ULT,
  FPU_CMP_OLE,
  FPU_CMP_ULE,
  FPU_CMP_SF,
  FPU_CMP_NGLE,
  FPU_CMP_SEQ,
  FPU_CMP_NGL,
  FPU_CMP_LT,
  FPU_CMP_NGE,
  FPU_CMP_LE,
  FPU_CMP_NGT
};


/* MPU */
#define MPM	(MPU1_SR[0])
#define MPC	(MPU1_SR[1])
#define MPC_REGNO 1
#define TID	(MPU1_SR[2])
#define PPA	(MPU1_SR[3])
#define PPM	(MPU1_SR[4])
#define PPC	(MPU1_SR[5])
#define DCC	(MPU1_SR[6])
#define DCV0	(MPU1_SR[7])
#define DCV1	(MPU1_SR[8])
#define SPAL	(MPU1_SR[10])
#define SPAU	(MPU1_SR[11])
#define IPA0L	(MPU1_SR[12])
#define IPA0U	(MPU1_SR[13])
#define IPA1L	(MPU1_SR[14])
#define IPA1U	(MPU1_SR[15])
#define IPA2L	(MPU1_SR[16])
#define IPA2U	(MPU1_SR[17])
#define IPA3L	(MPU1_SR[18])
#define IPA3U	(MPU1_SR[19])
#define DPA0L	(MPU1_SR[20])
#define DPA0U	(MPU1_SR[21])
#define DPA1L	(MPU1_SR[22])
#define DPA1U	(MPU1_SR[23])
#define DPA2L	(MPU1_SR[24])
#define DPA2U	(MPU1_SR[25])
#define DPA3L	(MPU1_SR[26])
#define DPA3U	(MPU1_SR[27])

#define PPC_PPE 0x1
#define SPAL_SPE 0x1
#define SPAL_SPS 0x10

#define VIP	(MPU0_SR[0])
#define VMECR	(MPU0_SR[4])
#define VMTID	(MPU0_SR[5])
#define VMADR	(MPU0_SR[6])
#define VPECR	(MPU0_SR[8])
#define VPTID	(MPU0_SR[9])
#define VPADR	(MPU0_SR[10])
#define VDECR	(MPU0_SR[12])
#define VDTID	(MPU0_SR[13])

#define MPM_AUE	0x2
#define MPM_MPE	0x1

#define VMECR_VMX   0x2
#define VMECR_VMR   0x4
#define VMECR_VMW   0x8
#define VMECR_VMS   0x10
#define VMECR_VMRMW 0x20
#define VMECR_VMMS  0x40

#define IPA2ADDR(IPA)	((IPA) & 0x1fffff80)
#define IPA_IPE	0x1 
#define IPA_IPX	0x2 
#define IPA_IPR	0x4 
#define IPE0	(IPA0L & IPA_IPE)
#define IPE1	(IPA1L & IPA_IPE)
#define IPE2	(IPA2L & IPA_IPE)
#define IPE3	(IPA3L & IPA_IPE)
#define IPX0	(IPA0L & IPA_IPX)
#define IPX1	(IPA1L & IPA_IPX)
#define IPX2	(IPA2L & IPA_IPX)
#define IPX3	(IPA3L & IPA_IPX)
#define IPR0	(IPA0L & IPA_IPR)
#define IPR1	(IPA1L & IPA_IPR)
#define IPR2	(IPA2L & IPA_IPR)
#define IPR3	(IPA3L & IPA_IPR)

#define DPA2ADDR(DPA)	((DPA) & 0x1fffff80)
#define DPA_DPE 0x1	
#define DPA_DPR 0x4	
#define DPA_DPW 0x8	
#define DPE0	(DPA0L & DPA_DPE)
#define DPE1	(DPA1L & DPA_DPE)
#define DPE2	(DPA2L & DPA_DPE)
#define DPE3	(DPA3L & DPA_DPE)
#define DPR0	(DPA0L & DPA_DPR)
#define DPR1	(DPA1L & DPA_DPR)
#define DPR2	(DPA2L & DPA_DPR)
#define DPR3	(DPA3L & DPA_DPR)
#define DPW0	(DPA0L & DPA_DPW)
#define DPW1	(DPA1L & DPA_DPW)
#define DPW2	(DPA2L & DPA_DPW)
#define DPW3	(DPA3L & DPA_DPW)

#define DCC_DCE0 0x1
#define DCC_DCE1 0x10000

#define PPA2ADDR(PPA)	((PPA) & 0x1fffff80) 
#define PPC_PPC 0xfffffffe
#define PPC_PPE 0x1
#define PPC_PPM 0x0000fff8


#define SEXT3(x)	((((x)&0x7)^(~0x3))+0x4)	

/* sign-extend a 4-bit number */
#define SEXT4(x)	((((x)&0xf)^(~0x7))+0x8)	

/* sign-extend a 5-bit number */
#define SEXT5(x)	((((x)&0x1f)^(~0xf))+0x10)	

/* sign-extend a 9-bit number */
#define SEXT9(x)	((((x)&0x1ff)^(~0xff))+0x100)

/* sign-extend a 22-bit number */
#define SEXT22(x)	((((x)&0x3fffff)^(~0x1fffff))+0x200000)

/* sign extend a 40 bit number */
#define SEXT40(x)	((((x) & UNSIGNED64 (0xffffffffff)) \
			  ^ (~UNSIGNED64 (0x7fffffffff))) \
			 + UNSIGNED64 (0x8000000000))

/* sign extend a 44 bit number */
#define SEXT44(x)	((((x) & UNSIGNED64 (0xfffffffffff)) \
			  ^ (~ UNSIGNED64 (0x7ffffffffff))) \
			 + UNSIGNED64 (0x80000000000))

/* sign extend a 60 bit number */
#define SEXT60(x)	((((x) & UNSIGNED64 (0xfffffffffffffff)) \
			  ^ (~ UNSIGNED64 (0x7ffffffffffffff))) \
			 + UNSIGNED64 (0x800000000000000))

/* No sign extension */
#define NOP(x)		(x)

#define INC_ADDR(x,i)	x = ((State.MD && x == MOD_E) ? MOD_S : (x)+(i))

#define RLW(x) load_mem (x, 4)

/* Function declarations.  */

#define IMEM16(EA) \
sim_core_read_aligned_2 (CPU, PC, exec_map, (EA))

#define IMEM16_IMMED(EA,N) \
sim_core_read_aligned_2 (STATE_CPU (sd, 0), \
			 PC, exec_map, (EA) + (N) * 2)

#define load_mem(ADDR,LEN) \
sim_core_read_unaligned_##LEN (STATE_CPU (simulator, 0), \
			       PC, read_map, (ADDR))

#define store_mem(ADDR,LEN,DATA) \
sim_core_write_unaligned_##LEN (STATE_CPU (simulator, 0), \
				PC, write_map, (ADDR), (DATA))


/* compare cccc field against PSW */
int condition_met (unsigned code);


/* Debug/tracing calls */

enum op_types
{
  OP_UNKNOWN,
  OP_NONE,
  OP_TRAP,
  OP_REG,
  OP_REG_REG,
  OP_REG_REG_CMP,
  OP_REG_REG_MOVE,
  OP_IMM_REG,
  OP_IMM_REG_CMP,
  OP_IMM_REG_MOVE,
  OP_COND_BR,
  OP_LOAD16,
  OP_STORE16,
  OP_LOAD32,
  OP_STORE32,
  OP_JUMP,
  OP_IMM_REG_REG,
  OP_UIMM_REG_REG,
  OP_IMM16_REG_REG,
  OP_UIMM16_REG_REG,
  OP_BIT,
  OP_EX1,
  OP_EX2,
  OP_LDSR,
  OP_STSR,
  OP_BIT_CHANGE,
  OP_REG_REG_REG,
  OP_REG_REG3,
  OP_IMM_REG_REG_REG,
  OP_PUSHPOP1,
  OP_PUSHPOP2,
  OP_PUSHPOP3,
};

#ifdef DEBUG
void trace_input (char *name, enum op_types type, int size);
void trace_output (enum op_types result);
void trace_result (int has_result, unsigned32 result);

extern int trace_num_values;
extern unsigned32 trace_values[];
extern unsigned32 trace_pc;
extern const char *trace_name;
extern int trace_module;

#define TRACE_BRANCH0() \
do { \
  if (TRACE_BRANCH_P (CPU)) { \
    trace_module = TRACE_BRANCH_IDX; \
    trace_pc = cia; \
    trace_name = itable[MY_INDEX].name; \
    trace_num_values = 0; \
    trace_result (1, (nia)); \
  } \
} while (0)

#define TRACE_BRANCH1(IN1) \
do { \
  if (TRACE_BRANCH_P (CPU)) { \
    trace_module = TRACE_BRANCH_IDX; \
    trace_pc = cia; \
    trace_name = itable[MY_INDEX].name; \
    trace_values[0] = (IN1); \
    trace_num_values = 1; \
    trace_result (1, (nia)); \
  } \
} while (0)

#define TRACE_BRANCH2(IN1, IN2) \
do { \
  if (TRACE_BRANCH_P (CPU)) { \
    trace_module = TRACE_BRANCH_IDX; \
    trace_pc = cia; \
    trace_name = itable[MY_INDEX].name; \
    trace_values[0] = (IN1); \
    trace_values[1] = (IN2); \
    trace_num_values = 2; \
    trace_result (1, (nia)); \
  } \
} while (0)

#define TRACE_BRANCH3(IN1, IN2, IN3) \
do { \
  if (TRACE_BRANCH_P (CPU)) { \
    trace_module = TRACE_BRANCH_IDX; \
    trace_pc = cia; \
    trace_name = itable[MY_INDEX].name; \
    trace_values[0] = (IN1); \
    trace_values[1] = (IN2); \
    trace_values[2] = (IN3); \
    trace_num_values = 3; \
    trace_result (1, (nia)); \
  } \
} while (0)

#define TRACE_LD(ADDR,RESULT) \
do { \
  if (TRACE_MEMORY_P (CPU)) { \
    trace_module = TRACE_MEMORY_IDX; \
    trace_pc = cia; \
    trace_name = itable[MY_INDEX].name; \
    trace_values[0] = (ADDR); \
    trace_num_values = 1; \
    trace_result (1, (RESULT)); \
  } \
} while (0)

#define TRACE_LD_NAME(NAME, ADDR,RESULT) \
do { \
  if (TRACE_MEMORY_P (CPU)) { \
    trace_module = TRACE_MEMORY_IDX; \
    trace_pc = cia; \
    trace_name = (NAME); \
    trace_values[0] = (ADDR); \
    trace_num_values = 1; \
    trace_result (1, (RESULT)); \
  } \
} while (0)

#define TRACE_ST(ADDR,RESULT) \
do { \
  if (TRACE_MEMORY_P (CPU)) { \
    trace_module = TRACE_MEMORY_IDX; \
    trace_pc = cia; \
    trace_name = itable[MY_INDEX].name; \
    trace_values[0] = (ADDR); \
    trace_num_values = 1; \
    trace_result (1, (RESULT)); \
  } \
} while (0)

#define TRACE_FP_INPUT_FPU1(V0)	\
do { \
  if (TRACE_FPU_P (CPU)) \
    { \
      unsigned64 f0; \
      sim_fpu_to64 (&f0, (V0)); \
      trace_input_fp1 (SD, CPU, TRACE_FPU_IDX, f0); \
    } \
} while (0)

#define TRACE_FP_INPUT_FPU2(V0, V1) \
do { \
  if (TRACE_FPU_P (CPU)) \
    { \
      unsigned64 f0, f1; \
      sim_fpu_to64 (&f0, (V0)); \
      sim_fpu_to64 (&f1, (V1)); \
      trace_input_fp2 (SD, CPU, TRACE_FPU_IDX, f0, f1);	\
    } \
} while (0)

#define TRACE_FP_INPUT_FPU3(V0, V1, V2) \
do { \
  if (TRACE_FPU_P (CPU)) \
    { \
      unsigned64 f0, f1, f2; \
      sim_fpu_to64 (&f0, (V0)); \
      sim_fpu_to64 (&f1, (V1)); \
      sim_fpu_to64 (&f2, (V2)); \
      trace_input_fp3 (SD, CPU, TRACE_FPU_IDX, f0, f1, f2); \
    } \
} while (0)

#define TRACE_FP_INPUT_BOOL1_FPU2(V0, V1, V2) \
do { \
  if (TRACE_FPU_P (CPU)) \
    { \
      int d0 = (V0); \
      unsigned64 f1, f2; \
      TRACE_DATA *data = CPU_TRACE_DATA (CPU); \
      TRACE_IDX (data) = TRACE_FPU_IDX;	\
      sim_fpu_to64 (&f1, (V1)); \
      sim_fpu_to64 (&f2, (V2)); \
      save_data (SD, data, trace_fmt_bool, sizeof (d0), &d0); \
      save_data (SD, data, trace_fmt_fp, sizeof (fp_word), &f1); \
      save_data (SD, data, trace_fmt_fp, sizeof (fp_word), &f2); \
    } \
} while (0)

#define TRACE_FP_INPUT_WORD2(V0, V1) \
do { \
  if (TRACE_FPU_P (CPU)) \
    trace_input_word2 (SD, CPU, TRACE_FPU_IDX, (V0), (V1)); \
} while (0)

#define TRACE_FP_RESULT_FPU1(R0) \
do { \
  if (TRACE_FPU_P (CPU)) \
    { \
      unsigned64 f0; \
      sim_fpu_to64 (&f0, (R0));	\
      trace_result_fp1 (SD, CPU, TRACE_FPU_IDX, f0); \
    } \
} while (0)

#define TRACE_FP_RESULT_WORD1(R0) TRACE_FP_RESULT_WORD(R0)

#define TRACE_FP_RESULT_WORD2(R0, R1) \
do { \
  if (TRACE_FPU_P (CPU)) \
    trace_result_word2 (SD, CPU, TRACE_FPU_IDX, (R0), (R1)); \
} while (0)

#else
#define trace_input(NAME, IN1, IN2)
#define trace_output(RESULT)
#define trace_result(HAS_RESULT, RESULT)

#define TRACE_ALU_INPUT0()
#define TRACE_ALU_INPUT1(IN0)
#define TRACE_ALU_INPUT2(IN0, IN1)
#define TRACE_ALU_INPUT2(IN0, IN1)
#define TRACE_ALU_INPUT2(IN0, IN1 INS2)
#define TRACE_ALU_RESULT(RESULT)

#define TRACE_BRANCH0()
#define TRACE_BRANCH1(IN1)
#define TRACE_BRANCH2(IN1, IN2)
#define TRACE_BRANCH2(IN1, IN2, IN3)

#define TRACE_LD(ADDR,RESULT)
#define TRACE_ST(ADDR,RESULT)

#endif

#define GPR_SET(N, VAL) (State.regs[(N)] = (VAL))
#define GPR_CLEAR(N)    (State.regs[(N)] = 0)

extern void divun ( unsigned int       N,
		    unsigned long int  als,
		    unsigned long int  sfi,
		    unsigned32 /*unsigned long int*/ *  quotient_ptr,
		    unsigned32 /*unsigned long int*/ *  remainder_ptr,
		    int *overflow_ptr
		    );
extern void divn ( unsigned int       N,
		   unsigned long int  als,
		   unsigned long int  sfi,
		   signed32 /*signed long int*/ *  quotient_ptr,
		   signed32 /*signed long int*/ *  remainder_ptr,
		   int *overflow_ptr
		   );
extern int type1_regs[];
extern int type2_regs[];
extern int type3_regs[];

#define SESR_OV   (1 << 0)
#define SESR_SOV  (1 << 1)

#define SESR      (State.sregs[12])

#define ROUND_Q62_Q31(X) ((((X) + (1 << 30)) >> 31) & 0xffffffff)
#define ROUND_Q62_Q15(X) ((((X) + (1 << 30)) >> 47) & 0xffff)
#define ROUND_Q31_Q15(X) ((((X) + (1 << 15)) >> 15) & 0xffff)
#define ROUND_Q30_Q15(X) ((((X) + (1 << 14)) >> 15) & 0xffff)

#define SAT16(X)			\
  do					\
    {					\
      signed64 z = (X);			\
      if (z > 0x7fff)			\
	{				\
	  SESR |= SESR_OV | SESR_SOV;	\
	  z = 0x7fff;			\
	}				\
      else if (z < -0x8000)		\
	{				\
	  SESR |= SESR_OV | SESR_SOV;	\
	  z = - 0x8000;			\
	}				\
      (X) = z;				\
    }					\
  while (0)

#define SAT32(X)			\
  do					\
    {					\
      signed64 z = (X);			\
      if (z > 0x7fffffff)		\
	{				\
	  SESR |= SESR_OV | SESR_SOV;	\
	  z = 0x7fffffff;		\
	}				\
      else if (z < -0x80000000)		\
	{				\
	  SESR |= SESR_OV | SESR_SOV;	\
	  z = - 0x80000000;		\
	}				\
      (X) = z;				\
    }					\
  while (0)

#define ABS16(X)			\
  do					\
    {					\
      signed64 z = (X) & 0xffff;	\
      if (z == 0x8000)			\
	{				\
	  SESR |= SESR_OV | SESR_SOV;	\
	  z = 0x7fff;			\
	}				\
      else if (z & 0x8000)		\
	{				\
	  z = (- z) & 0xffff;		\
	}				\
      (X) = z;				\
    }					\
  while (0)

#define ABS32(X)			\
  do					\
    {					\
      signed64 z = (X) & 0xffffffff;	\
      if (z == 0x80000000)		\
	{				\
	  SESR |= SESR_OV | SESR_SOV;	\
	  z = 0x7fffffff;		\
	}				\
      else if (z & 0x80000000)		\
	{				\
	  z = (- z) & 0xffffffff;	\
	}				\
      (X) = z;				\
    }					\
  while (0)

#endif
Commit	Line	Data
c906108c SS	1	#ifndef SIM_MAIN_H
	2	#define SIM_MAIN_H
	3
	4	/* General config options */
	5
	6	#define WITH_CORE
	7	#define WITH_MODULO_MEMORY 1
	8	#define WITH_WATCHPOINTS 1
	9
	10
	11	/* The v850 has 32bit words, numbered 31 (MSB) to 0 (LSB) */
	12
	13	#define WITH_TARGET_WORD_MSB 31
	14
a3976a7c	15	#include "config.h"
c906108c SS	16	#include "sim-basics.h"
c906108c SS	17	#include "sim-signal.h"
2aaed979	18	#include "sim-fpu.h"
c906108c SS	19
	20	typedef address_word sim_cia;
	21
14c9ad2e MF	22	typedef struct _sim_cpu SIM_CPU;
14c9ad2e MF	23
c906108c SS	24	#include "sim-base.h"
	25
	26	#include "simops.h"
	27	#include "bfd.h"
	28
	29
	30	typedef signed8 int8;
	31	typedef unsigned8 uint8;
	32	typedef signed16 int16;
	33	typedef unsigned16 uint16;
	34	typedef signed32 int32;
	35	typedef unsigned32 uint32;
	36	typedef unsigned32 reg_t;
a3976a7c	37	typedef unsigned64 reg64_t;
c906108c SS	38
	39
	40	/* The current state of the processor; registers, memory, etc. */
	41
	42	typedef struct _v850_regs {
	43	reg_t regs[32]; /* general-purpose registers */
	44	reg_t sregs[32]; /* system registers, including psw */
	45	reg_t pc;
2aaed979 KB	46	int dummy_mem; /* where invalid accesses go */
	47	reg_t mpu0_sregs[28]; /* mpu0 system registers */
	48	reg_t mpu1_sregs[28]; /* mpu1 system registers */
	49	reg_t fpu_sregs[28]; /* fpu system registers */
a3976a7c NC	50	reg_t selID_sregs[7][32]; /* system registers, selID 1 thru selID 7 */
a3976a7c NC	51	reg64_t vregs[32]; /* vector registers. */
c906108c SS	52	} v850_regs;
	53
	54	struct _sim_cpu
	55	{
	56	/* ... simulator specific members ... */
	57	v850_regs reg;
	58	reg_t psw_mask; /* only allow non-reserved bits to be set */
	59	sim_event *pending_nmi;
	60	/* ... base type ... */
	61	sim_cpu_base base;
	62	};
	63
	64	#define CIA_GET(CPU) ((CPU)->reg.pc + 0)
	65	#define CIA_SET(CPU,VAL) ((CPU)->reg.pc = (VAL))
	66
	67	struct sim_state {
14c9ad2e	68	sim_cpu *cpu[MAX_NR_PROCESSORS];
c906108c	69	#if (WITH_SMP)
14c9ad2e	70	#define STATE_CPU(sd,n) ((sd)->cpu[n])
c906108c	71	#else
14c9ad2e	72	#define STATE_CPU(sd,n) ((sd)->cpu[0])
c906108c SS	73	#endif
	74	#if 0
	75	SIM_ADDR rom_size;
	76	SIM_ADDR low_end;
	77	SIM_ADDR high_start;
	78	SIM_ADDR high_base;
	79	void *mem;
	80	#endif
	81	sim_state_base base;
	82	};
	83
	84	/* For compatibility, until all functions converted to passing
	85	SIM_DESC as an argument */
	86	extern SIM_DESC simulator;
	87
	88
	89	#define V850_ROM_SIZE 0x8000
	90	#define V850_LOW_END 0x200000
	91	#define V850_HIGH_START 0xffe000
	92
	93
	94	/* Because we are still using the old semantic table, provide compat
	95	macro's that store the instruction where the old simops expects
	96	it. */
	97
	98	extern uint32 OP[4];
	99	#if 0
	100	OP[0] = inst & 0x1f; /* RRRRR -> reg1 */
	101	OP[1] = (inst >> 11) & 0x1f; /* rrrrr -> reg2 */
	102	OP[2] = (inst >> 16) & 0xffff; /* wwwww -> reg3 OR imm16 */
	103	OP[3] = inst;
	104	#endif
	105
	106	#define SAVE_1 \
	107	PC = cia; \
	108	OP[0] = instruction_0 & 0x1f; \
	109	OP[1] = (instruction_0 >> 11) & 0x1f; \
	110	OP[2] = 0; \
	111	OP[3] = instruction_0
	112
	113	#define COMPAT_1(CALL) \
	114	SAVE_1; \
	115	PC += (CALL); \
	116	nia = PC
	117
	118	#define SAVE_2 \
	119	PC = cia; \
	120	OP[0] = instruction_0 & 0x1f; \
	121	OP[1] = (instruction_0 >> 11) & 0x1f; \
	122	OP[2] = instruction_1; \
	123	OP[3] = (instruction_1 << 16) \| instruction_0
	124
	125	#define COMPAT_2(CALL) \
	126	SAVE_2; \
	127	PC += (CALL); \
	128	nia = PC
	129
	130
	131	/* new */
	132	#define GR ((CPU)->reg.regs)
	133	#define SR ((CPU)->reg.sregs)
a3976a7c	134	#define VR ((CPU)->reg.vregs)
2aaed979 KB	135	#define MPU0_SR ((STATE_CPU (sd, 0))->reg.mpu0_sregs)
	136	#define MPU1_SR ((STATE_CPU (sd, 0))->reg.mpu1_sregs)
	137	#define FPU_SR ((STATE_CPU (sd, 0))->reg.fpu_sregs)
c906108c SS	138
	139	/* old */
	140	#define State (STATE_CPU (simulator, 0)->reg)
	141	#define PC (State.pc)
2aaed979 KB	142	#define SP_REGNO 3
2aaed979 KB	143	#define SP (State.regs[SP_REGNO])
c906108c SS	144	#define EP (State.regs[30])
	145
	146	#define EIPC (State.sregs[0])
	147	#define EIPSW (State.sregs[1])
	148	#define FEPC (State.sregs[2])
	149	#define FEPSW (State.sregs[3])
	150	#define ECR (State.sregs[4])
	151	#define PSW (State.sregs[5])
2aaed979 KB	152	#define PSW_REGNO 5
	153	#define EIIC (State.sregs[13])
	154	#define FEIC (State.sregs[14])
	155	#define DBIC (SR[15])
c906108c SS	156	#define CTPC (SR[16])
	157	#define CTPSW (SR[17])
	158	#define DBPC (State.sregs[18])
	159	#define DBPSW (State.sregs[19])
	160	#define CTBP (State.sregs[20])
2aaed979 KB	161	#define DIR (SR[21])
	162	#define EIWR (SR[28])
	163	#define FEWR (SR[29])
	164	#define DBWR (SR[30])
	165	#define BSEL (SR[31])
c906108c SS	166
	167	#define PSW_US BIT32 (8)
	168	#define PSW_NP 0x80
	169	#define PSW_EP 0x40
	170	#define PSW_ID 0x20
	171	#define PSW_SAT 0x10
	172	#define PSW_CY 0x8
	173	#define PSW_OV 0x4
	174	#define PSW_S 0x2
	175	#define PSW_Z 0x1
	176
2aaed979 KB	177	#define PSW_NPV (1<<18)
	178	#define PSW_DMP (1<<17)
	179	#define PSW_IMP (1<<16)
	180
	181	#define ECR_EICC 0x0000ffff
	182	#define ECR_FECC 0xffff0000
	183
	184	/* FPU */
	185
	186	#define FPSR (FPU_SR[6])
	187	#define FPSR_REGNO 6
	188	#define FPEPC (FPU_SR[7])
	189	#define FPST (FPU_SR[8])
	190	#define FPST_REGNO 8
	191	#define FPCC (FPU_SR[9])
	192	#define FPCFG (FPU_SR[10])
	193	#define FPCFG_REGNO 10
	194
	195	#define FPSR_DEM 0x00200000
	196	#define FPSR_SEM 0x00100000
	197	#define FPSR_RM 0x000c0000
	198	#define FPSR_RN 0x00000000
	199	#define FPSR_FS 0x00020000
	200	#define FPSR_PR 0x00010000
	201
	202	#define FPSR_XC 0x0000fc00
	203	#define FPSR_XCE 0x00008000
	204	#define FPSR_XCV 0x00004000
	205	#define FPSR_XCZ 0x00002000
	206	#define FPSR_XCO 0x00001000
	207	#define FPSR_XCU 0x00000800
	208	#define FPSR_XCI 0x00000400
	209
	210	#define FPSR_XE 0x000003e0
	211	#define FPSR_XEV 0x00000200
	212	#define FPSR_XEZ 0x00000100
	213	#define FPSR_XEO 0x00000080
	214	#define FPSR_XEU 0x00000040
	215	#define FPSR_XEI 0x00000020
	216
	217	#define FPSR_XP 0x0000001f
	218	#define FPSR_XPV 0x00000010
	219	#define FPSR_XPZ 0x00000008
	220	#define FPSR_XPO 0x00000004
	221	#define FPSR_XPU 0x00000002
	222	#define FPSR_XPI 0x00000001
	223
	224	#define FPST_PR 0x00008000
	225	#define FPST_XCE 0x00002000
	226	#define FPST_XCV 0x00001000
	227	#define FPST_XCZ 0x00000800
	228	#define FPST_XCO 0x00000400
	229	#define FPST_XCU 0x00000200
	230	#define FPST_XCI 0x00000100
	231
	232	#define FPST_XPV 0x00000010
	233	#define FPST_XPZ 0x00000008
	234	#define FPST_XPO 0x00000004
	235	#define FPST_XPU 0x00000002
	236	#define FPST_XPI 0x00000001
	237
	238	#define FPCFG_RM 0x00000180
	239	#define FPCFG_XEV 0x00000010
	240	#define FPCFG_XEZ 0x00000008
241	#define FPCFG_XEO 0x00000004
242	#define FPCFG_XEU 0x00000002
243	#define FPCFG_XEI 0x00000001
244
245	#define GET_FPCC()\
246	((FPSR >> 24) &0xf)
247
248	#define CLEAR_FPCC(bbb)\
249	(FPSR &= ~(1 << (bbb+24)))
250
251	#define SET_FPCC(bbb)\
252	(FPSR \|= 1 << (bbb+24))
253
254	#define TEST_FPCC(bbb)\
255	((FPSR & (1 << (bbb+24))) != 0)
256
257	#define FPSR_GET_ROUND() \
258	(((FPSR & FPSR_RM) == FPSR_RN) ? sim_fpu_round_near \
259	: ((FPSR & FPSR_RM) == 0x00040000) ? sim_fpu_round_up \
260	: ((FPSR & FPSR_RM) == 0x00080000) ? sim_fpu_round_down \
261	: sim_fpu_round_zero)
262
263
264	enum FPU_COMPARE {
265	FPU_CMP_F = 0,
266	FPU_CMP_UN,
267	FPU_CMP_EQ,
268	FPU_CMP_UEQ,
269	FPU_CMP_OLT,
270	FPU_CMP_ULT,
271	FPU_CMP_OLE,
272	FPU_CMP_ULE,
273	FPU_CMP_SF,
274	FPU_CMP_NGLE,
275	FPU_CMP_SEQ,
276	FPU_CMP_NGL,
277	FPU_CMP_LT,
278	FPU_CMP_NGE,
279	FPU_CMP_LE,
280	FPU_CMP_NGT
281	};
282
283
284	/* MPU */
285	#define MPM (MPU1_SR[0])
286	#define MPC (MPU1_SR[1])
287	#define MPC_REGNO 1
288	#define TID (MPU1_SR[2])
289	#define PPA (MPU1_SR[3])
290	#define PPM (MPU1_SR[4])
291	#define PPC (MPU1_SR[5])
292	#define DCC (MPU1_SR[6])
293	#define DCV0 (MPU1_SR[7])
294	#define DCV1 (MPU1_SR[8])
295	#define SPAL (MPU1_SR[10])
296	#define SPAU (MPU1_SR[11])
297	#define IPA0L (MPU1_SR[12])
298	#define IPA0U (MPU1_SR[13])
299	#define IPA1L (MPU1_SR[14])
300	#define IPA1U (MPU1_SR[15])
301	#define IPA2L (MPU1_SR[16])
302	#define IPA2U (MPU1_SR[17])
303	#define IPA3L (MPU1_SR[18])
304	#define IPA3U (MPU1_SR[19])
305	#define DPA0L (MPU1_SR[20])
306	#define DPA0U (MPU1_SR[21])
307	#define DPA1L (MPU1_SR[22])
308	#define DPA1U (MPU1_SR[23])
309	#define DPA2L (MPU1_SR[24])
310	#define DPA2U (MPU1_SR[25])
311	#define DPA3L (MPU1_SR[26])
312	#define DPA3U (MPU1_SR[27])
313
314	#define PPC_PPE 0x1
315	#define SPAL_SPE 0x1
316	#define SPAL_SPS 0x10
317
318	#define VIP (MPU0_SR[0])
319	#define VMECR (MPU0_SR[4])
320	#define VMTID (MPU0_SR[5])
321	#define VMADR (MPU0_SR[6])
322	#define VPECR (MPU0_SR[8])
323	#define VPTID (MPU0_SR[9])
324	#define VPADR (MPU0_SR[10])
325	#define VDECR (MPU0_SR[12])
326	#define VDTID (MPU0_SR[13])
327
328	#define MPM_AUE 0x2
329	#define MPM_MPE 0x1
330
331	#define VMECR_VMX 0x2
332	#define VMECR_VMR 0x4
333	#define VMECR_VMW 0x8
334	#define VMECR_VMS 0x10
335	#define VMECR_VMRMW 0x20
336	#define VMECR_VMMS 0x40
337
338	#define IPA2ADDR(IPA) ((IPA) & 0x1fffff80)
339	#define IPA_IPE 0x1
340	#define IPA_IPX 0x2
341	#define IPA_IPR 0x4
342	#define IPE0 (IPA0L & IPA_IPE)
343	#define IPE1 (IPA1L & IPA_IPE)
344	#define IPE2 (IPA2L & IPA_IPE)
345	#define IPE3 (IPA3L & IPA_IPE)
346	#define IPX0 (IPA0L & IPA_IPX)
347	#define IPX1 (IPA1L & IPA_IPX)
348	#define IPX2 (IPA2L & IPA_IPX)
349	#define IPX3 (IPA3L & IPA_IPX)
350	#define IPR0 (IPA0L & IPA_IPR)
351	#define IPR1 (IPA1L & IPA_IPR)
352	#define IPR2 (IPA2L & IPA_IPR)
353	#define IPR3 (IPA3L & IPA_IPR)
354
355	#define DPA2ADDR(DPA) ((DPA) & 0x1fffff80)
356	#define DPA_DPE 0x1
357	#define DPA_DPR 0x4
358	#define DPA_DPW 0x8
359	#define DPE0 (DPA0L & DPA_DPE)
360	#define DPE1 (DPA1L & DPA_DPE)
361	#define DPE2 (DPA2L & DPA_DPE)
362	#define DPE3 (DPA3L & DPA_DPE)
363	#define DPR0 (DPA0L & DPA_DPR)
364	#define DPR1 (DPA1L & DPA_DPR)
365	#define DPR2 (DPA2L & DPA_DPR)
366	#define DPR3 (DPA3L & DPA_DPR)
367	#define DPW0 (DPA0L & DPA_DPW)
368	#define DPW1 (DPA1L & DPA_DPW)
369	#define DPW2 (DPA2L & DPA_DPW)
370	#define DPW3 (DPA3L & DPA_DPW)
371
372	#define DCC_DCE0 0x1
373	#define DCC_DCE1 0x10000
374
375	#define PPA2ADDR(PPA) ((PPA) & 0x1fffff80)
376	#define PPC_PPC 0xfffffffe
377	#define PPC_PPE 0x1
378	#define PPC_PPM 0x0000fff8
379
380
c906108c SS	381	#define SEXT3(x) ((((x)&0x7)^(~0x3))+0x4)
	382
	383	/* sign-extend a 4-bit number */
	384	#define SEXT4(x) ((((x)&0xf)^(~0x7))+0x8)
	385
	386	/* sign-extend a 5-bit number */
	387	#define SEXT5(x) ((((x)&0x1f)^(~0xf))+0x10)
	388
	389	/* sign-extend a 9-bit number */
	390	#define SEXT9(x) ((((x)&0x1ff)^(~0xff))+0x100)
	391
	392	/* sign-extend a 22-bit number */
	393	#define SEXT22(x) ((((x)&0x3fffff)^(~0x1fffff))+0x200000)
	394
	395	/* sign extend a 40 bit number */
	396	#define SEXT40(x) ((((x) & UNSIGNED64 (0xffffffffff)) \
	397	^ (~UNSIGNED64 (0x7fffffffff))) \
	398	+ UNSIGNED64 (0x8000000000))
	399
	400	/* sign extend a 44 bit number */
	401	#define SEXT44(x) ((((x) & UNSIGNED64 (0xfffffffffff)) \
	402	^ (~ UNSIGNED64 (0x7ffffffffff))) \
	403	+ UNSIGNED64 (0x80000000000))
	404
	405	/* sign extend a 60 bit number */
	406	#define SEXT60(x) ((((x) & UNSIGNED64 (0xfffffffffffffff)) \
	407	^ (~ UNSIGNED64 (0x7ffffffffffffff))) \
	408	+ UNSIGNED64 (0x800000000000000))
	409
	410	/* No sign extension */
	411	#define NOP(x) (x)
	412
	413	#define INC_ADDR(x,i) x = ((State.MD && x == MOD_E) ? MOD_S : (x)+(i))
	414
	415	#define RLW(x) load_mem (x, 4)
	416
	417	/* Function declarations. */
	418
	419	#define IMEM16(EA) \
	420	sim_core_read_aligned_2 (CPU, PC, exec_map, (EA))
	421
	422	#define IMEM16_IMMED(EA,N) \
	423	sim_core_read_aligned_2 (STATE_CPU (sd, 0), \
	424	PC, exec_map, (EA) + (N) * 2)
	425
	426	#define load_mem(ADDR,LEN) \
	427	sim_core_read_unaligned_##LEN (STATE_CPU (simulator, 0), \
	428	PC, read_map, (ADDR))
	429
	430	#define store_mem(ADDR,LEN,DATA) \
	431	sim_core_write_unaligned_##LEN (STATE_CPU (simulator, 0), \
	432	PC, write_map, (ADDR), (DATA))
	433
	434
	435	/* compare cccc field against PSW */
	436	int condition_met (unsigned code);
	437
	438
	439	/* Debug/tracing calls */
	440
	441	enum op_types
	442	{
	443	OP_UNKNOWN,
	444	OP_NONE,
445	OP_TRAP,
446	OP_REG,
447	OP_REG_REG,
448	OP_REG_REG_CMP,
449	OP_REG_REG_MOVE,
450	OP_IMM_REG,
451	OP_IMM_REG_CMP,
452	OP_IMM_REG_MOVE,
453	OP_COND_BR,
454	OP_LOAD16,
455	OP_STORE16,
456	OP_LOAD32,
457	OP_STORE32,
458	OP_JUMP,
459	OP_IMM_REG_REG,
460	OP_UIMM_REG_REG,
461	OP_IMM16_REG_REG,
462	OP_UIMM16_REG_REG,
463	OP_BIT,
464	OP_EX1,
465	OP_EX2,
466	OP_LDSR,
467	OP_STSR,
468	OP_BIT_CHANGE,
469	OP_REG_REG_REG,
470	OP_REG_REG3,
471	OP_IMM_REG_REG_REG,
472	OP_PUSHPOP1,
473	OP_PUSHPOP2,
474	OP_PUSHPOP3,
475	};
476
477	#ifdef DEBUG
bdca5ee4 TT	478	void trace_input (char *name, enum op_types type, int size);
	479	void trace_output (enum op_types result);
	480	void trace_result (int has_result, unsigned32 result);
c906108c SS	481
	482	extern int trace_num_values;
	483	extern unsigned32 trace_values[];
	484	extern unsigned32 trace_pc;
	485	extern const char *trace_name;
	486	extern int trace_module;
	487
	488	#define TRACE_BRANCH0() \
	489	do { \
	490	if (TRACE_BRANCH_P (CPU)) { \
	491	trace_module = TRACE_BRANCH_IDX; \
	492	trace_pc = cia; \
	493	trace_name = itable[MY_INDEX].name; \
	494	trace_num_values = 0; \
	495	trace_result (1, (nia)); \
	496	} \
	497	} while (0)
	498
	499	#define TRACE_BRANCH1(IN1) \
	500	do { \
	501	if (TRACE_BRANCH_P (CPU)) { \
	502	trace_module = TRACE_BRANCH_IDX; \
	503	trace_pc = cia; \
	504	trace_name = itable[MY_INDEX].name; \
	505	trace_values[0] = (IN1); \
	506	trace_num_values = 1; \
	507	trace_result (1, (nia)); \
	508	} \
	509	} while (0)
	510
	511	#define TRACE_BRANCH2(IN1, IN2) \
	512	do { \
	513	if (TRACE_BRANCH_P (CPU)) { \
	514	trace_module = TRACE_BRANCH_IDX; \
	515	trace_pc = cia; \
	516	trace_name = itable[MY_INDEX].name; \
	517	trace_values[0] = (IN1); \
	518	trace_values[1] = (IN2); \
	519	trace_num_values = 2; \
	520	trace_result (1, (nia)); \
	521	} \
	522	} while (0)
	523
	524	#define TRACE_BRANCH3(IN1, IN2, IN3) \
	525	do { \
	526	if (TRACE_BRANCH_P (CPU)) { \
	527	trace_module = TRACE_BRANCH_IDX; \
	528	trace_pc = cia; \
	529	trace_name = itable[MY_INDEX].name; \
	530	trace_values[0] = (IN1); \
	531	trace_values[1] = (IN2); \
	532	trace_values[2] = (IN3); \
	533	trace_num_values = 3; \
	534	trace_result (1, (nia)); \
	535	} \
	536	} while (0)
	537
	538	#define TRACE_LD(ADDR,RESULT) \
	539	do { \
	540	if (TRACE_MEMORY_P (CPU)) { \
	541	trace_module = TRACE_MEMORY_IDX; \
	542	trace_pc = cia; \
	543	trace_name = itable[MY_INDEX].name; \
	544	trace_values[0] = (ADDR); \
545	trace_num_values = 1; \
546	trace_result (1, (RESULT)); \
547	} \
548	} while (0)
549
550	#define TRACE_LD_NAME(NAME, ADDR,RESULT) \
551	do { \
552	if (TRACE_MEMORY_P (CPU)) { \
553	trace_module = TRACE_MEMORY_IDX; \
554	trace_pc = cia; \
555	trace_name = (NAME); \
556	trace_values[0] = (ADDR); \
557	trace_num_values = 1; \
558	trace_result (1, (RESULT)); \
559	} \
560	} while (0)
561
562	#define TRACE_ST(ADDR,RESULT) \
563	do { \
564	if (TRACE_MEMORY_P (CPU)) { \
565	trace_module = TRACE_MEMORY_IDX; \
566	trace_pc = cia; \
567	trace_name = itable[MY_INDEX].name; \
568	trace_values[0] = (ADDR); \
569	trace_num_values = 1; \
570	trace_result (1, (RESULT)); \
571	} \
572	} while (0)
573
2aaed979 KB	574	#define TRACE_FP_INPUT_FPU1(V0) \
	575	do { \
	576	if (TRACE_FPU_P (CPU)) \
	577	{ \
	578	unsigned64 f0; \
	579	sim_fpu_to64 (&f0, (V0)); \
	580	trace_input_fp1 (SD, CPU, TRACE_FPU_IDX, f0); \
	581	} \
	582	} while (0)
	583
	584	#define TRACE_FP_INPUT_FPU2(V0, V1) \
	585	do { \
	586	if (TRACE_FPU_P (CPU)) \
	587	{ \
	588	unsigned64 f0, f1; \
	589	sim_fpu_to64 (&f0, (V0)); \
	590	sim_fpu_to64 (&f1, (V1)); \
	591	trace_input_fp2 (SD, CPU, TRACE_FPU_IDX, f0, f1); \
	592	} \
	593	} while (0)
	594
	595	#define TRACE_FP_INPUT_FPU3(V0, V1, V2) \
	596	do { \
	597	if (TRACE_FPU_P (CPU)) \
	598	{ \
	599	unsigned64 f0, f1, f2; \
	600	sim_fpu_to64 (&f0, (V0)); \
	601	sim_fpu_to64 (&f1, (V1)); \
	602	sim_fpu_to64 (&f2, (V2)); \
	603	trace_input_fp3 (SD, CPU, TRACE_FPU_IDX, f0, f1, f2); \
	604	} \
	605	} while (0)
	606
	607	#define TRACE_FP_INPUT_BOOL1_FPU2(V0, V1, V2) \
	608	do { \
	609	if (TRACE_FPU_P (CPU)) \
	610	{ \
	611	int d0 = (V0); \
	612	unsigned64 f1, f2; \
	613	TRACE_DATA *data = CPU_TRACE_DATA (CPU); \
	614	TRACE_IDX (data) = TRACE_FPU_IDX; \
	615	sim_fpu_to64 (&f1, (V1)); \
	616	sim_fpu_to64 (&f2, (V2)); \
	617	save_data (SD, data, trace_fmt_bool, sizeof (d0), &d0); \
	618	save_data (SD, data, trace_fmt_fp, sizeof (fp_word), &f1); \
	619	save_data (SD, data, trace_fmt_fp, sizeof (fp_word), &f2); \
	620	} \
	621	} while (0)
	622
	623	#define TRACE_FP_INPUT_WORD2(V0, V1) \
	624	do { \
	625	if (TRACE_FPU_P (CPU)) \
	626	trace_input_word2 (SD, CPU, TRACE_FPU_IDX, (V0), (V1)); \
	627	} while (0)
	628
	629	#define TRACE_FP_RESULT_FPU1(R0) \
	630	do { \
	631	if (TRACE_FPU_P (CPU)) \
	632	{ \
	633	unsigned64 f0; \
	634	sim_fpu_to64 (&f0, (R0)); \
	635	trace_result_fp1 (SD, CPU, TRACE_FPU_IDX, f0); \
	636	} \
	637	} while (0)
638
639	#define TRACE_FP_RESULT_WORD1(R0) TRACE_FP_RESULT_WORD(R0)
640
641	#define TRACE_FP_RESULT_WORD2(R0, R1) \
642	do { \
643	if (TRACE_FPU_P (CPU)) \
644	trace_result_word2 (SD, CPU, TRACE_FPU_IDX, (R0), (R1)); \
645	} while (0)
646
c906108c SS	647	#else
	648	#define trace_input(NAME, IN1, IN2)
	649	#define trace_output(RESULT)
	650	#define trace_result(HAS_RESULT, RESULT)
	651
	652	#define TRACE_ALU_INPUT0()
	653	#define TRACE_ALU_INPUT1(IN0)
	654	#define TRACE_ALU_INPUT2(IN0, IN1)
	655	#define TRACE_ALU_INPUT2(IN0, IN1)
	656	#define TRACE_ALU_INPUT2(IN0, IN1 INS2)
	657	#define TRACE_ALU_RESULT(RESULT)
	658
	659	#define TRACE_BRANCH0()
	660	#define TRACE_BRANCH1(IN1)
	661	#define TRACE_BRANCH2(IN1, IN2)
	662	#define TRACE_BRANCH2(IN1, IN2, IN3)
	663
	664	#define TRACE_LD(ADDR,RESULT)
	665	#define TRACE_ST(ADDR,RESULT)
	666
	667	#endif
	668
e551c257 NC	669	#define GPR_SET(N, VAL) (State.regs[(N)] = (VAL))
e551c257 NC	670	#define GPR_CLEAR(N) (State.regs[(N)] = 0)
c906108c SS	671
	672	extern void divun ( unsigned int N,
	673	unsigned long int als,
	674	unsigned long int sfi,
	675	unsigned32 /unsigned long int/ * quotient_ptr,
	676	unsigned32 /unsigned long int/ * remainder_ptr,
0da2b665	677	int *overflow_ptr
c906108c SS	678	);
	679	extern void divn ( unsigned int N,
	680	unsigned long int als,
	681	unsigned long int sfi,
	682	signed32 /signed long int/ * quotient_ptr,
	683	signed32 /signed long int/ * remainder_ptr,
0da2b665	684	int *overflow_ptr
c906108c SS	685	);
	686	extern int type1_regs[];
	687	extern int type2_regs[];
	688	extern int type3_regs[];
	689
a3976a7c NC	690	#define SESR_OV (1 << 0)
	691	#define SESR_SOV (1 << 1)
	692
	693	#define SESR (State.sregs[12])
	694
	695	#define ROUND_Q62_Q31(X) ((((X) + (1 << 30)) >> 31) & 0xffffffff)
	696	#define ROUND_Q62_Q15(X) ((((X) + (1 << 30)) >> 47) & 0xffff)
	697	#define ROUND_Q31_Q15(X) ((((X) + (1 << 15)) >> 15) & 0xffff)
	698	#define ROUND_Q30_Q15(X) ((((X) + (1 << 14)) >> 15) & 0xffff)
	699
	700	#define SAT16(X) \
	701	do \
	702	{ \
	703	signed64 z = (X); \
	704	if (z > 0x7fff) \
	705	{ \
	706	SESR \|= SESR_OV \| SESR_SOV; \
	707	z = 0x7fff; \
	708	} \
	709	else if (z < -0x8000) \
	710	{ \
	711	SESR \|= SESR_OV \| SESR_SOV; \
	712	z = - 0x8000; \
	713	} \
	714	(X) = z; \
	715	} \
	716	while (0)
	717
	718	#define SAT32(X) \
	719	do \
	720	{ \
	721	signed64 z = (X); \
	722	if (z > 0x7fffffff) \
	723	{ \
	724	SESR \|= SESR_OV \| SESR_SOV; \
	725	z = 0x7fffffff; \
	726	} \
	727	else if (z < -0x80000000) \
	728	{ \
	729	SESR \|= SESR_OV \| SESR_SOV; \
	730	z = - 0x80000000; \
	731	} \
	732	(X) = z; \
	733	} \
	734	while (0)
	735
	736	#define ABS16(X) \
	737	do \
	738	{ \
	739	signed64 z = (X) & 0xffff; \
	740	if (z == 0x8000) \
	741	{ \
	742	SESR \|= SESR_OV \| SESR_SOV; \
	743	z = 0x7fff; \
	744	} \
	745	else if (z & 0x8000) \
	746	{ \
	747	z = (- z) & 0xffff; \
	748	} \
	749	(X) = z; \
	750	} \
	751	while (0)
	752
	753	#define ABS32(X) \
754	do \
755	{ \
756	signed64 z = (X) & 0xffffffff; \
757	if (z == 0x80000000) \
758	{ \
759	SESR \|= SESR_OV \| SESR_SOV; \
760	z = 0x7fffffff; \
761	} \
762	else if (z & 0x80000000) \
763	{ \
764	z = (- z) & 0xffffffff; \
765	} \
766	(X) = z; \
767	} \
768	while (0)
769
c906108c	770	#endif