[thirdparty/u-boot.git] / src / arm / broadcom / bcm-hr2.dtsi

/*
 *  BSD LICENSE
 *
 *  Copyright(c) 2017 Broadcom.  All rights reserved.
 *
 *  Redistribution and use in source and binary forms, with or without
 *  modification, are permitted provided that the following conditions
 *  are met:
 *
 *    * Redistributions of source code must retain the above copyright
 *      notice, this list of conditions and the following disclaimer.
 *    * Redistributions in binary form must reproduce the above copyright
 *      notice, this list of conditions and the following disclaimer in
 *      the documentation and/or other materials provided with the
 *      distribution.
 *    * Neither the name of Broadcom Corporation nor the names of its
 *      contributors may be used to endorse or promote products derived
 *      from this software without specific prior written permission.
 *
 *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
 *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
 *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
 *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
 *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
 *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */

#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>

/ {
	compatible = "brcm,hr2";
	model = "Broadcom Hurricane 2 SoC";
	interrupt-parent = <&gic>;
	#address-cells = <1>;
	#size-cells = <1>;

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu0: cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a9";
			next-level-cache = <&L2>;
			reg = <0x0>;
		};
	};

	pmu {
		compatible = "arm,cortex-a9-pmu";
		interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-affinity = <&cpu0>;
	};

	mpcore@19000000 {
		compatible = "simple-bus";
		ranges = <0x00000000 0x19000000 0x00023000>;
		#address-cells = <1>;
		#size-cells = <1>;

		a9pll: arm_clk@0 {
			#clock-cells = <0>;
			compatible = "brcm,hr2-armpll";
			clocks = <&osc>;
			reg = <0x0 0x1000>;
		};

		timer@20200 {
			compatible = "arm,cortex-a9-global-timer";
			reg = <0x20200 0x100>;
			interrupts = <GIC_PPI 11 IRQ_TYPE_EDGE_RISING>;
			clocks = <&periph_clk>;
		};

		twd-timer@20600 {
			compatible = "arm,cortex-a9-twd-timer";
			reg = <0x20600 0x20>;
			interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) |
						  IRQ_TYPE_EDGE_RISING)>;
			clocks = <&periph_clk>;
		};

		twd-watchdog@20620 {
			compatible = "arm,cortex-a9-twd-wdt";
			reg = <0x20620 0x20>;
			interrupts = <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) |
						  IRQ_TYPE_EDGE_RISING)>;
			clocks = <&periph_clk>;
		};

		gic: interrupt-controller@21000 {
			compatible = "arm,cortex-a9-gic";
			#interrupt-cells = <3>;
			#address-cells = <0>;
			interrupt-controller;
			reg = <0x21000 0x1000>,
			      <0x20100 0x100>;
		};

		L2: cache-controller@22000 {
			compatible = "arm,pl310-cache";
			reg = <0x22000 0x1000>;
			cache-unified;
			cache-level = <2>;
		};
	};

	clocks {
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;

		osc: oscillator {
			#clock-cells = <0>;
			compatible = "fixed-clock";
			clock-frequency = <25000000>;
		};

		periph_clk: periph_clk {
			#clock-cells = <0>;
			compatible = "fixed-factor-clock";
			clocks = <&a9pll>;
			clock-div = <2>;
			clock-mult = <1>;
		};
	};

	axi@18000000 {
		compatible = "simple-bus";
		ranges = <0x00000000 0x18000000 0x0011c40c>;
		#address-cells = <1>;
		#size-cells = <1>;

		uart0: serial@300 {
			compatible = "ns16550a";
			reg = <0x0300 0x100>;
			interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&osc>;
			status = "disabled";
		};

		uart1: serial@400 {
			compatible = "ns16550a";
			reg = <0x0400 0x100>;
			interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&osc>;
			status = "disabled";
		};

		dma@20000 {
			compatible = "arm,pl330", "arm,primecell";
			reg = <0x20000 0x1000>;
			interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
			#dma-cells = <1>;
			status = "disabled";
		};

		amac0: ethernet@22000 {
			compatible = "brcm,nsp-amac";
			reg = <0x22000 0x1000>,
			      <0x110000 0x1000>;
			reg-names = "amac_base", "idm_base";
			interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>;
			status = "disabled";
		};

		nand_controller: nand-controller@26000 {
			compatible = "brcm,nand-iproc", "brcm,brcmnand-v6.1";
			reg = <0x26000 0x600>,
			      <0x11b408 0x600>,
			      <0x026f00 0x20>;
			reg-names = "nand", "iproc-idm", "iproc-ext";
			interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;

			#address-cells = <1>;
			#size-cells = <0>;

			brcm,nand-has-wp;
		};

		gpiob: gpio@30000 {
			compatible = "brcm,iproc-hr2-gpio", "brcm,iproc-gpio";
			reg = <0x30000 0x50>;
			#gpio-cells = <2>;
			gpio-controller;
			ngpios = <4>;
			interrupt-controller;
			interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
		};

		pwm: pwm@31000 {
			compatible = "brcm,iproc-pwm";
			reg = <0x31000 0x28>;
			clocks = <&osc>;
			#pwm-cells = <3>;
			status = "disabled";
		};

		rng: rng@33000 {
			compatible = "brcm,bcm-nsp-rng";
			reg = <0x33000 0x14>;
		};

		qspi: spi@27200 {
			compatible = "brcm,spi-nsp-qspi", "brcm,spi-bcm-qspi";
			reg = <0x027200 0x184>,
			      <0x027000 0x124>,
			      <0x11c408 0x004>,
			      <0x0273a0 0x01c>;
			reg-names = "mspi", "bspi", "intr_regs",
				    "intr_status_reg";
			interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "spi_lr_fullness_reached",
					  "spi_lr_session_aborted",
					  "spi_lr_impatient",
					  "spi_lr_session_done",
					  "spi_lr_overhead",
					  "mspi_done",
					  "mspi_halted";
			num-cs = <2>;
			#address-cells = <1>;
			#size-cells = <0>;

			/* partitions defined in board DTS */
		};

		ccbtimer0: timer@34000 {
			compatible = "arm,sp804";
			reg = <0x34000 0x1000>;
			interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
		};

		ccbtimer1: timer@35000 {
			compatible = "arm,sp804";
			reg = <0x35000 0x1000>;
			interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
		};

		i2c0: i2c@38000 {
			compatible = "brcm,iproc-i2c";
			reg = <0x38000 0x50>;
			#address-cells = <1>;
			#size-cells = <0>;
			interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
			clock-frequency = <100000>;
		};

		watchdog: watchdog@39000 {
			compatible = "arm,sp805", "arm,primecell";
			reg = <0x39000 0x1000>;
			interrupts = <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>;
		};

		i2c1: i2c@3b000 {
			compatible = "brcm,iproc-i2c";
			reg = <0x3b000 0x50>;
			#address-cells = <1>;
			#size-cells = <0>;
			interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
			clock-frequency = <100000>;
		};
	};

	pflash: nor@20000000 {
		compatible = "cfi-flash", "jedec-flash";
		reg = <0x20000000 0x04000000>;
		status = "disabled";
		#address-cells = <1>;
		#size-cells = <1>;

		/* partitions defined in board DTS */
	};

	pcie0: pcie@18012000 {
		compatible = "brcm,iproc-pcie";
		reg = <0x18012000 0x1000>;

		#interrupt-cells = <1>;
		interrupt-map-mask = <0 0 0 0>;
		interrupt-map = <0 0 0 0 &gic GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;

		linux,pci-domain = <0>;

		bus-range = <0x00 0xff>;

		#address-cells = <3>;
		#size-cells = <2>;
		device_type = "pci";

		/* Note: The HW does not support I/O resources.  So,
		 * only the memory resource range is being specified.
		 */
		ranges = <0x82000000 0 0x08000000 0x08000000 0 0x8000000>;

		status = "disabled";

		msi-parent = <&msi0>;
		msi0: msi {
			compatible = "brcm,iproc-msi";
			msi-controller;
			interrupt-parent = <&gic>;
			interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>;
			brcm,pcie-msi-inten;
		};
	};

	pcie1: pcie@18013000 {
		compatible = "brcm,iproc-pcie";
		reg = <0x18013000 0x1000>;

		#interrupt-cells = <1>;
		interrupt-map-mask = <0 0 0 0>;
		interrupt-map = <0 0 0 0 &gic GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>;

		linux,pci-domain = <1>;

		bus-range = <0x00 0xff>;

		#address-cells = <3>;
		#size-cells = <2>;
		device_type = "pci";

		/* Note: The HW does not support I/O resources.  So,
		 * only the memory resource range is being specified.
		 */
		ranges = <0x82000000 0 0x40000000 0x40000000 0 0x8000000>;

		status = "disabled";

		msi-parent = <&msi1>;
		msi1: msi {
			compatible = "brcm,iproc-msi";
			msi-controller;
			interrupt-parent = <&gic>;
			interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>;
			brcm,pcie-msi-inten;
		};
	};
};
Commit	Line	Data
53633a89 TR	1	/*
	2	* BSD LICENSE
	3	*
	4	* Copyright(c) 2017 Broadcom. All rights reserved.
	5	*
	6	* Redistribution and use in source and binary forms, with or without
	7	* modification, are permitted provided that the following conditions
	8	* are met:
	9	*
	10	* * Redistributions of source code must retain the above copyright
	11	* notice, this list of conditions and the following disclaimer.
	12	* * Redistributions in binary form must reproduce the above copyright
	13	* notice, this list of conditions and the following disclaimer in
	14	* the documentation and/or other materials provided with the
	15	* distribution.
	16	* * Neither the name of Broadcom Corporation nor the names of its
	17	* contributors may be used to endorse or promote products derived
	18	* from this software without specific prior written permission.
	19	*
	20	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
	21	* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
	22	* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
	23	* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
	24	* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
	25	* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
	26	* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
	27	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
	28	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
	29	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
	30	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
	31	*/
	32
	33	#include <dt-bindings/interrupt-controller/arm-gic.h>
	34	#include <dt-bindings/interrupt-controller/irq.h>
	35
	36	/ {
	37	compatible = "brcm,hr2";
	38	model = "Broadcom Hurricane 2 SoC";
	39	interrupt-parent = <&gic>;
	40	#address-cells = <1>;
	41	#size-cells = <1>;
	42
	43	cpus {
	44	#address-cells = <1>;
	45	#size-cells = <0>;
	46
	47	cpu0: cpu@0 {
	48	device_type = "cpu";
	49	compatible = "arm,cortex-a9";
	50	next-level-cache = <&L2>;
	51	reg = <0x0>;
	52	};
	53	};
	54
	55	pmu {
	56	compatible = "arm,cortex-a9-pmu";
	57	interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
	58	<GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
	59	interrupt-affinity = <&cpu0>;
	60	};
	61
	62	mpcore@19000000 {
	63	compatible = "simple-bus";
	64	ranges = <0x00000000 0x19000000 0x00023000>;
65	#address-cells = <1>;
66	#size-cells = <1>;
67
68	a9pll: arm_clk@0 {
69	#clock-cells = <0>;
70	compatible = "brcm,hr2-armpll";
71	clocks = <&osc>;
72	reg = <0x0 0x1000>;
73	};
74
75	timer@20200 {
76	compatible = "arm,cortex-a9-global-timer";
77	reg = <0x20200 0x100>;
78	interrupts = <GIC_PPI 11 IRQ_TYPE_EDGE_RISING>;
79	clocks = <&periph_clk>;
80	};
81
82	twd-timer@20600 {
83	compatible = "arm,cortex-a9-twd-timer";
84	reg = <0x20600 0x20>;
85	interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) \|
86	IRQ_TYPE_EDGE_RISING)>;
87	clocks = <&periph_clk>;
88	};
89
90	twd-watchdog@20620 {
91	compatible = "arm,cortex-a9-twd-wdt";
92	reg = <0x20620 0x20>;
93	interrupts = <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) \|
94	IRQ_TYPE_EDGE_RISING)>;
95	clocks = <&periph_clk>;
96	};
97
98	gic: interrupt-controller@21000 {
99	compatible = "arm,cortex-a9-gic";
100	#interrupt-cells = <3>;
101	#address-cells = <0>;
102	interrupt-controller;
103	reg = <0x21000 0x1000>,
104	<0x20100 0x100>;
105	};
106
107	L2: cache-controller@22000 {
108	compatible = "arm,pl310-cache";
109	reg = <0x22000 0x1000>;
110	cache-unified;
111	cache-level = <2>;
112	};
113	};
114
115	clocks {
116	#address-cells = <1>;
117	#size-cells = <1>;
118	ranges;
119
120	osc: oscillator {
121	#clock-cells = <0>;
122	compatible = "fixed-clock";
123	clock-frequency = <25000000>;
124	};
125
126	periph_clk: periph_clk {
127	#clock-cells = <0>;
128	compatible = "fixed-factor-clock";
129	clocks = <&a9pll>;
130	clock-div = <2>;
131	clock-mult = <1>;
132	};
133	};
134
135	axi@18000000 {
136	compatible = "simple-bus";
137	ranges = <0x00000000 0x18000000 0x0011c40c>;
138	#address-cells = <1>;
139	#size-cells = <1>;
140
141	uart0: serial@300 {
142	compatible = "ns16550a";
143	reg = <0x0300 0x100>;
144	interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
145	clocks = <&osc>;
146	status = "disabled";
147	};
148
149	uart1: serial@400 {
150	compatible = "ns16550a";
151	reg = <0x0400 0x100>;
152	interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
153	clocks = <&osc>;
154	status = "disabled";
155	};
156
157	dma@20000 {
158	compatible = "arm,pl330", "arm,primecell";
159	reg = <0x20000 0x1000>;
160	interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
161	<GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,
162	<GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
163	<GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>,
164	<GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
165	<GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
166	<GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
167	<GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
168	<GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
169	#dma-cells = <1>;
170	status = "disabled";
171	};
172
173	amac0: ethernet@22000 {
174	compatible = "brcm,nsp-amac";
175	reg = <0x22000 0x1000>,
176	<0x110000 0x1000>;
177	reg-names = "amac_base", "idm_base";
178	interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>;
179	status = "disabled";
180	};
181
182	nand_controller: nand-controller@26000 {
183	compatible = "brcm,nand-iproc", "brcm,brcmnand-v6.1";
184	reg = <0x26000 0x600>,
185	<0x11b408 0x600>,
186	<0x026f00 0x20>;
187	reg-names = "nand", "iproc-idm", "iproc-ext";
188	interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
189
190	#address-cells = <1>;
191	#size-cells = <0>;
192
193	brcm,nand-has-wp;
194	};
195
196	gpiob: gpio@30000 {
197	compatible = "brcm,iproc-hr2-gpio", "brcm,iproc-gpio";
198	reg = <0x30000 0x50>;
199	#gpio-cells = <2>;
200	gpio-controller;
201	ngpios = <4>;
202	interrupt-controller;
203	interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
204	};
205
206	pwm: pwm@31000 {
207	compatible = "brcm,iproc-pwm";
208	reg = <0x31000 0x28>;
209	clocks = <&osc>;
210	#pwm-cells = <3>;
211	status = "disabled";
212	};
213
214	rng: rng@33000 {
215	compatible = "brcm,bcm-nsp-rng";
216	reg = <0x33000 0x14>;
217	};
218
219	qspi: spi@27200 {
220	compatible = "brcm,spi-nsp-qspi", "brcm,spi-bcm-qspi";
221	reg = <0x027200 0x184>,
222	<0x027000 0x124>,
223	<0x11c408 0x004>,
224	<0x0273a0 0x01c>;
225	reg-names = "mspi", "bspi", "intr_regs",
226	"intr_status_reg";
227	interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>,
228	<GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>,
229	<GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>,
230	<GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>,
231	<GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>,
232	<GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>,
233	<GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
234	interrupt-names = "spi_lr_fullness_reached",
235	"spi_lr_session_aborted",
236	"spi_lr_impatient",
237	"spi_lr_session_done",
238	"spi_lr_overhead",
239	"mspi_done",
240	"mspi_halted";
241	num-cs = <2>;
242	#address-cells = <1>;
243	#size-cells = <0>;
244
245	/* partitions defined in board DTS */
246	};
247
248	ccbtimer0: timer@34000 {
249	compatible = "arm,sp804";
250	reg = <0x34000 0x1000>;
251	interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
252	<GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
253	};
254
255	ccbtimer1: timer@35000 {
256	compatible = "arm,sp804";
257	reg = <0x35000 0x1000>;
258	interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
259	<GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
260	};
261
262	i2c0: i2c@38000 {
263	compatible = "brcm,iproc-i2c";
264	reg = <0x38000 0x50>;
265	#address-cells = <1>;
266	#size-cells = <0>;
267	interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
268	clock-frequency = <100000>;
269	};
270
271	watchdog: watchdog@39000 {
272	compatible = "arm,sp805", "arm,primecell";
273	reg = <0x39000 0x1000>;
274	interrupts = <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>;
275	};
276
277	i2c1: i2c@3b000 {
278	compatible = "brcm,iproc-i2c";
279	reg = <0x3b000 0x50>;
280	#address-cells = <1>;
281	#size-cells = <0>;
282	interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
283	clock-frequency = <100000>;
284	};
285	};
286
287	pflash: nor@20000000 {
288	compatible = "cfi-flash", "jedec-flash";
289	reg = <0x20000000 0x04000000>;
290	status = "disabled";
291	#address-cells = <1>;
292	#size-cells = <1>;
293
294	/* partitions defined in board DTS */
295	};
296
297	pcie0: pcie@18012000 {
298	compatible = "brcm,iproc-pcie";
299	reg = <0x18012000 0x1000>;
300
301	#interrupt-cells = <1>;
302	interrupt-map-mask = <0 0 0 0>;
303	interrupt-map = <0 0 0 0 &gic GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
304
305	linux,pci-domain = <0>;
306
307	bus-range = <0x00 0xff>;
308
309	#address-cells = <3>;
310	#size-cells = <2>;
311	device_type = "pci";
312
313	/* Note: The HW does not support I/O resources. So,
314	* only the memory resource range is being specified.
315	*/
316	ranges = <0x82000000 0 0x08000000 0x08000000 0 0x8000000>;
317
318	status = "disabled";
319
320	msi-parent = <&msi0>;
321	msi0: msi {
322	compatible = "brcm,iproc-msi";
323	msi-controller;
324	interrupt-parent = <&gic>;
325	interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
326	<GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
327	<GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
328	<GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>;
329	brcm,pcie-msi-inten;
330	};
331	};
332
333	pcie1: pcie@18013000 {
334	compatible = "brcm,iproc-pcie";
335	reg = <0x18013000 0x1000>;
336
337	#interrupt-cells = <1>;
338	interrupt-map-mask = <0 0 0 0>;
339	interrupt-map = <0 0 0 0 &gic GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>;
340
341	linux,pci-domain = <1>;
342
343	bus-range = <0x00 0xff>;
344
345	#address-cells = <3>;
346	#size-cells = <2>;
347	device_type = "pci";
348
349	/* Note: The HW does not support I/O resources. So,
350	* only the memory resource range is being specified.
351	*/
352	ranges = <0x82000000 0 0x40000000 0x40000000 0 0x8000000>;
353
354	status = "disabled";
355
356	msi-parent = <&msi1>;
357	msi1: msi {
358	compatible = "brcm,iproc-msi";
359	msi-controller;
360	interrupt-parent = <&gic>;
361	interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
362	<GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
363	<GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
364	<GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>;
365	brcm,pcie-msi-inten;
366	};
367	};
368	};