[thirdparty/qemu.git] / target / hppa / cpu.h

/*
 * PA-RISC emulation cpu definitions for qemu.
 *
 * Copyright (c) 2016 Richard Henderson <rth@twiddle.net>
 *
 * This library is free software; you can redistribute it and/or
 * modify it under the terms of the GNU Lesser General Public
 * License as published by the Free Software Foundation; either
 * version 2.1 of the License, or (at your option) any later version.
 *
 * This library is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * Lesser General Public License for more details.
 *
 * You should have received a copy of the GNU Lesser General Public
 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
 */

#ifndef HPPA_CPU_H
#define HPPA_CPU_H

#include "cpu-qom.h"
#include "exec/cpu-defs.h"
#include "qemu/cpu-float.h"
#include "qemu/interval-tree.h"
#include "hw/registerfields.h"

#define MMU_ABS_W_IDX     6
#define MMU_ABS_IDX       7
#define MMU_KERNEL_IDX    8
#define MMU_KERNEL_P_IDX  9
#define MMU_PL1_IDX       10
#define MMU_PL1_P_IDX     11
#define MMU_PL2_IDX       12
#define MMU_PL2_P_IDX     13
#define MMU_USER_IDX      14
#define MMU_USER_P_IDX    15

#define MMU_IDX_MMU_DISABLED(MIDX)  ((MIDX) < MMU_KERNEL_IDX)
#define MMU_IDX_TO_PRIV(MIDX)       (((MIDX) - MMU_KERNEL_IDX) / 2)
#define MMU_IDX_TO_P(MIDX)          (((MIDX) - MMU_KERNEL_IDX) & 1)
#define PRIV_P_TO_MMU_IDX(PRIV, P)  ((PRIV) * 2 + !!(P) + MMU_KERNEL_IDX)

#define PRIV_KERNEL       0
#define PRIV_USER         3

#define TARGET_INSN_START_EXTRA_WORDS 2

/* No need to flush MMU_ABS*_IDX  */
#define HPPA_MMU_FLUSH_MASK                             \
        (1 << MMU_KERNEL_IDX | 1 << MMU_KERNEL_P_IDX |  \
         1 << MMU_PL1_IDX    | 1 << MMU_PL1_P_IDX    |  \
         1 << MMU_PL2_IDX    | 1 << MMU_PL2_P_IDX    |  \
         1 << MMU_USER_IDX   | 1 << MMU_USER_P_IDX)

/* Indices to flush for access_id changes. */
#define HPPA_MMU_FLUSH_P_MASK \
        (1 << MMU_KERNEL_P_IDX | 1 << MMU_PL1_P_IDX  |  \
         1 << MMU_PL2_P_IDX    | 1 << MMU_USER_P_IDX)

/* Hardware exceptions, interrupts, faults, and traps.  */
#define EXCP_HPMC                1  /* high priority machine check */
#define EXCP_POWER_FAIL          2
#define EXCP_RC                  3  /* recovery counter */
#define EXCP_EXT_INTERRUPT       4  /* external interrupt */
#define EXCP_LPMC                5  /* low priority machine check */
#define EXCP_ITLB_MISS           6  /* itlb miss / instruction page fault */
#define EXCP_IMP                 7  /* instruction memory protection trap */
#define EXCP_ILL                 8  /* illegal instruction trap */
#define EXCP_BREAK               9  /* break instruction */
#define EXCP_PRIV_OPR            10 /* privileged operation trap */
#define EXCP_PRIV_REG            11 /* privileged register trap */
#define EXCP_OVERFLOW            12 /* signed overflow trap */
#define EXCP_COND                13 /* trap-on-condition */
#define EXCP_ASSIST              14 /* assist exception trap */
#define EXCP_DTLB_MISS           15 /* dtlb miss / data page fault */
#define EXCP_NA_ITLB_MISS        16 /* non-access itlb miss */
#define EXCP_NA_DTLB_MISS        17 /* non-access dtlb miss */
#define EXCP_DMP                 18 /* data memory protection trap */
#define EXCP_DMB                 19 /* data memory break trap */
#define EXCP_TLB_DIRTY           20 /* tlb dirty bit trap */
#define EXCP_PAGE_REF            21 /* page reference trap */
#define EXCP_ASSIST_EMU          22 /* assist emulation trap */
#define EXCP_HPT                 23 /* high-privilege transfer trap */
#define EXCP_LPT                 24 /* low-privilege transfer trap */
#define EXCP_TB                  25 /* taken branch trap */
#define EXCP_DMAR                26 /* data memory access rights trap */
#define EXCP_DMPI                27 /* data memory protection id trap */
#define EXCP_UNALIGN             28 /* unaligned data reference trap */
#define EXCP_PER_INTERRUPT       29 /* performance monitor interrupt */

/* Exceptions for linux-user emulation.  */
#define EXCP_SYSCALL             30
#define EXCP_SYSCALL_LWS         31

/* Emulated hardware TOC button */
#define EXCP_TOC                 32 /* TOC = Transfer of control (NMI) */

#define CPU_INTERRUPT_NMI       CPU_INTERRUPT_TGT_EXT_3         /* TOC */

/* Taken from Linux kernel: arch/parisc/include/asm/psw.h */
#define PSW_I            0x00000001
#define PSW_D            0x00000002
#define PSW_P            0x00000004
#define PSW_Q            0x00000008
#define PSW_R            0x00000010
#define PSW_F            0x00000020
#define PSW_G            0x00000040 /* PA1.x only */
#define PSW_O            0x00000080 /* PA2.0 only */
#define PSW_CB           0x0000ff00
#define PSW_M            0x00010000
#define PSW_V            0x00020000
#define PSW_C            0x00040000
#define PSW_B            0x00080000
#define PSW_X            0x00100000
#define PSW_N            0x00200000
#define PSW_L            0x00400000
#define PSW_H            0x00800000
#define PSW_T            0x01000000
#define PSW_S            0x02000000
#define PSW_E            0x04000000
#define PSW_W            0x08000000 /* PA2.0 only */
#define PSW_Z            0x40000000 /* PA1.x only */
#define PSW_Y            0x80000000 /* PA1.x only */

#define PSW_SM (PSW_W | PSW_E | PSW_O | PSW_G | PSW_F \
               | PSW_R | PSW_Q | PSW_P | PSW_D | PSW_I)

/* ssm/rsm instructions number PSW_W and PSW_E differently */
#define PSW_SM_I         PSW_I      /* Enable External Interrupts */
#define PSW_SM_D         PSW_D
#define PSW_SM_P         PSW_P
#define PSW_SM_Q         PSW_Q      /* Enable Interrupt State Collection */
#define PSW_SM_R         PSW_R      /* Enable Recover Counter Trap */
#define PSW_SM_E         0x100
#define PSW_SM_W         0x200      /* PA2.0 only : Enable Wide Mode */

#define CR_RC            0
#define CR_PSW_DEFAULT   6          /* see SeaBIOS PDC_PSW firmware call */
#define  PDC_PSW_WIDE_BIT 2
#define CR_PID1          8
#define CR_PID2          9
#define CR_PID3          12
#define CR_PID4          13
#define CR_SCRCCR        10
#define CR_SAR           11
#define CR_IVA           14
#define CR_EIEM          15
#define CR_IT            16
#define CR_IIASQ         17
#define CR_IIAOQ         18
#define CR_IIR           19
#define CR_ISR           20
#define CR_IOR           21
#define CR_IPSW          22
#define CR_EIRR          23

FIELD(FPSR, ENA_I, 0, 1)
FIELD(FPSR, ENA_U, 1, 1)
FIELD(FPSR, ENA_O, 2, 1)
FIELD(FPSR, ENA_Z, 3, 1)
FIELD(FPSR, ENA_V, 4, 1)
FIELD(FPSR, ENABLES, 0, 5)
FIELD(FPSR, D, 5, 1)
FIELD(FPSR, T, 6, 1)
FIELD(FPSR, RM, 9, 2)
FIELD(FPSR, CQ, 11, 11)
FIELD(FPSR, CQ0_6, 15, 7)
FIELD(FPSR, CQ0_4, 17, 5)
FIELD(FPSR, CQ0_2, 19, 3)
FIELD(FPSR, CQ0, 21, 1)
FIELD(FPSR, CA, 15, 7)
FIELD(FPSR, CA0, 21, 1)
FIELD(FPSR, C, 26, 1)
FIELD(FPSR, FLG_I, 27, 1)
FIELD(FPSR, FLG_U, 28, 1)
FIELD(FPSR, FLG_O, 29, 1)
FIELD(FPSR, FLG_Z, 30, 1)
FIELD(FPSR, FLG_V, 31, 1)
FIELD(FPSR, FLAGS, 27, 5)

typedef struct HPPATLBEntry {
    union {
        IntervalTreeNode itree;
        struct HPPATLBEntry *unused_next;
    };

    target_ulong pa;

    unsigned entry_valid : 1;

    unsigned u : 1;
    unsigned t : 1;
    unsigned d : 1;
    unsigned b : 1;
    unsigned ar_type : 3;
    unsigned ar_pl1 : 2;
    unsigned ar_pl2 : 2;
    unsigned access_id : 16;
} HPPATLBEntry;

typedef struct CPUArchState {
    target_ulong iaoq_f;     /* front */
    target_ulong iaoq_b;     /* back, aka next instruction */

    target_ulong gr[32];
    uint64_t fr[32];
    uint64_t sr[8];          /* stored shifted into place for gva */

    uint32_t psw;            /* All psw bits except the following:  */
    uint32_t psw_xb;         /* X and B, in their normal positions */
    target_ulong psw_n;      /* boolean */
    target_long psw_v;       /* in most significant bit */

    /* Splitting the carry-borrow field into the MSB and "the rest", allows
     * for "the rest" to be deleted when it is unused, but the MSB is in use.
     * In addition, it's easier to compute carry-in for bit B+1 than it is to
     * compute carry-out for bit B (3 vs 4 insns for addition, assuming the
     * host has the appropriate add-with-carry insn to compute the msb).
     * Therefore the carry bits are stored as: cb_msb : cb & 0x11111110.
     */
    target_ulong psw_cb;     /* in least significant bit of next nibble */
    target_ulong psw_cb_msb; /* boolean */

    uint64_t iasq_f;
    uint64_t iasq_b;

    uint32_t fr0_shadow;     /* flags, c, ca/cq, rm, d, enables */
    float_status fp_status;

    target_ulong cr[32];     /* control registers */
    target_ulong cr_back[2]; /* back of cr17/cr18 */
    target_ulong shadow[7];  /* shadow registers */

    /*
     * During unwind of a memory insn, the base register of the address.
     * This is used to construct CR_IOR for pa2.0.
     */
    uint32_t unwind_breg;

    /*
     * ??? The number of entries isn't specified by the architecture.
     * BTLBs are not supported in 64-bit machines.
     */
#define PA10_BTLB_FIXED         16
#define PA10_BTLB_VARIABLE      0
#define HPPA_TLB_ENTRIES        256

    /* Index for round-robin tlb eviction. */
    uint32_t tlb_last;

    /*
     * For pa1.x, the partial initialized, still invalid tlb entry
     * which has had ITLBA performed, but not yet ITLBP.
     */
    HPPATLBEntry *tlb_partial;

    /* Linked list of all invalid (unused) tlb entries. */
    HPPATLBEntry *tlb_unused;

    /* Root of the search tree for all valid tlb entries. */
    IntervalTreeRoot tlb_root;

    HPPATLBEntry tlb[HPPA_TLB_ENTRIES];
} CPUHPPAState;

/**
 * HPPACPU:
 * @env: #CPUHPPAState
 *
 * An HPPA CPU.
 */
struct ArchCPU {
    CPUState parent_obj;

    CPUHPPAState env;
    QEMUTimer *alarm_timer;
};

/**
 * HPPACPUClass:
 * @parent_realize: The parent class' realize handler.
 * @parent_reset: The parent class' reset handler.
 *
 * An HPPA CPU model.
 */
struct HPPACPUClass {
    CPUClass parent_class;

    DeviceRealize parent_realize;
    DeviceReset parent_reset;
};

#include "exec/cpu-all.h"

static inline bool hppa_is_pa20(CPUHPPAState *env)
{
    return object_dynamic_cast(OBJECT(env_cpu(env)), TYPE_HPPA64_CPU) != NULL;
}

static inline int HPPA_BTLB_ENTRIES(CPUHPPAState *env)
{
    return hppa_is_pa20(env) ? 0 : PA10_BTLB_FIXED + PA10_BTLB_VARIABLE;
}

void hppa_translate_init(void);

#define CPU_RESOLVING_TYPE TYPE_HPPA_CPU

static inline uint64_t gva_offset_mask(target_ulong psw)
{
    return (psw & PSW_W
            ? MAKE_64BIT_MASK(0, 62)
            : MAKE_64BIT_MASK(0, 32));
}

static inline target_ulong hppa_form_gva_psw(target_ulong psw, uint64_t spc,
                                             target_ulong off)
{
#ifdef CONFIG_USER_ONLY
    return off;
#else
    return spc | (off & gva_offset_mask(psw));
#endif
}

static inline target_ulong hppa_form_gva(CPUHPPAState *env, uint64_t spc,
                                         target_ulong off)
{
    return hppa_form_gva_psw(env->psw, spc, off);
}

hwaddr hppa_abs_to_phys_pa2_w0(vaddr addr);
hwaddr hppa_abs_to_phys_pa2_w1(vaddr addr);

/*
 * Since PSW_{I,CB} will never need to be in tb->flags, reuse them.
 * TB_FLAG_SR_SAME indicates that SR4 through SR7 all contain the
 * same value.
 */
#define TB_FLAG_SR_SAME     PSW_I
#define TB_FLAG_PRIV_SHIFT  8
#define TB_FLAG_UNALIGN     0x400
#define CS_BASE_DIFFPAGE    (1 << 12)
#define CS_BASE_DIFFSPACE   (1 << 13)

void cpu_get_tb_cpu_state(CPUHPPAState *env, vaddr *pc,
                          uint64_t *cs_base, uint32_t *pflags);

target_ulong cpu_hppa_get_psw(CPUHPPAState *env);
void cpu_hppa_put_psw(CPUHPPAState *env, target_ulong);
void cpu_hppa_loaded_fr0(CPUHPPAState *env);

#ifdef CONFIG_USER_ONLY
static inline void cpu_hppa_change_prot_id(CPUHPPAState *env) { }
#else
void cpu_hppa_change_prot_id(CPUHPPAState *env);
#endif

int hppa_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg);
int hppa_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
void hppa_cpu_dump_state(CPUState *cs, FILE *f, int);
#ifndef CONFIG_USER_ONLY
void hppa_ptlbe(CPUHPPAState *env);
hwaddr hppa_cpu_get_phys_page_debug(CPUState *cs, vaddr addr);
void hppa_set_ior_and_isr(CPUHPPAState *env, vaddr addr, bool mmu_disabled);
bool hppa_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
                       MMUAccessType access_type, int mmu_idx,
                       bool probe, uintptr_t retaddr);
void hppa_cpu_do_interrupt(CPUState *cpu);
bool hppa_cpu_exec_interrupt(CPUState *cpu, int int_req);
int hppa_get_physical_address(CPUHPPAState *env, vaddr addr, int mmu_idx,
                              int type, hwaddr *pphys, int *pprot);
void hppa_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr,
                                     vaddr addr, unsigned size,
                                     MMUAccessType access_type,
                                     int mmu_idx, MemTxAttrs attrs,
                                     MemTxResult response, uintptr_t retaddr);
extern const MemoryRegionOps hppa_io_eir_ops;
extern const VMStateDescription vmstate_hppa_cpu;
void hppa_cpu_alarm_timer(void *);
int hppa_artype_for_page(CPUHPPAState *env, target_ulong vaddr);
#endif
G_NORETURN void hppa_dynamic_excp(CPUHPPAState *env, int excp, uintptr_t ra);

#define CPU_RESOLVING_TYPE TYPE_HPPA_CPU

#endif /* HPPA_CPU_H */
Commit	Line	Data
61766fe9 RH	1	/*
	2	* PA-RISC emulation cpu definitions for qemu.
	3	*
	4	* Copyright (c) 2016 Richard Henderson <rth@twiddle.net>
	5	*
	6	* This library is free software; you can redistribute it and/or
	7	* modify it under the terms of the GNU Lesser General Public
	8	* License as published by the Free Software Foundation; either
d6ea4236	9	* version 2.1 of the License, or (at your option) any later version.
61766fe9 RH	10	*
	11	* This library is distributed in the hope that it will be useful,
	12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	14	* Lesser General Public License for more details.
	15	*
	16	* You should have received a copy of the GNU Lesser General Public
	17	* License along with this library; if not, see <http://www.gnu.org/licenses/>.
	18	*/
	19
	20	#ifndef HPPA_CPU_H
	21	#define HPPA_CPU_H
	22
61766fe9	23	#include "cpu-qom.h"
74433bf0	24	#include "exec/cpu-defs.h"
69242e7e	25	#include "qemu/cpu-float.h"
66866cc7	26	#include "qemu/interval-tree.h"
f33a22c1	27	#include "hw/registerfields.h"
61766fe9	28
451d993d RH	29	#define MMU_ABS_W_IDX 6
	30	#define MMU_ABS_IDX 7
	31	#define MMU_KERNEL_IDX 8
	32	#define MMU_KERNEL_P_IDX 9
	33	#define MMU_PL1_IDX 10
	34	#define MMU_PL1_P_IDX 11
	35	#define MMU_PL2_IDX 12
	36	#define MMU_PL2_P_IDX 13
	37	#define MMU_USER_IDX 14
	38	#define MMU_USER_P_IDX 15
	39
	40	#define MMU_IDX_MMU_DISABLED(MIDX) ((MIDX) < MMU_KERNEL_IDX)
bb67ec32 RH	41	#define MMU_IDX_TO_PRIV(MIDX) (((MIDX) - MMU_KERNEL_IDX) / 2)
	42	#define MMU_IDX_TO_P(MIDX) (((MIDX) - MMU_KERNEL_IDX) & 1)
	43	#define PRIV_P_TO_MMU_IDX(PRIV, P) ((PRIV) * 2 + !!(P) + MMU_KERNEL_IDX)
c01e5dfb	44
3c13b0ff RH	45	#define PRIV_KERNEL 0
	46	#define PRIV_USER 3
	47
f5b5c857	48	#define TARGET_INSN_START_EXTRA_WORDS 2
61766fe9	49
451d993d	50	/* No need to flush MMU_ABS_IDX /
88b7ad10	51	#define HPPA_MMU_FLUSH_MASK \
bb67ec32 RH	52	(1 << MMU_KERNEL_IDX \| 1 << MMU_KERNEL_P_IDX \| \
	53	1 << MMU_PL1_IDX \| 1 << MMU_PL1_P_IDX \| \
	54	1 << MMU_PL2_IDX \| 1 << MMU_PL2_P_IDX \| \
	55	1 << MMU_USER_IDX \| 1 << MMU_USER_P_IDX)
	56
385b3280	57	/* Indices to flush for access_id changes. */
bb67ec32 RH	58	#define HPPA_MMU_FLUSH_P_MASK \
	59	(1 << MMU_KERNEL_P_IDX \| 1 << MMU_PL1_P_IDX \| \
	60	1 << MMU_PL2_P_IDX \| 1 << MMU_USER_P_IDX)
88b7ad10	61
8b81968c	62	/* Hardware exceptions, interrupts, faults, and traps. */
2986721d RH	63	#define EXCP_HPMC 1 /* high priority machine check */
	64	#define EXCP_POWER_FAIL 2
	65	#define EXCP_RC 3 /* recovery counter */
	66	#define EXCP_EXT_INTERRUPT 4 /* external interrupt */
	67	#define EXCP_LPMC 5 /* low priority machine check */
	68	#define EXCP_ITLB_MISS 6 /* itlb miss / instruction page fault */
	69	#define EXCP_IMP 7 /* instruction memory protection trap */
	70	#define EXCP_ILL 8 /* illegal instruction trap */
	71	#define EXCP_BREAK 9 /* break instruction */
	72	#define EXCP_PRIV_OPR 10 /* privileged operation trap */
	73	#define EXCP_PRIV_REG 11 /* privileged register trap */
	74	#define EXCP_OVERFLOW 12 /* signed overflow trap */
	75	#define EXCP_COND 13 /* trap-on-condition */
	76	#define EXCP_ASSIST 14 /* assist exception trap */
	77	#define EXCP_DTLB_MISS 15 /* dtlb miss / data page fault */
	78	#define EXCP_NA_ITLB_MISS 16 /* non-access itlb miss */
	79	#define EXCP_NA_DTLB_MISS 17 /* non-access dtlb miss */
	80	#define EXCP_DMP 18 /* data memory protection trap */
	81	#define EXCP_DMB 19 /* data memory break trap */
	82	#define EXCP_TLB_DIRTY 20 /* tlb dirty bit trap */
	83	#define EXCP_PAGE_REF 21 /* page reference trap */
	84	#define EXCP_ASSIST_EMU 22 /* assist emulation trap */
	85	#define EXCP_HPT 23 /* high-privilege transfer trap */
	86	#define EXCP_LPT 24 /* low-privilege transfer trap */
	87	#define EXCP_TB 25 /* taken branch trap */
	88	#define EXCP_DMAR 26 /* data memory access rights trap */
	89	#define EXCP_DMPI 27 /* data memory protection id trap */
	90	#define EXCP_UNALIGN 28 /* unaligned data reference trap */
	91	#define EXCP_PER_INTERRUPT 29 /* performance monitor interrupt */
	92
	93	/* Exceptions for linux-user emulation. */
	94	#define EXCP_SYSCALL 30
	95	#define EXCP_SYSCALL_LWS 31
61766fe9	96
4a4554c6 HD	97	/* Emulated hardware TOC button */
	98	#define EXCP_TOC 32 /* TOC = Transfer of control (NMI) */
	99
	100	#define CPU_INTERRUPT_NMI CPU_INTERRUPT_TGT_EXT_3 /* TOC */
	101
fa57e327 RH	102	/* Taken from Linux kernel: arch/parisc/include/asm/psw.h */
	103	#define PSW_I 0x00000001
	104	#define PSW_D 0x00000002
	105	#define PSW_P 0x00000004
	106	#define PSW_Q 0x00000008
	107	#define PSW_R 0x00000010
	108	#define PSW_F 0x00000020
	109	#define PSW_G 0x00000040 /* PA1.x only */
	110	#define PSW_O 0x00000080 /* PA2.0 only */
	111	#define PSW_CB 0x0000ff00
	112	#define PSW_M 0x00010000
	113	#define PSW_V 0x00020000
	114	#define PSW_C 0x00040000
	115	#define PSW_B 0x00080000
	116	#define PSW_X 0x00100000
	117	#define PSW_N 0x00200000
	118	#define PSW_L 0x00400000
	119	#define PSW_H 0x00800000
	120	#define PSW_T 0x01000000
	121	#define PSW_S 0x02000000
	122	#define PSW_E 0x04000000
fa57e327	123	#define PSW_W 0x08000000 /* PA2.0 only */
fa57e327 RH	124	#define PSW_Z 0x40000000 /* PA1.x only */
	125	#define PSW_Y 0x80000000 /* PA1.x only */
	126
	127	#define PSW_SM (PSW_W \| PSW_E \| PSW_O \| PSW_G \| PSW_F \
	128	\| PSW_R \| PSW_Q \| PSW_P \| PSW_D \| PSW_I)
	129
	130	/* ssm/rsm instructions number PSW_W and PSW_E differently */
	131	#define PSW_SM_I PSW_I /* Enable External Interrupts */
	132	#define PSW_SM_D PSW_D
	133	#define PSW_SM_P PSW_P
	134	#define PSW_SM_Q PSW_Q /* Enable Interrupt State Collection */
	135	#define PSW_SM_R PSW_R /* Enable Recover Counter Trap */
fa57e327 RH	136	#define PSW_SM_E 0x100
fa57e327 RH	137	#define PSW_SM_W 0x200 /* PA2.0 only : Enable Wide Mode */
fa57e327	138
35136a77	139	#define CR_RC 0
ab9af359 HD	140	#define CR_PSW_DEFAULT 6 /* see SeaBIOS PDC_PSW firmware call */
ab9af359 HD	141	#define PDC_PSW_WIDE_BIT 2
d5de20bd SS	142	#define CR_PID1 8
	143	#define CR_PID2 9
	144	#define CR_PID3 12
	145	#define CR_PID4 13
35136a77 RH	146	#define CR_SCRCCR 10
	147	#define CR_SAR 11
	148	#define CR_IVA 14
	149	#define CR_EIEM 15
	150	#define CR_IT 16
	151	#define CR_IIASQ 17
	152	#define CR_IIAOQ 18
	153	#define CR_IIR 19
	154	#define CR_ISR 20
	155	#define CR_IOR 21
	156	#define CR_IPSW 22
	157	#define CR_EIRR 23
	158
f33a22c1 RH	159	FIELD(FPSR, ENA_I, 0, 1)
	160	FIELD(FPSR, ENA_U, 1, 1)
	161	FIELD(FPSR, ENA_O, 2, 1)
	162	FIELD(FPSR, ENA_Z, 3, 1)
	163	FIELD(FPSR, ENA_V, 4, 1)
	164	FIELD(FPSR, ENABLES, 0, 5)
	165	FIELD(FPSR, D, 5, 1)
	166	FIELD(FPSR, T, 6, 1)
	167	FIELD(FPSR, RM, 9, 2)
	168	FIELD(FPSR, CQ, 11, 11)
	169	FIELD(FPSR, CQ0_6, 15, 7)
	170	FIELD(FPSR, CQ0_4, 17, 5)
	171	FIELD(FPSR, CQ0_2, 19, 3)
	172	FIELD(FPSR, CQ0, 21, 1)
	173	FIELD(FPSR, CA, 15, 7)
	174	FIELD(FPSR, CA0, 21, 1)
	175	FIELD(FPSR, C, 26, 1)
	176	FIELD(FPSR, FLG_I, 27, 1)
	177	FIELD(FPSR, FLG_U, 28, 1)
	178	FIELD(FPSR, FLG_O, 29, 1)
	179	FIELD(FPSR, FLG_Z, 30, 1)
	180	FIELD(FPSR, FLG_V, 31, 1)
	181	FIELD(FPSR, FLAGS, 27, 5)
	182
729cd350	183	typedef struct HPPATLBEntry {
d7553f35 RH	184	union {
	185	IntervalTreeNode itree;
	186	struct HPPATLBEntry *unused_next;
	187	};
66866cc7	188
c53e401e	189	target_ulong pa;
f8cda28b RH	190
	191	unsigned entry_valid : 1;
	192
650cdb2a RH	193	unsigned u : 1;
	194	unsigned t : 1;
	195	unsigned d : 1;
	196	unsigned b : 1;
650cdb2a RH	197	unsigned ar_type : 3;
	198	unsigned ar_pl1 : 2;
	199	unsigned ar_pl2 : 2;
650cdb2a	200	unsigned access_id : 16;
729cd350	201	} HPPATLBEntry;
650cdb2a	202
1ea4a06a	203	typedef struct CPUArchState {
c53e401e RH	204	target_ulong iaoq_f; /* front */
c53e401e RH	205	target_ulong iaoq_b; /* back, aka next instruction */
f8c0fd98	206
c53e401e	207	target_ulong gr[32];
61766fe9	208	uint64_t fr[32];
33423472	209	uint64_t sr[8]; /* stored shifted into place for gva */
61766fe9	210
ebc9401a RH	211	uint32_t psw; /* All psw bits except the following: */
ebc9401a RH	212	uint32_t psw_xb; /* X and B, in their normal positions */
c53e401e RH	213	target_ulong psw_n; /* boolean */
c53e401e RH	214	target_long psw_v; /* in most significant bit */
61766fe9 RH	215
	216	/* Splitting the carry-borrow field into the MSB and "the rest", allows
	217	* for "the rest" to be deleted when it is unused, but the MSB is in use.
	218	* In addition, it's easier to compute carry-in for bit B+1 than it is to
	219	* compute carry-out for bit B (3 vs 4 insns for addition, assuming the
	220	* host has the appropriate add-with-carry insn to compute the msb).
	221	* Therefore the carry bits are stored as: cb_msb : cb & 0x11111110.
	222	*/
c53e401e RH	223	target_ulong psw_cb; /* in least significant bit of next nibble */
c53e401e RH	224	target_ulong psw_cb_msb; /* boolean */
61766fe9	225
c301f34e RH	226	uint64_t iasq_f;
c301f34e RH	227	uint64_t iasq_b;
61766fe9	228
61766fe9 RH	229	uint32_t fr0_shadow; /* flags, c, ca/cq, rm, d, enables */
	230	float_status fp_status;
	231
c53e401e RH	232	target_ulong cr[32]; /* control registers */
	233	target_ulong cr_back[2]; /* back of cr17/cr18 */
	234	target_ulong shadow[7]; /* shadow registers */
35136a77	235
f5b5c857 RH	236	/*
	237	* During unwind of a memory insn, the base register of the address.
	238	* This is used to construct CR_IOR for pa2.0.
	239	*/
	240	uint32_t unwind_breg;
	241
9cf2112b RH	242	/*
	243	* ??? The number of entries isn't specified by the architecture.
	244	* BTLBs are not supported in 64-bit machines.
	245	*/
	246	#define PA10_BTLB_FIXED 16
	247	#define PA10_BTLB_VARIABLE 0
df5c6a50	248	#define HPPA_TLB_ENTRIES 256
df5c6a50	249
d7553f35	250	/* Index for round-robin tlb eviction. */
650cdb2a	251	uint32_t tlb_last;
d7553f35 RH	252
	253	/*
	254	* For pa1.x, the partial initialized, still invalid tlb entry
	255	* which has had ITLBA performed, but not yet ITLBP.
	256	*/
	257	HPPATLBEntry *tlb_partial;
	258
	259	/* Linked list of all invalid (unused) tlb entries. */
	260	HPPATLBEntry *tlb_unused;
	261
	262	/* Root of the search tree for all valid tlb entries. */
	263	IntervalTreeRoot tlb_root;
	264
	265	HPPATLBEntry tlb[HPPA_TLB_ENTRIES];
1ea4a06a	266	} CPUHPPAState;
61766fe9 RH	267
	268	/**
	269	* HPPACPU:
	270	* @env: #CPUHPPAState
	271	*
	272	* An HPPA CPU.
	273	*/
b36e239e	274	struct ArchCPU {
61766fe9	275	CPUState parent_obj;
61766fe9 RH	276
61766fe9 RH	277	CPUHPPAState env;
49c29d6c	278	QEMUTimer *alarm_timer;
61766fe9 RH	279	};
61766fe9 RH	280
9348028e PMD	281	/**
	282	* HPPACPUClass:
	283	* @parent_realize: The parent class' realize handler.
	284	* @parent_reset: The parent class' reset handler.
	285	*
	286	* An HPPA CPU model.
	287	*/
	288	struct HPPACPUClass {
	289	CPUClass parent_class;
	290
	291	DeviceRealize parent_realize;
	292	DeviceReset parent_reset;
	293	};
	294
61766fe9 RH	295	#include "exec/cpu-all.h"
61766fe9 RH	296
bd6243a3 RH	297	static inline bool hppa_is_pa20(CPUHPPAState *env)
	298	{
	299	return object_dynamic_cast(OBJECT(env_cpu(env)), TYPE_HPPA64_CPU) != NULL;
	300	}
	301
9cf2112b RH	302	static inline int HPPA_BTLB_ENTRIES(CPUHPPAState *env)
	303	{
	304	return hppa_is_pa20(env) ? 0 : PA10_BTLB_FIXED + PA10_BTLB_VARIABLE;
	305	}
	306
61766fe9 RH	307	void hppa_translate_init(void);
61766fe9 RH	308
0dacec87	309	#define CPU_RESOLVING_TYPE TYPE_HPPA_CPU
61766fe9	310
7d50b696 SS	311	static inline uint64_t gva_offset_mask(target_ulong psw)
	312	{
	313	return (psw & PSW_W
	314	? MAKE_64BIT_MASK(0, 62)
	315	: MAKE_64BIT_MASK(0, 32));
	316	}
	317
c53e401e RH	318	static inline target_ulong hppa_form_gva_psw(target_ulong psw, uint64_t spc,
c53e401e RH	319	target_ulong off)
c301f34e RH	320	{
	321	#ifdef CONFIG_USER_ONLY
	322	return off;
	323	#else
7d50b696	324	return spc \| (off & gva_offset_mask(psw));
c301f34e RH	325	#endif
	326	}
	327
	328	static inline target_ulong hppa_form_gva(CPUHPPAState *env, uint64_t spc,
c53e401e	329	target_ulong off)
c301f34e RH	330	{
	331	return hppa_form_gva_psw(env->psw, spc, off);
	332	}
	333
ccdf741c RH	334	hwaddr hppa_abs_to_phys_pa2_w0(vaddr addr);
	335	hwaddr hppa_abs_to_phys_pa2_w1(vaddr addr);
	336
217d1a5e RH	337	/*
217d1a5e RH	338	* Since PSW_{I,CB} will never need to be in tb->flags, reuse them.
494737b7 RH	339	* TB_FLAG_SR_SAME indicates that SR4 through SR7 all contain the
	340	* same value.
	341	*/
	342	#define TB_FLAG_SR_SAME PSW_I
c301f34e	343	#define TB_FLAG_PRIV_SHIFT 8
217d1a5e	344	#define TB_FLAG_UNALIGN 0x400
9dfcd243 RH	345	#define CS_BASE_DIFFPAGE (1 << 12)
9dfcd243 RH	346	#define CS_BASE_DIFFSPACE (1 << 13)
c301f34e	347
b61603bf RH	348	void cpu_get_tb_cpu_state(CPUHPPAState env, vaddr pc,
b61603bf RH	349	uint64_t cs_base, uint32_t pflags);
61766fe9	350
c53e401e RH	351	target_ulong cpu_hppa_get_psw(CPUHPPAState *env);
c53e401e RH	352	void cpu_hppa_put_psw(CPUHPPAState *env, target_ulong);
61766fe9 RH	353	void cpu_hppa_loaded_fr0(CPUHPPAState *env);
61766fe9 RH	354
d5de20bd SS	355	#ifdef CONFIG_USER_ONLY
	356	static inline void cpu_hppa_change_prot_id(CPUHPPAState *env) { }
	357	#else
	358	void cpu_hppa_change_prot_id(CPUHPPAState *env);
	359	#endif
	360
a010bdbe	361	int hppa_cpu_gdb_read_register(CPUState cpu, GByteArray buf, int reg);
61766fe9	362	int hppa_cpu_gdb_write_register(CPUState cpu, uint8_t buf, int reg);
90c84c56	363	void hppa_cpu_dump_state(CPUState cs, FILE f, int);
860e0b96	364	#ifndef CONFIG_USER_ONLY
d7553f35	365	void hppa_ptlbe(CPUHPPAState *env);
6d2d454a	366	hwaddr hppa_cpu_get_phys_page_debug(CPUState *cs, vaddr addr);
3824e0d6	367	void hppa_set_ior_and_isr(CPUHPPAState *env, vaddr addr, bool mmu_disabled);
3c7bef03 RH	368	bool hppa_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
	369	MMUAccessType access_type, int mmu_idx,
	370	bool probe, uintptr_t retaddr);
68fa1780 PMD	371	void hppa_cpu_do_interrupt(CPUState *cpu);
68fa1780 PMD	372	bool hppa_cpu_exec_interrupt(CPUState *cpu, int int_req);
650cdb2a	373	int hppa_get_physical_address(CPUHPPAState *env, vaddr addr, int mmu_idx,
190d7fa5	374	int type, hwaddr pphys, int pprot);
9ccbe394 HD	375	void hppa_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr,
	376	vaddr addr, unsigned size,
	377	MMUAccessType access_type,
	378	int mmu_idx, MemTxAttrs attrs,
	379	MemTxResult response, uintptr_t retaddr);
4f5f2548	380	extern const MemoryRegionOps hppa_io_eir_ops;
8a9358cc	381	extern const VMStateDescription vmstate_hppa_cpu;
49c29d6c	382	void hppa_cpu_alarm_timer(void *);
43e05652	383	int hppa_artype_for_page(CPUHPPAState *env, target_ulong vaddr);
650cdb2a	384	#endif
8905770b	385	G_NORETURN void hppa_dynamic_excp(CPUHPPAState *env, int excp, uintptr_t ra);
61766fe9	386
d3ae32d4 RH	387	#define CPU_RESOLVING_TYPE TYPE_HPPA_CPU
d3ae32d4 RH	388
61766fe9	389	#endif /* HPPA_CPU_H */