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1d0cb67d AF |
1 | /* |
2 | * QEMU PowerPC CPU | |
3 | * | |
4 | * Copyright (c) 2012 SUSE LINUX Products GmbH | |
5 | * | |
6 | * This library is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU Lesser General Public | |
8 | * License as published by the Free Software Foundation; either | |
9 | * version 2.1 of the License, or (at your option) any later version. | |
10 | * | |
11 | * This library is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
14 | * Lesser General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU Lesser General Public | |
17 | * License along with this library; if not, see | |
18 | * <http://www.gnu.org/licenses/lgpl-2.1.html> | |
19 | */ | |
20 | #ifndef QEMU_PPC_CPU_QOM_H | |
21 | #define QEMU_PPC_CPU_QOM_H | |
22 | ||
2e5b09fd | 23 | #include "hw/core/cpu.h" |
db1015e9 | 24 | #include "qom/object.h" |
1d0cb67d AF |
25 | |
26 | #ifdef TARGET_PPC64 | |
27 | #define TYPE_POWERPC_CPU "powerpc64-cpu" | |
1d0cb67d AF |
28 | #else |
29 | #define TYPE_POWERPC_CPU "powerpc-cpu" | |
30 | #endif | |
31 | ||
db1015e9 EH |
32 | typedef struct PowerPCCPU PowerPCCPU; |
33 | typedef struct PowerPCCPUClass PowerPCCPUClass; | |
1d0cb67d AF |
34 | #define POWERPC_CPU_CLASS(klass) \ |
35 | OBJECT_CLASS_CHECK(PowerPCCPUClass, (klass), TYPE_POWERPC_CPU) | |
36 | #define POWERPC_CPU(obj) \ | |
37 | OBJECT_CHECK(PowerPCCPU, (obj), TYPE_POWERPC_CPU) | |
38 | #define POWERPC_CPU_GET_CLASS(obj) \ | |
39 | OBJECT_GET_CLASS(PowerPCCPUClass, (obj), TYPE_POWERPC_CPU) | |
40 | ||
2d34fe39 PB |
41 | typedef struct CPUPPCState CPUPPCState; |
42 | typedef struct ppc_tb_t ppc_tb_t; | |
43 | typedef struct ppc_dcr_t ppc_dcr_t; | |
44 | ||
45 | /*****************************************************************************/ | |
46 | /* MMU model */ | |
47 | typedef enum powerpc_mmu_t powerpc_mmu_t; | |
48 | enum powerpc_mmu_t { | |
49 | POWERPC_MMU_UNKNOWN = 0x00000000, | |
50 | /* Standard 32 bits PowerPC MMU */ | |
51 | POWERPC_MMU_32B = 0x00000001, | |
52 | /* PowerPC 6xx MMU with software TLB */ | |
53 | POWERPC_MMU_SOFT_6xx = 0x00000002, | |
54 | /* PowerPC 74xx MMU with software TLB */ | |
55 | POWERPC_MMU_SOFT_74xx = 0x00000003, | |
56 | /* PowerPC 4xx MMU with software TLB */ | |
57 | POWERPC_MMU_SOFT_4xx = 0x00000004, | |
58 | /* PowerPC 4xx MMU with software TLB and zones protections */ | |
59 | POWERPC_MMU_SOFT_4xx_Z = 0x00000005, | |
60 | /* PowerPC MMU in real mode only */ | |
61 | POWERPC_MMU_REAL = 0x00000006, | |
62 | /* Freescale MPC8xx MMU model */ | |
63 | POWERPC_MMU_MPC8xx = 0x00000007, | |
64 | /* BookE MMU model */ | |
65 | POWERPC_MMU_BOOKE = 0x00000008, | |
66 | /* BookE 2.06 MMU model */ | |
67 | POWERPC_MMU_BOOKE206 = 0x00000009, | |
68 | /* PowerPC 601 MMU model (specific BATs format) */ | |
69 | POWERPC_MMU_601 = 0x0000000A, | |
70 | #define POWERPC_MMU_64 0x00010000 | |
2d34fe39 PB |
71 | /* 64 bits PowerPC MMU */ |
72 | POWERPC_MMU_64B = POWERPC_MMU_64 | 0x00000001, | |
73 | /* Architecture 2.03 and later (has LPCR) */ | |
74 | POWERPC_MMU_2_03 = POWERPC_MMU_64 | 0x00000002, | |
75 | /* Architecture 2.06 variant */ | |
58969eee | 76 | POWERPC_MMU_2_06 = POWERPC_MMU_64 | 0x00000003, |
2d34fe39 | 77 | /* Architecture 2.07 variant */ |
58969eee | 78 | POWERPC_MMU_2_07 = POWERPC_MMU_64 | 0x00000004, |
86cf1e9f | 79 | /* Architecture 3.00 variant */ |
ca79b3b7 | 80 | POWERPC_MMU_3_00 = POWERPC_MMU_64 | 0x00000005, |
2d34fe39 PB |
81 | }; |
82 | ||
83 | /*****************************************************************************/ | |
84 | /* Exception model */ | |
85 | typedef enum powerpc_excp_t powerpc_excp_t; | |
86 | enum powerpc_excp_t { | |
87 | POWERPC_EXCP_UNKNOWN = 0, | |
88 | /* Standard PowerPC exception model */ | |
89 | POWERPC_EXCP_STD, | |
90 | /* PowerPC 40x exception model */ | |
91 | POWERPC_EXCP_40x, | |
92 | /* PowerPC 601 exception model */ | |
93 | POWERPC_EXCP_601, | |
94 | /* PowerPC 602 exception model */ | |
95 | POWERPC_EXCP_602, | |
96 | /* PowerPC 603 exception model */ | |
97 | POWERPC_EXCP_603, | |
98 | /* PowerPC 603e exception model */ | |
99 | POWERPC_EXCP_603E, | |
100 | /* PowerPC G2 exception model */ | |
101 | POWERPC_EXCP_G2, | |
102 | /* PowerPC 604 exception model */ | |
103 | POWERPC_EXCP_604, | |
104 | /* PowerPC 7x0 exception model */ | |
105 | POWERPC_EXCP_7x0, | |
106 | /* PowerPC 7x5 exception model */ | |
107 | POWERPC_EXCP_7x5, | |
108 | /* PowerPC 74xx exception model */ | |
109 | POWERPC_EXCP_74xx, | |
110 | /* BookE exception model */ | |
111 | POWERPC_EXCP_BOOKE, | |
112 | /* PowerPC 970 exception model */ | |
113 | POWERPC_EXCP_970, | |
114 | /* POWER7 exception model */ | |
115 | POWERPC_EXCP_POWER7, | |
116 | /* POWER8 exception model */ | |
117 | POWERPC_EXCP_POWER8, | |
a790e82b BH |
118 | /* POWER9 exception model */ |
119 | POWERPC_EXCP_POWER9, | |
2d34fe39 PB |
120 | }; |
121 | ||
7778a575 BH |
122 | /*****************************************************************************/ |
123 | /* PM instructions */ | |
124 | typedef enum { | |
125 | PPC_PM_DOZE, | |
126 | PPC_PM_NAP, | |
127 | PPC_PM_SLEEP, | |
128 | PPC_PM_RVWINKLE, | |
21c0d66a | 129 | PPC_PM_STOP, |
7778a575 BH |
130 | } powerpc_pm_insn_t; |
131 | ||
2d34fe39 PB |
132 | /*****************************************************************************/ |
133 | /* Input pins model */ | |
134 | typedef enum powerpc_input_t powerpc_input_t; | |
135 | enum powerpc_input_t { | |
136 | PPC_FLAGS_INPUT_UNKNOWN = 0, | |
137 | /* PowerPC 6xx bus */ | |
138 | PPC_FLAGS_INPUT_6xx, | |
139 | /* BookE bus */ | |
140 | PPC_FLAGS_INPUT_BookE, | |
141 | /* PowerPC 405 bus */ | |
142 | PPC_FLAGS_INPUT_405, | |
143 | /* PowerPC 970 bus */ | |
144 | PPC_FLAGS_INPUT_970, | |
145 | /* PowerPC POWER7 bus */ | |
146 | PPC_FLAGS_INPUT_POWER7, | |
67afe775 BH |
147 | /* PowerPC POWER9 bus */ |
148 | PPC_FLAGS_INPUT_POWER9, | |
2d34fe39 PB |
149 | /* PowerPC 401 bus */ |
150 | PPC_FLAGS_INPUT_401, | |
151 | /* Freescale RCPU bus */ | |
152 | PPC_FLAGS_INPUT_RCPU, | |
153 | }; | |
154 | ||
b07c59f7 | 155 | typedef struct PPCHash64Options PPCHash64Options; |
d0e39c5d | 156 | |
1d0cb67d AF |
157 | /** |
158 | * PowerPCCPUClass: | |
4776ce60 | 159 | * @parent_realize: The parent class' realize handler. |
1d0cb67d AF |
160 | * @parent_reset: The parent class' reset handler. |
161 | * | |
162 | * A PowerPC CPU model. | |
163 | */ | |
db1015e9 | 164 | struct PowerPCCPUClass { |
1d0cb67d AF |
165 | /*< private >*/ |
166 | CPUClass parent_class; | |
167 | /*< public >*/ | |
168 | ||
4776ce60 | 169 | DeviceRealize parent_realize; |
7bbc124e | 170 | DeviceUnrealize parent_unrealize; |
781c67ca | 171 | DeviceReset parent_reset; |
b8e99967 | 172 | void (*parent_parse_features)(const char *type, char *str, Error **errp); |
2985b86b | 173 | |
cfe34f44 | 174 | uint32_t pvr; |
03ae4133 | 175 | bool (*pvr_match)(struct PowerPCCPUClass *pcc, uint32_t pvr); |
8cd2ce7a TH |
176 | uint64_t pcr_mask; /* Available bits in PCR register */ |
177 | uint64_t pcr_supported; /* Bits for supported PowerISA versions */ | |
cfe34f44 AF |
178 | uint32_t svr; |
179 | uint64_t insns_flags; | |
180 | uint64_t insns_flags2; | |
181 | uint64_t msr_mask; | |
e232eccc | 182 | uint64_t lpcr_mask; /* Available bits in the LPCR */ |
403aacdb | 183 | uint64_t lpcr_pm; /* Power-saving mode Exit Cause Enable bits */ |
cfe34f44 AF |
184 | powerpc_mmu_t mmu_model; |
185 | powerpc_excp_t excp_model; | |
186 | powerpc_input_t bus_model; | |
187 | uint32_t flags; | |
188 | int bfd_mach; | |
0cbad81f | 189 | uint32_t l1_dcache_size, l1_icache_size; |
707c7c2e FR |
190 | #ifndef CONFIG_USER_ONLY |
191 | unsigned int gdb_num_sprs; | |
192 | const char *gdb_spr_xml; | |
193 | #endif | |
b07c59f7 | 194 | const PPCHash64Options *hash64_opts; |
c64abd1f | 195 | struct ppc_radix_page_info *radix_page_info; |
a8dafa52 | 196 | uint32_t lrg_decr_bits; |
289af4ac | 197 | int n_host_threads; |
cfe34f44 AF |
198 | void (*init_proc)(CPUPPCState *env); |
199 | int (*check_pow)(CPUPPCState *env); | |
b2305601 | 200 | int (*handle_mmu_fault)(PowerPCCPU *cpu, vaddr eaddr, int rwx, int mmu_idx); |
382d2db6 | 201 | bool (*interrupts_big_endian)(PowerPCCPU *cpu); |
db1015e9 | 202 | }; |
1d0cb67d | 203 | |
a90db158 | 204 | #ifndef CONFIG_USER_ONLY |
98a8b524 AK |
205 | typedef struct PPCTimebase { |
206 | uint64_t guest_timebase; | |
207 | int64_t time_of_the_day_ns; | |
d14f3397 | 208 | bool runstate_paused; |
98a8b524 AK |
209 | } PPCTimebase; |
210 | ||
8a9358cc | 211 | extern const VMStateDescription vmstate_ppc_timebase; |
98a8b524 AK |
212 | |
213 | #define VMSTATE_PPC_TIMEBASE_V(_field, _state, _version) { \ | |
214 | .name = (stringify(_field)), \ | |
215 | .version_id = (_version), \ | |
216 | .size = sizeof(PPCTimebase), \ | |
217 | .vmsd = &vmstate_ppc_timebase, \ | |
218 | .flags = VMS_STRUCT, \ | |
219 | .offset = vmstate_offset_value(_state, _field, PPCTimebase), \ | |
220 | } | |
42043e4f LV |
221 | |
222 | void cpu_ppc_clock_vm_state_change(void *opaque, int running, | |
223 | RunState state); | |
a90db158 AK |
224 | #endif |
225 | ||
1d0cb67d | 226 | #endif |