[thirdparty/qemu.git] / target / sparc / insns.decode

# SPDX-License-Identifier: LGPL-2.0+
#
# Sparc instruction decode definitions.
# Copyright (c) 2023 Richard Henderson <rth@twiddle.net>

##
## Major Opcodes 00 and 01 -- branches, call, and sethi.
##

&bcc    i a cond cc
BPcc    00 a:1 cond:4   001 cc:1 0 - i:s19                 &bcc
Bicc    00 a:1 cond:4   010          i:s22                 &bcc cc=0
FBPfcc  00 a:1 cond:4   101 cc:2   - i:s19                 &bcc
FBfcc   00 a:1 cond:4   110          i:s22                 &bcc cc=0

%d16    20:s2 0:14
BPr     00 a:1 0 cond:3 011 ..     - rs1:5 ..............  i=%d16

NCP     00 -   ----     111 ----------------------         # CBcc

SETHI   00 rd:5         100 i:22

CALL    01 i:s30

##
## Major Opcode 10 -- integer, floating-point, vis, and system insns.
##

&r_r_ri     rd rs1 rs2_or_imm imm:bool
@n_r_ri     .. ..... ...... rs1:5 imm:1 rs2_or_imm:s13     &r_r_ri rd=0

{
  [
    STBAR           10 00000 101000 01111 0 0000000000000
    MEMBAR          10 00000 101000 01111 1 000000 cmask:3 mmask:4

    RDCCR           10 rd:5  101000 00010 0 0000000000000
    RDASI           10 rd:5  101000 00011 0 0000000000000
    RDTICK          10 rd:5  101000 00100 0 0000000000000
    RDPC            10 rd:5  101000 00101 0 0000000000000
    RDFPRS          10 rd:5  101000 00110 0 0000000000000
    RDASR17         10 rd:5  101000 10001 0 0000000000000
    RDGSR           10 rd:5  101000 10011 0 0000000000000
    RDSOFTINT       10 rd:5  101000 10110 0 0000000000000
    RDTICK_CMPR     10 rd:5  101000 10111 0 0000000000000
    RDSTICK         10 rd:5  101000 11000 0 0000000000000
    RDSTICK_CMPR    10 rd:5  101000 11001 0 0000000000000
    RDSTRAND_STATUS 10 rd:5  101000 11010 0 0000000000000
  ]
  # Before v8, all rs1 accepted; otherwise rs1==0.
  RDY               10 rd:5  101000 rs1:5 0 0000000000000
}

{
  [
    WRY             10 00000 110000 ..... . .............  @n_r_ri
    WRCCR           10 00010 110000 ..... . .............  @n_r_ri
    WRASI           10 00011 110000 ..... . .............  @n_r_ri
    WRFPRS          10 00110 110000 ..... . .............  @n_r_ri
    {
      WRGSR         10 10011 110000 ..... . .............  @n_r_ri
      WRPOWERDOWN   10 10011 110000 ..... . .............  @n_r_ri
    }
    WRSOFTINT_SET   10 10100 110000 ..... . .............  @n_r_ri
    WRSOFTINT_CLR   10 10101 110000 ..... . .............  @n_r_ri
    WRSOFTINT       10 10110 110000 ..... . .............  @n_r_ri
    WRTICK_CMPR     10 10111 110000 ..... . .............  @n_r_ri
    WRSTICK         10 11000 110000 ..... . .............  @n_r_ri
    WRSTICK_CMPR    10 11001 110000 ..... . .............  @n_r_ri
  ]
  # Before v8, rs1==0 was WRY, and the rest executed as nop.
  [
    NOP_v7          10 ----- 110000 ----- 0 00000000 -----
    NOP_v7          10 ----- 110000 ----- 1 -------- -----
  ]
}

{
  RDPSR             10 rd:5  101001 00000 0 0000000000000
  RDHPR_hpstate     10 rd:5  101001 00000 0 0000000000000
}
RDHPR_htstate       10 rd:5  101001 00001 0 0000000000000
RDHPR_hintp         10 rd:5  101001 00011 0 0000000000000
RDHPR_htba          10 rd:5  101001 00101 0 0000000000000
RDHPR_hver          10 rd:5  101001 00110 0 0000000000000
RDHPR_hstick_cmpr   10 rd:5  101001 11111 0 0000000000000

{
  WRPSR             10 00000 110001 ..... . .............  @n_r_ri
  SAVED             10 00000 110001 00000 0 0000000000000
}
RESTORED            10 00001 110001 00000 0 0000000000000
# UA2005 ALLCLEAN
# UA2005 OTHERW
# UA2005 NORMALW
# UA2005 INVALW

{
  RDWIM             10 rd:5  101010 00000 0 0000000000000
  RDPR_tpc          10 rd:5  101010 00000 0 0000000000000
}
RDPR_tnpc           10 rd:5  101010 00001 0 0000000000000
RDPR_tstate         10 rd:5  101010 00010 0 0000000000000
RDPR_tt             10 rd:5  101010 00011 0 0000000000000
RDPR_tick           10 rd:5  101010 00100 0 0000000000000
RDPR_tba            10 rd:5  101010 00101 0 0000000000000
RDPR_pstate         10 rd:5  101010 00110 0 0000000000000
RDPR_tl             10 rd:5  101010 00111 0 0000000000000
RDPR_pil            10 rd:5  101010 01000 0 0000000000000
RDPR_cwp            10 rd:5  101010 01001 0 0000000000000
RDPR_cansave        10 rd:5  101010 01010 0 0000000000000
RDPR_canrestore     10 rd:5  101010 01011 0 0000000000000
RDPR_cleanwin       10 rd:5  101010 01100 0 0000000000000
RDPR_otherwin       10 rd:5  101010 01101 0 0000000000000
RDPR_wstate         10 rd:5  101010 01110 0 0000000000000
RDPR_gl             10 rd:5  101010 10000 0 0000000000000
RDPR_strand_status  10 rd:5  101010 11010 0 0000000000000
RDPR_ver            10 rd:5  101010 11111 0 0000000000000

{
  FLUSHW    10 00000 101011 00000 0 0000000000000
  RDTBR     10 rd:5  101011 00000 0 0000000000000
}

Tcc_r       10 0 cond:4 111010 rs1:5 0 cc:1 0000000 rs2:5
{
  # For v7, the entire simm13 field is present, but masked to 7 bits.
  # For v8, [12:7] are reserved.  However, a compatibility note for
  # the Tcc insn in the v9 manual suggests that the v8 reserved field
  # was ignored and did not produce traps.
  Tcc_i_v7  10 0 cond:4 111010 rs1:5 1 ------ i:7

  # For v9, bits [12:11] are cc1 and cc0 (and cc0 must be 0).
  # Bits [10:8] are reserved and the OSA2011 manual says they must be 0.
  Tcc_i_v9  10 0 cond:4 111010 rs1:5 1 cc:1 0 000 i:8
}
Commit	Line	Data
878cc677 RH	1	# SPDX-License-Identifier: LGPL-2.0+
	2	#
	3	# Sparc instruction decode definitions.
	4	# Copyright (c) 2023 Richard Henderson <rth@twiddle.net>
	5
6d2a0768 RH	6	##
	7	## Major Opcodes 00 and 01 -- branches, call, and sethi.
	8	##
	9
276567aa RH	10	&bcc i a cond cc
	11	BPcc 00 a:1 cond:4 001 cc:1 0 - i:s19 &bcc
	12	Bicc 00 a:1 cond:4 010 i:s22 &bcc cc=0
45196ea4 RH	13	FBPfcc 00 a:1 cond:4 101 cc:2 - i:s19 &bcc
45196ea4 RH	14	FBfcc 00 a:1 cond:4 110 i:s22 &bcc cc=0
276567aa	15
ab9ffe98 RH	16	%d16 20:s2 0:14
	17	BPr 00 a:1 0 cond:3 011 .. - rs1:5 .............. i=%d16
	18
45196ea4 RH	19	NCP 00 - ---- 111 ---------------------- # CBcc
45196ea4 RH	20
6d2a0768 RH	21	SETHI 00 rd:5 100 i:22
6d2a0768 RH	22
23ada1b1	23	CALL 01 i:s30
30376636	24
0faef01b RH	25	##
	26	## Major Opcode 10 -- integer, floating-point, vis, and system insns.
	27	##
	28
	29	&r_r_ri rd rs1 rs2_or_imm imm:bool
	30	@n_r_ri .. ..... ...... rs1:5 imm:1 rs2_or_imm:s13 &r_r_ri rd=0
	31
af25071c RH	32	{
	33	[
	34	STBAR 10 00000 101000 01111 0 0000000000000
	35	MEMBAR 10 00000 101000 01111 1 000000 cmask:3 mmask:4
	36
	37	RDCCR 10 rd:5 101000 00010 0 0000000000000
	38	RDASI 10 rd:5 101000 00011 0 0000000000000
	39	RDTICK 10 rd:5 101000 00100 0 0000000000000
	40	RDPC 10 rd:5 101000 00101 0 0000000000000
	41	RDFPRS 10 rd:5 101000 00110 0 0000000000000
	42	RDASR17 10 rd:5 101000 10001 0 0000000000000
	43	RDGSR 10 rd:5 101000 10011 0 0000000000000
	44	RDSOFTINT 10 rd:5 101000 10110 0 0000000000000
	45	RDTICK_CMPR 10 rd:5 101000 10111 0 0000000000000
	46	RDSTICK 10 rd:5 101000 11000 0 0000000000000
	47	RDSTICK_CMPR 10 rd:5 101000 11001 0 0000000000000
	48	RDSTRAND_STATUS 10 rd:5 101000 11010 0 0000000000000
	49	]
	50	# Before v8, all rs1 accepted; otherwise rs1==0.
	51	RDY 10 rd:5 101000 rs1:5 0 0000000000000
	52	}
	53
0faef01b RH	54	{
	55	[
	56	WRY 10 00000 110000 ..... . ............. @n_r_ri
	57	WRCCR 10 00010 110000 ..... . ............. @n_r_ri
	58	WRASI 10 00011 110000 ..... . ............. @n_r_ri
	59	WRFPRS 10 00110 110000 ..... . ............. @n_r_ri
	60	{
	61	WRGSR 10 10011 110000 ..... . ............. @n_r_ri
	62	WRPOWERDOWN 10 10011 110000 ..... . ............. @n_r_ri
	63	}
	64	WRSOFTINT_SET 10 10100 110000 ..... . ............. @n_r_ri
	65	WRSOFTINT_CLR 10 10101 110000 ..... . ............. @n_r_ri
	66	WRSOFTINT 10 10110 110000 ..... . ............. @n_r_ri
	67	WRTICK_CMPR 10 10111 110000 ..... . ............. @n_r_ri
	68	WRSTICK 10 11000 110000 ..... . ............. @n_r_ri
	69	WRSTICK_CMPR 10 11001 110000 ..... . ............. @n_r_ri
	70	]
	71	# Before v8, rs1==0 was WRY, and the rest executed as nop.
	72	[
	73	NOP_v7 10 ----- 110000 ----- 0 00000000 -----
	74	NOP_v7 10 ----- 110000 ----- 1 -------- -----
	75	]
	76	}
	77
668bb9b7 RH	78	{
	79	RDPSR 10 rd:5 101001 00000 0 0000000000000
	80	RDHPR_hpstate 10 rd:5 101001 00000 0 0000000000000
	81	}
	82	RDHPR_htstate 10 rd:5 101001 00001 0 0000000000000
	83	RDHPR_hintp 10 rd:5 101001 00011 0 0000000000000
	84	RDHPR_htba 10 rd:5 101001 00101 0 0000000000000
	85	RDHPR_hver 10 rd:5 101001 00110 0 0000000000000
	86	RDHPR_hstick_cmpr 10 rd:5 101001 11111 0 0000000000000
	87
25524734 RH	88	{
	89	WRPSR 10 00000 110001 ..... . ............. @n_r_ri
	90	SAVED 10 00000 110001 00000 0 0000000000000
	91	}
	92	RESTORED 10 00001 110001 00000 0 0000000000000
	93	# UA2005 ALLCLEAN
	94	# UA2005 OTHERW
	95	# UA2005 NORMALW
	96	# UA2005 INVALW
	97
5d617bfb RH	98	{
	99	RDWIM 10 rd:5 101010 00000 0 0000000000000
	100	RDPR_tpc 10 rd:5 101010 00000 0 0000000000000
	101	}
	102	RDPR_tnpc 10 rd:5 101010 00001 0 0000000000000
	103	RDPR_tstate 10 rd:5 101010 00010 0 0000000000000
	104	RDPR_tt 10 rd:5 101010 00011 0 0000000000000
	105	RDPR_tick 10 rd:5 101010 00100 0 0000000000000
	106	RDPR_tba 10 rd:5 101010 00101 0 0000000000000
	107	RDPR_pstate 10 rd:5 101010 00110 0 0000000000000
	108	RDPR_tl 10 rd:5 101010 00111 0 0000000000000
	109	RDPR_pil 10 rd:5 101010 01000 0 0000000000000
	110	RDPR_cwp 10 rd:5 101010 01001 0 0000000000000
	111	RDPR_cansave 10 rd:5 101010 01010 0 0000000000000
	112	RDPR_canrestore 10 rd:5 101010 01011 0 0000000000000
	113	RDPR_cleanwin 10 rd:5 101010 01100 0 0000000000000
	114	RDPR_otherwin 10 rd:5 101010 01101 0 0000000000000
	115	RDPR_wstate 10 rd:5 101010 01110 0 0000000000000
	116	RDPR_gl 10 rd:5 101010 10000 0 0000000000000
	117	RDPR_strand_status 10 rd:5 101010 11010 0 0000000000000
	118	RDPR_ver 10 rd:5 101010 11111 0 0000000000000
	119
e8325dc0 RH	120	{
	121	FLUSHW 10 00000 101011 00000 0 0000000000000
	122	RDTBR 10 rd:5 101011 00000 0 0000000000000
	123	}
	124
30376636 RH	125	Tcc_r 10 0 cond:4 111010 rs1:5 0 cc:1 0000000 rs2:5
	126	{
	127	# For v7, the entire simm13 field is present, but masked to 7 bits.
	128	# For v8, [12:7] are reserved. However, a compatibility note for
	129	# the Tcc insn in the v9 manual suggests that the v8 reserved field
	130	# was ignored and did not produce traps.
	131	Tcc_i_v7 10 0 cond:4 111010 rs1:5 1 ------ i:7
	132
	133	# For v9, bits [12:11] are cc1 and cc0 (and cc0 must be 0).
	134	# Bits [10:8] are reserved and the OSA2011 manual says they must be 0.
	135	Tcc_i_v9 10 0 cond:4 111010 rs1:5 1 cc:1 0 000 i:8
	136	}