[thirdparty/qemu.git] / target / sparc / int64_helper.c

/*
 * Sparc64 interrupt helpers
 *
 *  Copyright (c) 2003-2005 Fabrice Bellard
 *
 * This library is free software; you can redistribute it and/or
 * modify it under the terms of the GNU Lesser General Public
 * License as published by the Free Software Foundation; either
 * version 2.1 of the License, or (at your option) any later version.
 *
 * This library is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * Lesser General Public License for more details.
 *
 * You should have received a copy of the GNU Lesser General Public
 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
 */

#include "qemu/osdep.h"
#include "qemu/main-loop.h"
#include "cpu.h"
#include "exec/helper-proto.h"
#include "exec/log.h"
#include "trace.h"

#define DEBUG_PCALL

#ifdef DEBUG_PCALL
static const char * const excp_names[0x80] = {
    [TT_TFAULT] = "Instruction Access Fault",
    [TT_TMISS] = "Instruction Access MMU Miss",
    [TT_CODE_ACCESS] = "Instruction Access Error",
    [TT_ILL_INSN] = "Illegal Instruction",
    [TT_PRIV_INSN] = "Privileged Instruction",
    [TT_NFPU_INSN] = "FPU Disabled",
    [TT_FP_EXCP] = "FPU Exception",
    [TT_TOVF] = "Tag Overflow",
    [TT_CLRWIN] = "Clean Windows",
    [TT_DIV_ZERO] = "Division By Zero",
    [TT_DFAULT] = "Data Access Fault",
    [TT_DMISS] = "Data Access MMU Miss",
    [TT_DATA_ACCESS] = "Data Access Error",
    [TT_DPROT] = "Data Protection Error",
    [TT_UNALIGNED] = "Unaligned Memory Access",
    [TT_PRIV_ACT] = "Privileged Action",
    [TT_EXTINT | 0x1] = "External Interrupt 1",
    [TT_EXTINT | 0x2] = "External Interrupt 2",
    [TT_EXTINT | 0x3] = "External Interrupt 3",
    [TT_EXTINT | 0x4] = "External Interrupt 4",
    [TT_EXTINT | 0x5] = "External Interrupt 5",
    [TT_EXTINT | 0x6] = "External Interrupt 6",
    [TT_EXTINT | 0x7] = "External Interrupt 7",
    [TT_EXTINT | 0x8] = "External Interrupt 8",
    [TT_EXTINT | 0x9] = "External Interrupt 9",
    [TT_EXTINT | 0xa] = "External Interrupt 10",
    [TT_EXTINT | 0xb] = "External Interrupt 11",
    [TT_EXTINT | 0xc] = "External Interrupt 12",
    [TT_EXTINT | 0xd] = "External Interrupt 13",
    [TT_EXTINT | 0xe] = "External Interrupt 14",
    [TT_EXTINT | 0xf] = "External Interrupt 15",
};
#endif

void cpu_check_irqs(CPUSPARCState *env)
{
    CPUState *cs;
    uint32_t pil = env->pil_in |
                  (env->softint & ~(SOFTINT_TIMER | SOFTINT_STIMER));

    /* We should be holding the BQL before we mess with IRQs */
    g_assert(qemu_mutex_iothread_locked());

    /* TT_IVEC has a higher priority (16) than TT_EXTINT (31..17) */
    if (env->ivec_status & 0x20) {
        return;
    }
    cs = env_cpu(env);
    /*
     * check if TM or SM in SOFTINT are set
     * setting these also causes interrupt 14
     */
    if (env->softint & (SOFTINT_TIMER | SOFTINT_STIMER)) {
        pil |= 1 << 14;
    }

    /*
     * The bit corresponding to psrpil is (1<< psrpil),
     * the next bit is (2 << psrpil).
     */
    if (pil < (2 << env->psrpil)) {
        if (cs->interrupt_request & CPU_INTERRUPT_HARD) {
            trace_sparc64_cpu_check_irqs_reset_irq(env->interrupt_index);
            env->interrupt_index = 0;
            cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD);
        }
        return;
    }

    if (cpu_interrupts_enabled(env)) {

        unsigned int i;

        for (i = 15; i > env->psrpil; i--) {
            if (pil & (1 << i)) {
                int old_interrupt = env->interrupt_index;
                int new_interrupt = TT_EXTINT | i;

                if (unlikely(env->tl > 0 && cpu_tsptr(env)->tt > new_interrupt
                  && ((cpu_tsptr(env)->tt & 0x1f0) == TT_EXTINT))) {
                    trace_sparc64_cpu_check_irqs_noset_irq(env->tl,
                                                      cpu_tsptr(env)->tt,
                                                      new_interrupt);
                } else if (old_interrupt != new_interrupt) {
                    env->interrupt_index = new_interrupt;
                    trace_sparc64_cpu_check_irqs_set_irq(i, old_interrupt,
                                                         new_interrupt);
                    cpu_interrupt(cs, CPU_INTERRUPT_HARD);
                }
                break;
            }
        }
    } else if (cs->interrupt_request & CPU_INTERRUPT_HARD) {
        trace_sparc64_cpu_check_irqs_disabled(pil, env->pil_in, env->softint,
                                              env->interrupt_index);
        env->interrupt_index = 0;
        cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD);
    }
}

void sparc_cpu_do_interrupt(CPUState *cs)
{
    SPARCCPU *cpu = SPARC_CPU(cs);
    CPUSPARCState *env = &cpu->env;
    int intno = cs->exception_index;
    trap_state *tsptr;

#ifdef DEBUG_PCALL
    if (qemu_loglevel_mask(CPU_LOG_INT)) {
        static int count;
        const char *name;

        if (intno < 0 || intno >= 0x1ff) {
            name = "Unknown";
        } else if (intno >= 0x180) {
            name = "Hyperprivileged Trap Instruction";
        } else if (intno >= 0x100) {
            name = "Trap Instruction";
        } else if (intno >= 0xc0) {
            name = "Window Fill";
        } else if (intno >= 0x80) {
            name = "Window Spill";
        } else {
            name = excp_names[intno];
            if (!name) {
                name = "Unknown";
            }
        }

        qemu_log("%6d: %s (v=%04x)\n", count, name, intno);
        log_cpu_state(cs, 0);
#if 0
        {
            int i;
            uint8_t *ptr;

            qemu_log("       code=");
            ptr = (uint8_t *)env->pc;
            for (i = 0; i < 16; i++) {
                qemu_log(" %02x", ldub(ptr + i));
            }
            qemu_log("\n");
        }
#endif
        count++;
    }
#endif
#if !defined(CONFIG_USER_ONLY)
    if (env->tl >= env->maxtl) {
        cpu_abort(cs, "Trap 0x%04x while trap level (%d) >= MAXTL (%d),"
                  " Error state", cs->exception_index, env->tl, env->maxtl);
        return;
    }
#endif
    if (env->tl < env->maxtl - 1) {
        env->tl++;
    } else {
        env->pstate |= PS_RED;
        if (env->tl < env->maxtl) {
            env->tl++;
        }
    }
    tsptr = cpu_tsptr(env);

    tsptr->tstate = sparc64_tstate(env);
    tsptr->tpc = env->pc;
    tsptr->tnpc = env->npc;
    tsptr->tt = intno;

    if (cpu_has_hypervisor(env)) {
        env->htstate[env->tl] = env->hpstate;
        /* XXX OpenSPARC T1 - UltraSPARC T3 have MAXPTL=2
           but this may change in the future */
        if (env->tl > 2) {
            env->hpstate |= HS_PRIV;
        }
    }

    if (env->def.features & CPU_FEATURE_GL) {
        cpu_gl_switch_gregs(env, env->gl + 1);
        env->gl++;
    }

    switch (intno) {
    case TT_IVEC:
        if (!cpu_has_hypervisor(env)) {
            cpu_change_pstate(env, PS_PEF | PS_PRIV | PS_IG);
        }
        break;
    case TT_TFAULT:
    case TT_DFAULT:
    case TT_TMISS ... TT_TMISS + 3:
    case TT_DMISS ... TT_DMISS + 3:
    case TT_DPROT ... TT_DPROT + 3:
        if (cpu_has_hypervisor(env)) {
            env->hpstate |= HS_PRIV;
            env->pstate = PS_PEF | PS_PRIV;
        } else {
            cpu_change_pstate(env, PS_PEF | PS_PRIV | PS_MG);
        }
        break;
    case TT_INSN_REAL_TRANSLATION_MISS ... TT_DATA_REAL_TRANSLATION_MISS:
    case TT_HTRAP ... TT_HTRAP + 127:
        env->hpstate |= HS_PRIV;
        break;
    default:
        cpu_change_pstate(env, PS_PEF | PS_PRIV | PS_AG);
        break;
    }

    if (intno == TT_CLRWIN) {
        cpu_set_cwp(env, cpu_cwp_dec(env, env->cwp - 1));
    } else if ((intno & 0x1c0) == TT_SPILL) {
        cpu_set_cwp(env, cpu_cwp_dec(env, env->cwp - env->cansave - 2));
    } else if ((intno & 0x1c0) == TT_FILL) {
        cpu_set_cwp(env, cpu_cwp_inc(env, env->cwp + 1));
    }

    if (cpu_hypervisor_mode(env)) {
        env->pc = (env->htba & ~0x3fffULL) | (intno << 5);
    } else {
        env->pc = env->tbr  & ~0x7fffULL;
        env->pc |= ((env->tl > 1) ? 1 << 14 : 0) | (intno << 5);
    }
    env->npc = env->pc + 4;
    cs->exception_index = -1;
}

trap_state *cpu_tsptr(CPUSPARCState* env)
{
    return &env->ts[env->tl & MAXTL_MASK];
}

static bool do_modify_softint(CPUSPARCState *env, uint32_t value)
{
    if (env->softint != value) {
        env->softint = value;
#if !defined(CONFIG_USER_ONLY)
        if (cpu_interrupts_enabled(env)) {
            qemu_mutex_lock_iothread();
            cpu_check_irqs(env);
            qemu_mutex_unlock_iothread();
        }
#endif
        return true;
    }
    return false;
}

void helper_set_softint(CPUSPARCState *env, uint64_t value)
{
    if (do_modify_softint(env, env->softint | (uint32_t)value)) {
        trace_int_helper_set_softint(env->softint);
    }
}

void helper_clear_softint(CPUSPARCState *env, uint64_t value)
{
    if (do_modify_softint(env, env->softint & (uint32_t)~value)) {
        trace_int_helper_clear_softint(env->softint);
    }
}

void helper_write_softint(CPUSPARCState *env, uint64_t value)
{
    if (do_modify_softint(env, (uint32_t)value)) {
        trace_int_helper_write_softint(env->softint);
    }
}
Commit	Line	Data
ab3b491f BS	1	/*
	2	* Sparc64 interrupt helpers
	3	*
	4	* Copyright (c) 2003-2005 Fabrice Bellard
	5	*
	6	* This library is free software; you can redistribute it and/or
	7	* modify it under the terms of the GNU Lesser General Public
	8	* License as published by the Free Software Foundation; either
5650b549	9	* version 2.1 of the License, or (at your option) any later version.
ab3b491f BS	10	*
	11	* This library is distributed in the hope that it will be useful,
	12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	14	* Lesser General Public License for more details.
	15	*
	16	* You should have received a copy of the GNU Lesser General Public
	17	* License along with this library; if not, see <http://www.gnu.org/licenses/>.
	18	*/
	19
db5ebe5f	20	#include "qemu/osdep.h"
5ee59930	21	#include "qemu/main-loop.h"
ab3b491f	22	#include "cpu.h"
2ef6175a	23	#include "exec/helper-proto.h"
508127e2	24	#include "exec/log.h"
11e66bca	25	#include "trace.h"
ab3b491f	26
b884fc5e	27	#define DEBUG_PCALL
ab3b491f BS	28
	29	#ifdef DEBUG_PCALL
	30	static const char * const excp_names[0x80] = {
	31	[TT_TFAULT] = "Instruction Access Fault",
	32	[TT_TMISS] = "Instruction Access MMU Miss",
	33	[TT_CODE_ACCESS] = "Instruction Access Error",
	34	[TT_ILL_INSN] = "Illegal Instruction",
	35	[TT_PRIV_INSN] = "Privileged Instruction",
	36	[TT_NFPU_INSN] = "FPU Disabled",
	37	[TT_FP_EXCP] = "FPU Exception",
	38	[TT_TOVF] = "Tag Overflow",
	39	[TT_CLRWIN] = "Clean Windows",
	40	[TT_DIV_ZERO] = "Division By Zero",
	41	[TT_DFAULT] = "Data Access Fault",
	42	[TT_DMISS] = "Data Access MMU Miss",
	43	[TT_DATA_ACCESS] = "Data Access Error",
	44	[TT_DPROT] = "Data Protection Error",
	45	[TT_UNALIGNED] = "Unaligned Memory Access",
	46	[TT_PRIV_ACT] = "Privileged Action",
	47	[TT_EXTINT \| 0x1] = "External Interrupt 1",
	48	[TT_EXTINT \| 0x2] = "External Interrupt 2",
	49	[TT_EXTINT \| 0x3] = "External Interrupt 3",
	50	[TT_EXTINT \| 0x4] = "External Interrupt 4",
	51	[TT_EXTINT \| 0x5] = "External Interrupt 5",
	52	[TT_EXTINT \| 0x6] = "External Interrupt 6",
	53	[TT_EXTINT \| 0x7] = "External Interrupt 7",
	54	[TT_EXTINT \| 0x8] = "External Interrupt 8",
	55	[TT_EXTINT \| 0x9] = "External Interrupt 9",
	56	[TT_EXTINT \| 0xa] = "External Interrupt 10",
	57	[TT_EXTINT \| 0xb] = "External Interrupt 11",
	58	[TT_EXTINT \| 0xc] = "External Interrupt 12",
	59	[TT_EXTINT \| 0xd] = "External Interrupt 13",
	60	[TT_EXTINT \| 0xe] = "External Interrupt 14",
	61	[TT_EXTINT \| 0xf] = "External Interrupt 15",
	62	};
	63	#endif
	64
10fb1340 PMD	65	void cpu_check_irqs(CPUSPARCState *env)
	66	{
	67	CPUState *cs;
	68	uint32_t pil = env->pil_in \|
	69	(env->softint & ~(SOFTINT_TIMER \| SOFTINT_STIMER));
	70
	71	/* We should be holding the BQL before we mess with IRQs */
	72	g_assert(qemu_mutex_iothread_locked());
	73
	74	/* TT_IVEC has a higher priority (16) than TT_EXTINT (31..17) */
	75	if (env->ivec_status & 0x20) {
	76	return;
	77	}
	78	cs = env_cpu(env);
	79	/*
	80	* check if TM or SM in SOFTINT are set
	81	* setting these also causes interrupt 14
	82	*/
	83	if (env->softint & (SOFTINT_TIMER \| SOFTINT_STIMER)) {
	84	pil \|= 1 << 14;
	85	}
	86
	87	/*
	88	* The bit corresponding to psrpil is (1<< psrpil),
	89	* the next bit is (2 << psrpil).
	90	*/
	91	if (pil < (2 << env->psrpil)) {
	92	if (cs->interrupt_request & CPU_INTERRUPT_HARD) {
	93	trace_sparc64_cpu_check_irqs_reset_irq(env->interrupt_index);
	94	env->interrupt_index = 0;
	95	cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD);
	96	}
	97	return;
	98	}
	99
	100	if (cpu_interrupts_enabled(env)) {
	101
	102	unsigned int i;
	103
	104	for (i = 15; i > env->psrpil; i--) {
	105	if (pil & (1 << i)) {
	106	int old_interrupt = env->interrupt_index;
	107	int new_interrupt = TT_EXTINT \| i;
	108
	109	if (unlikely(env->tl > 0 && cpu_tsptr(env)->tt > new_interrupt
	110	&& ((cpu_tsptr(env)->tt & 0x1f0) == TT_EXTINT))) {
	111	trace_sparc64_cpu_check_irqs_noset_irq(env->tl,
	112	cpu_tsptr(env)->tt,
	113	new_interrupt);
	114	} else if (old_interrupt != new_interrupt) {
	115	env->interrupt_index = new_interrupt;
	116	trace_sparc64_cpu_check_irqs_set_irq(i, old_interrupt,
	117	new_interrupt);
	118	cpu_interrupt(cs, CPU_INTERRUPT_HARD);
	119	}
	120	break;
	121	}
	122	}
	123	} else if (cs->interrupt_request & CPU_INTERRUPT_HARD) {
	124	trace_sparc64_cpu_check_irqs_disabled(pil, env->pil_in, env->softint,
	125	env->interrupt_index);
	126	env->interrupt_index = 0;
	127	cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD);
	128	}
129	}
130
97a8ea5a	131	void sparc_cpu_do_interrupt(CPUState *cs)
ab3b491f	132	{
97a8ea5a AF	133	SPARCCPU *cpu = SPARC_CPU(cs);
97a8ea5a AF	134	CPUSPARCState *env = &cpu->env;
27103424	135	int intno = cs->exception_index;
ab3b491f BS	136	trap_state *tsptr;
	137
	138	#ifdef DEBUG_PCALL
	139	if (qemu_loglevel_mask(CPU_LOG_INT)) {
	140	static int count;
	141	const char *name;
	142
6e040755	143	if (intno < 0 \|\| intno >= 0x1ff) {
ab3b491f	144	name = "Unknown";
6e040755 AT	145	} else if (intno >= 0x180) {
6e040755 AT	146	name = "Hyperprivileged Trap Instruction";
ab3b491f BS	147	} else if (intno >= 0x100) {
	148	name = "Trap Instruction";
	149	} else if (intno >= 0xc0) {
	150	name = "Window Fill";
	151	} else if (intno >= 0x80) {
	152	name = "Window Spill";
	153	} else {
	154	name = excp_names[intno];
	155	if (!name) {
	156	name = "Unknown";
	157	}
	158	}
	159
b884fc5e	160	qemu_log("%6d: %s (v=%04x)\n", count, name, intno);
a0762859	161	log_cpu_state(cs, 0);
ab3b491f BS	162	#if 0
	163	{
	164	int i;
	165	uint8_t *ptr;
	166
	167	qemu_log(" code=");
	168	ptr = (uint8_t *)env->pc;
	169	for (i = 0; i < 16; i++) {
	170	qemu_log(" %02x", ldub(ptr + i));
	171	}
	172	qemu_log("\n");
	173	}
	174	#endif
	175	count++;
	176	}
	177	#endif
	178	#if !defined(CONFIG_USER_ONLY)
	179	if (env->tl >= env->maxtl) {
a47dddd7	180	cpu_abort(cs, "Trap 0x%04x while trap level (%d) >= MAXTL (%d),"
27103424	181	" Error state", cs->exception_index, env->tl, env->maxtl);
ab3b491f BS	182	return;
	183	}
	184	#endif
	185	if (env->tl < env->maxtl - 1) {
	186	env->tl++;
	187	} else {
	188	env->pstate \|= PS_RED;
	189	if (env->tl < env->maxtl) {
	190	env->tl++;
	191	}
	192	}
	193	tsptr = cpu_tsptr(env);
	194
7a5805a0	195	tsptr->tstate = sparc64_tstate(env);
ab3b491f BS	196	tsptr->tpc = env->pc;
	197	tsptr->tnpc = env->npc;
	198	tsptr->tt = intno;
	199
6e040755 AT	200	if (cpu_has_hypervisor(env)) {
	201	env->htstate[env->tl] = env->hpstate;
	202	/* XXX OpenSPARC T1 - UltraSPARC T3 have MAXPTL=2
	203	but this may change in the future */
	204	if (env->tl > 2) {
	205	env->hpstate \|= HS_PRIV;
	206	}
	207	}
	208
576e1c4c	209	if (env->def.features & CPU_FEATURE_GL) {
cbc3a6a4 AT	210	cpu_gl_switch_gregs(env, env->gl + 1);
	211	env->gl++;
	212	}
	213
ab3b491f BS	214	switch (intno) {
ab3b491f BS	215	case TT_IVEC:
6e040755 AT	216	if (!cpu_has_hypervisor(env)) {
	217	cpu_change_pstate(env, PS_PEF \| PS_PRIV \| PS_IG);
	218	}
ab3b491f BS	219	break;
	220	case TT_TFAULT:
	221	case TT_DFAULT:
	222	case TT_TMISS ... TT_TMISS + 3:
	223	case TT_DMISS ... TT_DMISS + 3:
	224	case TT_DPROT ... TT_DPROT + 3:
6e040755 AT	225	if (cpu_has_hypervisor(env)) {
	226	env->hpstate \|= HS_PRIV;
	227	env->pstate = PS_PEF \| PS_PRIV;
	228	} else {
	229	cpu_change_pstate(env, PS_PEF \| PS_PRIV \| PS_MG);
	230	}
	231	break;
	232	case TT_INSN_REAL_TRANSLATION_MISS ... TT_DATA_REAL_TRANSLATION_MISS:
	233	case TT_HTRAP ... TT_HTRAP + 127:
	234	env->hpstate \|= HS_PRIV;
ab3b491f BS	235	break;
	236	default:
	237	cpu_change_pstate(env, PS_PEF \| PS_PRIV \| PS_AG);
	238	break;
	239	}
	240
	241	if (intno == TT_CLRWIN) {
	242	cpu_set_cwp(env, cpu_cwp_dec(env, env->cwp - 1));
	243	} else if ((intno & 0x1c0) == TT_SPILL) {
	244	cpu_set_cwp(env, cpu_cwp_dec(env, env->cwp - env->cansave - 2));
	245	} else if ((intno & 0x1c0) == TT_FILL) {
	246	cpu_set_cwp(env, cpu_cwp_inc(env, env->cwp + 1));
	247	}
6e040755 AT	248
	249	if (cpu_hypervisor_mode(env)) {
	250	env->pc = (env->htba & ~0x3fffULL) \| (intno << 5);
	251	} else {
	252	env->pc = env->tbr & ~0x7fffULL;
	253	env->pc \|= ((env->tl > 1) ? 1 << 14 : 0) \| (intno << 5);
	254	}
ab3b491f	255	env->npc = env->pc + 4;
27103424	256	cs->exception_index = -1;
ab3b491f	257	}
2336c1f1	258
c5f9864e	259	trap_state cpu_tsptr(CPUSPARCState env)
2336c1f1 BS	260	{
	261	return &env->ts[env->tl & MAXTL_MASK];
	262	}
79227036	263
c5f9864e	264	static bool do_modify_softint(CPUSPARCState *env, uint32_t value)
79227036 BS	265	{
	266	if (env->softint != value) {
	267	env->softint = value;
79227036 BS	268	#if !defined(CONFIG_USER_ONLY)
79227036 BS	269	if (cpu_interrupts_enabled(env)) {
5ee59930	270	qemu_mutex_lock_iothread();
79227036	271	cpu_check_irqs(env);
5ee59930	272	qemu_mutex_unlock_iothread();
79227036 BS	273	}
79227036 BS	274	#endif
11e66bca	275	return true;
79227036	276	}
11e66bca	277	return false;
79227036 BS	278	}
79227036 BS	279
c5f9864e	280	void helper_set_softint(CPUSPARCState *env, uint64_t value)
79227036	281	{
11e66bca BS	282	if (do_modify_softint(env, env->softint \| (uint32_t)value)) {
	283	trace_int_helper_set_softint(env->softint);
	284	}
79227036 BS	285	}
79227036 BS	286
c5f9864e	287	void helper_clear_softint(CPUSPARCState *env, uint64_t value)
79227036	288	{
11e66bca BS	289	if (do_modify_softint(env, env->softint & (uint32_t)~value)) {
	290	trace_int_helper_clear_softint(env->softint);
	291	}
79227036 BS	292	}
79227036 BS	293
c5f9864e	294	void helper_write_softint(CPUSPARCState *env, uint64_t value)
79227036	295	{
11e66bca BS	296	if (do_modify_softint(env, (uint32_t)value)) {
	297	trace_int_helper_write_softint(env->softint);
	298	}
79227036	299	}