[thirdparty/qemu.git] / target-ppc / mmu-hash32.c

/*
 *  PowerPC MMU, TLB and BAT emulation helpers for QEMU.
 *
 *  Copyright (c) 2003-2007 Jocelyn Mayer
 *  Copyright (c) 2013 David Gibson, IBM Corporation
 *
 * This library is free software; you can redistribute it and/or
 * modify it under the terms of the GNU Lesser General Public
 * License as published by the Free Software Foundation; either
 * version 2 of the License, or (at your option) any later version.
 *
 * This library is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * Lesser General Public License for more details.
 *
 * You should have received a copy of the GNU Lesser General Public
 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
 */

#include "cpu.h"
#include "exec/helper-proto.h"
#include "sysemu/kvm.h"
#include "kvm_ppc.h"
#include "mmu-hash32.h"

//#define DEBUG_MMU
//#define DEBUG_BAT

#ifdef DEBUG_MMU
#  define LOG_MMU(...) qemu_log(__VA_ARGS__)
#  define LOG_MMU_STATE(cpu) log_cpu_state((cpu), 0)
#else
#  define LOG_MMU(...) do { } while (0)
#  define LOG_MMU_STATE(cpu) do { } while (0)
#endif

#ifdef DEBUG_BATS
#  define LOG_BATS(...) qemu_log(__VA_ARGS__)
#else
#  define LOG_BATS(...) do { } while (0)
#endif

struct mmu_ctx_hash32 {
    hwaddr raddr;      /* Real address              */
    int prot;                      /* Protection bits           */
    int key;                       /* Access key                */
};

static int ppc_hash32_pp_prot(int key, int pp, int nx)
{
    int prot;

    if (key == 0) {
        switch (pp) {
        case 0x0:
        case 0x1:
        case 0x2:
            prot = PAGE_READ | PAGE_WRITE;
            break;

        case 0x3:
            prot = PAGE_READ;
            break;

        default:
            abort();
        }
    } else {
        switch (pp) {
        case 0x0:
            prot = 0;
            break;

        case 0x1:
        case 0x3:
            prot = PAGE_READ;
            break;

        case 0x2:
            prot = PAGE_READ | PAGE_WRITE;
            break;

        default:
            abort();
        }
    }
    if (nx == 0) {
        prot |= PAGE_EXEC;
    }

    return prot;
}

static int ppc_hash32_pte_prot(CPUPPCState *env,
                               target_ulong sr, ppc_hash_pte32_t pte)
{
    unsigned pp, key;

    key = !!(msr_pr ? (sr & SR32_KP) : (sr & SR32_KS));
    pp = pte.pte1 & HPTE32_R_PP;

    return ppc_hash32_pp_prot(key, pp, !!(sr & SR32_NX));
}

static target_ulong hash32_bat_size(CPUPPCState *env,
                                    target_ulong batu, target_ulong batl)
{
    if ((msr_pr && !(batu & BATU32_VP))
        || (!msr_pr && !(batu & BATU32_VS))) {
        return 0;
    }

    return BATU32_BEPI & ~((batu & BATU32_BL) << 15);
}

static int hash32_bat_prot(CPUPPCState *env,
                           target_ulong batu, target_ulong batl)
{
    int pp, prot;

    prot = 0;
    pp = batl & BATL32_PP;
    if (pp != 0) {
        prot = PAGE_READ | PAGE_EXEC;
        if (pp == 0x2) {
            prot |= PAGE_WRITE;
        }
    }
    return prot;
}

static target_ulong hash32_bat_601_size(CPUPPCState *env,
                                target_ulong batu, target_ulong batl)
{
    if (!(batl & BATL32_601_V)) {
        return 0;
    }

    return BATU32_BEPI & ~((batl & BATL32_601_BL) << 17);
}

static int hash32_bat_601_prot(CPUPPCState *env,
                               target_ulong batu, target_ulong batl)
{
    int key, pp;

    pp = batu & BATU32_601_PP;
    if (msr_pr == 0) {
        key = !!(batu & BATU32_601_KS);
    } else {
        key = !!(batu & BATU32_601_KP);
    }
    return ppc_hash32_pp_prot(key, pp, 0);
}

static hwaddr ppc_hash32_bat_lookup(CPUPPCState *env, target_ulong ea, int rwx,
                                    int *prot)
{
    target_ulong *BATlt, *BATut;
    int i;

    LOG_BATS("%s: %cBAT v " TARGET_FMT_lx "\n", __func__,
             rwx == 2 ? 'I' : 'D', ea);
    if (rwx == 2) {
        BATlt = env->IBAT[1];
        BATut = env->IBAT[0];
    } else {
        BATlt = env->DBAT[1];
        BATut = env->DBAT[0];
    }
    for (i = 0; i < env->nb_BATs; i++) {
        target_ulong batu = BATut[i];
        target_ulong batl = BATlt[i];
        target_ulong mask;

        if (unlikely(env->mmu_model == POWERPC_MMU_601)) {
            mask = hash32_bat_601_size(env, batu, batl);
        } else {
            mask = hash32_bat_size(env, batu, batl);
        }
        LOG_BATS("%s: %cBAT%d v " TARGET_FMT_lx " BATu " TARGET_FMT_lx
                 " BATl " TARGET_FMT_lx "\n", __func__,
                 type == ACCESS_CODE ? 'I' : 'D', i, ea, batu, batl);

        if (mask && ((ea & mask) == (batu & BATU32_BEPI))) {
            hwaddr raddr = (batl & mask) | (ea & ~mask);

            if (unlikely(env->mmu_model == POWERPC_MMU_601)) {
                *prot = hash32_bat_601_prot(env, batu, batl);
            } else {
                *prot = hash32_bat_prot(env, batu, batl);
            }

            return raddr & TARGET_PAGE_MASK;
        }
    }

    /* No hit */
#if defined(DEBUG_BATS)
    if (qemu_log_enabled()) {
        LOG_BATS("no BAT match for " TARGET_FMT_lx ":\n", ea);
        for (i = 0; i < 4; i++) {
            BATu = &BATut[i];
            BATl = &BATlt[i];
            BEPIu = *BATu & BATU32_BEPIU;
            BEPIl = *BATu & BATU32_BEPIL;
            bl = (*BATu & 0x00001FFC) << 15;
            LOG_BATS("%s: %cBAT%d v " TARGET_FMT_lx " BATu " TARGET_FMT_lx
                     " BATl " TARGET_FMT_lx "\n\t" TARGET_FMT_lx " "
                     TARGET_FMT_lx " " TARGET_FMT_lx "\n",
                     __func__, type == ACCESS_CODE ? 'I' : 'D', i, ea,
                     *BATu, *BATl, BEPIu, BEPIl, bl);
        }
    }
#endif

    return -1;
}

static int ppc_hash32_direct_store(CPUPPCState *env, target_ulong sr,
                                   target_ulong eaddr, int rwx,
                                   hwaddr *raddr, int *prot)
{
    CPUState *cs = CPU(ppc_env_get_cpu(env));
    int key = !!(msr_pr ? (sr & SR32_KP) : (sr & SR32_KS));

    LOG_MMU("direct store...\n");

    if ((sr & 0x1FF00000) >> 20 == 0x07f) {
        /* Memory-forced I/O controller interface access */
        /* If T=1 and BUID=x'07F', the 601 performs a memory access
         * to SR[28-31] LA[4-31], bypassing all protection mechanisms.
         */
        *raddr = ((sr & 0xF) << 28) | (eaddr & 0x0FFFFFFF);
        *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
        return 0;
    }

    if (rwx == 2) {
        /* No code fetch is allowed in direct-store areas */
        cs->exception_index = POWERPC_EXCP_ISI;
        env->error_code = 0x10000000;
        return 1;
    }

    switch (env->access_type) {
    case ACCESS_INT:
        /* Integer load/store : only access allowed */
        break;
    case ACCESS_FLOAT:
        /* Floating point load/store */
        cs->exception_index = POWERPC_EXCP_ALIGN;
        env->error_code = POWERPC_EXCP_ALIGN_FP;
        env->spr[SPR_DAR] = eaddr;
        return 1;
    case ACCESS_RES:
        /* lwarx, ldarx or srwcx. */
        env->error_code = 0;
        env->spr[SPR_DAR] = eaddr;
        if (rwx == 1) {
            env->spr[SPR_DSISR] = 0x06000000;
        } else {
            env->spr[SPR_DSISR] = 0x04000000;
        }
        return 1;
    case ACCESS_CACHE:
        /* dcba, dcbt, dcbtst, dcbf, dcbi, dcbst, dcbz, or icbi */
        /* Should make the instruction do no-op.
         * As it already do no-op, it's quite easy :-)
         */
        *raddr = eaddr;
        return 0;
    case ACCESS_EXT:
        /* eciwx or ecowx */
        cs->exception_index = POWERPC_EXCP_DSI;
        env->error_code = 0;
        env->spr[SPR_DAR] = eaddr;
        if (rwx == 1) {
            env->spr[SPR_DSISR] = 0x06100000;
        } else {
            env->spr[SPR_DSISR] = 0x04100000;
        }
        return 1;
    default:
        qemu_log("ERROR: instruction should not need "
                 "address translation\n");
        abort();
    }
    if ((rwx == 1 || key != 1) && (rwx == 0 || key != 0)) {
        *raddr = eaddr;
        return 0;
    } else {
        cs->exception_index = POWERPC_EXCP_DSI;
        env->error_code = 0;
        env->spr[SPR_DAR] = eaddr;
        if (rwx == 1) {
            env->spr[SPR_DSISR] = 0x0a000000;
        } else {
            env->spr[SPR_DSISR] = 0x08000000;
        }
        return 1;
    }
}

hwaddr get_pteg_offset32(CPUPPCState *env, hwaddr hash)
{
    return (hash * HASH_PTEG_SIZE_32) & env->htab_mask;
}

static hwaddr ppc_hash32_pteg_search(CPUPPCState *env, hwaddr pteg_off,
                                     bool secondary, target_ulong ptem,
                                     ppc_hash_pte32_t *pte)
{
    hwaddr pte_offset = pteg_off;
    target_ulong pte0, pte1;
    int i;

    for (i = 0; i < HPTES_PER_GROUP; i++) {
        pte0 = ppc_hash32_load_hpte0(env, pte_offset);
        pte1 = ppc_hash32_load_hpte1(env, pte_offset);

        if ((pte0 & HPTE32_V_VALID)
            && (secondary == !!(pte0 & HPTE32_V_SECONDARY))
            && HPTE32_V_COMPARE(pte0, ptem)) {
            pte->pte0 = pte0;
            pte->pte1 = pte1;
            return pte_offset;
        }

        pte_offset += HASH_PTE_SIZE_32;
    }

    return -1;
}

static hwaddr ppc_hash32_htab_lookup(CPUPPCState *env,
                                     target_ulong sr, target_ulong eaddr,
                                     ppc_hash_pte32_t *pte)
{
    hwaddr pteg_off, pte_offset;
    hwaddr hash;
    uint32_t vsid, pgidx, ptem;

    vsid = sr & SR32_VSID;
    pgidx = (eaddr & ~SEGMENT_MASK_256M) >> TARGET_PAGE_BITS;
    hash = vsid ^ pgidx;
    ptem = (vsid << 7) | (pgidx >> 10);

    /* Page address translation */
    LOG_MMU("htab_base " TARGET_FMT_plx " htab_mask " TARGET_FMT_plx
            " hash " TARGET_FMT_plx "\n",
            env->htab_base, env->htab_mask, hash);

    /* Primary PTEG lookup */
    LOG_MMU("0 htab=" TARGET_FMT_plx "/" TARGET_FMT_plx
            " vsid=%" PRIx32 " ptem=%" PRIx32
            " hash=" TARGET_FMT_plx "\n",
            env->htab_base, env->htab_mask, vsid, ptem, hash);
    pteg_off = get_pteg_offset32(env, hash);
    pte_offset = ppc_hash32_pteg_search(env, pteg_off, 0, ptem, pte);
    if (pte_offset == -1) {
        /* Secondary PTEG lookup */
        LOG_MMU("1 htab=" TARGET_FMT_plx "/" TARGET_FMT_plx
                " vsid=%" PRIx32 " api=%" PRIx32
                " hash=" TARGET_FMT_plx "\n", env->htab_base,
                env->htab_mask, vsid, ptem, ~hash);
        pteg_off = get_pteg_offset32(env, ~hash);
        pte_offset = ppc_hash32_pteg_search(env, pteg_off, 1, ptem, pte);
    }

    return pte_offset;
}

static hwaddr ppc_hash32_pte_raddr(target_ulong sr, ppc_hash_pte32_t pte,
                                   target_ulong eaddr)
{
    hwaddr rpn = pte.pte1 & HPTE32_R_RPN;
    hwaddr mask = ~TARGET_PAGE_MASK;

    return (rpn & ~mask) | (eaddr & mask);
}

int ppc_hash32_handle_mmu_fault(PowerPCCPU *cpu, target_ulong eaddr, int rwx,
                                int mmu_idx)
{
    CPUState *cs = CPU(cpu);
    CPUPPCState *env = &cpu->env;
    target_ulong sr;
    hwaddr pte_offset;
    ppc_hash_pte32_t pte;
    int prot;
    uint32_t new_pte1;
    const int need_prot[] = {PAGE_READ, PAGE_WRITE, PAGE_EXEC};
    hwaddr raddr;

    assert((rwx == 0) || (rwx == 1) || (rwx == 2));

    /* 1. Handle real mode accesses */
    if (((rwx == 2) && (msr_ir == 0)) || ((rwx != 2) && (msr_dr == 0))) {
        /* Translation is off */
        raddr = eaddr;
        tlb_set_page(cs, eaddr & TARGET_PAGE_MASK, raddr & TARGET_PAGE_MASK,
                     PAGE_READ | PAGE_WRITE | PAGE_EXEC, mmu_idx,
                     TARGET_PAGE_SIZE);
        return 0;
    }

    /* 2. Check Block Address Translation entries (BATs) */
    if (env->nb_BATs != 0) {
        raddr = ppc_hash32_bat_lookup(env, eaddr, rwx, &prot);
        if (raddr != -1) {
            if (need_prot[rwx] & ~prot) {
                if (rwx == 2) {
                    cs->exception_index = POWERPC_EXCP_ISI;
                    env->error_code = 0x08000000;
                } else {
                    cs->exception_index = POWERPC_EXCP_DSI;
                    env->error_code = 0;
                    env->spr[SPR_DAR] = eaddr;
                    if (rwx == 1) {
                        env->spr[SPR_DSISR] = 0x0a000000;
                    } else {
                        env->spr[SPR_DSISR] = 0x08000000;
                    }
                }
                return 1;
            }

            tlb_set_page(cs, eaddr & TARGET_PAGE_MASK,
                         raddr & TARGET_PAGE_MASK, prot, mmu_idx,
                         TARGET_PAGE_SIZE);
            return 0;
        }
    }

    /* 3. Look up the Segment Register */
    sr = env->sr[eaddr >> 28];

    /* 4. Handle direct store segments */
    if (sr & SR32_T) {
        if (ppc_hash32_direct_store(env, sr, eaddr, rwx,
                                    &raddr, &prot) == 0) {
            tlb_set_page(cs, eaddr & TARGET_PAGE_MASK,
                         raddr & TARGET_PAGE_MASK, prot, mmu_idx,
                         TARGET_PAGE_SIZE);
            return 0;
        } else {
            return 1;
        }
    }

    /* 5. Check for segment level no-execute violation */
    if ((rwx == 2) && (sr & SR32_NX)) {
        cs->exception_index = POWERPC_EXCP_ISI;
        env->error_code = 0x10000000;
        return 1;
    }

    /* 6. Locate the PTE in the hash table */
    pte_offset = ppc_hash32_htab_lookup(env, sr, eaddr, &pte);
    if (pte_offset == -1) {
        if (rwx == 2) {
            cs->exception_index = POWERPC_EXCP_ISI;
            env->error_code = 0x40000000;
        } else {
            cs->exception_index = POWERPC_EXCP_DSI;
            env->error_code = 0;
            env->spr[SPR_DAR] = eaddr;
            if (rwx == 1) {
                env->spr[SPR_DSISR] = 0x42000000;
            } else {
                env->spr[SPR_DSISR] = 0x40000000;
            }
        }

        return 1;
    }
    LOG_MMU("found PTE at offset %08" HWADDR_PRIx "\n", pte_offset);

    /* 7. Check access permissions */

    prot = ppc_hash32_pte_prot(env, sr, pte);

    if (need_prot[rwx] & ~prot) {
        /* Access right violation */
        LOG_MMU("PTE access rejected\n");
        if (rwx == 2) {
            cs->exception_index = POWERPC_EXCP_ISI;
            env->error_code = 0x08000000;
        } else {
            cs->exception_index = POWERPC_EXCP_DSI;
            env->error_code = 0;
            env->spr[SPR_DAR] = eaddr;
            if (rwx == 1) {
                env->spr[SPR_DSISR] = 0x0a000000;
            } else {
                env->spr[SPR_DSISR] = 0x08000000;
            }
        }
        return 1;
    }

    LOG_MMU("PTE access granted !\n");

    /* 8. Update PTE referenced and changed bits if necessary */

    new_pte1 = pte.pte1 | HPTE32_R_R; /* set referenced bit */
    if (rwx == 1) {
        new_pte1 |= HPTE32_R_C; /* set changed (dirty) bit */
    } else {
        /* Treat the page as read-only for now, so that a later write
         * will pass through this function again to set the C bit */
        prot &= ~PAGE_WRITE;
    }

    if (new_pte1 != pte.pte1) {
        ppc_hash32_store_hpte1(env, pte_offset, new_pte1);
    }

    /* 9. Determine the real address from the PTE */

    raddr = ppc_hash32_pte_raddr(sr, pte, eaddr);

    tlb_set_page(cs, eaddr & TARGET_PAGE_MASK, raddr & TARGET_PAGE_MASK,
                 prot, mmu_idx, TARGET_PAGE_SIZE);

    return 0;
}

hwaddr ppc_hash32_get_phys_page_debug(CPUPPCState *env, target_ulong eaddr)
{
    target_ulong sr;
    hwaddr pte_offset;
    ppc_hash_pte32_t pte;
    int prot;

    if (msr_dr == 0) {
        /* Translation is off */
        return eaddr;
    }

    if (env->nb_BATs != 0) {
        hwaddr raddr = ppc_hash32_bat_lookup(env, eaddr, 0, &prot);
        if (raddr != -1) {
            return raddr;
        }
    }

    sr = env->sr[eaddr >> 28];

    if (sr & SR32_T) {
        /* FIXME: Add suitable debug support for Direct Store segments */
        return -1;
    }

    pte_offset = ppc_hash32_htab_lookup(env, sr, eaddr, &pte);
    if (pte_offset == -1) {
        return -1;
    }

    return ppc_hash32_pte_raddr(sr, pte, eaddr) & TARGET_PAGE_MASK;
}
Commit	Line	Data
9d7c3f4a DG	1	/*
	2	* PowerPC MMU, TLB and BAT emulation helpers for QEMU.
	3	*
	4	* Copyright (c) 2003-2007 Jocelyn Mayer
	5	* Copyright (c) 2013 David Gibson, IBM Corporation
	6	*
	7	* This library is free software; you can redistribute it and/or
	8	* modify it under the terms of the GNU Lesser General Public
	9	* License as published by the Free Software Foundation; either
	10	* version 2 of the License, or (at your option) any later version.
	11	*
	12	* This library is distributed in the hope that it will be useful,
	13	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	14	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	15	* Lesser General Public License for more details.
	16	*
	17	* You should have received a copy of the GNU Lesser General Public
	18	* License along with this library; if not, see <http://www.gnu.org/licenses/>.
	19	*/
	20
	21	#include "cpu.h"
2ef6175a	22	#include "exec/helper-proto.h"
9d7c3f4a DG	23	#include "sysemu/kvm.h"
	24	#include "kvm_ppc.h"
	25	#include "mmu-hash32.h"
	26
	27	//#define DEBUG_MMU
98132796	28	//#define DEBUG_BAT
9d7c3f4a DG	29
	30	#ifdef DEBUG_MMU
	31	# define LOG_MMU(...) qemu_log(__VA_ARGS__)
77710e7a	32	# define LOG_MMU_STATE(cpu) log_cpu_state((cpu), 0)
9d7c3f4a DG	33	#else
9d7c3f4a DG	34	# define LOG_MMU(...) do { } while (0)
77710e7a	35	# define LOG_MMU_STATE(cpu) do { } while (0)
9d7c3f4a DG	36	#endif
9d7c3f4a DG	37
98132796 DG	38	#ifdef DEBUG_BATS
	39	# define LOG_BATS(...) qemu_log(__VA_ARGS__)
	40	#else
	41	# define LOG_BATS(...) do { } while (0)
	42	#endif
	43
5dc68eb0 DG	44	struct mmu_ctx_hash32 {
5dc68eb0 DG	45	hwaddr raddr; /* Real address */
5dc68eb0	46	int prot; /* Protection bits */
5dc68eb0	47	int key; /* Access key */
5dc68eb0 DG	48	};
5dc68eb0 DG	49
e01b4445	50	static int ppc_hash32_pp_prot(int key, int pp, int nx)
496272a7	51	{
e01b4445	52	int prot;
496272a7	53
496272a7 DG	54	if (key == 0) {
	55	switch (pp) {
	56	case 0x0:
	57	case 0x1:
	58	case 0x2:
e01b4445 DG	59	prot = PAGE_READ \| PAGE_WRITE;
	60	break;
	61
496272a7	62	case 0x3:
e01b4445	63	prot = PAGE_READ;
496272a7	64	break;
e01b4445 DG	65
	66	default:
	67	abort();
496272a7 DG	68	}
	69	} else {
	70	switch (pp) {
	71	case 0x0:
e01b4445	72	prot = 0;
496272a7	73	break;
e01b4445	74
496272a7 DG	75	case 0x1:
496272a7 DG	76	case 0x3:
e01b4445	77	prot = PAGE_READ;
496272a7	78	break;
e01b4445	79
496272a7	80	case 0x2:
e01b4445	81	prot = PAGE_READ \| PAGE_WRITE;
496272a7	82	break;
e01b4445 DG	83
	84	default:
	85	abort();
496272a7 DG	86	}
	87	}
	88	if (nx == 0) {
e01b4445	89	prot \|= PAGE_EXEC;
496272a7 DG	90	}
496272a7 DG	91
e01b4445	92	return prot;
496272a7 DG	93	}
496272a7 DG	94
e01b4445 DG	95	static int ppc_hash32_pte_prot(CPUPPCState *env,
e01b4445 DG	96	target_ulong sr, ppc_hash_pte32_t pte)
496272a7	97	{
e01b4445	98	unsigned pp, key;
496272a7	99
e01b4445 DG	100	key = !!(msr_pr ? (sr & SR32_KP) : (sr & SR32_KS));
e01b4445 DG	101	pp = pte.pte1 & HPTE32_R_PP;
496272a7	102
e01b4445	103	return ppc_hash32_pp_prot(key, pp, !!(sr & SR32_NX));
496272a7 DG	104	}
496272a7 DG	105
6fc76aa9 DG	106	static target_ulong hash32_bat_size(CPUPPCState *env,
6fc76aa9 DG	107	target_ulong batu, target_ulong batl)
98132796	108	{
6fc76aa9 DG	109	if ((msr_pr && !(batu & BATU32_VP))
	110	\|\| (!msr_pr && !(batu & BATU32_VS))) {
	111	return 0;
98132796	112	}
6fc76aa9 DG	113
6fc76aa9 DG	114	return BATU32_BEPI & ~((batu & BATU32_BL) << 15);
98132796 DG	115	}
98132796 DG	116
e1d49515 DG	117	static int hash32_bat_prot(CPUPPCState *env,
	118	target_ulong batu, target_ulong batl)
	119	{
	120	int pp, prot;
	121
	122	prot = 0;
	123	pp = batl & BATL32_PP;
	124	if (pp != 0) {
	125	prot = PAGE_READ \| PAGE_EXEC;
	126	if (pp == 0x2) {
	127	prot \|= PAGE_WRITE;
	128	}
	129	}
	130	return prot;
	131	}
	132
6fc76aa9	133	static target_ulong hash32_bat_601_size(CPUPPCState *env,
e1d49515	134	target_ulong batu, target_ulong batl)
98132796	135	{
6fc76aa9 DG	136	if (!(batl & BATL32_601_V)) {
	137	return 0;
	138	}
	139
	140	return BATU32_BEPI & ~((batl & BATL32_601_BL) << 17);
e1d49515 DG	141	}
	142
	143	static int hash32_bat_601_prot(CPUPPCState *env,
	144	target_ulong batu, target_ulong batl)
	145	{
	146	int key, pp;
	147
	148	pp = batu & BATU32_601_PP;
	149	if (msr_pr == 0) {
	150	key = !!(batu & BATU32_601_KS);
	151	} else {
	152	key = !!(batu & BATU32_601_KP);
	153	}
e01b4445	154	return ppc_hash32_pp_prot(key, pp, 0);
98132796 DG	155	}
98132796 DG	156
145e52f3 DG	157	static hwaddr ppc_hash32_bat_lookup(CPUPPCState *env, target_ulong ea, int rwx,
145e52f3 DG	158	int *prot)
98132796	159	{
9986ed1e	160	target_ulong BATlt, BATut;
145e52f3	161	int i;
98132796 DG	162
98132796 DG	163	LOG_BATS("%s: %cBAT v " TARGET_FMT_lx "\n", __func__,
145e52f3	164	rwx == 2 ? 'I' : 'D', ea);
91cda45b	165	if (rwx == 2) {
98132796 DG	166	BATlt = env->IBAT[1];
98132796 DG	167	BATut = env->IBAT[0];
91cda45b	168	} else {
98132796 DG	169	BATlt = env->DBAT[1];
98132796 DG	170	BATut = env->DBAT[0];
98132796 DG	171	}
98132796 DG	172	for (i = 0; i < env->nb_BATs; i++) {
9986ed1e DG	173	target_ulong batu = BATut[i];
9986ed1e DG	174	target_ulong batl = BATlt[i];
6fc76aa9	175	target_ulong mask;
9986ed1e	176
98132796	177	if (unlikely(env->mmu_model == POWERPC_MMU_601)) {
6fc76aa9	178	mask = hash32_bat_601_size(env, batu, batl);
98132796	179	} else {
6fc76aa9	180	mask = hash32_bat_size(env, batu, batl);
98132796 DG	181	}
	182	LOG_BATS("%s: %cBAT%d v " TARGET_FMT_lx " BATu " TARGET_FMT_lx
	183	" BATl " TARGET_FMT_lx "\n", __func__,
145e52f3 DG	184	type == ACCESS_CODE ? 'I' : 'D', i, ea, batu, batl);
	185
	186	if (mask && ((ea & mask) == (batu & BATU32_BEPI))) {
	187	hwaddr raddr = (batl & mask) \| (ea & ~mask);
	188
	189	if (unlikely(env->mmu_model == POWERPC_MMU_601)) {
	190	*prot = hash32_bat_601_prot(env, batu, batl);
	191	} else {
	192	*prot = hash32_bat_prot(env, batu, batl);
98132796	193	}
145e52f3 DG	194
145e52f3 DG	195	return raddr & TARGET_PAGE_MASK;
98132796 DG	196	}
98132796 DG	197	}
145e52f3 DG	198
145e52f3 DG	199	/* No hit */
98132796	200	#if defined(DEBUG_BATS)
145e52f3 DG	201	if (qemu_log_enabled()) {
	202	LOG_BATS("no BAT match for " TARGET_FMT_lx ":\n", ea);
	203	for (i = 0; i < 4; i++) {
	204	BATu = &BATut[i];
	205	BATl = &BATlt[i];
	206	BEPIu = *BATu & BATU32_BEPIU;
	207	BEPIl = *BATu & BATU32_BEPIL;
	208	bl = (*BATu & 0x00001FFC) << 15;
	209	LOG_BATS("%s: %cBAT%d v " TARGET_FMT_lx " BATu " TARGET_FMT_lx
	210	" BATl " TARGET_FMT_lx "\n\t" TARGET_FMT_lx " "
	211	TARGET_FMT_lx " " TARGET_FMT_lx "\n",
	212	__func__, type == ACCESS_CODE ? 'I' : 'D', i, ea,
	213	BATu, BATl, BEPIu, BEPIl, bl);
98132796	214	}
98132796	215	}
145e52f3 DG	216	#endif
	217
	218	return -1;
98132796 DG	219	}
98132796 DG	220
723ed73a DG	221	static int ppc_hash32_direct_store(CPUPPCState *env, target_ulong sr,
	222	target_ulong eaddr, int rwx,
	223	hwaddr raddr, int prot)
	224	{
27103424	225	CPUState *cs = CPU(ppc_env_get_cpu(env));
723ed73a DG	226	int key = !!(msr_pr ? (sr & SR32_KP) : (sr & SR32_KS));
	227
	228	LOG_MMU("direct store...\n");
	229
	230	if ((sr & 0x1FF00000) >> 20 == 0x07f) {
	231	/* Memory-forced I/O controller interface access */
	232	/* If T=1 and BUID=x'07F', the 601 performs a memory access
	233	* to SR[28-31] LA[4-31], bypassing all protection mechanisms.
	234	*/
	235	*raddr = ((sr & 0xF) << 28) \| (eaddr & 0x0FFFFFFF);
	236	*prot = PAGE_READ \| PAGE_WRITE \| PAGE_EXEC;
	237	return 0;
	238	}
	239
	240	if (rwx == 2) {
	241	/* No code fetch is allowed in direct-store areas */
27103424	242	cs->exception_index = POWERPC_EXCP_ISI;
caa597bd DG	243	env->error_code = 0x10000000;
caa597bd DG	244	return 1;
723ed73a DG	245	}
	246
	247	switch (env->access_type) {
	248	case ACCESS_INT:
	249	/* Integer load/store : only access allowed */
	250	break;
	251	case ACCESS_FLOAT:
	252	/* Floating point load/store */
27103424	253	cs->exception_index = POWERPC_EXCP_ALIGN;
caa597bd DG	254	env->error_code = POWERPC_EXCP_ALIGN_FP;
	255	env->spr[SPR_DAR] = eaddr;
	256	return 1;
723ed73a DG	257	case ACCESS_RES:
723ed73a DG	258	/* lwarx, ldarx or srwcx. */
caa597bd DG	259	env->error_code = 0;
	260	env->spr[SPR_DAR] = eaddr;
	261	if (rwx == 1) {
	262	env->spr[SPR_DSISR] = 0x06000000;
	263	} else {
	264	env->spr[SPR_DSISR] = 0x04000000;
	265	}
	266	return 1;
723ed73a DG	267	case ACCESS_CACHE:
	268	/* dcba, dcbt, dcbtst, dcbf, dcbi, dcbst, dcbz, or icbi */
	269	/* Should make the instruction do no-op.
	270	* As it already do no-op, it's quite easy :-)
	271	*/
	272	*raddr = eaddr;
	273	return 0;
	274	case ACCESS_EXT:
	275	/* eciwx or ecowx */
27103424	276	cs->exception_index = POWERPC_EXCP_DSI;
caa597bd DG	277	env->error_code = 0;
	278	env->spr[SPR_DAR] = eaddr;
	279	if (rwx == 1) {
	280	env->spr[SPR_DSISR] = 0x06100000;
	281	} else {
	282	env->spr[SPR_DSISR] = 0x04100000;
	283	}
	284	return 1;
723ed73a DG	285	default:
	286	qemu_log("ERROR: instruction should not need "
	287	"address translation\n");
caa597bd	288	abort();
723ed73a DG	289	}
	290	if ((rwx == 1 \|\| key != 1) && (rwx == 0 \|\| key != 0)) {
	291	*raddr = eaddr;
caa597bd	292	return 0;
723ed73a	293	} else {
27103424	294	cs->exception_index = POWERPC_EXCP_DSI;
caa597bd DG	295	env->error_code = 0;
	296	env->spr[SPR_DAR] = eaddr;
	297	if (rwx == 1) {
	298	env->spr[SPR_DSISR] = 0x0a000000;
	299	} else {
	300	env->spr[SPR_DSISR] = 0x08000000;
	301	}
	302	return 1;
723ed73a DG	303	}
	304	}
	305
59191721 DG	306	hwaddr get_pteg_offset32(CPUPPCState *env, hwaddr hash)
59191721 DG	307	{
d5aea6f3	308	return (hash * HASH_PTEG_SIZE_32) & env->htab_mask;
59191721 DG	309	}
59191721 DG	310
aea390e4 DG	311	static hwaddr ppc_hash32_pteg_search(CPUPPCState *env, hwaddr pteg_off,
	312	bool secondary, target_ulong ptem,
	313	ppc_hash_pte32_t *pte)
	314	{
	315	hwaddr pte_offset = pteg_off;
	316	target_ulong pte0, pte1;
	317	int i;
	318
	319	for (i = 0; i < HPTES_PER_GROUP; i++) {
	320	pte0 = ppc_hash32_load_hpte0(env, pte_offset);
	321	pte1 = ppc_hash32_load_hpte1(env, pte_offset);
	322
	323	if ((pte0 & HPTE32_V_VALID)
	324	&& (secondary == !!(pte0 & HPTE32_V_SECONDARY))
	325	&& HPTE32_V_COMPARE(pte0, ptem)) {
	326	pte->pte0 = pte0;
	327	pte->pte1 = pte1;
	328	return pte_offset;
	329	}
	330
	331	pte_offset += HASH_PTE_SIZE_32;
	332	}
	333
	334	return -1;
	335	}
	336
7f3bdc2d DG	337	static hwaddr ppc_hash32_htab_lookup(CPUPPCState *env,
	338	target_ulong sr, target_ulong eaddr,
	339	ppc_hash_pte32_t *pte)
c69b6151	340	{
aea390e4	341	hwaddr pteg_off, pte_offset;
a1ff751a DG	342	hwaddr hash;
a1ff751a DG	343	uint32_t vsid, pgidx, ptem;
c69b6151	344
a1ff751a	345	vsid = sr & SR32_VSID;
a1ff751a DG	346	pgidx = (eaddr & ~SEGMENT_MASK_256M) >> TARGET_PAGE_BITS;
	347	hash = vsid ^ pgidx;
	348	ptem = (vsid << 7) \| (pgidx >> 10);
	349
	350	/* Page address translation */
	351	LOG_MMU("htab_base " TARGET_FMT_plx " htab_mask " TARGET_FMT_plx
	352	" hash " TARGET_FMT_plx "\n",
	353	env->htab_base, env->htab_mask, hash);
	354
	355	/* Primary PTEG lookup */
	356	LOG_MMU("0 htab=" TARGET_FMT_plx "/" TARGET_FMT_plx
	357	" vsid=%" PRIx32 " ptem=%" PRIx32
	358	" hash=" TARGET_FMT_plx "\n",
	359	env->htab_base, env->htab_mask, vsid, ptem, hash);
	360	pteg_off = get_pteg_offset32(env, hash);
7f3bdc2d	361	pte_offset = ppc_hash32_pteg_search(env, pteg_off, 0, ptem, pte);
a1ff751a DG	362	if (pte_offset == -1) {
	363	/* Secondary PTEG lookup */
	364	LOG_MMU("1 htab=" TARGET_FMT_plx "/" TARGET_FMT_plx
	365	" vsid=%" PRIx32 " api=%" PRIx32
	366	" hash=" TARGET_FMT_plx "\n", env->htab_base,
	367	env->htab_mask, vsid, ptem, ~hash);
	368	pteg_off = get_pteg_offset32(env, ~hash);
7f3bdc2d	369	pte_offset = ppc_hash32_pteg_search(env, pteg_off, 1, ptem, pte);
a1ff751a DG	370	}
a1ff751a DG	371
7f3bdc2d	372	return pte_offset;
c69b6151	373	}
0480884f	374
6d11d998 DG	375	static hwaddr ppc_hash32_pte_raddr(target_ulong sr, ppc_hash_pte32_t pte,
	376	target_ulong eaddr)
	377	{
75d5ec89	378	hwaddr rpn = pte.pte1 & HPTE32_R_RPN;
6d11d998 DG	379	hwaddr mask = ~TARGET_PAGE_MASK;
	380
	381	return (rpn & ~mask) \| (eaddr & mask);
	382	}
	383
d0e39c5d	384	int ppc_hash32_handle_mmu_fault(PowerPCCPU *cpu, target_ulong eaddr, int rwx,
caa597bd	385	int mmu_idx)
0480884f	386	{
d0e39c5d AF	387	CPUState *cs = CPU(cpu);
d0e39c5d AF	388	CPUPPCState *env = &cpu->env;
a1ff751a	389	target_ulong sr;
7f3bdc2d DG	390	hwaddr pte_offset;
7f3bdc2d DG	391	ppc_hash_pte32_t pte;
caa597bd	392	int prot;
b3440746	393	uint32_t new_pte1;
e01b4445	394	const int need_prot[] = {PAGE_READ, PAGE_WRITE, PAGE_EXEC};
caa597bd	395	hwaddr raddr;
0480884f	396
6a980110 DG	397	assert((rwx == 0) \|\| (rwx == 1) \|\| (rwx == 2));
6a980110 DG	398
65d61643 DG	399	/* 1. Handle real mode accesses */
	400	if (((rwx == 2) && (msr_ir == 0)) \|\| ((rwx != 2) && (msr_dr == 0))) {
	401	/* Translation is off */
caa597bd	402	raddr = eaddr;
0c591eb0	403	tlb_set_page(cs, eaddr & TARGET_PAGE_MASK, raddr & TARGET_PAGE_MASK,
caa597bd DG	404	PAGE_READ \| PAGE_WRITE \| PAGE_EXEC, mmu_idx,
caa597bd DG	405	TARGET_PAGE_SIZE);
65d61643 DG	406	return 0;
	407	}
	408
	409	/* 2. Check Block Address Translation entries (BATs) */
	410	if (env->nb_BATs != 0) {
caa597bd DG	411	raddr = ppc_hash32_bat_lookup(env, eaddr, rwx, &prot);
	412	if (raddr != -1) {
	413	if (need_prot[rwx] & ~prot) {
	414	if (rwx == 2) {
27103424	415	cs->exception_index = POWERPC_EXCP_ISI;
caa597bd DG	416	env->error_code = 0x08000000;
caa597bd DG	417	} else {
27103424	418	cs->exception_index = POWERPC_EXCP_DSI;
caa597bd DG	419	env->error_code = 0;
	420	env->spr[SPR_DAR] = eaddr;
	421	if (rwx == 1) {
	422	env->spr[SPR_DSISR] = 0x0a000000;
	423	} else {
	424	env->spr[SPR_DSISR] = 0x08000000;
	425	}
	426	}
	427	return 1;
e01b4445	428	}
caa597bd	429
0c591eb0	430	tlb_set_page(cs, eaddr & TARGET_PAGE_MASK,
caa597bd DG	431	raddr & TARGET_PAGE_MASK, prot, mmu_idx,
caa597bd DG	432	TARGET_PAGE_SIZE);
e01b4445	433	return 0;
65d61643 DG	434	}
	435	}
	436
4b9605a5	437	/* 3. Look up the Segment Register */
0480884f	438	sr = env->sr[eaddr >> 28];
4b9605a5	439
4b9605a5 DG	440	/* 4. Handle direct store segments */
4b9605a5 DG	441	if (sr & SR32_T) {
caa597bd DG	442	if (ppc_hash32_direct_store(env, sr, eaddr, rwx,
caa597bd DG	443	&raddr, &prot) == 0) {
0c591eb0	444	tlb_set_page(cs, eaddr & TARGET_PAGE_MASK,
caa597bd DG	445	raddr & TARGET_PAGE_MASK, prot, mmu_idx,
	446	TARGET_PAGE_SIZE);
	447	return 0;
	448	} else {
	449	return 1;
	450	}
4b9605a5 DG	451	}
4b9605a5 DG	452
bb218042	453	/* 5. Check for segment level no-execute violation */
e01b4445	454	if ((rwx == 2) && (sr & SR32_NX)) {
27103424	455	cs->exception_index = POWERPC_EXCP_ISI;
caa597bd DG	456	env->error_code = 0x10000000;
caa597bd DG	457	return 1;
bb218042	458	}
7f3bdc2d DG	459
	460	/* 6. Locate the PTE in the hash table */
	461	pte_offset = ppc_hash32_htab_lookup(env, sr, eaddr, &pte);
	462	if (pte_offset == -1) {
caa597bd	463	if (rwx == 2) {
27103424	464	cs->exception_index = POWERPC_EXCP_ISI;
caa597bd DG	465	env->error_code = 0x40000000;
caa597bd DG	466	} else {
27103424	467	cs->exception_index = POWERPC_EXCP_DSI;
caa597bd DG	468	env->error_code = 0;
	469	env->spr[SPR_DAR] = eaddr;
	470	if (rwx == 1) {
	471	env->spr[SPR_DSISR] = 0x42000000;
	472	} else {
	473	env->spr[SPR_DSISR] = 0x40000000;
	474	}
	475	}
	476
	477	return 1;
7f3bdc2d DG	478	}
	479	LOG_MMU("found PTE at offset %08" HWADDR_PRIx "\n", pte_offset);
	480
	481	/* 7. Check access permissions */
6a980110	482
caa597bd	483	prot = ppc_hash32_pte_prot(env, sr, pte);
6a980110	484
caa597bd	485	if (need_prot[rwx] & ~prot) {
6a980110 DG	486	/* Access right violation */
6a980110 DG	487	LOG_MMU("PTE access rejected\n");
caa597bd	488	if (rwx == 2) {
27103424	489	cs->exception_index = POWERPC_EXCP_ISI;
caa597bd DG	490	env->error_code = 0x08000000;
caa597bd DG	491	} else {
27103424	492	cs->exception_index = POWERPC_EXCP_DSI;
caa597bd DG	493	env->error_code = 0;
	494	env->spr[SPR_DAR] = eaddr;
	495	if (rwx == 1) {
	496	env->spr[SPR_DSISR] = 0x0a000000;
	497	} else {
	498	env->spr[SPR_DSISR] = 0x08000000;
	499	}
	500	}
	501	return 1;
6a980110 DG	502	}
6a980110 DG	503
87dc3fd1 DG	504	LOG_MMU("PTE access granted !\n");
	505
	506	/* 8. Update PTE referenced and changed bits if necessary */
	507
b3440746 DG	508	new_pte1 = pte.pte1 \| HPTE32_R_R; /* set referenced bit */
	509	if (rwx == 1) {
	510	new_pte1 \|= HPTE32_R_C; /* set changed (dirty) bit */
	511	} else {
	512	/* Treat the page as read-only for now, so that a later write
	513	* will pass through this function again to set the C bit */
caa597bd	514	prot &= ~PAGE_WRITE;
b3440746 DG	515	}
	516
	517	if (new_pte1 != pte.pte1) {
	518	ppc_hash32_store_hpte1(env, pte_offset, new_pte1);
7f3bdc2d	519	}
0480884f	520
6d11d998 DG	521	/* 9. Determine the real address from the PTE */
6d11d998 DG	522
caa597bd DG	523	raddr = ppc_hash32_pte_raddr(sr, pte, eaddr);
caa597bd DG	524
0c591eb0	525	tlb_set_page(cs, eaddr & TARGET_PAGE_MASK, raddr & TARGET_PAGE_MASK,
caa597bd	526	prot, mmu_idx, TARGET_PAGE_SIZE);
e01b4445 DG	527
e01b4445 DG	528	return 0;
0480884f	529	}
629bd516	530
5883d8b2	531	hwaddr ppc_hash32_get_phys_page_debug(CPUPPCState *env, target_ulong eaddr)
f2ad6be8	532	{
5883d8b2 DG	533	target_ulong sr;
	534	hwaddr pte_offset;
	535	ppc_hash_pte32_t pte;
	536	int prot;
	537
	538	if (msr_dr == 0) {
	539	/* Translation is off */
	540	return eaddr;
	541	}
f2ad6be8	542
5883d8b2 DG	543	if (env->nb_BATs != 0) {
	544	hwaddr raddr = ppc_hash32_bat_lookup(env, eaddr, 0, &prot);
	545	if (raddr != -1) {
	546	return raddr;
	547	}
	548	}
	549
	550	sr = env->sr[eaddr >> 28];
	551
	552	if (sr & SR32_T) {
	553	/* FIXME: Add suitable debug support for Direct Store segments */
	554	return -1;
	555	}
	556
	557	pte_offset = ppc_hash32_htab_lookup(env, sr, eaddr, &pte);
	558	if (pte_offset == -1) {
f2ad6be8 DG	559	return -1;
	560	}
	561
5883d8b2	562	return ppc_hash32_pte_raddr(sr, pte, eaddr) & TARGET_PAGE_MASK;
f2ad6be8	563	}