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target-sparc: Use defines from asi.h
[thirdparty/qemu.git] / target-sparc / ldst_helper.c
CommitLineData
fafd8bce
BS		 1/*
2 * Helpers for loads and stores
3 *
4 * Copyright (c) 2003-2005 Fabrice Bellard
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19
db5ebe5f 20#include "qemu/osdep.h"
fafd8bce 21#include "cpu.h"
2ef6175a 22#include "exec/helper-proto.h"
63c91552 23#include "exec/exec-all.h"
f08b6170 24#include "exec/cpu_ldst.h"
0cc1f4bf 25#include "asi.h"
fafd8bce 26
fafd8bce
BS		 27//#define DEBUG_MMU
28//#define DEBUG_MXCC
29//#define DEBUG_UNALIGNED
30//#define DEBUG_UNASSIGNED
31//#define DEBUG_ASI
32//#define DEBUG_CACHE_CONTROL
33
34#ifdef DEBUG_MMU
35#define DPRINTF_MMU(fmt, ...) \
36 do { printf("MMU: " fmt , ## __VA_ARGS__); } while (0)
37#else
38#define DPRINTF_MMU(fmt, ...) do {} while (0)
39#endif
40
41#ifdef DEBUG_MXCC
42#define DPRINTF_MXCC(fmt, ...) \
43 do { printf("MXCC: " fmt , ## __VA_ARGS__); } while (0)
44#else
45#define DPRINTF_MXCC(fmt, ...) do {} while (0)
46#endif
47
48#ifdef DEBUG_ASI
49#define DPRINTF_ASI(fmt, ...) \
50 do { printf("ASI: " fmt , ## __VA_ARGS__); } while (0)
51#endif
52
53#ifdef DEBUG_CACHE_CONTROL
54#define DPRINTF_CACHE_CONTROL(fmt, ...) \
55 do { printf("CACHE_CONTROL: " fmt , ## __VA_ARGS__); } while (0)
56#else
57#define DPRINTF_CACHE_CONTROL(fmt, ...) do {} while (0)
58#endif
59
60#ifdef TARGET_SPARC64
61#ifndef TARGET_ABI32
62#define AM_CHECK(env1) ((env1)->pstate & PS_AM)
63#else
64#define AM_CHECK(env1) (1)
65#endif
66#endif
67
fafd8bce
BS		 68#define QT0 (env->qt0)
69#define QT1 (env->qt1)
70
fafd8bce
BS		 71#if defined(TARGET_SPARC64) && !defined(CONFIG_USER_ONLY)
72/* Calculates TSB pointer value for fault page size 8k or 64k */
73static uint64_t ultrasparc_tsb_pointer(uint64_t tsb_register,
74 uint64_t tag_access_register,
75 int page_size)
76{
77 uint64_t tsb_base = tsb_register & ~0x1fffULL;
78 int tsb_split = (tsb_register & 0x1000ULL) ? 1 : 0;
79 int tsb_size = tsb_register & 0xf;
80
81 /* discard lower 13 bits which hold tag access context */
82 uint64_t tag_access_va = tag_access_register & ~0x1fffULL;
83
84 /* now reorder bits */
85 uint64_t tsb_base_mask = ~0x1fffULL;
86 uint64_t va = tag_access_va;
87
88 /* move va bits to correct position */
89 if (page_size == 8*1024) {
90 va >>= 9;
91 } else if (page_size == 64*1024) {
92 va >>= 12;
93 }
94
95 if (tsb_size) {
96 tsb_base_mask <<= tsb_size;
97 }
98
99 /* calculate tsb_base mask and adjust va if split is in use */
100 if (tsb_split) {
101 if (page_size == 8*1024) {
102 va &= ~(1ULL << (13 + tsb_size));
103 } else if (page_size == 64*1024) {
104 va |= (1ULL << (13 + tsb_size));
105 }
106 tsb_base_mask <<= 1;
107 }
108
109 return ((tsb_base & tsb_base_mask) | (va & ~tsb_base_mask)) & ~0xfULL;
110}
111
112/* Calculates tag target register value by reordering bits
113 in tag access register */
114static uint64_t ultrasparc_tag_target(uint64_t tag_access_register)
115{
116 return ((tag_access_register & 0x1fff) << 48) | (tag_access_register >> 22);
117}
118
119static void replace_tlb_entry(SparcTLBEntry *tlb,
120 uint64_t tlb_tag, uint64_t tlb_tte,
c5f9864e 121 CPUSPARCState *env1)
fafd8bce
BS		 122{
123 target_ulong mask, size, va, offset;
124
125 /* flush page range if translation is valid */
126 if (TTE_IS_VALID(tlb->tte)) {
31b030d4 127 CPUState *cs = CPU(sparc_env_get_cpu(env1));
fafd8bce
BS		 128
129 mask = 0xffffffffffffe000ULL;
130 mask <<= 3 * ((tlb->tte >> 61) & 3);
131 size = ~mask + 1;
132
133 va = tlb->tag & mask;
134
135 for (offset = 0; offset < size; offset += TARGET_PAGE_SIZE) {
31b030d4 136 tlb_flush_page(cs, va + offset);
fafd8bce
BS		 137 }
138 }
139
140 tlb->tag = tlb_tag;
141 tlb->tte = tlb_tte;
142}
143
144static void demap_tlb(SparcTLBEntry *tlb, target_ulong demap_addr,
c5f9864e 145 const char *strmmu, CPUSPARCState *env1)
fafd8bce
BS		 146{
147 unsigned int i;
148 target_ulong mask;
149 uint64_t context;
150
151 int is_demap_context = (demap_addr >> 6) & 1;
152
153 /* demap context */
154 switch ((demap_addr >> 4) & 3) {
155 case 0: /* primary */
156 context = env1->dmmu.mmu_primary_context;
157 break;
158 case 1: /* secondary */
159 context = env1->dmmu.mmu_secondary_context;
160 break;
161 case 2: /* nucleus */
162 context = 0;
163 break;
164 case 3: /* reserved */
165 default:
166 return;
167 }
168
169 for (i = 0; i < 64; i++) {
170 if (TTE_IS_VALID(tlb[i].tte)) {
171
172 if (is_demap_context) {
173 /* will remove non-global entries matching context value */
174 if (TTE_IS_GLOBAL(tlb[i].tte) ||
175 !tlb_compare_context(&tlb[i], context)) {
176 continue;
177 }
178 } else {
179 /* demap page
180 will remove any entry matching VA */
181 mask = 0xffffffffffffe000ULL;
182 mask <<= 3 * ((tlb[i].tte >> 61) & 3);
183
184 if (!compare_masked(demap_addr, tlb[i].tag, mask)) {
185 continue;
186 }
187
188 /* entry should be global or matching context value */
189 if (!TTE_IS_GLOBAL(tlb[i].tte) &&
190 !tlb_compare_context(&tlb[i], context)) {
191 continue;
192 }
193 }
194
195 replace_tlb_entry(&tlb[i], 0, 0, env1);
196#ifdef DEBUG_MMU
197 DPRINTF_MMU("%s demap invalidated entry [%02u]\n", strmmu, i);
198 dump_mmu(stdout, fprintf, env1);
199#endif
200 }
201 }
202}
203
204static void replace_tlb_1bit_lru(SparcTLBEntry *tlb,
205 uint64_t tlb_tag, uint64_t tlb_tte,
c5f9864e 206 const char *strmmu, CPUSPARCState *env1)
fafd8bce
BS		 207{
208 unsigned int i, replace_used;
209
210 /* Try replacing invalid entry */
211 for (i = 0; i < 64; i++) {
212 if (!TTE_IS_VALID(tlb[i].tte)) {
213 replace_tlb_entry(&tlb[i], tlb_tag, tlb_tte, env1);
214#ifdef DEBUG_MMU
215 DPRINTF_MMU("%s lru replaced invalid entry [%i]\n", strmmu, i);
216 dump_mmu(stdout, fprintf, env1);
217#endif
218 return;
219 }
220 }
221
222 /* All entries are valid, try replacing unlocked entry */
223
224 for (replace_used = 0; replace_used < 2; ++replace_used) {
225
226 /* Used entries are not replaced on first pass */
227
228 for (i = 0; i < 64; i++) {
229 if (!TTE_IS_LOCKED(tlb[i].tte) && !TTE_IS_USED(tlb[i].tte)) {
230
231 replace_tlb_entry(&tlb[i], tlb_tag, tlb_tte, env1);
232#ifdef DEBUG_MMU
233 DPRINTF_MMU("%s lru replaced unlocked %s entry [%i]\n",
234 strmmu, (replace_used ? "used" : "unused"), i);
235 dump_mmu(stdout, fprintf, env1);
236#endif
237 return;
238 }
239 }
240
241 /* Now reset used bit and search for unused entries again */
242
243 for (i = 0; i < 64; i++) {
244 TTE_SET_UNUSED(tlb[i].tte);
245 }
246 }
247
248#ifdef DEBUG_MMU
249 DPRINTF_MMU("%s lru replacement failed: no entries available\n", strmmu);
250#endif
251 /* error state? */
252}
253
254#endif
255
e60538c7 256#if defined(TARGET_SPARC64) || defined(CONFIG_USER_ONLY)
c5f9864e 257static inline target_ulong address_mask(CPUSPARCState *env1, target_ulong addr)
fafd8bce
BS		 258{
259#ifdef TARGET_SPARC64
260 if (AM_CHECK(env1)) {
261 addr &= 0xffffffffULL;
262 }
263#endif
264 return addr;
265}
e60538c7 266#endif
fafd8bce 267
69694625 268#ifdef TARGET_SPARC64
fafd8bce
BS		 269/* returns true if access using this ASI is to have address translated by MMU
270 otherwise access is to raw physical address */
69694625 271/* TODO: check sparc32 bits */
fafd8bce
BS		 272static inline int is_translating_asi(int asi)
273{
fafd8bce
BS		 274 /* Ultrasparc IIi translating asi
275 - note this list is defined by cpu implementation
276 */
277 switch (asi) {
278 case 0x04 ... 0x11:
279 case 0x16 ... 0x19:
280 case 0x1E ... 0x1F:
281 case 0x24 ... 0x2C:
282 case 0x70 ... 0x73:
283 case 0x78 ... 0x79:
284 case 0x80 ... 0xFF:
285 return 1;
286
287 default:
288 return 0;
289 }
fafd8bce
BS		 290}
291
fe8d8f0f 292static inline target_ulong asi_address_mask(CPUSPARCState *env,
fafd8bce
BS		 293 int asi, target_ulong addr)
294{
295 if (is_translating_asi(asi)) {
296 return address_mask(env, addr);
297 } else {
298 return addr;
299 }
300}
e60538c7 301#endif
fafd8bce 302
fe8d8f0f 303void helper_check_align(CPUSPARCState *env, target_ulong addr, uint32_t align)
fafd8bce
BS		 304{
305 if (addr & align) {
306#ifdef DEBUG_UNALIGNED
307 printf("Unaligned access to 0x" TARGET_FMT_lx " from 0x" TARGET_FMT_lx
308 "\n", addr, env->pc);
309#endif
310 helper_raise_exception(env, TT_UNALIGNED);
311 }
312}
313
314#if !defined(TARGET_SPARC64) && !defined(CONFIG_USER_ONLY) && \
315 defined(DEBUG_MXCC)
c5f9864e 316static void dump_mxcc(CPUSPARCState *env)
fafd8bce
BS		 317{
318 printf("mxccdata: %016" PRIx64 " %016" PRIx64 " %016" PRIx64 " %016" PRIx64
319 "\n",
320 env->mxccdata[0], env->mxccdata[1],
321 env->mxccdata[2], env->mxccdata[3]);
322 printf("mxccregs: %016" PRIx64 " %016" PRIx64 " %016" PRIx64 " %016" PRIx64
323 "\n"
324 " %016" PRIx64 " %016" PRIx64 " %016" PRIx64 " %016" PRIx64
325 "\n",
326 env->mxccregs[0], env->mxccregs[1],
327 env->mxccregs[2], env->mxccregs[3],
328 env->mxccregs[4], env->mxccregs[5],
329 env->mxccregs[6], env->mxccregs[7]);
330}
331#endif
332
333#if (defined(TARGET_SPARC64) || !defined(CONFIG_USER_ONLY)) \
334 && defined(DEBUG_ASI)
335static void dump_asi(const char *txt, target_ulong addr, int asi, int size,
336 uint64_t r1)
337{
338 switch (size) {
339 case 1:
340 DPRINTF_ASI("%s "TARGET_FMT_lx " asi 0x%02x = %02" PRIx64 "\n", txt,
341 addr, asi, r1 & 0xff);
342 break;
343 case 2:
344 DPRINTF_ASI("%s "TARGET_FMT_lx " asi 0x%02x = %04" PRIx64 "\n", txt,
345 addr, asi, r1 & 0xffff);
346 break;
347 case 4:
348 DPRINTF_ASI("%s "TARGET_FMT_lx " asi 0x%02x = %08" PRIx64 "\n", txt,
349 addr, asi, r1 & 0xffffffff);
350 break;
351 case 8:
352 DPRINTF_ASI("%s "TARGET_FMT_lx " asi 0x%02x = %016" PRIx64 "\n", txt,
353 addr, asi, r1);
354 break;
355 }
356}
357#endif
358
359#ifndef TARGET_SPARC64
360#ifndef CONFIG_USER_ONLY
361
362
363/* Leon3 cache control */
364
fe8d8f0f
BS		 365static void leon3_cache_control_st(CPUSPARCState *env, target_ulong addr,
366 uint64_t val, int size)
fafd8bce
BS		 367{
368 DPRINTF_CACHE_CONTROL("st addr:%08x, val:%" PRIx64 ", size:%d\n",
369 addr, val, size);
370
371 if (size != 4) {
372 DPRINTF_CACHE_CONTROL("32bits only\n");
373 return;
374 }
375
376 switch (addr) {
377 case 0x00: /* Cache control */
378
379 /* These values must always be read as zeros */
380 val &= ~CACHE_CTRL_FD;
381 val &= ~CACHE_CTRL_FI;
382 val &= ~CACHE_CTRL_IB;
383 val &= ~CACHE_CTRL_IP;
384 val &= ~CACHE_CTRL_DP;
385
386 env->cache_control = val;
387 break;
388 case 0x04: /* Instruction cache configuration */
389 case 0x08: /* Data cache configuration */
390 /* Read Only */
391 break;
392 default:
393 DPRINTF_CACHE_CONTROL("write unknown register %08x\n", addr);
394 break;
395 };
396}
397
fe8d8f0f
BS		 398static uint64_t leon3_cache_control_ld(CPUSPARCState *env, target_ulong addr,
399 int size)
fafd8bce
BS		 400{
401 uint64_t ret = 0;
402
403 if (size != 4) {
404 DPRINTF_CACHE_CONTROL("32bits only\n");
405 return 0;
406 }
407
408 switch (addr) {
409 case 0x00: /* Cache control */
410 ret = env->cache_control;
411 break;
412
413 /* Configuration registers are read and only always keep those
414 predefined values */
415
416 case 0x04: /* Instruction cache configuration */
417 ret = 0x10220000;
418 break;
419 case 0x08: /* Data cache configuration */
420 ret = 0x18220000;
421 break;
422 default:
423 DPRINTF_CACHE_CONTROL("read unknown register %08x\n", addr);
424 break;
425 };
426 DPRINTF_CACHE_CONTROL("ld addr:%08x, ret:0x%" PRIx64 ", size:%d\n",
427 addr, ret, size);
428 return ret;
429}
430
fe8d8f0f
BS		 431uint64_t helper_ld_asi(CPUSPARCState *env, target_ulong addr, int asi, int size,
432 int sign)
fafd8bce 433{
2fad1112 434 CPUState *cs = CPU(sparc_env_get_cpu(env));
fafd8bce
BS		 435 uint64_t ret = 0;
436#if defined(DEBUG_MXCC) || defined(DEBUG_ASI)
437 uint32_t last_addr = addr;
438#endif
439
fe8d8f0f 440 helper_check_align(env, addr, size - 1);
fafd8bce 441 switch (asi) {
0cc1f4bf
RH		 442 case ASI_M_MXCC: /* SuperSparc MXCC registers, or... */
443 /* case ASI_LEON_CACHEREGS: Leon3 cache control */
fafd8bce
BS		 444 switch (addr) {
445 case 0x00: /* Leon3 Cache Control */
446 case 0x08: /* Leon3 Instruction Cache config */
447 case 0x0C: /* Leon3 Date Cache config */
448 if (env->def->features & CPU_FEATURE_CACHE_CTRL) {
fe8d8f0f 449 ret = leon3_cache_control_ld(env, addr, size);
fafd8bce
BS		 450 }
451 break;
452 case 0x01c00a00: /* MXCC control register */
453 if (size == 8) {
454 ret = env->mxccregs[3];
455 } else {
71547a3b
BS		 456 qemu_log_mask(LOG_UNIMP,
457 "%08x: unimplemented access size: %d\n", addr,
458 size);
fafd8bce
BS		 459 }
460 break;
461 case 0x01c00a04: /* MXCC control register */
462 if (size == 4) {
463 ret = env->mxccregs[3];
464 } else {
71547a3b
BS		 465 qemu_log_mask(LOG_UNIMP,
466 "%08x: unimplemented access size: %d\n", addr,
467 size);
fafd8bce
BS		 468 }
469 break;
470 case 0x01c00c00: /* Module reset register */
471 if (size == 8) {
472 ret = env->mxccregs[5];
473 /* should we do something here? */
474 } else {
71547a3b
BS		 475 qemu_log_mask(LOG_UNIMP,
476 "%08x: unimplemented access size: %d\n", addr,
477 size);
fafd8bce
BS		 478 }
479 break;
480 case 0x01c00f00: /* MBus port address register */
481 if (size == 8) {
482 ret = env->mxccregs[7];
483 } else {
71547a3b
BS		 484 qemu_log_mask(LOG_UNIMP,
485 "%08x: unimplemented access size: %d\n", addr,
486 size);
fafd8bce
BS		 487 }
488 break;
489 default:
71547a3b
BS		 490 qemu_log_mask(LOG_UNIMP,
491 "%08x: unimplemented address, size: %d\n", addr,
492 size);
fafd8bce
BS		 493 break;
494 }
495 DPRINTF_MXCC("asi = %d, size = %d, sign = %d, "
496 "addr = %08x -> ret = %" PRIx64 ","
497 "addr = %08x\n", asi, size, sign, last_addr, ret, addr);
498#ifdef DEBUG_MXCC
499 dump_mxcc(env);
500#endif
501 break;
0cc1f4bf
RH		 502 case ASI_M_FLUSH_PROBE: /* SuperSparc MMU probe */
503 case ASI_LEON_MMUFLUSH: /* LEON3 MMU probe */
fafd8bce
BS		 504 {
505 int mmulev;
506
507 mmulev = (addr >> 8) & 15;
508 if (mmulev > 4) {
509 ret = 0;
510 } else {
511 ret = mmu_probe(env, addr, mmulev);
512 }
513 DPRINTF_MMU("mmu_probe: 0x%08x (lev %d) -> 0x%08" PRIx64 "\n",
514 addr, mmulev, ret);
515 }
516 break;
0cc1f4bf
RH		 517 case ASI_M_MMUREGS: /* SuperSparc MMU regs */
518 case ASI_LEON_MMUREGS: /* LEON3 MMU regs */
fafd8bce
BS		 519 {
520 int reg = (addr >> 8) & 0x1f;
521
522 ret = env->mmuregs[reg];
523 if (reg == 3) { /* Fault status cleared on read */
524 env->mmuregs[3] = 0;
525 } else if (reg == 0x13) { /* Fault status read */
526 ret = env->mmuregs[3];
527 } else if (reg == 0x14) { /* Fault address read */
528 ret = env->mmuregs[4];
529 }
530 DPRINTF_MMU("mmu_read: reg[%d] = 0x%08" PRIx64 "\n", reg, ret);
531 }
532 break;
0cc1f4bf
RH		 533 case ASI_M_TLBDIAG: /* Turbosparc ITLB Diagnostic */
534 case ASI_M_DIAGS: /* Turbosparc DTLB Diagnostic */
535 case ASI_M_IODIAG: /* Turbosparc IOTLB Diagnostic */
fafd8bce 536 break;
0cc1f4bf 537 case ASI_KERNELTXT: /* Supervisor code access */
fafd8bce
BS		 538 switch (size) {
539 case 1:
0184e266 540 ret = cpu_ldub_code(env, addr);
fafd8bce
BS		 541 break;
542 case 2:
0184e266 543 ret = cpu_lduw_code(env, addr);
fafd8bce
BS		 544 break;
545 default:
546 case 4:
0184e266 547 ret = cpu_ldl_code(env, addr);
fafd8bce
BS		 548 break;
549 case 8:
0184e266 550 ret = cpu_ldq_code(env, addr);
fafd8bce
BS		 551 break;
552 }
553 break;
0cc1f4bf 554 case ASI_USERDATA: /* User data access */
fafd8bce
BS		 555 switch (size) {
556 case 1:
fe8d8f0f 557 ret = cpu_ldub_user(env, addr);
fafd8bce
BS		 558 break;
559 case 2:
fe8d8f0f 560 ret = cpu_lduw_user(env, addr);
fafd8bce
BS		 561 break;
562 default:
563 case 4:
fe8d8f0f 564 ret = cpu_ldl_user(env, addr);
fafd8bce
BS		 565 break;
566 case 8:
fe8d8f0f 567 ret = cpu_ldq_user(env, addr);
fafd8bce
BS		 568 break;
569 }
570 break;
0cc1f4bf
RH		 571 case ASI_KERNELDATA: /* Supervisor data access */
572 case ASI_P: /* Implicit primary context data access (v9 only?) */
fafd8bce
BS		 573 switch (size) {
574 case 1:
fe8d8f0f 575 ret = cpu_ldub_kernel(env, addr);
fafd8bce
BS		 576 break;
577 case 2:
fe8d8f0f 578 ret = cpu_lduw_kernel(env, addr);
fafd8bce
BS		 579 break;
580 default:
581 case 4:
fe8d8f0f 582 ret = cpu_ldl_kernel(env, addr);
fafd8bce
BS		 583 break;
584 case 8:
fe8d8f0f 585 ret = cpu_ldq_kernel(env, addr);
fafd8bce
BS		 586 break;
587 }
588 break;
0cc1f4bf
RH		 589 case ASI_M_TXTC_TAG: /* SparcStation 5 I-cache tag */
590 case ASI_M_TXTC_DATA: /* SparcStation 5 I-cache data */
591 case ASI_M_DATAC_TAG: /* SparcStation 5 D-cache tag */
592 case ASI_M_DATAC_DATA: /* SparcStation 5 D-cache data */
fafd8bce 593 break;
0cc1f4bf
RH		 594 case ASI_M_BYPASS: /* MMU passthrough */
595 case ASI_LEON_BYPASS: /* LEON MMU passthrough */
fafd8bce
BS		 596 switch (size) {
597 case 1:
2c17449b 598 ret = ldub_phys(cs->as, addr);
fafd8bce
BS		 599 break;
600 case 2:
41701aa4 601 ret = lduw_phys(cs->as, addr);
fafd8bce
BS		 602 break;
603 default:
604 case 4:
fdfba1a2 605 ret = ldl_phys(cs->as, addr);
fafd8bce
BS		 606 break;
607 case 8:
2c17449b 608 ret = ldq_phys(cs->as, addr);
fafd8bce
BS		 609 break;
610 }
611 break;
612 case 0x21 ... 0x2f: /* MMU passthrough, 0x100000000 to 0xfffffffff */
613 switch (size) {
614 case 1:
2c17449b 615 ret = ldub_phys(cs->as, (hwaddr)addr
a8170e5e 616 | ((hwaddr)(asi & 0xf) << 32));
fafd8bce
BS		 617 break;
618 case 2:
41701aa4 619 ret = lduw_phys(cs->as, (hwaddr)addr
a8170e5e 620 | ((hwaddr)(asi & 0xf) << 32));
fafd8bce
BS		 621 break;
622 default:
623 case 4:
fdfba1a2 624 ret = ldl_phys(cs->as, (hwaddr)addr
a8170e5e 625 | ((hwaddr)(asi & 0xf) << 32));
fafd8bce
BS		 626 break;
627 case 8:
2c17449b 628 ret = ldq_phys(cs->as, (hwaddr)addr
a8170e5e 629 | ((hwaddr)(asi & 0xf) << 32));
fafd8bce
BS		 630 break;
631 }
632 break;
633 case 0x30: /* Turbosparc secondary cache diagnostic */
634 case 0x31: /* Turbosparc RAM snoop */
635 case 0x32: /* Turbosparc page table descriptor diagnostic */
636 case 0x39: /* data cache diagnostic register */
637 ret = 0;
638 break;
639 case 0x38: /* SuperSPARC MMU Breakpoint Control Registers */
640 {
641 int reg = (addr >> 8) & 3;
642
643 switch (reg) {
644 case 0: /* Breakpoint Value (Addr) */
645 ret = env->mmubpregs[reg];
646 break;
647 case 1: /* Breakpoint Mask */
648 ret = env->mmubpregs[reg];
649 break;
650 case 2: /* Breakpoint Control */
651 ret = env->mmubpregs[reg];
652 break;
653 case 3: /* Breakpoint Status */
654 ret = env->mmubpregs[reg];
655 env->mmubpregs[reg] = 0ULL;
656 break;
657 }
658 DPRINTF_MMU("read breakpoint reg[%d] 0x%016" PRIx64 "\n", reg,
659 ret);
660 }
661 break;
662 case 0x49: /* SuperSPARC MMU Counter Breakpoint Value */
663 ret = env->mmubpctrv;
664 break;
665 case 0x4a: /* SuperSPARC MMU Counter Breakpoint Control */
666 ret = env->mmubpctrc;
667 break;
668 case 0x4b: /* SuperSPARC MMU Counter Breakpoint Status */
669 ret = env->mmubpctrs;
670 break;
671 case 0x4c: /* SuperSPARC MMU Breakpoint Action */
672 ret = env->mmubpaction;
673 break;
0cc1f4bf 674 case ASI_USERTXT: /* User code access, XXX */
fafd8bce 675 default:
2fad1112 676 cpu_unassigned_access(cs, addr, false, false, asi, size);
fafd8bce
BS		 677 ret = 0;
678 break;
679 }
680 if (sign) {
681 switch (size) {
682 case 1:
683 ret = (int8_t) ret;
684 break;
685 case 2:
686 ret = (int16_t) ret;
687 break;
688 case 4:
689 ret = (int32_t) ret;
690 break;
691 default:
692 break;
693 }
694 }
695#ifdef DEBUG_ASI
696 dump_asi("read ", last_addr, asi, size, ret);
697#endif
698 return ret;
699}
700
fe8d8f0f
BS		 701void helper_st_asi(CPUSPARCState *env, target_ulong addr, uint64_t val, int asi,
702 int size)
fafd8bce 703{
31b030d4
AF		 704 SPARCCPU *cpu = sparc_env_get_cpu(env);
705 CPUState *cs = CPU(cpu);
706
fe8d8f0f 707 helper_check_align(env, addr, size - 1);
fafd8bce 708 switch (asi) {
0cc1f4bf
RH		 709 case ASI_M_MXCC: /* SuperSparc MXCC registers, or... */
710 /* case ASI_LEON_CACHEREGS: Leon3 cache control */
fafd8bce
BS		 711 switch (addr) {
712 case 0x00: /* Leon3 Cache Control */
713 case 0x08: /* Leon3 Instruction Cache config */
714 case 0x0C: /* Leon3 Date Cache config */
715 if (env->def->features & CPU_FEATURE_CACHE_CTRL) {
fe8d8f0f 716 leon3_cache_control_st(env, addr, val, size);
fafd8bce
BS		 717 }
718 break;
719
720 case 0x01c00000: /* MXCC stream data register 0 */
721 if (size == 8) {
722 env->mxccdata[0] = val;
723 } else {
71547a3b
BS		 724 qemu_log_mask(LOG_UNIMP,
725 "%08x: unimplemented access size: %d\n", addr,
726 size);
fafd8bce
BS		 727 }
728 break;
729 case 0x01c00008: /* MXCC stream data register 1 */
730 if (size == 8) {
731 env->mxccdata[1] = val;
732 } else {
71547a3b
BS		 733 qemu_log_mask(LOG_UNIMP,
734 "%08x: unimplemented access size: %d\n", addr,
735 size);
fafd8bce
BS		 736 }
737 break;
738 case 0x01c00010: /* MXCC stream data register 2 */
739 if (size == 8) {
740 env->mxccdata[2] = val;
741 } else {
71547a3b
BS		 742 qemu_log_mask(LOG_UNIMP,
743 "%08x: unimplemented access size: %d\n", addr,
744 size);
fafd8bce
BS		 745 }
746 break;
747 case 0x01c00018: /* MXCC stream data register 3 */
748 if (size == 8) {
749 env->mxccdata[3] = val;
750 } else {
71547a3b
BS		 751 qemu_log_mask(LOG_UNIMP,
752 "%08x: unimplemented access size: %d\n", addr,
753 size);
fafd8bce
BS		 754 }
755 break;
756 case 0x01c00100: /* MXCC stream source */
757 if (size == 8) {
758 env->mxccregs[0] = val;
759 } else {
71547a3b
BS		 760 qemu_log_mask(LOG_UNIMP,
761 "%08x: unimplemented access size: %d\n", addr,
762 size);
fafd8bce 763 }
2c17449b
EI		 764 env->mxccdata[0] = ldq_phys(cs->as,
765 (env->mxccregs[0] & 0xffffffffULL) +
fafd8bce 766 0);
2c17449b
EI		 767 env->mxccdata[1] = ldq_phys(cs->as,
768 (env->mxccregs[0] & 0xffffffffULL) +
fafd8bce 769 8);
2c17449b
EI		 770 env->mxccdata[2] = ldq_phys(cs->as,
771 (env->mxccregs[0] & 0xffffffffULL) +
fafd8bce 772 16);
2c17449b
EI		 773 env->mxccdata[3] = ldq_phys(cs->as,
774 (env->mxccregs[0] & 0xffffffffULL) +
fafd8bce
BS		 775 24);
776 break;
777 case 0x01c00200: /* MXCC stream destination */
778 if (size == 8) {
779 env->mxccregs[1] = val;
780 } else {
71547a3b
BS		 781 qemu_log_mask(LOG_UNIMP,
782 "%08x: unimplemented access size: %d\n", addr,
783 size);
fafd8bce 784 }
f606604f 785 stq_phys(cs->as, (env->mxccregs[1] & 0xffffffffULL) + 0,
fafd8bce 786 env->mxccdata[0]);
f606604f 787 stq_phys(cs->as, (env->mxccregs[1] & 0xffffffffULL) + 8,
fafd8bce 788 env->mxccdata[1]);
f606604f 789 stq_phys(cs->as, (env->mxccregs[1] & 0xffffffffULL) + 16,
fafd8bce 790 env->mxccdata[2]);
f606604f 791 stq_phys(cs->as, (env->mxccregs[1] & 0xffffffffULL) + 24,
fafd8bce
BS		 792 env->mxccdata[3]);
793 break;
794 case 0x01c00a00: /* MXCC control register */
795 if (size == 8) {
796 env->mxccregs[3] = val;
797 } else {
71547a3b
BS		 798 qemu_log_mask(LOG_UNIMP,
799 "%08x: unimplemented access size: %d\n", addr,
800 size);
fafd8bce
BS		 801 }
802 break;
803 case 0x01c00a04: /* MXCC control register */
804 if (size == 4) {
805 env->mxccregs[3] = (env->mxccregs[3] & 0xffffffff00000000ULL)
806 | val;
807 } else {
71547a3b
BS		 808 qemu_log_mask(LOG_UNIMP,
809 "%08x: unimplemented access size: %d\n", addr,
810 size);
fafd8bce
BS		 811 }
812 break;
813 case 0x01c00e00: /* MXCC error register */
814 /* writing a 1 bit clears the error */
815 if (size == 8) {
816 env->mxccregs[6] &= ~val;
817 } else {
71547a3b
BS		 818 qemu_log_mask(LOG_UNIMP,
819 "%08x: unimplemented access size: %d\n", addr,
820 size);
fafd8bce
BS		 821 }
822 break;
823 case 0x01c00f00: /* MBus port address register */
824 if (size == 8) {
825 env->mxccregs[7] = val;
826 } else {
71547a3b
BS		 827 qemu_log_mask(LOG_UNIMP,
828 "%08x: unimplemented access size: %d\n", addr,
829 size);
fafd8bce
BS		 830 }
831 break;
832 default:
71547a3b
BS		 833 qemu_log_mask(LOG_UNIMP,
834 "%08x: unimplemented address, size: %d\n", addr,
835 size);
fafd8bce
BS		 836 break;
837 }
838 DPRINTF_MXCC("asi = %d, size = %d, addr = %08x, val = %" PRIx64 "\n",
839 asi, size, addr, val);
840#ifdef DEBUG_MXCC
841 dump_mxcc(env);
842#endif
843 break;
0cc1f4bf
RH		 844 case ASI_M_FLUSH_PROBE: /* SuperSparc MMU flush */
845 case ASI_LEON_MMUFLUSH: /* LEON3 MMU flush */
fafd8bce
BS		 846 {
847 int mmulev;
848
849 mmulev = (addr >> 8) & 15;
850 DPRINTF_MMU("mmu flush level %d\n", mmulev);
851 switch (mmulev) {
852 case 0: /* flush page */
31b030d4 853 tlb_flush_page(CPU(cpu), addr & 0xfffff000);
fafd8bce
BS		 854 break;
855 case 1: /* flush segment (256k) */
856 case 2: /* flush region (16M) */
857 case 3: /* flush context (4G) */
858 case 4: /* flush entire */
00c8cb0a 859 tlb_flush(CPU(cpu), 1);
fafd8bce
BS		 860 break;
861 default:
862 break;
863 }
864#ifdef DEBUG_MMU
865 dump_mmu(stdout, fprintf, env);
866#endif
867 }
868 break;
0cc1f4bf
RH		 869 case ASI_M_MMUREGS: /* write MMU regs */
870 case ASI_LEON_MMUREGS: /* LEON3 write MMU regs */
fafd8bce
BS		 871 {
872 int reg = (addr >> 8) & 0x1f;
873 uint32_t oldreg;
874
875 oldreg = env->mmuregs[reg];
876 switch (reg) {
877 case 0: /* Control Register */
878 env->mmuregs[reg] = (env->mmuregs[reg] & 0xff000000) |
879 (val & 0x00ffffff);
880 /* Mappings generated during no-fault mode or MMU
881 disabled mode are invalid in normal mode */
882 if ((oldreg & (MMU_E | MMU_NF | env->def->mmu_bm)) !=
883 (env->mmuregs[reg] & (MMU_E | MMU_NF | env->def->mmu_bm))) {
00c8cb0a 884 tlb_flush(CPU(cpu), 1);
fafd8bce
BS		 885 }
886 break;
887 case 1: /* Context Table Pointer Register */
888 env->mmuregs[reg] = val & env->def->mmu_ctpr_mask;
889 break;
890 case 2: /* Context Register */
891 env->mmuregs[reg] = val & env->def->mmu_cxr_mask;
892 if (oldreg != env->mmuregs[reg]) {
893 /* we flush when the MMU context changes because
894 QEMU has no MMU context support */
00c8cb0a 895 tlb_flush(CPU(cpu), 1);
fafd8bce
BS		 896 }
897 break;
898 case 3: /* Synchronous Fault Status Register with Clear */
899 case 4: /* Synchronous Fault Address Register */
900 break;
901 case 0x10: /* TLB Replacement Control Register */
902 env->mmuregs[reg] = val & env->def->mmu_trcr_mask;
903 break;
904 case 0x13: /* Synchronous Fault Status Register with Read
905 and Clear */
906 env->mmuregs[3] = val & env->def->mmu_sfsr_mask;
907 break;
908 case 0x14: /* Synchronous Fault Address Register */
909 env->mmuregs[4] = val;
910 break;
911 default:
912 env->mmuregs[reg] = val;
913 break;
914 }
915 if (oldreg != env->mmuregs[reg]) {
916 DPRINTF_MMU("mmu change reg[%d]: 0x%08x -> 0x%08x\n",
917 reg, oldreg, env->mmuregs[reg]);
918 }
919#ifdef DEBUG_MMU
920 dump_mmu(stdout, fprintf, env);
921#endif
922 }
923 break;
0cc1f4bf
RH		 924 case ASI_M_TLBDIAG: /* Turbosparc ITLB Diagnostic */
925 case ASI_M_DIAGS: /* Turbosparc DTLB Diagnostic */
926 case ASI_M_IODIAG: /* Turbosparc IOTLB Diagnostic */
fafd8bce 927 break;
0cc1f4bf 928 case ASI_USERDATA: /* User data access */
fafd8bce
BS		 929 switch (size) {
930 case 1:
fe8d8f0f 931 cpu_stb_user(env, addr, val);
fafd8bce
BS		 932 break;
933 case 2:
fe8d8f0f 934 cpu_stw_user(env, addr, val);
fafd8bce
BS		 935 break;
936 default:
937 case 4:
fe8d8f0f 938 cpu_stl_user(env, addr, val);
fafd8bce
BS		 939 break;
940 case 8:
fe8d8f0f 941 cpu_stq_user(env, addr, val);
fafd8bce
BS		 942 break;
943 }
944 break;
0cc1f4bf
RH		 945 case ASI_KERNELDATA: /* Supervisor data access */
946 case ASI_P:
fafd8bce
BS		 947 switch (size) {
948 case 1:
fe8d8f0f 949 cpu_stb_kernel(env, addr, val);
fafd8bce
BS		 950 break;
951 case 2:
fe8d8f0f 952 cpu_stw_kernel(env, addr, val);
fafd8bce
BS		 953 break;
954 default:
955 case 4:
fe8d8f0f 956 cpu_stl_kernel(env, addr, val);
fafd8bce
BS		 957 break;
958 case 8:
fe8d8f0f 959 cpu_stq_kernel(env, addr, val);
fafd8bce
BS		 960 break;
961 }
962 break;
0cc1f4bf
RH		 963 case ASI_M_TXTC_TAG: /* I-cache tag */
964 case ASI_M_TXTC_DATA: /* I-cache data */
965 case ASI_M_DATAC_TAG: /* D-cache tag */
966 case ASI_M_DATAC_DATA: /* D-cache data */
967 case ASI_M_FLUSH_PAGE: /* I/D-cache flush page */
968 case ASI_M_FLUSH_SEG: /* I/D-cache flush segment */
969 case ASI_M_FLUSH_REGION: /* I/D-cache flush region */
970 case ASI_M_FLUSH_CTX: /* I/D-cache flush context */
971 case ASI_M_FLUSH_USER: /* I/D-cache flush user */
fafd8bce 972 break;
0cc1f4bf 973 case ASI_M_BCOPY: /* Block copy, sta access */
fafd8bce
BS		 974 {
975 /* val = src
976 addr = dst
977 copy 32 bytes */
978 unsigned int i;
979 uint32_t src = val & ~3, dst = addr & ~3, temp;
980
981 for (i = 0; i < 32; i += 4, src += 4, dst += 4) {
fe8d8f0f
BS		 982 temp = cpu_ldl_kernel(env, src);
983 cpu_stl_kernel(env, dst, temp);
fafd8bce
BS		 984 }
985 }
986 break;
0cc1f4bf 987 case ASI_M_BFILL: /* Block fill, stda access */
fafd8bce
BS		 988 {
989 /* addr = dst
990 fill 32 bytes with val */
991 unsigned int i;
992 uint32_t dst = addr & 7;
993
994 for (i = 0; i < 32; i += 8, dst += 8) {
fe8d8f0f 995 cpu_stq_kernel(env, dst, val);
fafd8bce
BS		 996 }
997 }
998 break;
0cc1f4bf
RH		 999 case ASI_M_BYPASS: /* MMU passthrough */
1000 case ASI_LEON_BYPASS: /* LEON MMU passthrough */
fafd8bce
BS		 1001 {
1002 switch (size) {
1003 case 1:
db3be60d 1004 stb_phys(cs->as, addr, val);
fafd8bce
BS		 1005 break;
1006 case 2:
5ce5944d 1007 stw_phys(cs->as, addr, val);
fafd8bce
BS		 1008 break;
1009 case 4:
1010 default:
ab1da857 1011 stl_phys(cs->as, addr, val);
fafd8bce
BS		 1012 break;
1013 case 8:
f606604f 1014 stq_phys(cs->as, addr, val);
fafd8bce
BS		 1015 break;
1016 }
1017 }
1018 break;
1019 case 0x21 ... 0x2f: /* MMU passthrough, 0x100000000 to 0xfffffffff */
1020 {
1021 switch (size) {
1022 case 1:
db3be60d 1023 stb_phys(cs->as, (hwaddr)addr
a8170e5e 1024 | ((hwaddr)(asi & 0xf) << 32), val);
fafd8bce
BS		 1025 break;
1026 case 2:
5ce5944d 1027 stw_phys(cs->as, (hwaddr)addr
a8170e5e 1028 | ((hwaddr)(asi & 0xf) << 32), val);
fafd8bce
BS		 1029 break;
1030 case 4:
1031 default:
ab1da857 1032 stl_phys(cs->as, (hwaddr)addr
a8170e5e 1033 | ((hwaddr)(asi & 0xf) << 32), val);
fafd8bce
BS		 1034 break;
1035 case 8:
f606604f 1036 stq_phys(cs->as, (hwaddr)addr
a8170e5e 1037 | ((hwaddr)(asi & 0xf) << 32), val);
fafd8bce
BS		 1038 break;
1039 }
1040 }
1041 break;
1042 case 0x30: /* store buffer tags or Turbosparc secondary cache diagnostic */
1043 case 0x31: /* store buffer data, Ross RT620 I-cache flush or
1044 Turbosparc snoop RAM */
1045 case 0x32: /* store buffer control or Turbosparc page table
1046 descriptor diagnostic */
1047 case 0x36: /* I-cache flash clear */
1048 case 0x37: /* D-cache flash clear */
1049 break;
1050 case 0x38: /* SuperSPARC MMU Breakpoint Control Registers*/
1051 {
1052 int reg = (addr >> 8) & 3;
1053
1054 switch (reg) {
1055 case 0: /* Breakpoint Value (Addr) */
1056 env->mmubpregs[reg] = (val & 0xfffffffffULL);
1057 break;
1058 case 1: /* Breakpoint Mask */
1059 env->mmubpregs[reg] = (val & 0xfffffffffULL);
1060 break;
1061 case 2: /* Breakpoint Control */
1062 env->mmubpregs[reg] = (val & 0x7fULL);
1063 break;
1064 case 3: /* Breakpoint Status */
1065 env->mmubpregs[reg] = (val & 0xfULL);
1066 break;
1067 }
1068 DPRINTF_MMU("write breakpoint reg[%d] 0x%016x\n", reg,
1069 env->mmuregs[reg]);
1070 }
1071 break;
1072 case 0x49: /* SuperSPARC MMU Counter Breakpoint Value */
1073 env->mmubpctrv = val & 0xffffffff;
1074 break;
1075 case 0x4a: /* SuperSPARC MMU Counter Breakpoint Control */
1076 env->mmubpctrc = val & 0x3;
1077 break;
1078 case 0x4b: /* SuperSPARC MMU Counter Breakpoint Status */
1079 env->mmubpctrs = val & 0x3;
1080 break;
1081 case 0x4c: /* SuperSPARC MMU Breakpoint Action */
1082 env->mmubpaction = val & 0x1fff;
1083 break;
0cc1f4bf
RH		 1084 case ASI_USERTXT: /* User code access, XXX */
1085 case ASI_KERNELTXT: /* Supervisor code access, XXX */
fafd8bce 1086 default:
c658b94f
AF		 1087 cpu_unassigned_access(CPU(sparc_env_get_cpu(env)),
1088 addr, true, false, asi, size);
fafd8bce
BS		 1089 break;
1090 }
1091#ifdef DEBUG_ASI
1092 dump_asi("write", addr, asi, size, val);
1093#endif
1094}
1095
1096#endif /* CONFIG_USER_ONLY */
1097#else /* TARGET_SPARC64 */
1098
1099#ifdef CONFIG_USER_ONLY
fe8d8f0f
BS		 1100uint64_t helper_ld_asi(CPUSPARCState *env, target_ulong addr, int asi, int size,
1101 int sign)
fafd8bce
BS		 1102{
1103 uint64_t ret = 0;
1104#if defined(DEBUG_ASI)
1105 target_ulong last_addr = addr;
1106#endif
1107
1108 if (asi < 0x80) {
1109 helper_raise_exception(env, TT_PRIV_ACT);
1110 }
1111
fe8d8f0f 1112 helper_check_align(env, addr, size - 1);
fafd8bce
BS		 1113 addr = asi_address_mask(env, asi, addr);
1114
1115 switch (asi) {
0cc1f4bf
RH		 1116 case ASI_PNF: /* Primary no-fault */
1117 case ASI_PNFL: /* Primary no-fault LE */
fafd8bce
BS		 1118 if (page_check_range(addr, size, PAGE_READ) == -1) {
1119#ifdef DEBUG_ASI
1120 dump_asi("read ", last_addr, asi, size, ret);
1121#endif
1122 return 0;
1123 }
1124 /* Fall through */
0cc1f4bf
RH		 1125 case ASI_P: /* Primary */
1126 case ASI_PL: /* Primary LE */
fafd8bce
BS		 1127 {
1128 switch (size) {
1129 case 1:
eb513f82 1130 ret = cpu_ldub_data(env, addr);
fafd8bce
BS		 1131 break;
1132 case 2:
eb513f82 1133 ret = cpu_lduw_data(env, addr);
fafd8bce
BS		 1134 break;
1135 case 4:
eb513f82 1136 ret = cpu_ldl_data(env, addr);
fafd8bce
BS		 1137 break;
1138 default:
1139 case 8:
eb513f82 1140 ret = cpu_ldq_data(env, addr);
fafd8bce
BS		 1141 break;
1142 }
1143 }
1144 break;
0cc1f4bf
RH		 1145 case ASI_SNF: /* Secondary no-fault */
1146 case ASI_SNFL: /* Secondary no-fault LE */
fafd8bce
BS		 1147 if (page_check_range(addr, size, PAGE_READ) == -1) {
1148#ifdef DEBUG_ASI
1149 dump_asi("read ", last_addr, asi, size, ret);
1150#endif
1151 return 0;
1152 }
1153 /* Fall through */
0cc1f4bf
RH		 1154 case ASI_S: /* Secondary */
1155 case ASI_SL: /* Secondary LE */
fafd8bce
BS		 1156 /* XXX */
1157 break;
1158 default:
1159 break;
1160 }
1161
1162 /* Convert from little endian */
1163 switch (asi) {
0cc1f4bf
RH		 1164 case ASI_PL: /* Primary LE */
1165 case ASI_SL: /* Secondary LE */
1166 case ASI_PNFL: /* Primary no-fault LE */
1167 case ASI_SNFL: /* Secondary no-fault LE */
fafd8bce
BS		 1168 switch (size) {
1169 case 2:
1170 ret = bswap16(ret);
1171 break;
1172 case 4:
1173 ret = bswap32(ret);
1174 break;
1175 case 8:
1176 ret = bswap64(ret);
1177 break;
1178 default:
1179 break;
1180 }
1181 default:
1182 break;
1183 }
1184
1185 /* Convert to signed number */
1186 if (sign) {
1187 switch (size) {
1188 case 1:
1189 ret = (int8_t) ret;
1190 break;
1191 case 2:
1192 ret = (int16_t) ret;
1193 break;
1194 case 4:
1195 ret = (int32_t) ret;
1196 break;
1197 default:
1198 break;
1199 }
1200 }
1201#ifdef DEBUG_ASI
1202 dump_asi("read ", last_addr, asi, size, ret);
1203#endif
1204 return ret;
1205}
1206
fe8d8f0f
BS		 1207void helper_st_asi(CPUSPARCState *env, target_ulong addr, target_ulong val,
1208 int asi, int size)
fafd8bce
BS		 1209{
1210#ifdef DEBUG_ASI
1211 dump_asi("write", addr, asi, size, val);
1212#endif
1213 if (asi < 0x80) {
1214 helper_raise_exception(env, TT_PRIV_ACT);
1215 }
1216
fe8d8f0f 1217 helper_check_align(env, addr, size - 1);
fafd8bce
BS		 1218 addr = asi_address_mask(env, asi, addr);
1219
1220 /* Convert to little endian */
1221 switch (asi) {
0cc1f4bf
RH		 1222 case ASI_PL: /* Primary LE */
1223 case ASI_SL: /* Secondary LE */
fafd8bce
BS		 1224 switch (size) {
1225 case 2:
1226 val = bswap16(val);
1227 break;
1228 case 4:
1229 val = bswap32(val);
1230 break;
1231 case 8:
1232 val = bswap64(val);
1233 break;
1234 default:
1235 break;
1236 }
1237 default:
1238 break;
1239 }
1240
1241 switch (asi) {
0cc1f4bf
RH		 1242 case ASI_P: /* Primary */
1243 case ASI_PL: /* Primary LE */
fafd8bce
BS		 1244 {
1245 switch (size) {
1246 case 1:
eb513f82 1247 cpu_stb_data(env, addr, val);
fafd8bce
BS		 1248 break;
1249 case 2:
eb513f82 1250 cpu_stw_data(env, addr, val);
fafd8bce
BS		 1251 break;
1252 case 4:
eb513f82 1253 cpu_stl_data(env, addr, val);
fafd8bce
BS		 1254 break;
1255 case 8:
1256 default:
eb513f82 1257 cpu_stq_data(env, addr, val);
fafd8bce
BS		 1258 break;
1259 }
1260 }
1261 break;
0cc1f4bf
RH		 1262 case ASI_S: /* Secondary */
1263 case ASI_SL: /* Secondary LE */
fafd8bce
BS		 1264 /* XXX */
1265 return;
1266
0cc1f4bf
RH		 1267 case ASI_PNF: /* Primary no-fault, RO */
1268 case ASI_SNF: /* Secondary no-fault, RO */
1269 case ASI_PNFL: /* Primary no-fault LE, RO */
1270 case ASI_SNFL: /* Secondary no-fault LE, RO */
fafd8bce 1271 default:
fe8d8f0f 1272 helper_raise_exception(env, TT_DATA_ACCESS);
fafd8bce
BS		 1273 return;
1274 }
1275}
1276
1277#else /* CONFIG_USER_ONLY */
1278
fe8d8f0f
BS		 1279uint64_t helper_ld_asi(CPUSPARCState *env, target_ulong addr, int asi, int size,
1280 int sign)
fafd8bce 1281{
2fad1112 1282 CPUState *cs = CPU(sparc_env_get_cpu(env));
fafd8bce
BS		 1283 uint64_t ret = 0;
1284#if defined(DEBUG_ASI)
1285 target_ulong last_addr = addr;
1286#endif
1287
1288 asi &= 0xff;
1289
1290 if ((asi < 0x80 && (env->pstate & PS_PRIV) == 0)
1291 || (cpu_has_hypervisor(env)
1292 && asi >= 0x30 && asi < 0x80
1293 && !(env->hpstate & HS_PRIV))) {
1294 helper_raise_exception(env, TT_PRIV_ACT);
1295 }
1296
fe8d8f0f 1297 helper_check_align(env, addr, size - 1);
fafd8bce
BS		 1298 addr = asi_address_mask(env, asi, addr);
1299
1300 /* process nonfaulting loads first */
1301 if ((asi & 0xf6) == 0x82) {
1302 int mmu_idx;
1303
1304 /* secondary space access has lowest asi bit equal to 1 */
1305 if (env->pstate & PS_PRIV) {
1306 mmu_idx = (asi & 1) ? MMU_KERNEL_SECONDARY_IDX : MMU_KERNEL_IDX;
1307 } else {
1308 mmu_idx = (asi & 1) ? MMU_USER_SECONDARY_IDX : MMU_USER_IDX;
1309 }
1310
1311 if (cpu_get_phys_page_nofault(env, addr, mmu_idx) == -1ULL) {
1312#ifdef DEBUG_ASI
1313 dump_asi("read ", last_addr, asi, size, ret);
1314#endif
1315 /* env->exception_index is set in get_physical_address_data(). */
27103424 1316 helper_raise_exception(env, cs->exception_index);
fafd8bce
BS		 1317 }
1318
1319 /* convert nonfaulting load ASIs to normal load ASIs */
1320 asi &= ~0x02;
1321 }
1322
1323 switch (asi) {
0cc1f4bf
RH		 1324 case ASI_AIUP: /* As if user primary */
1325 case ASI_AIUS: /* As if user secondary */
1326 case ASI_AIUPL: /* As if user primary LE */
1327 case ASI_AIUSL: /* As if user secondary LE */
1328 case ASI_P: /* Primary */
1329 case ASI_S: /* Secondary */
1330 case ASI_PL: /* Primary LE */
1331 case ASI_SL: /* Secondary LE */
1332 case ASI_BLK_INIT_QUAD_LDD_P: /* UA2007 Primary block init */
1333 case ASI_BLK_INIT_QUAD_LDD_S: /* UA2007 Secondary block init */
fafd8bce
BS		 1334 if ((asi & 0x80) && (env->pstate & PS_PRIV)) {
1335 if (cpu_hypervisor_mode(env)) {
1336 switch (size) {
1337 case 1:
fe8d8f0f 1338 ret = cpu_ldub_hypv(env, addr);
fafd8bce
BS		 1339 break;
1340 case 2:
fe8d8f0f 1341 ret = cpu_lduw_hypv(env, addr);
fafd8bce
BS		 1342 break;
1343 case 4:
fe8d8f0f 1344 ret = cpu_ldl_hypv(env, addr);
fafd8bce
BS		 1345 break;
1346 default:
1347 case 8:
fe8d8f0f 1348 ret = cpu_ldq_hypv(env, addr);
fafd8bce
BS		 1349 break;
1350 }
1351 } else {
1352 /* secondary space access has lowest asi bit equal to 1 */
1353 if (asi & 1) {
1354 switch (size) {
1355 case 1:
fe8d8f0f 1356 ret = cpu_ldub_kernel_secondary(env, addr);
fafd8bce
BS		 1357 break;
1358 case 2:
fe8d8f0f 1359 ret = cpu_lduw_kernel_secondary(env, addr);
fafd8bce
BS		 1360 break;
1361 case 4:
fe8d8f0f 1362 ret = cpu_ldl_kernel_secondary(env, addr);
fafd8bce
BS		 1363 break;
1364 default:
1365 case 8:
fe8d8f0f 1366 ret = cpu_ldq_kernel_secondary(env, addr);
fafd8bce
BS		 1367 break;
1368 }
1369 } else {
1370 switch (size) {
1371 case 1:
fe8d8f0f 1372 ret = cpu_ldub_kernel(env, addr);
fafd8bce
BS		 1373 break;
1374 case 2:
fe8d8f0f 1375 ret = cpu_lduw_kernel(env, addr);
fafd8bce
BS		 1376 break;
1377 case 4:
fe8d8f0f 1378 ret = cpu_ldl_kernel(env, addr);
fafd8bce
BS		 1379 break;
1380 default:
1381 case 8:
fe8d8f0f 1382 ret = cpu_ldq_kernel(env, addr);
fafd8bce
BS		 1383 break;
1384 }
1385 }
1386 }
1387 } else {
1388 /* secondary space access has lowest asi bit equal to 1 */
1389 if (asi & 1) {
1390 switch (size) {
1391 case 1:
fe8d8f0f 1392 ret = cpu_ldub_user_secondary(env, addr);
fafd8bce
BS		 1393 break;
1394 case 2:
fe8d8f0f 1395 ret = cpu_lduw_user_secondary(env, addr);
fafd8bce
BS		 1396 break;
1397 case 4:
fe8d8f0f 1398 ret = cpu_ldl_user_secondary(env, addr);
fafd8bce
BS		 1399 break;
1400 default:
1401 case 8:
fe8d8f0f 1402 ret = cpu_ldq_user_secondary(env, addr);
fafd8bce
BS		 1403 break;
1404 }
1405 } else {
1406 switch (size) {
1407 case 1:
fe8d8f0f 1408 ret = cpu_ldub_user(env, addr);
fafd8bce
BS		 1409 break;
1410 case 2:
fe8d8f0f 1411 ret = cpu_lduw_user(env, addr);
fafd8bce
BS		 1412 break;
1413 case 4:
fe8d8f0f 1414 ret = cpu_ldl_user(env, addr);
fafd8bce
BS		 1415 break;
1416 default:
1417 case 8:
fe8d8f0f 1418 ret = cpu_ldq_user(env, addr);
fafd8bce
BS		 1419 break;
1420 }
1421 }
1422 }
1423 break;
0cc1f4bf
RH		 1424 case ASI_REAL: /* Bypass */
1425 case ASI_REAL_IO: /* Bypass, non-cacheable */
1426 case ASI_REAL_L: /* Bypass LE */
1427 case ASI_REAL_IO_L: /* Bypass, non-cacheable LE */
fafd8bce
BS		 1428 {
1429 switch (size) {
1430 case 1:
2c17449b 1431 ret = ldub_phys(cs->as, addr);
fafd8bce
BS		 1432 break;
1433 case 2:
41701aa4 1434 ret = lduw_phys(cs->as, addr);
fafd8bce
BS		 1435 break;
1436 case 4:
fdfba1a2 1437 ret = ldl_phys(cs->as, addr);
fafd8bce
BS		 1438 break;
1439 default:
1440 case 8:
2c17449b 1441 ret = ldq_phys(cs->as, addr);
fafd8bce
BS		 1442 break;
1443 }
1444 break;
1445 }
0cc1f4bf
RH		 1446 case ASI_NUCLEUS_QUAD_LDD: /* Nucleus quad LDD 128 bit atomic */
1447 case ASI_NUCLEUS_QUAD_LDD_L: /* Nucleus quad LDD 128 bit atomic LE */
1448 /* Only ldda allowed */
fafd8bce
BS		 1449 helper_raise_exception(env, TT_ILL_INSN);
1450 return 0;
0cc1f4bf
RH		 1451 case ASI_N: /* Nucleus */
1452 case ASI_NL: /* Nucleus Little Endian (LE) */
fafd8bce
BS		 1453 {
1454 switch (size) {
1455 case 1:
fe8d8f0f 1456 ret = cpu_ldub_nucleus(env, addr);
fafd8bce
BS		 1457 break;
1458 case 2:
fe8d8f0f 1459 ret = cpu_lduw_nucleus(env, addr);
fafd8bce
BS		 1460 break;
1461 case 4:
fe8d8f0f 1462 ret = cpu_ldl_nucleus(env, addr);
fafd8bce
BS		 1463 break;
1464 default:
1465 case 8:
fe8d8f0f 1466 ret = cpu_ldq_nucleus(env, addr);
fafd8bce
BS		 1467 break;
1468 }
1469 break;
1470 }
0cc1f4bf 1471 case ASI_UPA_CONFIG: /* UPA config */
fafd8bce
BS		 1472 /* XXX */
1473 break;
0cc1f4bf 1474 case ASI_LSU_CONTROL: /* LSU */
fafd8bce
BS		 1475 ret = env->lsu;
1476 break;
0cc1f4bf 1477 case ASI_IMMU: /* I-MMU regs */
fafd8bce
BS		 1478 {
1479 int reg = (addr >> 3) & 0xf;
1480
1481 if (reg == 0) {
1482 /* I-TSB Tag Target register */
1483 ret = ultrasparc_tag_target(env->immu.tag_access);
1484 } else {
1485 ret = env->immuregs[reg];
1486 }
1487
1488 break;
1489 }
0cc1f4bf 1490 case ASI_IMMU_TSB_8KB_PTR: /* I-MMU 8k TSB pointer */
fafd8bce
BS		 1491 {
1492 /* env->immuregs[5] holds I-MMU TSB register value
1493 env->immuregs[6] holds I-MMU Tag Access register value */
1494 ret = ultrasparc_tsb_pointer(env->immu.tsb, env->immu.tag_access,
1495 8*1024);
1496 break;
1497 }
0cc1f4bf 1498 case ASI_IMMU_TSB_64KB_PTR: /* I-MMU 64k TSB pointer */
fafd8bce
BS		 1499 {
1500 /* env->immuregs[5] holds I-MMU TSB register value
1501 env->immuregs[6] holds I-MMU Tag Access register value */
1502 ret = ultrasparc_tsb_pointer(env->immu.tsb, env->immu.tag_access,
1503 64*1024);
1504 break;
1505 }
0cc1f4bf 1506 case ASI_ITLB_DATA_ACCESS: /* I-MMU data access */
fafd8bce
BS		 1507 {
1508 int reg = (addr >> 3) & 0x3f;
1509
1510 ret = env->itlb[reg].tte;
1511 break;
1512 }
0cc1f4bf 1513 case ASI_ITLB_TAG_READ: /* I-MMU tag read */
fafd8bce
BS		 1514 {
1515 int reg = (addr >> 3) & 0x3f;
1516
1517 ret = env->itlb[reg].tag;
1518 break;
1519 }
0cc1f4bf 1520 case ASI_DMMU: /* D-MMU regs */
fafd8bce
BS		 1521 {
1522 int reg = (addr >> 3) & 0xf;
1523
1524 if (reg == 0) {
1525 /* D-TSB Tag Target register */
1526 ret = ultrasparc_tag_target(env->dmmu.tag_access);
1527 } else {
1528 ret = env->dmmuregs[reg];
1529 }
1530 break;
1531 }
0cc1f4bf 1532 case ASI_DMMU_TSB_8KB_PTR: /* D-MMU 8k TSB pointer */
fafd8bce
BS		 1533 {
1534 /* env->dmmuregs[5] holds D-MMU TSB register value
1535 env->dmmuregs[6] holds D-MMU Tag Access register value */
1536 ret = ultrasparc_tsb_pointer(env->dmmu.tsb, env->dmmu.tag_access,
1537 8*1024);
1538 break;
1539 }
0cc1f4bf 1540 case ASI_DMMU_TSB_64KB_PTR: /* D-MMU 64k TSB pointer */
fafd8bce
BS		 1541 {
1542 /* env->dmmuregs[5] holds D-MMU TSB register value
1543 env->dmmuregs[6] holds D-MMU Tag Access register value */
1544 ret = ultrasparc_tsb_pointer(env->dmmu.tsb, env->dmmu.tag_access,
1545 64*1024);
1546 break;
1547 }
0cc1f4bf 1548 case ASI_DTLB_DATA_ACCESS: /* D-MMU data access */
fafd8bce
BS		 1549 {
1550 int reg = (addr >> 3) & 0x3f;
1551
1552 ret = env->dtlb[reg].tte;
1553 break;
1554 }
0cc1f4bf 1555 case ASI_DTLB_TAG_READ: /* D-MMU tag read */
fafd8bce
BS		 1556 {
1557 int reg = (addr >> 3) & 0x3f;
1558
1559 ret = env->dtlb[reg].tag;
1560 break;
1561 }
0cc1f4bf 1562 case ASI_INTR_DISPATCH_STAT: /* Interrupt dispatch, RO */
361dea40 1563 break;
0cc1f4bf 1564 case ASI_INTR_RECEIVE: /* Interrupt data receive */
361dea40
BS		 1565 ret = env->ivec_status;
1566 break;
0cc1f4bf 1567 case ASI_INTR_R: /* Incoming interrupt vector, RO */
361dea40
BS		 1568 {
1569 int reg = (addr >> 4) & 0x3;
1570 if (reg < 3) {
1571 ret = env->ivec_data[reg];
1572 }
1573 break;
1574 }
0cc1f4bf
RH		 1575 case ASI_DCACHE_DATA: /* D-cache data */
1576 case ASI_DCACHE_TAG: /* D-cache tag access */
1577 case ASI_ESTATE_ERROR_EN: /* E-cache error enable */
1578 case ASI_AFSR: /* E-cache asynchronous fault status */
1579 case ASI_AFAR: /* E-cache asynchronous fault address */
1580 case ASI_EC_TAG_DATA: /* E-cache tag data */
1581 case ASI_IC_INSTR: /* I-cache instruction access */
1582 case ASI_IC_TAG: /* I-cache tag access */
1583 case ASI_IC_PRE_DECODE: /* I-cache predecode */
1584 case ASI_IC_NEXT_FIELD: /* I-cache LRU etc. */
1585 case ASI_EC_W: /* E-cache tag */
1586 case ASI_EC_R: /* E-cache tag */
1587 break;
1588 case ASI_DMMU_TSB_DIRECT_PTR: /* D-MMU data pointer */
1589 case ASI_ITLB_DATA_IN: /* I-MMU data in, WO */
1590 case ASI_IMMU_DEMAP: /* I-MMU demap, WO */
1591 case ASI_DTLB_DATA_IN: /* D-MMU data in, WO */
1592 case ASI_DMMU_DEMAP: /* D-MMU demap, WO */
1593 case ASI_INTR_W: /* Interrupt vector, WO */
fafd8bce 1594 default:
2fad1112 1595 cpu_unassigned_access(cs, addr, false, false, 1, size);
fafd8bce
BS		 1596 ret = 0;
1597 break;
1598 }
1599
1600 /* Convert from little endian */
1601 switch (asi) {
0cc1f4bf
RH		 1602 case ASI_NL: /* Nucleus Little Endian (LE) */
1603 case ASI_AIUPL: /* As if user primary LE */
1604 case ASI_AIUSL: /* As if user secondary LE */
1605 case ASI_REAL_L: /* Bypass LE */
1606 case ASI_REAL_IO_L: /* Bypass, non-cacheable LE */
1607 case ASI_PL: /* Primary LE */
1608 case ASI_SL: /* Secondary LE */
fafd8bce
BS		 1609 switch(size) {
1610 case 2:
1611 ret = bswap16(ret);
1612 break;
1613 case 4:
1614 ret = bswap32(ret);
1615 break;
1616 case 8:
1617 ret = bswap64(ret);
1618 break;
1619 default:
1620 break;
1621 }
1622 default:
1623 break;
1624 }
1625
1626 /* Convert to signed number */
1627 if (sign) {
1628 switch (size) {
1629 case 1:
1630 ret = (int8_t) ret;
1631 break;
1632 case 2:
1633 ret = (int16_t) ret;
1634 break;
1635 case 4:
1636 ret = (int32_t) ret;
1637 break;
1638 default:
1639 break;
1640 }
1641 }
1642#ifdef DEBUG_ASI
1643 dump_asi("read ", last_addr, asi, size, ret);
1644#endif
1645 return ret;
1646}
1647
fe8d8f0f
BS		 1648void helper_st_asi(CPUSPARCState *env, target_ulong addr, target_ulong val,
1649 int asi, int size)
fafd8bce 1650{
00c8cb0a
AF		 1651 SPARCCPU *cpu = sparc_env_get_cpu(env);
1652 CPUState *cs = CPU(cpu);
1653
fafd8bce
BS		 1654#ifdef DEBUG_ASI
1655 dump_asi("write", addr, asi, size, val);
1656#endif
1657
1658 asi &= 0xff;
1659
1660 if ((asi < 0x80 && (env->pstate & PS_PRIV) == 0)
1661 || (cpu_has_hypervisor(env)
1662 && asi >= 0x30 && asi < 0x80
1663 && !(env->hpstate & HS_PRIV))) {
1664 helper_raise_exception(env, TT_PRIV_ACT);
1665 }
1666
fe8d8f0f 1667 helper_check_align(env, addr, size - 1);
fafd8bce
BS		 1668 addr = asi_address_mask(env, asi, addr);
1669
1670 /* Convert to little endian */
1671 switch (asi) {
0cc1f4bf
RH		 1672 case ASI_NL: /* Nucleus Little Endian (LE) */
1673 case ASI_AIUPL: /* As if user primary LE */
1674 case ASI_AIUSL: /* As if user secondary LE */
1675 case ASI_REAL_L: /* Bypass LE */
1676 case ASI_REAL_IO_L: /* Bypass, non-cacheable LE */
1677 case ASI_PL: /* Primary LE */
1678 case ASI_SL: /* Secondary LE */
fafd8bce
BS		 1679 switch (size) {
1680 case 2:
1681 val = bswap16(val);
1682 break;
1683 case 4:
1684 val = bswap32(val);
1685 break;
1686 case 8:
1687 val = bswap64(val);
1688 break;
1689 default:
1690 break;
1691 }
1692 default:
1693 break;
1694 }
1695
1696 switch (asi) {
0cc1f4bf
RH		 1697 case ASI_AIUP: /* As if user primary */
1698 case ASI_AIUS: /* As if user secondary */
1699 case ASI_AIUPL: /* As if user primary LE */
1700 case ASI_AIUSL: /* As if user secondary LE */
1701 case ASI_P: /* Primary */
1702 case ASI_S: /* Secondary */
1703 case ASI_PL: /* Primary LE */
1704 case ASI_SL: /* Secondary LE */
1705 case ASI_BLK_INIT_QUAD_LDD_P: /* UA2007 Primary block init */
1706 case ASI_BLK_INIT_QUAD_LDD_S: /* UA2007 Secondary block init */
fafd8bce
BS		 1707 if ((asi & 0x80) && (env->pstate & PS_PRIV)) {
1708 if (cpu_hypervisor_mode(env)) {
1709 switch (size) {
1710 case 1:
fe8d8f0f 1711 cpu_stb_hypv(env, addr, val);
fafd8bce
BS		 1712 break;
1713 case 2:
fe8d8f0f 1714 cpu_stw_hypv(env, addr, val);
fafd8bce
BS		 1715 break;
1716 case 4:
fe8d8f0f 1717 cpu_stl_hypv(env, addr, val);
fafd8bce
BS		 1718 break;
1719 case 8:
1720 default:
fe8d8f0f 1721 cpu_stq_hypv(env, addr, val);
fafd8bce
BS		 1722 break;
1723 }
1724 } else {
1725 /* secondary space access has lowest asi bit equal to 1 */
1726 if (asi & 1) {
1727 switch (size) {
1728 case 1:
fe8d8f0f 1729 cpu_stb_kernel_secondary(env, addr, val);
fafd8bce
BS		 1730 break;
1731 case 2:
fe8d8f0f 1732 cpu_stw_kernel_secondary(env, addr, val);
fafd8bce
BS		 1733 break;
1734 case 4:
fe8d8f0f 1735 cpu_stl_kernel_secondary(env, addr, val);
fafd8bce
BS		 1736 break;
1737 case 8:
1738 default:
fe8d8f0f 1739 cpu_stq_kernel_secondary(env, addr, val);
fafd8bce
BS		 1740 break;
1741 }
1742 } else {
1743 switch (size) {
1744 case 1:
fe8d8f0f 1745 cpu_stb_kernel(env, addr, val);
fafd8bce
BS		 1746 break;
1747 case 2:
fe8d8f0f 1748 cpu_stw_kernel(env, addr, val);
fafd8bce
BS		 1749 break;
1750 case 4:
fe8d8f0f 1751 cpu_stl_kernel(env, addr, val);
fafd8bce
BS		 1752 break;
1753 case 8:
1754 default:
fe8d8f0f 1755 cpu_stq_kernel(env, addr, val);
fafd8bce
BS		 1756 break;
1757 }
1758 }
1759 }
1760 } else {
1761 /* secondary space access has lowest asi bit equal to 1 */
1762 if (asi & 1) {
1763 switch (size) {
1764 case 1:
fe8d8f0f 1765 cpu_stb_user_secondary(env, addr, val);
fafd8bce
BS		 1766 break;
1767 case 2:
fe8d8f0f 1768 cpu_stw_user_secondary(env, addr, val);
fafd8bce
BS		 1769 break;
1770 case 4:
fe8d8f0f 1771 cpu_stl_user_secondary(env, addr, val);
fafd8bce
BS		 1772 break;
1773 case 8:
1774 default:
fe8d8f0f 1775 cpu_stq_user_secondary(env, addr, val);
fafd8bce
BS		 1776 break;
1777 }
1778 } else {
1779 switch (size) {
1780 case 1:
fe8d8f0f 1781 cpu_stb_user(env, addr, val);
fafd8bce
BS		 1782 break;
1783 case 2:
fe8d8f0f 1784 cpu_stw_user(env, addr, val);
fafd8bce
BS		 1785 break;
1786 case 4:
fe8d8f0f 1787 cpu_stl_user(env, addr, val);
fafd8bce
BS		 1788 break;
1789 case 8:
1790 default:
fe8d8f0f 1791 cpu_stq_user(env, addr, val);
fafd8bce
BS		 1792 break;
1793 }
1794 }
1795 }
1796 break;
0cc1f4bf
RH		 1797 case ASI_REAL: /* Bypass */
1798 case ASI_REAL_IO: /* Bypass, non-cacheable */
1799 case ASI_REAL_L: /* Bypass LE */
1800 case ASI_REAL_IO_L: /* Bypass, non-cacheable LE */
fafd8bce
BS		 1801 {
1802 switch (size) {
1803 case 1:
db3be60d 1804 stb_phys(cs->as, addr, val);
fafd8bce
BS		 1805 break;
1806 case 2:
5ce5944d 1807 stw_phys(cs->as, addr, val);
fafd8bce
BS		 1808 break;
1809 case 4:
ab1da857 1810 stl_phys(cs->as, addr, val);
fafd8bce
BS		 1811 break;
1812 case 8:
1813 default:
f606604f 1814 stq_phys(cs->as, addr, val);
fafd8bce
BS		 1815 break;
1816 }
1817 }
1818 return;
0cc1f4bf
RH		 1819 case ASI_NUCLEUS_QUAD_LDD: /* Nucleus quad LDD 128 bit atomic */
1820 case ASI_NUCLEUS_QUAD_LDD_L: /* Nucleus quad LDD 128 bit atomic LE */
1821 /* Only ldda allowed */
fafd8bce
BS		 1822 helper_raise_exception(env, TT_ILL_INSN);
1823 return;
0cc1f4bf
RH		 1824 case ASI_N: /* Nucleus */
1825 case ASI_NL: /* Nucleus Little Endian (LE) */
fafd8bce
BS		 1826 {
1827 switch (size) {
1828 case 1:
fe8d8f0f 1829 cpu_stb_nucleus(env, addr, val);
fafd8bce
BS		 1830 break;
1831 case 2:
fe8d8f0f 1832 cpu_stw_nucleus(env, addr, val);
fafd8bce
BS		 1833 break;
1834 case 4:
fe8d8f0f 1835 cpu_stl_nucleus(env, addr, val);
fafd8bce
BS		 1836 break;
1837 default:
1838 case 8:
fe8d8f0f 1839 cpu_stq_nucleus(env, addr, val);
fafd8bce
BS		 1840 break;
1841 }
1842 break;
1843 }
1844
0cc1f4bf 1845 case ASI_UPA_CONFIG: /* UPA config */
fafd8bce
BS		 1846 /* XXX */
1847 return;
0cc1f4bf 1848 case ASI_LSU_CONTROL: /* LSU */
fafd8bce
BS		 1849 {
1850 uint64_t oldreg;
1851
1852 oldreg = env->lsu;
1853 env->lsu = val & (DMMU_E | IMMU_E);
1854 /* Mappings generated during D/I MMU disabled mode are
1855 invalid in normal mode */
1856 if (oldreg != env->lsu) {
1857 DPRINTF_MMU("LSU change: 0x%" PRIx64 " -> 0x%" PRIx64 "\n",
1858 oldreg, env->lsu);
1859#ifdef DEBUG_MMU
05499f4b 1860 dump_mmu(stdout, fprintf, env);
fafd8bce 1861#endif
00c8cb0a 1862 tlb_flush(CPU(cpu), 1);
fafd8bce
BS		 1863 }
1864 return;
1865 }
0cc1f4bf 1866 case ASI_IMMU: /* I-MMU regs */
fafd8bce
BS		 1867 {
1868 int reg = (addr >> 3) & 0xf;
1869 uint64_t oldreg;
1870
1871 oldreg = env->immuregs[reg];
1872 switch (reg) {
1873 case 0: /* RO */
1874 return;
1875 case 1: /* Not in I-MMU */
1876 case 2:
1877 return;
1878 case 3: /* SFSR */
1879 if ((val & 1) == 0) {
1880 val = 0; /* Clear SFSR */
1881 }
1882 env->immu.sfsr = val;
1883 break;
1884 case 4: /* RO */
1885 return;
1886 case 5: /* TSB access */
1887 DPRINTF_MMU("immu TSB write: 0x%016" PRIx64 " -> 0x%016"
1888 PRIx64 "\n", env->immu.tsb, val);
1889 env->immu.tsb = val;
1890 break;
1891 case 6: /* Tag access */
1892 env->immu.tag_access = val;
1893 break;
1894 case 7:
1895 case 8:
1896 return;
1897 default:
1898 break;
1899 }
1900
1901 if (oldreg != env->immuregs[reg]) {
1902 DPRINTF_MMU("immu change reg[%d]: 0x%016" PRIx64 " -> 0x%016"
1903 PRIx64 "\n", reg, oldreg, env->immuregs[reg]);
1904 }
1905#ifdef DEBUG_MMU
1906 dump_mmu(stdout, fprintf, env);
1907#endif
1908 return;
1909 }
0cc1f4bf 1910 case ASI_ITLB_DATA_IN: /* I-MMU data in */
fafd8bce
BS		 1911 replace_tlb_1bit_lru(env->itlb, env->immu.tag_access, val, "immu", env);
1912 return;
0cc1f4bf 1913 case ASI_ITLB_DATA_ACCESS: /* I-MMU data access */
fafd8bce
BS		 1914 {
1915 /* TODO: auto demap */
1916
1917 unsigned int i = (addr >> 3) & 0x3f;
1918
1919 replace_tlb_entry(&env->itlb[i], env->immu.tag_access, val, env);
1920
1921#ifdef DEBUG_MMU
1922 DPRINTF_MMU("immu data access replaced entry [%i]\n", i);
1923 dump_mmu(stdout, fprintf, env);
1924#endif
1925 return;
1926 }
0cc1f4bf 1927 case ASI_IMMU_DEMAP: /* I-MMU demap */
fafd8bce
BS		 1928 demap_tlb(env->itlb, addr, "immu", env);
1929 return;
0cc1f4bf 1930 case ASI_DMMU: /* D-MMU regs */
fafd8bce
BS		 1931 {
1932 int reg = (addr >> 3) & 0xf;
1933 uint64_t oldreg;
1934
1935 oldreg = env->dmmuregs[reg];
1936 switch (reg) {
1937 case 0: /* RO */
1938 case 4:
1939 return;
1940 case 3: /* SFSR */
1941 if ((val & 1) == 0) {
1942 val = 0; /* Clear SFSR, Fault address */
1943 env->dmmu.sfar = 0;
1944 }
1945 env->dmmu.sfsr = val;
1946 break;
1947 case 1: /* Primary context */
1948 env->dmmu.mmu_primary_context = val;
1949 /* can be optimized to only flush MMU_USER_IDX
1950 and MMU_KERNEL_IDX entries */
00c8cb0a 1951 tlb_flush(CPU(cpu), 1);
fafd8bce
BS		 1952 break;
1953 case 2: /* Secondary context */
1954 env->dmmu.mmu_secondary_context = val;
1955 /* can be optimized to only flush MMU_USER_SECONDARY_IDX
1956 and MMU_KERNEL_SECONDARY_IDX entries */
00c8cb0a 1957 tlb_flush(CPU(cpu), 1);
fafd8bce
BS		 1958 break;
1959 case 5: /* TSB access */
1960 DPRINTF_MMU("dmmu TSB write: 0x%016" PRIx64 " -> 0x%016"
1961 PRIx64 "\n", env->dmmu.tsb, val);
1962 env->dmmu.tsb = val;
1963 break;
1964 case 6: /* Tag access */
1965 env->dmmu.tag_access = val;
1966 break;
1967 case 7: /* Virtual Watchpoint */
1968 case 8: /* Physical Watchpoint */
1969 default:
1970 env->dmmuregs[reg] = val;
1971 break;
1972 }
1973
1974 if (oldreg != env->dmmuregs[reg]) {
1975 DPRINTF_MMU("dmmu change reg[%d]: 0x%016" PRIx64 " -> 0x%016"
1976 PRIx64 "\n", reg, oldreg, env->dmmuregs[reg]);
1977 }
1978#ifdef DEBUG_MMU
1979 dump_mmu(stdout, fprintf, env);
1980#endif
1981 return;
1982 }
0cc1f4bf 1983 case ASI_DTLB_DATA_IN: /* D-MMU data in */
fafd8bce
BS		 1984 replace_tlb_1bit_lru(env->dtlb, env->dmmu.tag_access, val, "dmmu", env);
1985 return;
0cc1f4bf 1986 case ASI_DTLB_DATA_ACCESS: /* D-MMU data access */
fafd8bce
BS		 1987 {
1988 unsigned int i = (addr >> 3) & 0x3f;
1989
1990 replace_tlb_entry(&env->dtlb[i], env->dmmu.tag_access, val, env);
1991
1992#ifdef DEBUG_MMU
1993 DPRINTF_MMU("dmmu data access replaced entry [%i]\n", i);
1994 dump_mmu(stdout, fprintf, env);
1995#endif
1996 return;
1997 }
0cc1f4bf 1998 case ASI_DMMU_DEMAP: /* D-MMU demap */
fafd8bce
BS		 1999 demap_tlb(env->dtlb, addr, "dmmu", env);
2000 return;
0cc1f4bf 2001 case ASI_INTR_RECEIVE: /* Interrupt data receive */
361dea40 2002 env->ivec_status = val & 0x20;
fafd8bce 2003 return;
0cc1f4bf
RH		 2004 case ASI_DCACHE_DATA: /* D-cache data */
2005 case ASI_DCACHE_TAG: /* D-cache tag access */
2006 case ASI_ESTATE_ERROR_EN: /* E-cache error enable */
2007 case ASI_AFSR: /* E-cache asynchronous fault status */
2008 case ASI_AFAR: /* E-cache asynchronous fault address */
2009 case ASI_EC_TAG_DATA: /* E-cache tag data */
2010 case ASI_IC_INSTR: /* I-cache instruction access */
2011 case ASI_IC_TAG: /* I-cache tag access */
2012 case ASI_IC_PRE_DECODE: /* I-cache predecode */
2013 case ASI_IC_NEXT_FIELD: /* I-cache LRU etc. */
2014 case ASI_EC_W: /* E-cache tag */
2015 case ASI_EC_R: /* E-cache tag */
fafd8bce 2016 return;
0cc1f4bf
RH		 2017 case ASI_IMMU_TSB_8KB_PTR: /* I-MMU 8k TSB pointer, RO */
2018 case ASI_IMMU_TSB_64KB_PTR: /* I-MMU 64k TSB pointer, RO */
2019 case ASI_ITLB_TAG_READ: /* I-MMU tag read, RO */
2020 case ASI_DMMU_TSB_8KB_PTR: /* D-MMU 8k TSB pointer, RO */
2021 case ASI_DMMU_TSB_64KB_PTR: /* D-MMU 64k TSB pointer, RO */
2022 case ASI_DMMU_TSB_DIRECT_PTR: /* D-MMU data pointer, RO */
2023 case ASI_DTLB_TAG_READ: /* D-MMU tag read, RO */
2024 case ASI_INTR_DISPATCH_STAT: /* Interrupt dispatch, RO */
2025 case ASI_INTR_R: /* Incoming interrupt vector, RO */
2026 case ASI_PNF: /* Primary no-fault, RO */
2027 case ASI_SNF: /* Secondary no-fault, RO */
2028 case ASI_PNFL: /* Primary no-fault LE, RO */
2029 case ASI_SNFL: /* Secondary no-fault LE, RO */
fafd8bce 2030 default:
2fad1112 2031 cpu_unassigned_access(cs, addr, true, false, 1, size);
fafd8bce
BS		 2032 return;
2033 }
2034}
2035#endif /* CONFIG_USER_ONLY */
2036
fe8d8f0f 2037void helper_ldda_asi(CPUSPARCState *env, target_ulong addr, int asi, int rd)
fafd8bce
BS		 2038{
2039 if ((asi < 0x80 && (env->pstate & PS_PRIV) == 0)
2040 || (cpu_has_hypervisor(env)
2041 && asi >= 0x30 && asi < 0x80
2042 && !(env->hpstate & HS_PRIV))) {
2043 helper_raise_exception(env, TT_PRIV_ACT);
2044 }
2045
2046 addr = asi_address_mask(env, asi, addr);
2047
2048 switch (asi) {
2049#if !defined(CONFIG_USER_ONLY)
0cc1f4bf
RH		 2050 case ASI_NUCLEUS_QUAD_LDD: /* Nucleus quad LDD 128 bit atomic */
2051 case ASI_NUCLEUS_QUAD_LDD_L: /* Nucleus quad LDD 128 bit atomic LE */
fe8d8f0f 2052 helper_check_align(env, addr, 0xf);
fafd8bce 2053 if (rd == 0) {
fe8d8f0f 2054 env->gregs[1] = cpu_ldq_nucleus(env, addr + 8);
0cc1f4bf 2055 if (asi == ASI_NUCLEUS_QUAD_LDD_L) {
fafd8bce
BS		 2056 bswap64s(&env->gregs[1]);
2057 }
2058 } else if (rd < 8) {
fe8d8f0f
BS		 2059 env->gregs[rd] = cpu_ldq_nucleus(env, addr);
2060 env->gregs[rd + 1] = cpu_ldq_nucleus(env, addr + 8);
0cc1f4bf 2061 if (asi == ASI_NUCLEUS_QUAD_LDD_L) {
fafd8bce
BS		 2062 bswap64s(&env->gregs[rd]);
2063 bswap64s(&env->gregs[rd + 1]);
2064 }
2065 } else {
01a780d5
AT		 2066 env->regwptr[rd - 8] = cpu_ldq_nucleus(env, addr);
2067 env->regwptr[rd + 1 - 8] = cpu_ldq_nucleus(env, addr + 8);
0cc1f4bf 2068 if (asi == ASI_NUCLEUS_QUAD_LDD_L) {
01a780d5
AT		 2069 bswap64s(&env->regwptr[rd - 8]);
2070 bswap64s(&env->regwptr[rd + 1 - 8]);
fafd8bce
BS		 2071 }
2072 }
2073 break;
2074#endif
2075 default:
fe8d8f0f 2076 helper_check_align(env, addr, 0x3);
fafd8bce 2077 if (rd == 0) {
fe8d8f0f 2078 env->gregs[1] = helper_ld_asi(env, addr + 4, asi, 4, 0);
fafd8bce 2079 } else if (rd < 8) {
fe8d8f0f
BS		 2080 env->gregs[rd] = helper_ld_asi(env, addr, asi, 4, 0);
2081 env->gregs[rd + 1] = helper_ld_asi(env, addr + 4, asi, 4, 0);
fafd8bce 2082 } else {
01a780d5
AT		 2083 env->regwptr[rd - 8] = helper_ld_asi(env, addr, asi, 4, 0);
2084 env->regwptr[rd + 1 - 8] = helper_ld_asi(env, addr + 4, asi, 4, 0);
fafd8bce
BS		 2085 }
2086 break;
2087 }
2088}
2089
fe8d8f0f
BS		 2090void helper_ldf_asi(CPUSPARCState *env, target_ulong addr, int asi, int size,
2091 int rd)
fafd8bce
BS		 2092{
2093 unsigned int i;
30038fd8 2094 target_ulong val;
fafd8bce 2095
fe8d8f0f 2096 helper_check_align(env, addr, 3);
fafd8bce
BS		 2097 addr = asi_address_mask(env, asi, addr);
2098
2099 switch (asi) {
0cc1f4bf
RH		 2100 case ASI_BLK_P: /* UA2007/JPS1 Block load primary */
2101 case ASI_BLK_S: /* UA2007/JPS1 Block load secondary */
2102 case ASI_BLK_PL: /* UA2007/JPS1 Block load primary LE */
2103 case ASI_BLK_SL: /* UA2007/JPS1 Block load secondary LE */
fafd8bce
BS		 2104 if (rd & 7) {
2105 helper_raise_exception(env, TT_ILL_INSN);
2106 return;
2107 }
fe8d8f0f 2108 helper_check_align(env, addr, 0x3f);
30038fd8 2109 for (i = 0; i < 8; i++, rd += 2, addr += 8) {
fe8d8f0f 2110 env->fpr[rd / 2].ll = helper_ld_asi(env, addr, asi & 0x8f, 8, 0);
fafd8bce 2111 }
fafd8bce 2112 return;
30038fd8 2113
0cc1f4bf
RH		 2114 case ASI_BLK_AIUP_4V: /* UA2007 Block load primary, user privilege */
2115 case ASI_BLK_AIUS_4V: /* UA2007 Block load secondary, user privilege */
2116 case ASI_BLK_AIUP_L_4V: /* UA2007 Block load primary LE, user privilege */
2117 case ASI_BLK_AIUS_L_4V: /* UA2007 Block load secondary LE, user privilege */
2118 case ASI_BLK_AIUP: /* JPS1 Block load primary, user privilege */
2119 case ASI_BLK_AIUS: /* JPS1 Block load secondary, user privilege */
2120 case ASI_BLK_AIUPL: /* JPS1 Block load primary LE, user privilege */
2121 case ASI_BLK_AIUSL: /* JPS1 Block load secondary LE, user privilege */
fafd8bce
BS		 2122 if (rd & 7) {
2123 helper_raise_exception(env, TT_ILL_INSN);
2124 return;
2125 }
fe8d8f0f 2126 helper_check_align(env, addr, 0x3f);
00b2ace5 2127 for (i = 0; i < 8; i++, rd += 2, addr += 8) {
fe8d8f0f 2128 env->fpr[rd / 2].ll = helper_ld_asi(env, addr, asi & 0x19, 8, 0);
fafd8bce 2129 }
fafd8bce 2130 return;
30038fd8 2131
fafd8bce
BS		 2132 default:
2133 break;
2134 }
2135
2136 switch (size) {
2137 default:
2138 case 4:
fe8d8f0f 2139 val = helper_ld_asi(env, addr, asi, size, 0);
30038fd8 2140 if (rd & 1) {
fe8d8f0f 2141 env->fpr[rd / 2].l.lower = val;
30038fd8 2142 } else {
fe8d8f0f 2143 env->fpr[rd / 2].l.upper = val;
30038fd8 2144 }
fafd8bce
BS		 2145 break;
2146 case 8:
fe8d8f0f 2147 env->fpr[rd / 2].ll = helper_ld_asi(env, addr, asi, size, 0);
fafd8bce
BS		 2148 break;
2149 case 16:
fe8d8f0f
BS		 2150 env->fpr[rd / 2].ll = helper_ld_asi(env, addr, asi, 8, 0);
2151 env->fpr[rd / 2 + 1].ll = helper_ld_asi(env, addr + 8, asi, 8, 0);
fafd8bce
BS		 2152 break;
2153 }
2154}
2155
fe8d8f0f
BS		 2156void helper_stf_asi(CPUSPARCState *env, target_ulong addr, int asi, int size,
2157 int rd)
fafd8bce
BS		 2158{
2159 unsigned int i;
30038fd8 2160 target_ulong val;
fafd8bce 2161
fafd8bce
BS		 2162 addr = asi_address_mask(env, asi, addr);
2163
2164 switch (asi) {
0cc1f4bf
RH		 2165 case ASI_BLK_COMMIT_P: /* UA2007/JPS1 Block store primary (cache flush) */
2166 case ASI_BLK_COMMIT_S: /* UA2007/JPS1 Block store secondary (cache flush) */
2167 case ASI_BLK_P: /* UA2007/JPS1 Block store primary */
2168 case ASI_BLK_S: /* UA2007/JPS1 Block store secondary */
2169 case ASI_BLK_PL: /* UA2007/JPS1 Block store primary LE */
2170 case ASI_BLK_SL: /* UA2007/JPS1 Block store secondary LE */
fafd8bce
BS		 2171 if (rd & 7) {
2172 helper_raise_exception(env, TT_ILL_INSN);
2173 return;
2174 }
fe8d8f0f 2175 helper_check_align(env, addr, 0x3f);
30038fd8 2176 for (i = 0; i < 8; i++, rd += 2, addr += 8) {
fe8d8f0f 2177 helper_st_asi(env, addr, env->fpr[rd / 2].ll, asi & 0x8f, 8);
fafd8bce
BS		 2178 }
2179
2180 return;
0cc1f4bf
RH		 2181 case ASI_BLK_AIUP_4V: /* UA2007 Block load primary, user privilege */
2182 case ASI_BLK_AIUS_4V: /* UA2007 Block load secondary, user privilege */
2183 case ASI_BLK_AIUP_L_4V: /* UA2007 Block load primary LE, user privilege */
2184 case ASI_BLK_AIUS_L_4V: /* UA2007 Block load secondary LE, user privilege */
2185 case ASI_BLK_AIUP: /* JPS1 Block store primary, user privilege */
2186 case ASI_BLK_AIUS: /* JPS1 Block store secondary, user privilege */
2187 case ASI_BLK_AIUPL: /* JPS1 Block load primary LE, user privilege */
2188 case ASI_BLK_AIUSL: /* JPS1 Block load secondary LE, user privilege */
fafd8bce
BS		 2189 if (rd & 7) {
2190 helper_raise_exception(env, TT_ILL_INSN);
2191 return;
2192 }
fe8d8f0f 2193 helper_check_align(env, addr, 0x3f);
30038fd8 2194 for (i = 0; i < 8; i++, rd += 2, addr += 8) {
fe8d8f0f 2195 helper_st_asi(env, addr, env->fpr[rd / 2].ll, asi & 0x19, 8);
fafd8bce
BS		 2196 }
2197
2a5fade7 2198 return;
0cc1f4bf
RH		 2199 case ASI_FL16_P: /* 16-bit floating point load primary */
2200 case ASI_FL16_S: /* 16-bit floating point load secondary */
2201 case ASI_FL16_PL: /* 16-bit floating point load primary, LE */
2202 case ASI_FL16_SL: /* 16-bit floating point load secondary, LE */
2a5fade7
AT		 2203 helper_check_align(env, addr, 1);
2204 /* Fall through */
0cc1f4bf
RH		 2205 case ASI_FL8_P: /* 8-bit floating point load primary */
2206 case ASI_FL8_S: /* 8-bit floating point load secondary */
2207 case ASI_FL8_PL: /* 8-bit floating point load primary, LE */
2208 case ASI_FL8_SL: /* 8-bit floating point load secondary, LE */
2a5fade7
AT		 2209 val = env->fpr[rd / 2].l.lower;
2210 helper_st_asi(env, addr, val, asi & 0x8d, ((asi & 2) >> 1) + 1);
fafd8bce
BS		 2211 return;
2212 default:
2a5fade7 2213 helper_check_align(env, addr, 3);
fafd8bce
BS		 2214 break;
2215 }
2216
2217 switch (size) {
2218 default:
2219 case 4:
30038fd8 2220 if (rd & 1) {
fe8d8f0f 2221 val = env->fpr[rd / 2].l.lower;
30038fd8 2222 } else {
fe8d8f0f 2223 val = env->fpr[rd / 2].l.upper;
30038fd8 2224 }
fe8d8f0f 2225 helper_st_asi(env, addr, val, asi, size);
fafd8bce
BS		 2226 break;
2227 case 8:
fe8d8f0f 2228 helper_st_asi(env, addr, env->fpr[rd / 2].ll, asi, size);
fafd8bce
BS		 2229 break;
2230 case 16:
fe8d8f0f
BS		 2231 helper_st_asi(env, addr, env->fpr[rd / 2].ll, asi, 8);
2232 helper_st_asi(env, addr + 8, env->fpr[rd / 2 + 1].ll, asi, 8);
fafd8bce
BS		 2233 break;
2234 }
2235}
2236
16c358e9
SH		 2237target_ulong helper_casx_asi(CPUSPARCState *env, target_ulong addr,
2238 target_ulong val1, target_ulong val2,
2239 uint32_t asi)
fafd8bce
BS		 2240{
2241 target_ulong ret;
2242
16c358e9 2243 ret = helper_ld_asi(env, addr, asi, 8, 0);
fafd8bce 2244 if (val2 == ret) {
16c358e9 2245 helper_st_asi(env, addr, val1, asi, 8);
fafd8bce
BS		 2246 }
2247 return ret;
2248}
16c358e9 2249#endif /* TARGET_SPARC64 */
fafd8bce 2250
16c358e9
SH		 2251#if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64)
2252target_ulong helper_cas_asi(CPUSPARCState *env, target_ulong addr,
2253 target_ulong val1, target_ulong val2, uint32_t asi)
fafd8bce
BS		 2254{
2255 target_ulong ret;
2256
16c358e9
SH		 2257 val2 &= 0xffffffffUL;
2258 ret = helper_ld_asi(env, addr, asi, 4, 0);
2259 ret &= 0xffffffffUL;
fafd8bce 2260 if (val2 == ret) {
16c358e9 2261 helper_st_asi(env, addr, val1 & 0xffffffffUL, asi, 4);
fafd8bce
BS		 2262 }
2263 return ret;
2264}
16c358e9 2265#endif /* !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64) */
fafd8bce 2266
fe8d8f0f 2267void helper_ldqf(CPUSPARCState *env, target_ulong addr, int mem_idx)
fafd8bce
BS		 2268{
2269 /* XXX add 128 bit load */
2270 CPU_QuadU u;
2271
fe8d8f0f 2272 helper_check_align(env, addr, 7);
fafd8bce
BS		 2273#if !defined(CONFIG_USER_ONLY)
2274 switch (mem_idx) {
2275 case MMU_USER_IDX:
fe8d8f0f
BS		 2276 u.ll.upper = cpu_ldq_user(env, addr);
2277 u.ll.lower = cpu_ldq_user(env, addr + 8);
fafd8bce
BS		 2278 QT0 = u.q;
2279 break;
2280 case MMU_KERNEL_IDX:
fe8d8f0f
BS		 2281 u.ll.upper = cpu_ldq_kernel(env, addr);
2282 u.ll.lower = cpu_ldq_kernel(env, addr + 8);
fafd8bce
BS		 2283 QT0 = u.q;
2284 break;
2285#ifdef TARGET_SPARC64
2286 case MMU_HYPV_IDX:
fe8d8f0f
BS		 2287 u.ll.upper = cpu_ldq_hypv(env, addr);
2288 u.ll.lower = cpu_ldq_hypv(env, addr + 8);
fafd8bce
BS		 2289 QT0 = u.q;
2290 break;
2291#endif
2292 default:
2293 DPRINTF_MMU("helper_ldqf: need to check MMU idx %d\n", mem_idx);
2294 break;
2295 }
2296#else
eb513f82
PM		 2297 u.ll.upper = cpu_ldq_data(env, address_mask(env, addr));
2298 u.ll.lower = cpu_ldq_data(env, address_mask(env, addr + 8));
fafd8bce
BS		 2299 QT0 = u.q;
2300#endif
2301}
2302
fe8d8f0f 2303void helper_stqf(CPUSPARCState *env, target_ulong addr, int mem_idx)
fafd8bce
BS		 2304{
2305 /* XXX add 128 bit store */
2306 CPU_QuadU u;
2307
fe8d8f0f 2308 helper_check_align(env, addr, 7);
fafd8bce
BS		 2309#if !defined(CONFIG_USER_ONLY)
2310 switch (mem_idx) {
2311 case MMU_USER_IDX:
2312 u.q = QT0;
fe8d8f0f
BS		 2313 cpu_stq_user(env, addr, u.ll.upper);
2314 cpu_stq_user(env, addr + 8, u.ll.lower);
fafd8bce
BS		 2315 break;
2316 case MMU_KERNEL_IDX:
2317 u.q = QT0;
fe8d8f0f
BS		 2318 cpu_stq_kernel(env, addr, u.ll.upper);
2319 cpu_stq_kernel(env, addr + 8, u.ll.lower);
fafd8bce
BS		 2320 break;
2321#ifdef TARGET_SPARC64
2322 case MMU_HYPV_IDX:
2323 u.q = QT0;
fe8d8f0f
BS		 2324 cpu_stq_hypv(env, addr, u.ll.upper);
2325 cpu_stq_hypv(env, addr + 8, u.ll.lower);
fafd8bce
BS		 2326 break;
2327#endif
2328 default:
2329 DPRINTF_MMU("helper_stqf: need to check MMU idx %d\n", mem_idx);
2330 break;
2331 }
2332#else
2333 u.q = QT0;
eb513f82
PM		 2334 cpu_stq_data(env, address_mask(env, addr), u.ll.upper);
2335 cpu_stq_data(env, address_mask(env, addr + 8), u.ll.lower);
fafd8bce
BS		 2336#endif
2337}
2338
fafd8bce 2339#if !defined(CONFIG_USER_ONLY)
fe8d8f0f 2340#ifndef TARGET_SPARC64
c658b94f
AF		 2341void sparc_cpu_unassigned_access(CPUState *cs, hwaddr addr,
2342 bool is_write, bool is_exec, int is_asi,
2343 unsigned size)
fafd8bce 2344{
c658b94f
AF		 2345 SPARCCPU *cpu = SPARC_CPU(cs);
2346 CPUSPARCState *env = &cpu->env;
fafd8bce
BS		 2347 int fault_type;
2348
2349#ifdef DEBUG_UNASSIGNED
2350 if (is_asi) {
2351 printf("Unassigned mem %s access of %d byte%s to " TARGET_FMT_plx
2352 " asi 0x%02x from " TARGET_FMT_lx "\n",
2353 is_exec ? "exec" : is_write ? "write" : "read", size,
2354 size == 1 ? "" : "s", addr, is_asi, env->pc);
2355 } else {
2356 printf("Unassigned mem %s access of %d byte%s to " TARGET_FMT_plx
2357 " from " TARGET_FMT_lx "\n",
2358 is_exec ? "exec" : is_write ? "write" : "read", size,
2359 size == 1 ? "" : "s", addr, env->pc);
2360 }
2361#endif
2362 /* Don't overwrite translation and access faults */
2363 fault_type = (env->mmuregs[3] & 0x1c) >> 2;
2364 if ((fault_type > 4) || (fault_type == 0)) {
2365 env->mmuregs[3] = 0; /* Fault status register */
2366 if (is_asi) {
2367 env->mmuregs[3] |= 1 << 16;
2368 }
2369 if (env->psrs) {
2370 env->mmuregs[3] |= 1 << 5;
2371 }
2372 if (is_exec) {
2373 env->mmuregs[3] |= 1 << 6;
2374 }
2375 if (is_write) {
2376 env->mmuregs[3] |= 1 << 7;
2377 }
2378 env->mmuregs[3] |= (5 << 2) | 2;
2379 /* SuperSPARC will never place instruction fault addresses in the FAR */
2380 if (!is_exec) {
2381 env->mmuregs[4] = addr; /* Fault address register */
2382 }
2383 }
2384 /* overflow (same type fault was not read before another fault) */
2385 if (fault_type == ((env->mmuregs[3] & 0x1c)) >> 2) {
2386 env->mmuregs[3] |= 1;
2387 }
2388
2389 if ((env->mmuregs[0] & MMU_E) && !(env->mmuregs[0] & MMU_NF)) {
2390 if (is_exec) {
2391 helper_raise_exception(env, TT_CODE_ACCESS);
2392 } else {
2393 helper_raise_exception(env, TT_DATA_ACCESS);
2394 }
2395 }
2396
2397 /* flush neverland mappings created during no-fault mode,
2398 so the sequential MMU faults report proper fault types */
2399 if (env->mmuregs[0] & MMU_NF) {
00c8cb0a 2400 tlb_flush(cs, 1);
fafd8bce
BS		 2401 }
2402}
fafd8bce 2403#else
c658b94f
AF		 2404void sparc_cpu_unassigned_access(CPUState *cs, hwaddr addr,
2405 bool is_write, bool is_exec, int is_asi,
2406 unsigned size)
fafd8bce 2407{
c658b94f
AF		 2408 SPARCCPU *cpu = SPARC_CPU(cs);
2409 CPUSPARCState *env = &cpu->env;
2410
fafd8bce
BS		 2411#ifdef DEBUG_UNASSIGNED
2412 printf("Unassigned mem access to " TARGET_FMT_plx " from " TARGET_FMT_lx
2413 "\n", addr, env->pc);
2414#endif
2415
2416 if (is_exec) {
2417 helper_raise_exception(env, TT_CODE_ACCESS);
2418 } else {
2419 helper_raise_exception(env, TT_DATA_ACCESS);
2420 }
2421}
2422#endif
fafd8bce 2423#endif
0184e266 2424
c28ae41e 2425#if !defined(CONFIG_USER_ONLY)
b35399bb
SS		 2426void QEMU_NORETURN sparc_cpu_do_unaligned_access(CPUState *cs, vaddr addr,
2427 MMUAccessType access_type,
2428 int mmu_idx,
2429 uintptr_t retaddr)
0184e266 2430{
93e22326
PB		 2431 SPARCCPU *cpu = SPARC_CPU(cs);
2432 CPUSPARCState *env = &cpu->env;
2433
0184e266
BS		 2434#ifdef DEBUG_UNALIGNED
2435 printf("Unaligned access to 0x" TARGET_FMT_lx " from 0x" TARGET_FMT_lx
2436 "\n", addr, env->pc);
2437#endif
a8a826a3 2438 if (retaddr) {
3f38f309 2439 cpu_restore_state(CPU(cpu), retaddr);
a8a826a3 2440 }
0184e266
BS		 2441 helper_raise_exception(env, TT_UNALIGNED);
2442}
2443
2444/* try to fill the TLB and return an exception if error. If retaddr is
2445 NULL, it means that the function was called in C code (i.e. not
2446 from generated code or from helper.c) */
2447/* XXX: fix it to restore all registers */
b35399bb
SS		 2448void tlb_fill(CPUState *cs, target_ulong addr, MMUAccessType access_type,
2449 int mmu_idx, uintptr_t retaddr)
0184e266
BS		 2450{
2451 int ret;
2452
b35399bb 2453 ret = sparc_cpu_handle_mmu_fault(cs, addr, access_type, mmu_idx);
0184e266 2454 if (ret) {
a8a826a3 2455 if (retaddr) {
3f38f309 2456 cpu_restore_state(cs, retaddr);
a8a826a3 2457 }
5638d180 2458 cpu_loop_exit(cs);
0184e266
BS		 2459 }
2460}
2461#endif
Mirror of https://git.qemu.org/git/qemu.git