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128-bit float support for user mode
[thirdparty/qemu.git] / target-sparc / op_helper.c
CommitLineData
e8af50a3 1#include "exec.h"
eed152bb 2#include "host-utils.h"
e8af50a3 3
83469015 4//#define DEBUG_PCALL
e80cfcfc 5//#define DEBUG_MMU
952a328f 6//#define DEBUG_MXCC
94554550 7//#define DEBUG_UNALIGNED
6c36d3fa 8//#define DEBUG_UNASSIGNED
e80cfcfc 9
952a328f
BS		 10#ifdef DEBUG_MMU
11#define DPRINTF_MMU(fmt, args...) \
12do { printf("MMU: " fmt , ##args); } while (0)
13#else
14#define DPRINTF_MMU(fmt, args...)
15#endif
16
17#ifdef DEBUG_MXCC
18#define DPRINTF_MXCC(fmt, args...) \
19do { printf("MXCC: " fmt , ##args); } while (0)
20#else
21#define DPRINTF_MXCC(fmt, args...)
22#endif
23
9d893301
FB		 24void raise_exception(int tt)
25{
26 env->exception_index = tt;
27 cpu_loop_exit();
3b46e624 28}
9d893301 29
417454b0
BS		 30void check_ieee_exceptions()
31{
32 T0 = get_float_exception_flags(&env->fp_status);
33 if (T0)
34 {
0f8a249a
BS		 35 /* Copy IEEE 754 flags into FSR */
36 if (T0 & float_flag_invalid)
37 env->fsr |= FSR_NVC;
38 if (T0 & float_flag_overflow)
39 env->fsr |= FSR_OFC;
40 if (T0 & float_flag_underflow)
41 env->fsr |= FSR_UFC;
42 if (T0 & float_flag_divbyzero)
43 env->fsr |= FSR_DZC;
44 if (T0 & float_flag_inexact)
45 env->fsr |= FSR_NXC;
46
47 if ((env->fsr & FSR_CEXC_MASK) & ((env->fsr & FSR_TEM_MASK) >> 23))
48 {
49 /* Unmasked exception, generate a trap */
50 env->fsr |= FSR_FTT_IEEE_EXCP;
51 raise_exception(TT_FP_EXCP);
52 }
53 else
54 {
55 /* Accumulate exceptions */
56 env->fsr |= (env->fsr & FSR_CEXC_MASK) << 5;
57 }
417454b0
BS		 58 }
59}
60
a0c4cb4a
FB		 61#ifdef USE_INT_TO_FLOAT_HELPERS
62void do_fitos(void)
63{
417454b0 64 set_float_exception_flags(0, &env->fp_status);
ec230928 65 FT0 = int32_to_float32(*((int32_t *)&FT1), &env->fp_status);
417454b0 66 check_ieee_exceptions();
a0c4cb4a
FB		 67}
68
69void do_fitod(void)
70{
ec230928 71 DT0 = int32_to_float64(*((int32_t *)&FT1), &env->fp_status);
a0c4cb4a 72}
1e64e78d
BS		 73#ifdef TARGET_SPARC64
74void do_fxtos(void)
75{
76 set_float_exception_flags(0, &env->fp_status);
77 FT0 = int64_to_float32(*((int64_t *)&DT1), &env->fp_status);
78 check_ieee_exceptions();
79}
80
81void do_fxtod(void)
82{
83 set_float_exception_flags(0, &env->fp_status);
84 DT0 = int64_to_float64(*((int64_t *)&DT1), &env->fp_status);
85 check_ieee_exceptions();
86}
87#endif
a0c4cb4a
FB		 88#endif
89
90void do_fabss(void)
e8af50a3 91{
7a0e1f41 92 FT0 = float32_abs(FT1);
e8af50a3
FB		 93}
94
3475187d
FB		 95#ifdef TARGET_SPARC64
96void do_fabsd(void)
97{
98 DT0 = float64_abs(DT1);
99}
1f587329
BS		 100
101#if defined(CONFIG_USER_ONLY)
102void do_fabsq(void)
103{
104 QT0 = float128_abs(QT1);
105}
106#endif
3475187d
FB		 107#endif
108
a0c4cb4a 109void do_fsqrts(void)
e8af50a3 110{
417454b0 111 set_float_exception_flags(0, &env->fp_status);
7a0e1f41 112 FT0 = float32_sqrt(FT1, &env->fp_status);
417454b0 113 check_ieee_exceptions();
e8af50a3
FB		 114}
115
a0c4cb4a 116void do_fsqrtd(void)
e8af50a3 117{
417454b0 118 set_float_exception_flags(0, &env->fp_status);
7a0e1f41 119 DT0 = float64_sqrt(DT1, &env->fp_status);
417454b0 120 check_ieee_exceptions();
e8af50a3
FB		 121}
122
1f587329
BS		 123#if defined(CONFIG_USER_ONLY)
124void do_fsqrtq(void)
125{
126 set_float_exception_flags(0, &env->fp_status);
127 QT0 = float128_sqrt(QT1, &env->fp_status);
128 check_ieee_exceptions();
129}
130#endif
131
417454b0 132#define GEN_FCMP(name, size, reg1, reg2, FS, TRAP) \
65ce8c2f
FB		 133 void glue(do_, name) (void) \
134 { \
135 env->fsr &= ~((FSR_FCC1 | FSR_FCC0) << FS); \
136 switch (glue(size, _compare) (reg1, reg2, &env->fp_status)) { \
137 case float_relation_unordered: \
138 T0 = (FSR_FCC1 | FSR_FCC0) << FS; \
417454b0 139 if ((env->fsr & FSR_NVM) || TRAP) { \
65ce8c2f 140 env->fsr |= T0; \
417454b0
BS		 141 env->fsr |= FSR_NVC; \
142 env->fsr |= FSR_FTT_IEEE_EXCP; \
65ce8c2f
FB		 143 raise_exception(TT_FP_EXCP); \
144 } else { \
145 env->fsr |= FSR_NVA; \
146 } \
147 break; \
148 case float_relation_less: \
149 T0 = FSR_FCC0 << FS; \
150 break; \
151 case float_relation_greater: \
152 T0 = FSR_FCC1 << FS; \
153 break; \
154 default: \
155 T0 = 0; \
156 break; \
157 } \
158 env->fsr |= T0; \
e8af50a3 159 }
e8af50a3 160
417454b0
BS		 161GEN_FCMP(fcmps, float32, FT0, FT1, 0, 0);
162GEN_FCMP(fcmpd, float64, DT0, DT1, 0, 0);
163
164GEN_FCMP(fcmpes, float32, FT0, FT1, 0, 1);
165GEN_FCMP(fcmped, float64, DT0, DT1, 0, 1);
3475187d 166
1f587329
BS		 167#ifdef CONFIG_USER_ONLY
168GEN_FCMP(fcmpq, float128, QT0, QT1, 0, 0);
169GEN_FCMP(fcmpeq, float128, QT0, QT1, 0, 1);
170#endif
171
3475187d 172#ifdef TARGET_SPARC64
417454b0
BS		 173GEN_FCMP(fcmps_fcc1, float32, FT0, FT1, 22, 0);
174GEN_FCMP(fcmpd_fcc1, float64, DT0, DT1, 22, 0);
175
176GEN_FCMP(fcmps_fcc2, float32, FT0, FT1, 24, 0);
177GEN_FCMP(fcmpd_fcc2, float64, DT0, DT1, 24, 0);
178
179GEN_FCMP(fcmps_fcc3, float32, FT0, FT1, 26, 0);
180GEN_FCMP(fcmpd_fcc3, float64, DT0, DT1, 26, 0);
181
182GEN_FCMP(fcmpes_fcc1, float32, FT0, FT1, 22, 1);
183GEN_FCMP(fcmped_fcc1, float64, DT0, DT1, 22, 1);
3475187d 184
417454b0
BS		 185GEN_FCMP(fcmpes_fcc2, float32, FT0, FT1, 24, 1);
186GEN_FCMP(fcmped_fcc2, float64, DT0, DT1, 24, 1);
3475187d 187
417454b0
BS		 188GEN_FCMP(fcmpes_fcc3, float32, FT0, FT1, 26, 1);
189GEN_FCMP(fcmped_fcc3, float64, DT0, DT1, 26, 1);
1f587329
BS		 190#ifdef CONFIG_USER_ONLY
191GEN_FCMP(fcmpq_fcc1, float128, QT0, QT1, 22, 0);
192GEN_FCMP(fcmpq_fcc2, float128, QT0, QT1, 24, 0);
193GEN_FCMP(fcmpq_fcc3, float128, QT0, QT1, 26, 0);
194GEN_FCMP(fcmpeq_fcc1, float128, QT0, QT1, 22, 1);
195GEN_FCMP(fcmpeq_fcc2, float128, QT0, QT1, 24, 1);
196GEN_FCMP(fcmpeq_fcc3, float128, QT0, QT1, 26, 1);
197#endif
3475187d
FB		 198#endif
199
200#ifndef TARGET_SPARC64
81ad8ba2 201#ifndef CONFIG_USER_ONLY
952a328f
BS		 202
203#ifdef DEBUG_MXCC
204static void dump_mxcc(CPUState *env)
205{
206 printf("mxccdata: %016llx %016llx %016llx %016llx\n",
207 env->mxccdata[0], env->mxccdata[1], env->mxccdata[2], env->mxccdata[3]);
208 printf("mxccregs: %016llx %016llx %016llx %016llx\n"
209 " %016llx %016llx %016llx %016llx\n",
210 env->mxccregs[0], env->mxccregs[1], env->mxccregs[2], env->mxccregs[3],
211 env->mxccregs[4], env->mxccregs[5], env->mxccregs[6], env->mxccregs[7]);
212}
213#endif
214
a0c4cb4a 215void helper_ld_asi(int asi, int size, int sign)
e8af50a3 216{
83469015 217 uint32_t ret = 0;
e909ec2f 218 uint64_t tmp;
952a328f
BS		 219#ifdef DEBUG_MXCC
220 uint32_t last_T0 = T0;
221#endif
e80cfcfc
FB		 222
223 switch (asi) {
6c36d3fa 224 case 2: /* SuperSparc MXCC registers */
952a328f
BS		 225 switch (T0) {
226 case 0x01c00a00: /* MXCC control register */
227 if (size == 8) {
d07b4d0e
BS		 228 ret = env->mxccregs[3] >> 32;
229 T0 = env->mxccregs[3];
952a328f
BS		 230 } else
231 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", T0, size);
232 break;
233 case 0x01c00a04: /* MXCC control register */
234 if (size == 4)
235 ret = env->mxccregs[3];
236 else
237 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", T0, size);
238 break;
295db113
BS		 239 case 0x01c00c00: /* Module reset register */
240 if (size == 8) {
241 ret = env->mxccregs[5] >> 32;
242 T0 = env->mxccregs[5];
243 // should we do something here?
244 } else
245 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", T0, size);
246 break;
952a328f
BS		 247 case 0x01c00f00: /* MBus port address register */
248 if (size == 8) {
d07b4d0e
BS		 249 ret = env->mxccregs[7] >> 32;
250 T0 = env->mxccregs[7];
952a328f
BS		 251 } else
252 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", T0, size);
253 break;
254 default:
255 DPRINTF_MXCC("%08x: unimplemented address, size: %d\n", T0, size);
256 break;
257 }
258 DPRINTF_MXCC("asi = %d, size = %d, sign = %d, T0 = %08x -> ret = %08x,"
259 "T0 = %08x\n", asi, size, sign, last_T0, ret, T0);
260#ifdef DEBUG_MXCC
261 dump_mxcc(env);
262#endif
6c36d3fa 263 break;
e8af50a3 264 case 3: /* MMU probe */
0f8a249a
BS		 265 {
266 int mmulev;
267
268 mmulev = (T0 >> 8) & 15;
269 if (mmulev > 4)
270 ret = 0;
271 else {
272 ret = mmu_probe(env, T0, mmulev);
273 //bswap32s(&ret);
274 }
952a328f 275 DPRINTF_MMU("mmu_probe: 0x%08x (lev %d) -> 0x%08x\n", T0, mmulev, ret);
0f8a249a
BS		 276 }
277 break;
e8af50a3 278 case 4: /* read MMU regs */
0f8a249a 279 {
3dd9a152 280 int reg = (T0 >> 8) & 0x1f;
3b46e624 281
0f8a249a
BS		 282 ret = env->mmuregs[reg];
283 if (reg == 3) /* Fault status cleared on read */
3dd9a152
BS		 284 env->mmuregs[3] = 0;
285 else if (reg == 0x13) /* Fault status read */
286 ret = env->mmuregs[3];
287 else if (reg == 0x14) /* Fault address read */
288 ret = env->mmuregs[4];
952a328f 289 DPRINTF_MMU("mmu_read: reg[%d] = 0x%08x\n", reg, ret);
0f8a249a
BS		 290 }
291 break;
6c36d3fa
BS		 292 case 9: /* Supervisor code access */
293 switch(size) {
294 case 1:
295 ret = ldub_code(T0);
296 break;
297 case 2:
298 ret = lduw_code(T0 & ~1);
299 break;
300 default:
301 case 4:
302 ret = ldl_code(T0 & ~3);
303 break;
304 case 8:
e909ec2f
BS		 305 tmp = ldq_code(T0 & ~7);
306 ret = tmp >> 32;
2761992d 307 T0 = tmp;
6c36d3fa
BS		 308 break;
309 }
310 break;
81ad8ba2
BS		 311 case 0xa: /* User data access */
312 switch(size) {
313 case 1:
314 ret = ldub_user(T0);
315 break;
316 case 2:
317 ret = lduw_user(T0 & ~1);
318 break;
319 default:
320 case 4:
321 ret = ldl_user(T0 & ~3);
322 break;
323 case 8:
e909ec2f
BS		 324 tmp = ldq_user(T0 & ~7);
325 ret = tmp >> 32;
2761992d 326 T0 = tmp;
81ad8ba2
BS		 327 break;
328 }
329 break;
330 case 0xb: /* Supervisor data access */
331 switch(size) {
332 case 1:
333 ret = ldub_kernel(T0);
334 break;
335 case 2:
336 ret = lduw_kernel(T0 & ~1);
337 break;
338 default:
339 case 4:
340 ret = ldl_kernel(T0 & ~3);
341 break;
342 case 8:
e909ec2f
BS		 343 tmp = ldq_kernel(T0 & ~7);
344 ret = tmp >> 32;
2761992d 345 T0 = tmp;
81ad8ba2
BS		 346 break;
347 }
348 break;
6c36d3fa
BS		 349 case 0xc: /* I-cache tag */
350 case 0xd: /* I-cache data */
351 case 0xe: /* D-cache tag */
352 case 0xf: /* D-cache data */
353 break;
354 case 0x20: /* MMU passthrough */
02aab46a
FB		 355 switch(size) {
356 case 1:
357 ret = ldub_phys(T0);
358 break;
359 case 2:
360 ret = lduw_phys(T0 & ~1);
361 break;
362 default:
363 case 4:
364 ret = ldl_phys(T0 & ~3);
365 break;
9e61bde5 366 case 8:
e909ec2f
BS		 367 tmp = ldq_phys(T0 & ~7);
368 ret = tmp >> 32;
2761992d 369 T0 = tmp;
0f8a249a 370 break;
02aab46a 371 }
0f8a249a 372 break;
5dcb6b91
BS		 373 case 0x2e: /* MMU passthrough, 0xexxxxxxxx */
374 case 0x2f: /* MMU passthrough, 0xfxxxxxxxx */
375 switch(size) {
376 case 1:
377 ret = ldub_phys((target_phys_addr_t)T0
378 | ((target_phys_addr_t)(asi & 0xf) << 32));
379 break;
380 case 2:
381 ret = lduw_phys((target_phys_addr_t)(T0 & ~1)
382 | ((target_phys_addr_t)(asi & 0xf) << 32));
383 break;
384 default:
385 case 4:
386 ret = ldl_phys((target_phys_addr_t)(T0 & ~3)
387 | ((target_phys_addr_t)(asi & 0xf) << 32));
388 break;
389 case 8:
e909ec2f 390 tmp = ldq_phys((target_phys_addr_t)(T0 & ~7)
5dcb6b91 391 | ((target_phys_addr_t)(asi & 0xf) << 32));
e909ec2f 392 ret = tmp >> 32;
2761992d 393 T0 = tmp;
0f8a249a 394 break;
5dcb6b91 395 }
0f8a249a 396 break;
5dcb6b91 397 case 0x21 ... 0x2d: /* MMU passthrough, unassigned */
e8af50a3 398 default:
6c36d3fa 399 do_unassigned_access(T0, 0, 0, 1);
0f8a249a
BS		 400 ret = 0;
401 break;
e8af50a3 402 }
81ad8ba2
BS		 403 if (sign) {
404 switch(size) {
405 case 1:
406 T1 = (int8_t) ret;
e32664fb 407 break;
81ad8ba2
BS		 408 case 2:
409 T1 = (int16_t) ret;
e32664fb 410 break;
81ad8ba2
BS		 411 default:
412 T1 = ret;
413 break;
414 }
415 }
416 else
417 T1 = ret;
e8af50a3
FB		 418}
419
81ad8ba2 420void helper_st_asi(int asi, int size)
e8af50a3
FB		 421{
422 switch(asi) {
6c36d3fa 423 case 2: /* SuperSparc MXCC registers */
952a328f
BS		 424 switch (T0) {
425 case 0x01c00000: /* MXCC stream data register 0 */
426 if (size == 8)
427 env->mxccdata[0] = ((uint64_t)T1 << 32) | T2;
428 else
429 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", T0, size);
430 break;
431 case 0x01c00008: /* MXCC stream data register 1 */
432 if (size == 8)
433 env->mxccdata[1] = ((uint64_t)T1 << 32) | T2;
434 else
435 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", T0, size);
436 break;
437 case 0x01c00010: /* MXCC stream data register 2 */
438 if (size == 8)
439 env->mxccdata[2] = ((uint64_t)T1 << 32) | T2;
440 else
441 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", T0, size);
442 break;
443 case 0x01c00018: /* MXCC stream data register 3 */
444 if (size == 8)
445 env->mxccdata[3] = ((uint64_t)T1 << 32) | T2;
446 else
447 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", T0, size);
448 break;
449 case 0x01c00100: /* MXCC stream source */
450 if (size == 8)
451 env->mxccregs[0] = ((uint64_t)T1 << 32) | T2;
452 else
453 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", T0, size);
454 env->mxccdata[0] = ldq_phys((env->mxccregs[0] & 0xffffffffULL) + 0);
455 env->mxccdata[1] = ldq_phys((env->mxccregs[0] & 0xffffffffULL) + 8);
456 env->mxccdata[2] = ldq_phys((env->mxccregs[0] & 0xffffffffULL) + 16);
457 env->mxccdata[3] = ldq_phys((env->mxccregs[0] & 0xffffffffULL) + 24);
458 break;
459 case 0x01c00200: /* MXCC stream destination */
460 if (size == 8)
461 env->mxccregs[1] = ((uint64_t)T1 << 32) | T2;
462 else
463 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", T0, size);
464 stq_phys((env->mxccregs[1] & 0xffffffffULL) + 0, env->mxccdata[0]);
465 stq_phys((env->mxccregs[1] & 0xffffffffULL) + 8, env->mxccdata[1]);
466 stq_phys((env->mxccregs[1] & 0xffffffffULL) + 16, env->mxccdata[2]);
467 stq_phys((env->mxccregs[1] & 0xffffffffULL) + 24, env->mxccdata[3]);
468 break;
469 case 0x01c00a00: /* MXCC control register */
470 if (size == 8)
471 env->mxccregs[3] = ((uint64_t)T1 << 32) | T2;
472 else
473 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", T0, size);
474 break;
475 case 0x01c00a04: /* MXCC control register */
476 if (size == 4)
bd37ec21 477 env->mxccregs[3] = (env->mxccregs[0xa] & 0xffffffff00000000ULL) | T1;
952a328f
BS		 478 else
479 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", T0, size);
480 break;
481 case 0x01c00e00: /* MXCC error register */
bbf7d96b 482 // writing a 1 bit clears the error
952a328f 483 if (size == 8)
bbf7d96b 484 env->mxccregs[6] &= ~(((uint64_t)T1 << 32) | T2);
952a328f
BS		 485 else
486 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", T0, size);
952a328f
BS		 487 break;
488 case 0x01c00f00: /* MBus port address register */
489 if (size == 8)
490 env->mxccregs[7] = ((uint64_t)T1 << 32) | T2;
491 else
492 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", T0, size);
493 break;
494 default:
495 DPRINTF_MXCC("%08x: unimplemented address, size: %d\n", T0, size);
496 break;
497 }
498 DPRINTF_MXCC("asi = %d, size = %d, T0 = %08x, T1 = %08x\n", asi, size, T0, T1);
499#ifdef DEBUG_MXCC
500 dump_mxcc(env);
501#endif
6c36d3fa 502 break;
e8af50a3 503 case 3: /* MMU flush */
0f8a249a
BS		 504 {
505 int mmulev;
e80cfcfc 506
0f8a249a 507 mmulev = (T0 >> 8) & 15;
952a328f 508 DPRINTF_MMU("mmu flush level %d\n", mmulev);
0f8a249a
BS		 509 switch (mmulev) {
510 case 0: // flush page
511 tlb_flush_page(env, T0 & 0xfffff000);
512 break;
513 case 1: // flush segment (256k)
514 case 2: // flush region (16M)
515 case 3: // flush context (4G)
516 case 4: // flush entire
517 tlb_flush(env, 1);
518 break;
519 default:
520 break;
521 }
55754d9e 522#ifdef DEBUG_MMU
0f8a249a 523 dump_mmu(env);
55754d9e 524#endif
0f8a249a
BS		 525 return;
526 }
e8af50a3 527 case 4: /* write MMU regs */
0f8a249a 528 {
3dd9a152 529 int reg = (T0 >> 8) & 0x1f;
0f8a249a 530 uint32_t oldreg;
3b46e624 531
0f8a249a 532 oldreg = env->mmuregs[reg];
55754d9e
FB		 533 switch(reg) {
534 case 0:
3dd9a152
BS		 535 env->mmuregs[reg] = (env->mmuregs[reg] & 0xff000000) |
536 (T1 & 0x00ffffff);
0f8a249a
BS		 537 // Mappings generated during no-fault mode or MMU
538 // disabled mode are invalid in normal mode
3dd9a152
BS		 539 if ((oldreg & (MMU_E | MMU_NF | env->mmu_bm)) !=
540 (env->mmuregs[reg] & (MMU_E | MMU_NF | env->mmu_bm)))
55754d9e
FB		 541 tlb_flush(env, 1);
542 break;
543 case 2:
0f8a249a 544 env->mmuregs[reg] = T1;
55754d9e
FB		 545 if (oldreg != env->mmuregs[reg]) {
546 /* we flush when the MMU context changes because
547 QEMU has no MMU context support */
548 tlb_flush(env, 1);
549 }
550 break;
551 case 3:
552 case 4:
553 break;
3dd9a152
BS		 554 case 0x13:
555 env->mmuregs[3] = T1;
556 break;
557 case 0x14:
558 env->mmuregs[4] = T1;
559 break;
55754d9e 560 default:
0f8a249a 561 env->mmuregs[reg] = T1;
55754d9e
FB		 562 break;
563 }
55754d9e 564 if (oldreg != env->mmuregs[reg]) {
952a328f 565 DPRINTF_MMU("mmu change reg[%d]: 0x%08x -> 0x%08x\n", reg, oldreg, env->mmuregs[reg]);
55754d9e 566 }
952a328f 567#ifdef DEBUG_MMU
0f8a249a 568 dump_mmu(env);
55754d9e 569#endif
0f8a249a
BS		 570 return;
571 }
81ad8ba2
BS		 572 case 0xa: /* User data access */
573 switch(size) {
574 case 1:
575 stb_user(T0, T1);
576 break;
577 case 2:
578 stw_user(T0 & ~1, T1);
579 break;
580 default:
581 case 4:
582 stl_user(T0 & ~3, T1);
583 break;
584 case 8:
e909ec2f 585 stq_user(T0 & ~7, ((uint64_t)T1 << 32) | T2);
81ad8ba2
BS		 586 break;
587 }
588 break;
589 case 0xb: /* Supervisor data access */
590 switch(size) {
591 case 1:
592 stb_kernel(T0, T1);
593 break;
594 case 2:
595 stw_kernel(T0 & ~1, T1);
596 break;
597 default:
598 case 4:
599 stl_kernel(T0 & ~3, T1);
600 break;
601 case 8:
e909ec2f 602 stq_kernel(T0 & ~7, ((uint64_t)T1 << 32) | T2);
81ad8ba2
BS		 603 break;
604 }
605 break;
6c36d3fa
BS		 606 case 0xc: /* I-cache tag */
607 case 0xd: /* I-cache data */
608 case 0xe: /* D-cache tag */
609 case 0xf: /* D-cache data */
610 case 0x10: /* I/D-cache flush page */
611 case 0x11: /* I/D-cache flush segment */
612 case 0x12: /* I/D-cache flush region */
613 case 0x13: /* I/D-cache flush context */
614 case 0x14: /* I/D-cache flush user */
615 break;
e80cfcfc 616 case 0x17: /* Block copy, sta access */
0f8a249a
BS		 617 {
618 // value (T1) = src
619 // address (T0) = dst
620 // copy 32 bytes
6c36d3fa
BS		 621 unsigned int i;
622 uint32_t src = T1 & ~3, dst = T0 & ~3, temp;
3b46e624 623
6c36d3fa
BS		 624 for (i = 0; i < 32; i += 4, src += 4, dst += 4) {
625 temp = ldl_kernel(src);
626 stl_kernel(dst, temp);
627 }
0f8a249a
BS		 628 }
629 return;
e80cfcfc 630 case 0x1f: /* Block fill, stda access */
0f8a249a
BS		 631 {
632 // value (T1, T2)
633 // address (T0) = dst
634 // fill 32 bytes
6c36d3fa
BS		 635 unsigned int i;
636 uint32_t dst = T0 & 7;
637 uint64_t val;
e80cfcfc 638
6c36d3fa
BS		 639 val = (((uint64_t)T1) << 32) | T2;
640
641 for (i = 0; i < 32; i += 8, dst += 8)
642 stq_kernel(dst, val);
0f8a249a
BS		 643 }
644 return;
6c36d3fa 645 case 0x20: /* MMU passthrough */
0f8a249a 646 {
02aab46a
FB		 647 switch(size) {
648 case 1:
649 stb_phys(T0, T1);
650 break;
651 case 2:
652 stw_phys(T0 & ~1, T1);
653 break;
654 case 4:
655 default:
656 stl_phys(T0 & ~3, T1);
657 break;
9e61bde5 658 case 8:
e909ec2f 659 stq_phys(T0 & ~7, ((uint64_t)T1 << 32) | T2);
9e61bde5 660 break;
02aab46a 661 }
0f8a249a
BS		 662 }
663 return;
5dcb6b91
BS		 664 case 0x2e: /* MMU passthrough, 0xexxxxxxxx */
665 case 0x2f: /* MMU passthrough, 0xfxxxxxxxx */
0f8a249a 666 {
5dcb6b91
BS		 667 switch(size) {
668 case 1:
669 stb_phys((target_phys_addr_t)T0
670 | ((target_phys_addr_t)(asi & 0xf) << 32), T1);
671 break;
672 case 2:
673 stw_phys((target_phys_addr_t)(T0 & ~1)
674 | ((target_phys_addr_t)(asi & 0xf) << 32), T1);
675 break;
676 case 4:
677 default:
678 stl_phys((target_phys_addr_t)(T0 & ~3)
679 | ((target_phys_addr_t)(asi & 0xf) << 32), T1);
680 break;
681 case 8:
e909ec2f
BS		 682 stq_phys((target_phys_addr_t)(T0 & ~7)
683 | ((target_phys_addr_t)(asi & 0xf) << 32),
684 ((uint64_t)T1 << 32) | T2);
5dcb6b91
BS		 685 break;
686 }
0f8a249a
BS		 687 }
688 return;
6c36d3fa
BS		 689 case 0x31: /* Ross RT620 I-cache flush */
690 case 0x36: /* I-cache flash clear */
691 case 0x37: /* D-cache flash clear */
692 break;
693 case 9: /* Supervisor code access, XXX */
5dcb6b91 694 case 0x21 ... 0x2d: /* MMU passthrough, unassigned */
e8af50a3 695 default:
6c36d3fa 696 do_unassigned_access(T0, 1, 0, 1);
0f8a249a 697 return;
e8af50a3
FB		 698 }
699}
700
81ad8ba2
BS		 701#endif /* CONFIG_USER_ONLY */
702#else /* TARGET_SPARC64 */
703
704#ifdef CONFIG_USER_ONLY
705void helper_ld_asi(int asi, int size, int sign)
706{
707 uint64_t ret = 0;
708
709 if (asi < 0x80)
710 raise_exception(TT_PRIV_ACT);
711
712 switch (asi) {
713 case 0x80: // Primary
714 case 0x82: // Primary no-fault
715 case 0x88: // Primary LE
716 case 0x8a: // Primary no-fault LE
717 {
718 switch(size) {
719 case 1:
720 ret = ldub_raw(T0);
721 break;
722 case 2:
723 ret = lduw_raw(T0 & ~1);
724 break;
725 case 4:
726 ret = ldl_raw(T0 & ~3);
727 break;
728 default:
729 case 8:
730 ret = ldq_raw(T0 & ~7);
731 break;
732 }
733 }
734 break;
735 case 0x81: // Secondary
736 case 0x83: // Secondary no-fault
737 case 0x89: // Secondary LE
738 case 0x8b: // Secondary no-fault LE
739 // XXX
740 break;
741 default:
742 break;
743 }
744
745 /* Convert from little endian */
746 switch (asi) {
747 case 0x88: // Primary LE
748 case 0x89: // Secondary LE
749 case 0x8a: // Primary no-fault LE
750 case 0x8b: // Secondary no-fault LE
751 switch(size) {
752 case 2:
753 ret = bswap16(ret);
e32664fb 754 break;
81ad8ba2
BS		 755 case 4:
756 ret = bswap32(ret);
e32664fb 757 break;
81ad8ba2
BS		 758 case 8:
759 ret = bswap64(ret);
e32664fb 760 break;
81ad8ba2
BS		 761 default:
762 break;
763 }
764 default:
765 break;
766 }
767
768 /* Convert to signed number */
769 if (sign) {
770 switch(size) {
771 case 1:
772 ret = (int8_t) ret;
e32664fb 773 break;
81ad8ba2
BS		 774 case 2:
775 ret = (int16_t) ret;
e32664fb 776 break;
81ad8ba2
BS		 777 case 4:
778 ret = (int32_t) ret;
e32664fb 779 break;
81ad8ba2
BS		 780 default:
781 break;
782 }
783 }
784 T1 = ret;
785}
786
787void helper_st_asi(int asi, int size)
788{
789 if (asi < 0x80)
790 raise_exception(TT_PRIV_ACT);
791
792 /* Convert to little endian */
793 switch (asi) {
794 case 0x88: // Primary LE
795 case 0x89: // Secondary LE
796 switch(size) {
797 case 2:
798 T0 = bswap16(T0);
e32664fb 799 break;
81ad8ba2
BS		 800 case 4:
801 T0 = bswap32(T0);
e32664fb 802 break;
81ad8ba2
BS		 803 case 8:
804 T0 = bswap64(T0);
e32664fb 805 break;
81ad8ba2
BS		 806 default:
807 break;
808 }
809 default:
810 break;
811 }
812
813 switch(asi) {
814 case 0x80: // Primary
815 case 0x88: // Primary LE
816 {
817 switch(size) {
818 case 1:
819 stb_raw(T0, T1);
820 break;
821 case 2:
822 stw_raw(T0 & ~1, T1);
823 break;
824 case 4:
825 stl_raw(T0 & ~3, T1);
826 break;
827 case 8:
828 default:
829 stq_raw(T0 & ~7, T1);
830 break;
831 }
832 }
833 break;
834 case 0x81: // Secondary
835 case 0x89: // Secondary LE
836 // XXX
837 return;
838
839 case 0x82: // Primary no-fault, RO
840 case 0x83: // Secondary no-fault, RO
841 case 0x8a: // Primary no-fault LE, RO
842 case 0x8b: // Secondary no-fault LE, RO
843 default:
844 do_unassigned_access(T0, 1, 0, 1);
845 return;
846 }
847}
848
849#else /* CONFIG_USER_ONLY */
3475187d
FB		 850
851void helper_ld_asi(int asi, int size, int sign)
852{
83469015 853 uint64_t ret = 0;
3475187d 854
6f27aba6 855 if ((asi < 0x80 && (env->pstate & PS_PRIV) == 0)
20b749f6 856 || (asi >= 0x30 && asi < 0x80 && !(env->hpstate & HS_PRIV)))
0f8a249a 857 raise_exception(TT_PRIV_ACT);
3475187d
FB		 858
859 switch (asi) {
81ad8ba2
BS		 860 case 0x10: // As if user primary
861 case 0x18: // As if user primary LE
862 case 0x80: // Primary
863 case 0x82: // Primary no-fault
864 case 0x88: // Primary LE
865 case 0x8a: // Primary no-fault LE
866 if ((asi & 0x80) && (env->pstate & PS_PRIV)) {
6f27aba6
BS		 867 if (env->hpstate & HS_PRIV) {
868 switch(size) {
869 case 1:
870 ret = ldub_hypv(T0);
871 break;
872 case 2:
873 ret = lduw_hypv(T0 & ~1);
874 break;
875 case 4:
876 ret = ldl_hypv(T0 & ~3);
877 break;
878 default:
879 case 8:
880 ret = ldq_hypv(T0 & ~7);
881 break;
882 }
883 } else {
884 switch(size) {
885 case 1:
886 ret = ldub_kernel(T0);
887 break;
888 case 2:
889 ret = lduw_kernel(T0 & ~1);
890 break;
891 case 4:
892 ret = ldl_kernel(T0 & ~3);
893 break;
894 default:
895 case 8:
896 ret = ldq_kernel(T0 & ~7);
897 break;
898 }
81ad8ba2
BS		 899 }
900 } else {
901 switch(size) {
902 case 1:
903 ret = ldub_user(T0);
904 break;
905 case 2:
906 ret = lduw_user(T0 & ~1);
907 break;
908 case 4:
909 ret = ldl_user(T0 & ~3);
910 break;
911 default:
912 case 8:
913 ret = ldq_user(T0 & ~7);
914 break;
915 }
916 }
917 break;
3475187d
FB		 918 case 0x14: // Bypass
919 case 0x15: // Bypass, non-cacheable
81ad8ba2
BS		 920 case 0x1c: // Bypass LE
921 case 0x1d: // Bypass, non-cacheable LE
0f8a249a 922 {
02aab46a
FB		 923 switch(size) {
924 case 1:
925 ret = ldub_phys(T0);
926 break;
927 case 2:
928 ret = lduw_phys(T0 & ~1);
929 break;
930 case 4:
931 ret = ldl_phys(T0 & ~3);
932 break;
933 default:
934 case 8:
935 ret = ldq_phys(T0 & ~7);
936 break;
937 }
0f8a249a
BS		 938 break;
939 }
83469015
FB		 940 case 0x04: // Nucleus
941 case 0x0c: // Nucleus Little Endian (LE)
83469015 942 case 0x11: // As if user secondary
83469015 943 case 0x19: // As if user secondary LE
83469015
FB		 944 case 0x24: // Nucleus quad LDD 128 bit atomic
945 case 0x2c: // Nucleus quad LDD 128 bit atomic
946 case 0x4a: // UPA config
81ad8ba2 947 case 0x81: // Secondary
83469015 948 case 0x83: // Secondary no-fault
83469015 949 case 0x89: // Secondary LE
83469015 950 case 0x8b: // Secondary no-fault LE
0f8a249a
BS		 951 // XXX
952 break;
3475187d 953 case 0x45: // LSU
0f8a249a
BS		 954 ret = env->lsu;
955 break;
3475187d 956 case 0x50: // I-MMU regs
0f8a249a
BS		 957 {
958 int reg = (T0 >> 3) & 0xf;
3475187d 959
0f8a249a
BS		 960 ret = env->immuregs[reg];
961 break;
962 }
3475187d
FB		 963 case 0x51: // I-MMU 8k TSB pointer
964 case 0x52: // I-MMU 64k TSB pointer
965 case 0x55: // I-MMU data access
0f8a249a
BS		 966 // XXX
967 break;
83469015 968 case 0x56: // I-MMU tag read
0f8a249a
BS		 969 {
970 unsigned int i;
971
972 for (i = 0; i < 64; i++) {
973 // Valid, ctx match, vaddr match
974 if ((env->itlb_tte[i] & 0x8000000000000000ULL) != 0 &&
975 env->itlb_tag[i] == T0) {
976 ret = env->itlb_tag[i];
977 break;
978 }
979 }
980 break;
981 }
3475187d 982 case 0x58: // D-MMU regs
0f8a249a
BS		 983 {
984 int reg = (T0 >> 3) & 0xf;
3475187d 985
0f8a249a
BS		 986 ret = env->dmmuregs[reg];
987 break;
988 }
83469015 989 case 0x5e: // D-MMU tag read
0f8a249a
BS		 990 {
991 unsigned int i;
992
993 for (i = 0; i < 64; i++) {
994 // Valid, ctx match, vaddr match
995 if ((env->dtlb_tte[i] & 0x8000000000000000ULL) != 0 &&
996 env->dtlb_tag[i] == T0) {
997 ret = env->dtlb_tag[i];
998 break;
999 }
1000 }
1001 break;
1002 }
3475187d
FB		 1003 case 0x59: // D-MMU 8k TSB pointer
1004 case 0x5a: // D-MMU 64k TSB pointer
1005 case 0x5b: // D-MMU data pointer
1006 case 0x5d: // D-MMU data access
83469015
FB		 1007 case 0x48: // Interrupt dispatch, RO
1008 case 0x49: // Interrupt data receive
1009 case 0x7f: // Incoming interrupt vector, RO
0f8a249a
BS		 1010 // XXX
1011 break;
3475187d
FB		 1012 case 0x54: // I-MMU data in, WO
1013 case 0x57: // I-MMU demap, WO
1014 case 0x5c: // D-MMU data in, WO
1015 case 0x5f: // D-MMU demap, WO
83469015 1016 case 0x77: // Interrupt vector, WO
3475187d 1017 default:
6c36d3fa 1018 do_unassigned_access(T0, 0, 0, 1);
0f8a249a
BS		 1019 ret = 0;
1020 break;
3475187d 1021 }
81ad8ba2
BS		 1022
1023 /* Convert from little endian */
1024 switch (asi) {
1025 case 0x0c: // Nucleus Little Endian (LE)
1026 case 0x18: // As if user primary LE
1027 case 0x19: // As if user secondary LE
1028 case 0x1c: // Bypass LE
1029 case 0x1d: // Bypass, non-cacheable LE
1030 case 0x88: // Primary LE
1031 case 0x89: // Secondary LE
1032 case 0x8a: // Primary no-fault LE
1033 case 0x8b: // Secondary no-fault LE
1034 switch(size) {
1035 case 2:
1036 ret = bswap16(ret);
e32664fb 1037 break;
81ad8ba2
BS		 1038 case 4:
1039 ret = bswap32(ret);
e32664fb 1040 break;
81ad8ba2
BS		 1041 case 8:
1042 ret = bswap64(ret);
e32664fb 1043 break;
81ad8ba2
BS		 1044 default:
1045 break;
1046 }
1047 default:
1048 break;
1049 }
1050
1051 /* Convert to signed number */
1052 if (sign) {
1053 switch(size) {
1054 case 1:
1055 ret = (int8_t) ret;
e32664fb 1056 break;
81ad8ba2
BS		 1057 case 2:
1058 ret = (int16_t) ret;
e32664fb 1059 break;
81ad8ba2
BS		 1060 case 4:
1061 ret = (int32_t) ret;
e32664fb 1062 break;
81ad8ba2
BS		 1063 default:
1064 break;
1065 }
1066 }
3475187d
FB		 1067 T1 = ret;
1068}
1069
81ad8ba2 1070void helper_st_asi(int asi, int size)
3475187d 1071{
6f27aba6 1072 if ((asi < 0x80 && (env->pstate & PS_PRIV) == 0)
20b749f6 1073 || (asi >= 0x30 && asi < 0x80 && !(env->hpstate & HS_PRIV)))
0f8a249a 1074 raise_exception(TT_PRIV_ACT);
3475187d 1075
81ad8ba2
BS		 1076 /* Convert to little endian */
1077 switch (asi) {
1078 case 0x0c: // Nucleus Little Endian (LE)
1079 case 0x18: // As if user primary LE
1080 case 0x19: // As if user secondary LE
1081 case 0x1c: // Bypass LE
1082 case 0x1d: // Bypass, non-cacheable LE
81ad8ba2
BS		 1083 case 0x88: // Primary LE
1084 case 0x89: // Secondary LE
1085 switch(size) {
1086 case 2:
1087 T0 = bswap16(T0);
e32664fb 1088 break;
81ad8ba2
BS		 1089 case 4:
1090 T0 = bswap32(T0);
e32664fb 1091 break;
81ad8ba2
BS		 1092 case 8:
1093 T0 = bswap64(T0);
e32664fb 1094 break;
81ad8ba2
BS		 1095 default:
1096 break;
1097 }
1098 default:
1099 break;
1100 }
1101
3475187d 1102 switch(asi) {
81ad8ba2
BS		 1103 case 0x10: // As if user primary
1104 case 0x18: // As if user primary LE
1105 case 0x80: // Primary
1106 case 0x88: // Primary LE
1107 if ((asi & 0x80) && (env->pstate & PS_PRIV)) {
6f27aba6
BS		 1108 if (env->hpstate & HS_PRIV) {
1109 switch(size) {
1110 case 1:
1111 stb_hypv(T0, T1);
1112 break;
1113 case 2:
1114 stw_hypv(T0 & ~1, T1);
1115 break;
1116 case 4:
1117 stl_hypv(T0 & ~3, T1);
1118 break;
1119 case 8:
1120 default:
1121 stq_hypv(T0 & ~7, T1);
1122 break;
1123 }
1124 } else {
1125 switch(size) {
1126 case 1:
1127 stb_kernel(T0, T1);
1128 break;
1129 case 2:
1130 stw_kernel(T0 & ~1, T1);
1131 break;
1132 case 4:
1133 stl_kernel(T0 & ~3, T1);
1134 break;
1135 case 8:
1136 default:
1137 stq_kernel(T0 & ~7, T1);
1138 break;
1139 }
81ad8ba2
BS		 1140 }
1141 } else {
1142 switch(size) {
1143 case 1:
1144 stb_user(T0, T1);
1145 break;
1146 case 2:
1147 stw_user(T0 & ~1, T1);
1148 break;
1149 case 4:
1150 stl_user(T0 & ~3, T1);
1151 break;
1152 case 8:
1153 default:
1154 stq_user(T0 & ~7, T1);
1155 break;
1156 }
1157 }
1158 break;
3475187d
FB		 1159 case 0x14: // Bypass
1160 case 0x15: // Bypass, non-cacheable
81ad8ba2
BS		 1161 case 0x1c: // Bypass LE
1162 case 0x1d: // Bypass, non-cacheable LE
0f8a249a 1163 {
02aab46a
FB		 1164 switch(size) {
1165 case 1:
1166 stb_phys(T0, T1);
1167 break;
1168 case 2:
1169 stw_phys(T0 & ~1, T1);
1170 break;
1171 case 4:
1172 stl_phys(T0 & ~3, T1);
1173 break;
1174 case 8:
1175 default:
1176 stq_phys(T0 & ~7, T1);
1177 break;
1178 }
0f8a249a
BS		 1179 }
1180 return;
83469015
FB		 1181 case 0x04: // Nucleus
1182 case 0x0c: // Nucleus Little Endian (LE)
83469015 1183 case 0x11: // As if user secondary
83469015 1184 case 0x19: // As if user secondary LE
83469015
FB		 1185 case 0x24: // Nucleus quad LDD 128 bit atomic
1186 case 0x2c: // Nucleus quad LDD 128 bit atomic
1187 case 0x4a: // UPA config
51996525 1188 case 0x81: // Secondary
83469015 1189 case 0x89: // Secondary LE
0f8a249a
BS		 1190 // XXX
1191 return;
3475187d 1192 case 0x45: // LSU
0f8a249a
BS		 1193 {
1194 uint64_t oldreg;
1195
1196 oldreg = env->lsu;
1197 env->lsu = T1 & (DMMU_E | IMMU_E);
1198 // Mappings generated during D/I MMU disabled mode are
1199 // invalid in normal mode
1200 if (oldreg != env->lsu) {
952a328f 1201 DPRINTF_MMU("LSU change: 0x%" PRIx64 " -> 0x%" PRIx64 "\n", oldreg, env->lsu);
83469015 1202#ifdef DEBUG_MMU
0f8a249a 1203 dump_mmu(env);
83469015 1204#endif
0f8a249a
BS		 1205 tlb_flush(env, 1);
1206 }
1207 return;
1208 }
3475187d 1209 case 0x50: // I-MMU regs
0f8a249a
BS		 1210 {
1211 int reg = (T0 >> 3) & 0xf;
1212 uint64_t oldreg;
3b46e624 1213
0f8a249a 1214 oldreg = env->immuregs[reg];
3475187d
FB		 1215 switch(reg) {
1216 case 0: // RO
1217 case 4:
1218 return;
1219 case 1: // Not in I-MMU
1220 case 2:
1221 case 7:
1222 case 8:
1223 return;
1224 case 3: // SFSR
0f8a249a
BS		 1225 if ((T1 & 1) == 0)
1226 T1 = 0; // Clear SFSR
3475187d
FB		 1227 break;
1228 case 5: // TSB access
1229 case 6: // Tag access
1230 default:
1231 break;
1232 }
0f8a249a 1233 env->immuregs[reg] = T1;
3475187d 1234 if (oldreg != env->immuregs[reg]) {
952a328f 1235 DPRINTF_MMU("mmu change reg[%d]: 0x%08" PRIx64 " -> 0x%08" PRIx64 "\n", reg, oldreg, env->immuregs[reg]);
3475187d 1236 }
952a328f 1237#ifdef DEBUG_MMU
0f8a249a 1238 dump_mmu(env);
3475187d 1239#endif
0f8a249a
BS		 1240 return;
1241 }
3475187d 1242 case 0x54: // I-MMU data in
0f8a249a
BS		 1243 {
1244 unsigned int i;
1245
1246 // Try finding an invalid entry
1247 for (i = 0; i < 64; i++) {
1248 if ((env->itlb_tte[i] & 0x8000000000000000ULL) == 0) {
1249 env->itlb_tag[i] = env->immuregs[6];
1250 env->itlb_tte[i] = T1;
1251 return;
1252 }
1253 }
1254 // Try finding an unlocked entry
1255 for (i = 0; i < 64; i++) {
1256 if ((env->itlb_tte[i] & 0x40) == 0) {
1257 env->itlb_tag[i] = env->immuregs[6];
1258 env->itlb_tte[i] = T1;
1259 return;
1260 }
1261 }
1262 // error state?
1263 return;
1264 }
3475187d 1265 case 0x55: // I-MMU data access
0f8a249a
BS		 1266 {
1267 unsigned int i = (T0 >> 3) & 0x3f;
3475187d 1268
0f8a249a
BS		 1269 env->itlb_tag[i] = env->immuregs[6];
1270 env->itlb_tte[i] = T1;
1271 return;
1272 }
3475187d 1273 case 0x57: // I-MMU demap
0f8a249a
BS		 1274 // XXX
1275 return;
3475187d 1276 case 0x58: // D-MMU regs
0f8a249a
BS		 1277 {
1278 int reg = (T0 >> 3) & 0xf;
1279 uint64_t oldreg;
3b46e624 1280
0f8a249a 1281 oldreg = env->dmmuregs[reg];
3475187d
FB		 1282 switch(reg) {
1283 case 0: // RO
1284 case 4:
1285 return;
1286 case 3: // SFSR
0f8a249a
BS		 1287 if ((T1 & 1) == 0) {
1288 T1 = 0; // Clear SFSR, Fault address
1289 env->dmmuregs[4] = 0;
1290 }
1291 env->dmmuregs[reg] = T1;
3475187d
FB		 1292 break;
1293 case 1: // Primary context
1294 case 2: // Secondary context
1295 case 5: // TSB access
1296 case 6: // Tag access
1297 case 7: // Virtual Watchpoint
1298 case 8: // Physical Watchpoint
1299 default:
1300 break;
1301 }
0f8a249a 1302 env->dmmuregs[reg] = T1;
3475187d 1303 if (oldreg != env->dmmuregs[reg]) {
952a328f 1304 DPRINTF_MMU("mmu change reg[%d]: 0x%08" PRIx64 " -> 0x%08" PRIx64 "\n", reg, oldreg, env->dmmuregs[reg]);
3475187d 1305 }
952a328f 1306#ifdef DEBUG_MMU
0f8a249a 1307 dump_mmu(env);
3475187d 1308#endif
0f8a249a
BS		 1309 return;
1310 }
3475187d 1311 case 0x5c: // D-MMU data in
0f8a249a
BS		 1312 {
1313 unsigned int i;
1314
1315 // Try finding an invalid entry
1316 for (i = 0; i < 64; i++) {
1317 if ((env->dtlb_tte[i] & 0x8000000000000000ULL) == 0) {
1318 env->dtlb_tag[i] = env->dmmuregs[6];
1319 env->dtlb_tte[i] = T1;
1320 return;
1321 }
1322 }
1323 // Try finding an unlocked entry
1324 for (i = 0; i < 64; i++) {
1325 if ((env->dtlb_tte[i] & 0x40) == 0) {
1326 env->dtlb_tag[i] = env->dmmuregs[6];
1327 env->dtlb_tte[i] = T1;
1328 return;
1329 }
1330 }
1331 // error state?
1332 return;
1333 }
3475187d 1334 case 0x5d: // D-MMU data access
0f8a249a
BS		 1335 {
1336 unsigned int i = (T0 >> 3) & 0x3f;
3475187d 1337
0f8a249a
BS		 1338 env->dtlb_tag[i] = env->dmmuregs[6];
1339 env->dtlb_tte[i] = T1;
1340 return;
1341 }
3475187d 1342 case 0x5f: // D-MMU demap
83469015 1343 case 0x49: // Interrupt data receive
0f8a249a
BS		 1344 // XXX
1345 return;
3475187d
FB		 1346 case 0x51: // I-MMU 8k TSB pointer, RO
1347 case 0x52: // I-MMU 64k TSB pointer, RO
1348 case 0x56: // I-MMU tag read, RO
1349 case 0x59: // D-MMU 8k TSB pointer, RO
1350 case 0x5a: // D-MMU 64k TSB pointer, RO
1351 case 0x5b: // D-MMU data pointer, RO
1352 case 0x5e: // D-MMU tag read, RO
83469015
FB		 1353 case 0x48: // Interrupt dispatch, RO
1354 case 0x7f: // Incoming interrupt vector, RO
1355 case 0x82: // Primary no-fault, RO
1356 case 0x83: // Secondary no-fault, RO
1357 case 0x8a: // Primary no-fault LE, RO
1358 case 0x8b: // Secondary no-fault LE, RO
3475187d 1359 default:
6c36d3fa 1360 do_unassigned_access(T0, 1, 0, 1);
0f8a249a 1361 return;
3475187d
FB		 1362 }
1363}
81ad8ba2 1364#endif /* CONFIG_USER_ONLY */
3391c818
BS		 1365
1366void helper_ldf_asi(int asi, int size, int rd)
1367{
1368 target_ulong tmp_T0 = T0, tmp_T1 = T1;
1369 unsigned int i;
1370
1371 switch (asi) {
1372 case 0xf0: // Block load primary
1373 case 0xf1: // Block load secondary
1374 case 0xf8: // Block load primary LE
1375 case 0xf9: // Block load secondary LE
51996525
BS		 1376 if (rd & 7) {
1377 raise_exception(TT_ILL_INSN);
1378 return;
1379 }
1380 if (T0 & 0x3f) {
1381 raise_exception(TT_UNALIGNED);
1382 return;
1383 }
1384 for (i = 0; i < 16; i++) {
1385 helper_ld_asi(asi & 0x8f, 4, 0);
1386 *(uint32_t *)&env->fpr[rd++] = T1;
1387 T0 += 4;
3391c818
BS		 1388 }
1389 T0 = tmp_T0;
1390 T1 = tmp_T1;
1391
1392 return;
1393 default:
1394 break;
1395 }
1396
1397 helper_ld_asi(asi, size, 0);
1398 switch(size) {
1399 default:
1400 case 4:
1401 *((uint32_t *)&FT0) = T1;
1402 break;
1403 case 8:
1404 *((int64_t *)&DT0) = T1;
1405 break;
1f587329
BS		 1406#if defined(CONFIG_USER_ONLY)
1407 case 16:
1408 // XXX
1409 break;
1410#endif
3391c818
BS		 1411 }
1412 T1 = tmp_T1;
1413}
1414
1415void helper_stf_asi(int asi, int size, int rd)
1416{
1417 target_ulong tmp_T0 = T0, tmp_T1 = T1;
1418 unsigned int i;
1419
1420 switch (asi) {
1421 case 0xf0: // Block store primary
1422 case 0xf1: // Block store secondary
1423 case 0xf8: // Block store primary LE
1424 case 0xf9: // Block store secondary LE
51996525
BS		 1425 if (rd & 7) {
1426 raise_exception(TT_ILL_INSN);
1427 return;
1428 }
1429 if (T0 & 0x3f) {
1430 raise_exception(TT_UNALIGNED);
1431 return;
1432 }
1433 for (i = 0; i < 16; i++) {
1434 T1 = *(uint32_t *)&env->fpr[rd++];
1435 helper_st_asi(asi & 0x8f, 4);
1436 T0 += 4;
3391c818
BS		 1437 }
1438 T0 = tmp_T0;
1439 T1 = tmp_T1;
1440
1441 return;
1442 default:
1443 break;
1444 }
1445
1446 switch(size) {
1447 default:
1448 case 4:
1449 T1 = *((uint32_t *)&FT0);
1450 break;
1451 case 8:
1452 T1 = *((int64_t *)&DT0);
1453 break;
1f587329
BS		 1454#if defined(CONFIG_USER_ONLY)
1455 case 16:
1456 // XXX
1457 break;
1458#endif
3391c818
BS		 1459 }
1460 helper_st_asi(asi, size);
1461 T1 = tmp_T1;
1462}
1463
81ad8ba2 1464#endif /* TARGET_SPARC64 */
3475187d
FB		 1465
1466#ifndef TARGET_SPARC64
a0c4cb4a 1467void helper_rett()
e8af50a3 1468{
af7bf89b
FB		 1469 unsigned int cwp;
1470
d4218d99
BS		 1471 if (env->psret == 1)
1472 raise_exception(TT_ILL_INSN);
1473
e8af50a3 1474 env->psret = 1;
5fafdf24 1475 cwp = (env->cwp + 1) & (NWINDOWS - 1);
e8af50a3
FB		 1476 if (env->wim & (1 << cwp)) {
1477 raise_exception(TT_WIN_UNF);
1478 }
1479 set_cwp(cwp);
1480 env->psrs = env->psrps;
1481}
3475187d 1482#endif
e8af50a3 1483
8d5f07fa 1484void helper_ldfsr(void)
e8af50a3 1485{
7a0e1f41 1486 int rnd_mode;
e8af50a3
FB		 1487 switch (env->fsr & FSR_RD_MASK) {
1488 case FSR_RD_NEAREST:
7a0e1f41 1489 rnd_mode = float_round_nearest_even;
0f8a249a 1490 break;
ed910241 1491 default:
e8af50a3 1492 case FSR_RD_ZERO:
7a0e1f41 1493 rnd_mode = float_round_to_zero;
0f8a249a 1494 break;
e8af50a3 1495 case FSR_RD_POS:
7a0e1f41 1496 rnd_mode = float_round_up;
0f8a249a 1497 break;
e8af50a3 1498 case FSR_RD_NEG:
7a0e1f41 1499 rnd_mode = float_round_down;
0f8a249a 1500 break;
e8af50a3 1501 }
7a0e1f41 1502 set_float_rounding_mode(rnd_mode, &env->fp_status);
e8af50a3 1503}
e80cfcfc 1504
e80cfcfc
FB		 1505void helper_debug()
1506{
1507 env->exception_index = EXCP_DEBUG;
1508 cpu_loop_exit();
1509}
af7bf89b 1510
3475187d 1511#ifndef TARGET_SPARC64
af7bf89b
FB		 1512void do_wrpsr()
1513{
d4218d99
BS		 1514 if ((T0 & PSR_CWP) >= NWINDOWS)
1515 raise_exception(TT_ILL_INSN);
1516 else
1517 PUT_PSR(env, T0);
af7bf89b
FB		 1518}
1519
1520void do_rdpsr()
1521{
1522 T0 = GET_PSR(env);
1523}
3475187d
FB		 1524
1525#else
1526
1527void do_popc()
1528{
eed152bb 1529 T0 = ctpop64(T1);
3475187d 1530}
83469015
FB		 1531
1532static inline uint64_t *get_gregset(uint64_t pstate)
1533{
1534 switch (pstate) {
1535 default:
1536 case 0:
0f8a249a 1537 return env->bgregs;
83469015 1538 case PS_AG:
0f8a249a 1539 return env->agregs;
83469015 1540 case PS_MG:
0f8a249a 1541 return env->mgregs;
83469015 1542 case PS_IG:
0f8a249a 1543 return env->igregs;
83469015
FB		 1544 }
1545}
1546
8f1f22f6 1547static inline void change_pstate(uint64_t new_pstate)
83469015 1548{
8f1f22f6 1549 uint64_t pstate_regs, new_pstate_regs;
83469015
FB		 1550 uint64_t *src, *dst;
1551
83469015
FB		 1552 pstate_regs = env->pstate & 0xc01;
1553 new_pstate_regs = new_pstate & 0xc01;
1554 if (new_pstate_regs != pstate_regs) {
0f8a249a
BS		 1555 // Switch global register bank
1556 src = get_gregset(new_pstate_regs);
1557 dst = get_gregset(pstate_regs);
1558 memcpy32(dst, env->gregs);
1559 memcpy32(env->gregs, src);
83469015
FB		 1560 }
1561 env->pstate = new_pstate;
1562}
1563
8f1f22f6
BS		 1564void do_wrpstate(void)
1565{
1566 change_pstate(T0 & 0xf3f);
1567}
1568
83469015
FB		 1569void do_done(void)
1570{
1571 env->tl--;
1572 env->pc = env->tnpc[env->tl];
1573 env->npc = env->tnpc[env->tl] + 4;
1574 PUT_CCR(env, env->tstate[env->tl] >> 32);
1575 env->asi = (env->tstate[env->tl] >> 24) & 0xff;
8f1f22f6 1576 change_pstate((env->tstate[env->tl] >> 8) & 0xf3f);
17d996e1 1577 PUT_CWP64(env, env->tstate[env->tl] & 0xff);
83469015
FB		 1578}
1579
1580void do_retry(void)
1581{
1582 env->tl--;
1583 env->pc = env->tpc[env->tl];
1584 env->npc = env->tnpc[env->tl];
1585 PUT_CCR(env, env->tstate[env->tl] >> 32);
1586 env->asi = (env->tstate[env->tl] >> 24) & 0xff;
8f1f22f6 1587 change_pstate((env->tstate[env->tl] >> 8) & 0xf3f);
17d996e1 1588 PUT_CWP64(env, env->tstate[env->tl] & 0xff);
83469015 1589}
3475187d 1590#endif
ee5bbe38
FB		 1591
1592void set_cwp(int new_cwp)
1593{
1594 /* put the modified wrap registers at their proper location */
1595 if (env->cwp == (NWINDOWS - 1))
1596 memcpy32(env->regbase, env->regbase + NWINDOWS * 16);
1597 env->cwp = new_cwp;
1598 /* put the wrap registers at their temporary location */
1599 if (new_cwp == (NWINDOWS - 1))
1600 memcpy32(env->regbase + NWINDOWS * 16, env->regbase);
1601 env->regwptr = env->regbase + (new_cwp * 16);
1602 REGWPTR = env->regwptr;
1603}
1604
1605void cpu_set_cwp(CPUState *env1, int new_cwp)
1606{
1607 CPUState *saved_env;
1608#ifdef reg_REGWPTR
1609 target_ulong *saved_regwptr;
1610#endif
1611
1612 saved_env = env;
1613#ifdef reg_REGWPTR
1614 saved_regwptr = REGWPTR;
1615#endif
1616 env = env1;
1617 set_cwp(new_cwp);
1618 env = saved_env;
1619#ifdef reg_REGWPTR
1620 REGWPTR = saved_regwptr;
1621#endif
1622}
1623
1624#ifdef TARGET_SPARC64
1625void do_interrupt(int intno)
1626{
1627#ifdef DEBUG_PCALL
1628 if (loglevel & CPU_LOG_INT) {
0f8a249a
BS		 1629 static int count;
1630 fprintf(logfile, "%6d: v=%04x pc=%016" PRIx64 " npc=%016" PRIx64 " SP=%016" PRIx64 "\n",
ee5bbe38
FB		 1631 count, intno,
1632 env->pc,
1633 env->npc, env->regwptr[6]);
0f8a249a 1634 cpu_dump_state(env, logfile, fprintf, 0);
ee5bbe38 1635#if 0
0f8a249a
BS		 1636 {
1637 int i;
1638 uint8_t *ptr;
1639
1640 fprintf(logfile, " code=");
1641 ptr = (uint8_t *)env->pc;
1642 for(i = 0; i < 16; i++) {
1643 fprintf(logfile, " %02x", ldub(ptr + i));
1644 }
1645 fprintf(logfile, "\n");
1646 }
ee5bbe38 1647#endif
0f8a249a 1648 count++;
ee5bbe38
FB		 1649 }
1650#endif
5fafdf24 1651#if !defined(CONFIG_USER_ONLY)
83469015 1652 if (env->tl == MAXTL) {
c68ea704 1653 cpu_abort(env, "Trap 0x%04x while trap level is MAXTL, Error state", env->exception_index);
0f8a249a 1654 return;
ee5bbe38
FB		 1655 }
1656#endif
1657 env->tstate[env->tl] = ((uint64_t)GET_CCR(env) << 32) | ((env->asi & 0xff) << 24) |
0f8a249a 1658 ((env->pstate & 0xf3f) << 8) | GET_CWP64(env);
ee5bbe38
FB		 1659 env->tpc[env->tl] = env->pc;
1660 env->tnpc[env->tl] = env->npc;
1661 env->tt[env->tl] = intno;
8f1f22f6
BS		 1662 change_pstate(PS_PEF | PS_PRIV | PS_AG);
1663
1664 if (intno == TT_CLRWIN)
1665 set_cwp((env->cwp - 1) & (NWINDOWS - 1));
1666 else if ((intno & 0x1c0) == TT_SPILL)
1667 set_cwp((env->cwp - env->cansave - 2) & (NWINDOWS - 1));
1668 else if ((intno & 0x1c0) == TT_FILL)
1669 set_cwp((env->cwp + 1) & (NWINDOWS - 1));
83469015
FB		 1670 env->tbr &= ~0x7fffULL;
1671 env->tbr |= ((env->tl > 1) ? 1 << 14 : 0) | (intno << 5);
1672 if (env->tl < MAXTL - 1) {
0f8a249a 1673 env->tl++;
83469015 1674 } else {
0f8a249a
BS		 1675 env->pstate |= PS_RED;
1676 if (env->tl != MAXTL)
1677 env->tl++;
83469015 1678 }
ee5bbe38
FB		 1679 env->pc = env->tbr;
1680 env->npc = env->pc + 4;
1681 env->exception_index = 0;
1682}
1683#else
1684void do_interrupt(int intno)
1685{
1686 int cwp;
1687
1688#ifdef DEBUG_PCALL
1689 if (loglevel & CPU_LOG_INT) {
0f8a249a
BS		 1690 static int count;
1691 fprintf(logfile, "%6d: v=%02x pc=%08x npc=%08x SP=%08x\n",
ee5bbe38
FB		 1692 count, intno,
1693 env->pc,
1694 env->npc, env->regwptr[6]);
0f8a249a 1695 cpu_dump_state(env, logfile, fprintf, 0);
ee5bbe38 1696#if 0
0f8a249a
BS		 1697 {
1698 int i;
1699 uint8_t *ptr;
1700
1701 fprintf(logfile, " code=");
1702 ptr = (uint8_t *)env->pc;
1703 for(i = 0; i < 16; i++) {
1704 fprintf(logfile, " %02x", ldub(ptr + i));
1705 }
1706 fprintf(logfile, "\n");
1707 }
ee5bbe38 1708#endif
0f8a249a 1709 count++;
ee5bbe38
FB		 1710 }
1711#endif
5fafdf24 1712#if !defined(CONFIG_USER_ONLY)
ee5bbe38 1713 if (env->psret == 0) {
c68ea704 1714 cpu_abort(env, "Trap 0x%02x while interrupts disabled, Error state", env->exception_index);
0f8a249a 1715 return;
ee5bbe38
FB		 1716 }
1717#endif
1718 env->psret = 0;
5fafdf24 1719 cwp = (env->cwp - 1) & (NWINDOWS - 1);
ee5bbe38
FB		 1720 set_cwp(cwp);
1721 env->regwptr[9] = env->pc;
1722 env->regwptr[10] = env->npc;
1723 env->psrps = env->psrs;
1724 env->psrs = 1;
1725 env->tbr = (env->tbr & TBR_BASE_MASK) | (intno << 4);
1726 env->pc = env->tbr;
1727 env->npc = env->pc + 4;
1728 env->exception_index = 0;
1729}
1730#endif
1731
5fafdf24 1732#if !defined(CONFIG_USER_ONLY)
ee5bbe38 1733
d2889a3e
BS		 1734static void do_unaligned_access(target_ulong addr, int is_write, int is_user,
1735 void *retaddr);
1736
ee5bbe38 1737#define MMUSUFFIX _mmu
d2889a3e 1738#define ALIGNED_ONLY
273af660
TS		 1739#ifdef __s390__
1740# define GETPC() ((void*)((unsigned long)__builtin_return_address(0) & 0x7fffffffUL))
1741#else
1742# define GETPC() (__builtin_return_address(0))
1743#endif
ee5bbe38
FB		 1744
1745#define SHIFT 0
1746#include "softmmu_template.h"
1747
1748#define SHIFT 1
1749#include "softmmu_template.h"
1750
1751#define SHIFT 2
1752#include "softmmu_template.h"
1753
1754#define SHIFT 3
1755#include "softmmu_template.h"
1756
d2889a3e
BS		 1757static void do_unaligned_access(target_ulong addr, int is_write, int is_user,
1758 void *retaddr)
1759{
94554550
BS		 1760#ifdef DEBUG_UNALIGNED
1761 printf("Unaligned access to 0x%x from 0x%x\n", addr, env->pc);
1762#endif
1763 raise_exception(TT_UNALIGNED);
d2889a3e 1764}
ee5bbe38
FB		 1765
1766/* try to fill the TLB and return an exception if error. If retaddr is
1767 NULL, it means that the function was called in C code (i.e. not
1768 from generated code or from helper.c) */
1769/* XXX: fix it to restore all registers */
6ebbf390 1770void tlb_fill(target_ulong addr, int is_write, int mmu_idx, void *retaddr)
ee5bbe38
FB		 1771{
1772 TranslationBlock *tb;
1773 int ret;
1774 unsigned long pc;
1775 CPUState *saved_env;
1776
1777 /* XXX: hack to restore env in all cases, even if not called from
1778 generated code */
1779 saved_env = env;
1780 env = cpu_single_env;
1781
6ebbf390 1782 ret = cpu_sparc_handle_mmu_fault(env, addr, is_write, mmu_idx, 1);
ee5bbe38
FB		 1783 if (ret) {
1784 if (retaddr) {
1785 /* now we have a real cpu fault */
1786 pc = (unsigned long)retaddr;
1787 tb = tb_find_pc(pc);
1788 if (tb) {
1789 /* the PC is inside the translated code. It means that we have
1790 a virtual CPU fault */
1791 cpu_restore_state(tb, env, pc, (void *)T2);
1792 }
1793 }
1794 cpu_loop_exit();
1795 }
1796 env = saved_env;
1797}
1798
1799#endif
6c36d3fa
BS		 1800
1801#ifndef TARGET_SPARC64
5dcb6b91 1802void do_unassigned_access(target_phys_addr_t addr, int is_write, int is_exec,
6c36d3fa
BS		 1803 int is_asi)
1804{
1805 CPUState *saved_env;
1806
1807 /* XXX: hack to restore env in all cases, even if not called from
1808 generated code */
1809 saved_env = env;
1810 env = cpu_single_env;
1811 if (env->mmuregs[3]) /* Fault status register */
0f8a249a 1812 env->mmuregs[3] = 1; /* overflow (not read before another fault) */
6c36d3fa
BS		 1813 if (is_asi)
1814 env->mmuregs[3] |= 1 << 16;
1815 if (env->psrs)
1816 env->mmuregs[3] |= 1 << 5;
1817 if (is_exec)
1818 env->mmuregs[3] |= 1 << 6;
1819 if (is_write)
1820 env->mmuregs[3] |= 1 << 7;
1821 env->mmuregs[3] |= (5 << 2) | 2;
1822 env->mmuregs[4] = addr; /* Fault address register */
1823 if ((env->mmuregs[0] & MMU_E) && !(env->mmuregs[0] & MMU_NF)) {
1824#ifdef DEBUG_UNASSIGNED
5dcb6b91 1825 printf("Unassigned mem access to " TARGET_FMT_plx " from " TARGET_FMT_lx
6c36d3fa
BS		 1826 "\n", addr, env->pc);
1827#endif
1b2e93c1
BS		 1828 if (is_exec)
1829 raise_exception(TT_CODE_ACCESS);
1830 else
1831 raise_exception(TT_DATA_ACCESS);
6c36d3fa
BS		 1832 }
1833 env = saved_env;
1834}
1835#else
5dcb6b91 1836void do_unassigned_access(target_phys_addr_t addr, int is_write, int is_exec,
6c36d3fa
BS		 1837 int is_asi)
1838{
1839#ifdef DEBUG_UNASSIGNED
1840 CPUState *saved_env;
1841
1842 /* XXX: hack to restore env in all cases, even if not called from
1843 generated code */
1844 saved_env = env;
1845 env = cpu_single_env;
5dcb6b91 1846 printf("Unassigned mem access to " TARGET_FMT_plx " from " TARGET_FMT_lx "\n",
6c36d3fa
BS		 1847 addr, env->pc);
1848 env = saved_env;
1849#endif
1b2e93c1
BS		 1850 if (is_exec)
1851 raise_exception(TT_CODE_ACCESS);
1852 else
1853 raise_exception(TT_DATA_ACCESS);
6c36d3fa
BS		 1854}
1855#endif
20c9f095 1856
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