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fixed ins in case of page fault
[thirdparty/qemu.git] / target-sparc / translate.c
CommitLineData
7a3f1944
FB		 1/*
2 SPARC translation
3
4 Copyright (C) 2003 Thomas M. Ogrisegg <tom@fnord.at>
bd497938 5 Copyright (C) 2003 Fabrice Bellard
7a3f1944
FB		 6
7 This library is free software; you can redistribute it and/or
8 modify it under the terms of the GNU Lesser General Public
9 License as published by the Free Software Foundation; either
10 version 2 of the License, or (at your option) any later version.
11
12 This library is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 Lesser General Public License for more details.
16
17 You should have received a copy of the GNU Lesser General Public
18 License along with this library; if not, write to the Free Software
19 Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21
22/*
7a3f1944
FB		 23 TODO-list:
24
bd497938 25 NPC/PC static optimisations (use JUMP_TB when possible)
7a3f1944 26 FPU-Instructions
7a3f1944 27 Privileged instructions
bd497938 28 Coprocessor-Instructions
7a3f1944
FB		 29 Optimize synthetic instructions
30 Optional alignment and privileged instruction check
bd497938 31*/
7a3f1944
FB		 32
33#include <stdarg.h>
34#include <stdlib.h>
35#include <stdio.h>
36#include <string.h>
37#include <inttypes.h>
38
39#include "cpu.h"
40#include "exec-all.h"
41#include "disas.h"
42
43#define DEBUG_DISAS
44
72cbca10
FB		 45#define DYNAMIC_PC 1 /* dynamic pc value */
46#define JUMP_PC 2 /* dynamic pc value which takes only two values
47 according to jump_pc[T2] */
48
7a3f1944 49typedef struct DisasContext {
72cbca10
FB		 50 target_ulong pc; /* current Program Counter: integer or DYNAMIC_PC */
51 target_ulong npc; /* next PC: integer or DYNAMIC_PC or JUMP_PC */
52 target_ulong jump_pc[2]; /* used when JUMP_PC pc value is used */
cf495bcf 53 int is_br;
e8af50a3 54 int mem_idx;
cf495bcf 55 struct TranslationBlock *tb;
7a3f1944
FB		 56} DisasContext;
57
58static uint16_t *gen_opc_ptr;
59static uint32_t *gen_opparam_ptr;
60extern FILE *logfile;
61extern int loglevel;
62
63enum {
64#define DEF(s,n,copy_size) INDEX_op_ ## s,
65#include "opc.h"
66#undef DEF
cf495bcf 67 NB_OPS
7a3f1944
FB		 68};
69
70#include "gen-op.h"
71
72#define GET_FIELD(X, FROM, TO) \
73 ((X) >> (31 - (TO)) & ((1 << ((TO) - (FROM) + 1)) - 1))
74
75#define IS_IMM (insn & (1<<13))
76
cf495bcf 77static void disas_sparc_insn(DisasContext * dc);
7a3f1944 78
7a3f1944 79static GenOpFunc *gen_op_movl_TN_reg[2][32] = {
cf495bcf
FB		 80 {
81 gen_op_movl_g0_T0,
82 gen_op_movl_g1_T0,
83 gen_op_movl_g2_T0,
84 gen_op_movl_g3_T0,
85 gen_op_movl_g4_T0,
86 gen_op_movl_g5_T0,
87 gen_op_movl_g6_T0,
88 gen_op_movl_g7_T0,
89 gen_op_movl_o0_T0,
90 gen_op_movl_o1_T0,
91 gen_op_movl_o2_T0,
92 gen_op_movl_o3_T0,
93 gen_op_movl_o4_T0,
94 gen_op_movl_o5_T0,
95 gen_op_movl_o6_T0,
96 gen_op_movl_o7_T0,
97 gen_op_movl_l0_T0,
98 gen_op_movl_l1_T0,
99 gen_op_movl_l2_T0,
100 gen_op_movl_l3_T0,
101 gen_op_movl_l4_T0,
102 gen_op_movl_l5_T0,
103 gen_op_movl_l6_T0,
104 gen_op_movl_l7_T0,
105 gen_op_movl_i0_T0,
106 gen_op_movl_i1_T0,
107 gen_op_movl_i2_T0,
108 gen_op_movl_i3_T0,
109 gen_op_movl_i4_T0,
110 gen_op_movl_i5_T0,
111 gen_op_movl_i6_T0,
112 gen_op_movl_i7_T0,
113 },
114 {
115 gen_op_movl_g0_T1,
116 gen_op_movl_g1_T1,
117 gen_op_movl_g2_T1,
118 gen_op_movl_g3_T1,
119 gen_op_movl_g4_T1,
120 gen_op_movl_g5_T1,
121 gen_op_movl_g6_T1,
122 gen_op_movl_g7_T1,
123 gen_op_movl_o0_T1,
124 gen_op_movl_o1_T1,
125 gen_op_movl_o2_T1,
126 gen_op_movl_o3_T1,
127 gen_op_movl_o4_T1,
128 gen_op_movl_o5_T1,
129 gen_op_movl_o6_T1,
130 gen_op_movl_o7_T1,
131 gen_op_movl_l0_T1,
132 gen_op_movl_l1_T1,
133 gen_op_movl_l2_T1,
134 gen_op_movl_l3_T1,
135 gen_op_movl_l4_T1,
136 gen_op_movl_l5_T1,
137 gen_op_movl_l6_T1,
138 gen_op_movl_l7_T1,
139 gen_op_movl_i0_T1,
140 gen_op_movl_i1_T1,
141 gen_op_movl_i2_T1,
142 gen_op_movl_i3_T1,
143 gen_op_movl_i4_T1,
144 gen_op_movl_i5_T1,
145 gen_op_movl_i6_T1,
146 gen_op_movl_i7_T1,
147 }
7a3f1944
FB		 148};
149
150static GenOpFunc *gen_op_movl_reg_TN[3][32] = {
cf495bcf
FB		 151 {
152 gen_op_movl_T0_g0,
153 gen_op_movl_T0_g1,
154 gen_op_movl_T0_g2,
155 gen_op_movl_T0_g3,
156 gen_op_movl_T0_g4,
157 gen_op_movl_T0_g5,
158 gen_op_movl_T0_g6,
159 gen_op_movl_T0_g7,
160 gen_op_movl_T0_o0,
161 gen_op_movl_T0_o1,
162 gen_op_movl_T0_o2,
163 gen_op_movl_T0_o3,
164 gen_op_movl_T0_o4,
165 gen_op_movl_T0_o5,
166 gen_op_movl_T0_o6,
167 gen_op_movl_T0_o7,
168 gen_op_movl_T0_l0,
169 gen_op_movl_T0_l1,
170 gen_op_movl_T0_l2,
171 gen_op_movl_T0_l3,
172 gen_op_movl_T0_l4,
173 gen_op_movl_T0_l5,
174 gen_op_movl_T0_l6,
175 gen_op_movl_T0_l7,
176 gen_op_movl_T0_i0,
177 gen_op_movl_T0_i1,
178 gen_op_movl_T0_i2,
179 gen_op_movl_T0_i3,
180 gen_op_movl_T0_i4,
181 gen_op_movl_T0_i5,
182 gen_op_movl_T0_i6,
183 gen_op_movl_T0_i7,
184 },
185 {
186 gen_op_movl_T1_g0,
187 gen_op_movl_T1_g1,
188 gen_op_movl_T1_g2,
189 gen_op_movl_T1_g3,
190 gen_op_movl_T1_g4,
191 gen_op_movl_T1_g5,
192 gen_op_movl_T1_g6,
193 gen_op_movl_T1_g7,
194 gen_op_movl_T1_o0,
195 gen_op_movl_T1_o1,
196 gen_op_movl_T1_o2,
197 gen_op_movl_T1_o3,
198 gen_op_movl_T1_o4,
199 gen_op_movl_T1_o5,
200 gen_op_movl_T1_o6,
201 gen_op_movl_T1_o7,
202 gen_op_movl_T1_l0,
203 gen_op_movl_T1_l1,
204 gen_op_movl_T1_l2,
205 gen_op_movl_T1_l3,
206 gen_op_movl_T1_l4,
207 gen_op_movl_T1_l5,
208 gen_op_movl_T1_l6,
209 gen_op_movl_T1_l7,
210 gen_op_movl_T1_i0,
211 gen_op_movl_T1_i1,
212 gen_op_movl_T1_i2,
213 gen_op_movl_T1_i3,
214 gen_op_movl_T1_i4,
215 gen_op_movl_T1_i5,
216 gen_op_movl_T1_i6,
217 gen_op_movl_T1_i7,
218 },
219 {
220 gen_op_movl_T2_g0,
221 gen_op_movl_T2_g1,
222 gen_op_movl_T2_g2,
223 gen_op_movl_T2_g3,
224 gen_op_movl_T2_g4,
225 gen_op_movl_T2_g5,
226 gen_op_movl_T2_g6,
227 gen_op_movl_T2_g7,
228 gen_op_movl_T2_o0,
229 gen_op_movl_T2_o1,
230 gen_op_movl_T2_o2,
231 gen_op_movl_T2_o3,
232 gen_op_movl_T2_o4,
233 gen_op_movl_T2_o5,
234 gen_op_movl_T2_o6,
235 gen_op_movl_T2_o7,
236 gen_op_movl_T2_l0,
237 gen_op_movl_T2_l1,
238 gen_op_movl_T2_l2,
239 gen_op_movl_T2_l3,
240 gen_op_movl_T2_l4,
241 gen_op_movl_T2_l5,
242 gen_op_movl_T2_l6,
243 gen_op_movl_T2_l7,
244 gen_op_movl_T2_i0,
245 gen_op_movl_T2_i1,
246 gen_op_movl_T2_i2,
247 gen_op_movl_T2_i3,
248 gen_op_movl_T2_i4,
249 gen_op_movl_T2_i5,
250 gen_op_movl_T2_i6,
251 gen_op_movl_T2_i7,
252 }
7a3f1944
FB		 253};
254
255static GenOpFunc1 *gen_op_movl_TN_im[3] = {
cf495bcf
FB		 256 gen_op_movl_T0_im,
257 gen_op_movl_T1_im,
258 gen_op_movl_T2_im
7a3f1944
FB		 259};
260
e8af50a3
FB		 261#define GEN32(func, NAME) \
262static GenOpFunc *NAME ## _table [32] = { \
263NAME ## 0, NAME ## 1, NAME ## 2, NAME ## 3, \
264NAME ## 4, NAME ## 5, NAME ## 6, NAME ## 7, \
265NAME ## 8, NAME ## 9, NAME ## 10, NAME ## 11, \
266NAME ## 12, NAME ## 13, NAME ## 14, NAME ## 15, \
267NAME ## 16, NAME ## 17, NAME ## 18, NAME ## 19, \
268NAME ## 20, NAME ## 21, NAME ## 22, NAME ## 23, \
269NAME ## 24, NAME ## 25, NAME ## 26, NAME ## 27, \
270NAME ## 28, NAME ## 29, NAME ## 30, NAME ## 31, \
271}; \
272static inline void func(int n) \
273{ \
274 NAME ## _table[n](); \
275}
276
277/* floating point registers moves */
278GEN32(gen_op_load_fpr_FT0, gen_op_load_fpr_FT0_fprf);
279GEN32(gen_op_load_fpr_FT1, gen_op_load_fpr_FT1_fprf);
280GEN32(gen_op_load_fpr_FT2, gen_op_load_fpr_FT2_fprf);
281GEN32(gen_op_store_FT0_fpr, gen_op_store_FT0_fpr_fprf);
282GEN32(gen_op_store_FT1_fpr, gen_op_store_FT1_fpr_fprf);
283GEN32(gen_op_store_FT2_fpr, gen_op_store_FT2_fpr_fprf);
284
285GEN32(gen_op_load_fpr_DT0, gen_op_load_fpr_DT0_fprf);
286GEN32(gen_op_load_fpr_DT1, gen_op_load_fpr_DT1_fprf);
287GEN32(gen_op_load_fpr_DT2, gen_op_load_fpr_DT2_fprf);
288GEN32(gen_op_store_DT0_fpr, gen_op_store_DT0_fpr_fprf);
289GEN32(gen_op_store_DT1_fpr, gen_op_store_DT1_fpr_fprf);
290GEN32(gen_op_store_DT2_fpr, gen_op_store_DT2_fpr_fprf);
291
292#if defined(CONFIG_USER_ONLY)
293#define gen_op_ldst(name) gen_op_##name##_raw()
a0c4cb4a
FB		 294#define OP_LD_TABLE(width) \
295static void gen_op_##width##a(int insn, int is_ld, int size, int sign) \
296{ \
297}
e8af50a3
FB		 298#define supervisor(dc) 0
299#else
300#define gen_op_ldst(name) (*gen_op_##name[dc->mem_idx])()
301#define OP_LD_TABLE(width) \
302static GenOpFunc *gen_op_##width[] = { \
303 &gen_op_##width##_user, \
304 &gen_op_##width##_kernel, \
305}; \
306 \
307static void gen_op_##width##a(int insn, int is_ld, int size, int sign) \
308{ \
309 int asi; \
310 \
311 asi = GET_FIELD(insn, 19, 26); \
312 switch (asi) { \
313 case 10: /* User data access */ \
314 gen_op_##width##_user(); \
315 break; \
316 case 11: /* Supervisor data access */ \
317 gen_op_##width##_kernel(); \
318 break; \
319 case 0x20 ... 0x2f: /* MMU passthrough */ \
320 if (is_ld) \
321 gen_op_ld_asi(asi, size, sign); \
322 else \
323 gen_op_st_asi(asi, size, sign); \
324 break; \
325 default: \
326 if (is_ld) \
327 gen_op_ld_asi(asi, size, sign); \
328 else \
329 gen_op_st_asi(asi, size, sign); \
330 break; \
331 } \
332}
333
334#define supervisor(dc) (dc->mem_idx == 1)
335#endif
336
337OP_LD_TABLE(ld);
338OP_LD_TABLE(st);
339OP_LD_TABLE(ldub);
340OP_LD_TABLE(lduh);
341OP_LD_TABLE(ldsb);
342OP_LD_TABLE(ldsh);
343OP_LD_TABLE(stb);
344OP_LD_TABLE(sth);
345OP_LD_TABLE(std);
346OP_LD_TABLE(ldstub);
347OP_LD_TABLE(swap);
348OP_LD_TABLE(ldd);
349OP_LD_TABLE(stf);
350OP_LD_TABLE(stdf);
351OP_LD_TABLE(ldf);
352OP_LD_TABLE(lddf);
353
cf495bcf 354static inline void gen_movl_imm_TN(int reg, int imm)
7a3f1944 355{
cf495bcf 356 gen_op_movl_TN_im[reg] (imm);
7a3f1944
FB		 357}
358
cf495bcf 359static inline void gen_movl_imm_T1(int val)
7a3f1944 360{
cf495bcf 361 gen_movl_imm_TN(1, val);
7a3f1944
FB		 362}
363
cf495bcf 364static inline void gen_movl_imm_T0(int val)
7a3f1944 365{
cf495bcf 366 gen_movl_imm_TN(0, val);
7a3f1944
FB		 367}
368
cf495bcf 369static inline void gen_movl_reg_TN(int reg, int t)
7a3f1944 370{
cf495bcf
FB		 371 if (reg)
372 gen_op_movl_reg_TN[t][reg] ();
373 else
374 gen_movl_imm_TN(t, 0);
7a3f1944
FB		 375}
376
cf495bcf 377static inline void gen_movl_reg_T0(int reg)
7a3f1944 378{
cf495bcf 379 gen_movl_reg_TN(reg, 0);
7a3f1944
FB		 380}
381
cf495bcf 382static inline void gen_movl_reg_T1(int reg)
7a3f1944 383{
cf495bcf 384 gen_movl_reg_TN(reg, 1);
7a3f1944
FB		 385}
386
cf495bcf 387static inline void gen_movl_reg_T2(int reg)
7a3f1944 388{
cf495bcf 389 gen_movl_reg_TN(reg, 2);
7a3f1944
FB		 390}
391
cf495bcf 392static inline void gen_movl_TN_reg(int reg, int t)
7a3f1944 393{
cf495bcf
FB		 394 if (reg)
395 gen_op_movl_TN_reg[t][reg] ();
7a3f1944
FB		 396}
397
cf495bcf 398static inline void gen_movl_T0_reg(int reg)
7a3f1944 399{
cf495bcf 400 gen_movl_TN_reg(reg, 0);
7a3f1944
FB		 401}
402
cf495bcf 403static inline void gen_movl_T1_reg(int reg)
7a3f1944 404{
cf495bcf 405 gen_movl_TN_reg(reg, 1);
7a3f1944
FB		 406}
407
72cbca10
FB		 408/* call this function before using T2 as it may have been set for a jump */
409static inline void flush_T2(DisasContext * dc)
410{
411 if (dc->npc == JUMP_PC) {
412 gen_op_generic_branch(dc->jump_pc[0], dc->jump_pc[1]);
413 dc->npc = DYNAMIC_PC;
414 }
415}
416
417static inline void save_npc(DisasContext * dc)
418{
419 if (dc->npc == JUMP_PC) {
420 gen_op_generic_branch(dc->jump_pc[0], dc->jump_pc[1]);
421 dc->npc = DYNAMIC_PC;
422 } else if (dc->npc != DYNAMIC_PC) {
423 gen_op_movl_npc_im(dc->npc);
424 }
425}
426
427static inline void save_state(DisasContext * dc)
428{
429 gen_op_jmp_im((uint32_t)dc->pc);
430 save_npc(dc);
431}
432
cf495bcf 433static void gen_cond(int cond)
7a3f1944 434{
7a3f1944 435 switch (cond) {
cf495bcf
FB		 436 case 0x0:
437 gen_op_movl_T2_0();
438 break;
439 case 0x1:
440 gen_op_eval_be();
441 break;
442 case 0x2:
443 gen_op_eval_ble();
444 break;
445 case 0x3:
446 gen_op_eval_bl();
447 break;
448 case 0x4:
449 gen_op_eval_bleu();
450 break;
451 case 0x5:
452 gen_op_eval_bcs();
453 break;
454 case 0x6:
455 gen_op_eval_bneg();
456 break;
457 case 0x7:
458 gen_op_eval_bvs();
459 break;
460 case 0x8:
461 gen_op_movl_T2_1();
462 break;
463 case 0x9:
464 gen_op_eval_bne();
465 break;
466 case 0xa:
467 gen_op_eval_bg();
468 break;
469 case 0xb:
470 gen_op_eval_bge();
471 break;
472 case 0xc:
473 gen_op_eval_bgu();
474 break;
475 case 0xd:
476 gen_op_eval_bcc();
477 break;
478 case 0xe:
479 gen_op_eval_bpos();
480 break;
481 default:
482 case 0xf:
483 gen_op_eval_bvc();
484 break;
7a3f1944 485 }
7a3f1944
FB		 486}
487
e8af50a3
FB		 488static void gen_fcond(int cond)
489{
490 switch (cond) {
491 case 0x0:
492 gen_op_movl_T2_0();
493 break;
494 case 0x1:
495 gen_op_eval_fbne();
496 break;
497 case 0x2:
498 gen_op_eval_fblg();
499 break;
500 case 0x3:
501 gen_op_eval_fbul();
502 break;
503 case 0x4:
504 gen_op_eval_fbl();
505 break;
506 case 0x5:
507 gen_op_eval_fbug();
508 break;
509 case 0x6:
510 gen_op_eval_fbg();
511 break;
512 case 0x7:
513 gen_op_eval_fbu();
514 break;
515 case 0x8:
516 gen_op_movl_T2_1();
517 break;
518 case 0x9:
519 gen_op_eval_fbe();
520 break;
521 case 0xa:
522 gen_op_eval_fbue();
523 break;
524 case 0xb:
525 gen_op_eval_fbge();
526 break;
527 case 0xc:
528 gen_op_eval_fbuge();
529 break;
530 case 0xd:
531 gen_op_eval_fble();
532 break;
533 case 0xe:
534 gen_op_eval_fbule();
535 break;
536 default:
537 case 0xf:
538 gen_op_eval_fbo();
539 break;
540 }
541}
cf495bcf
FB		 542
543static void do_branch(DisasContext * dc, uint32_t target, uint32_t insn)
7a3f1944 544{
cf495bcf
FB		 545 unsigned int cond = GET_FIELD(insn, 3, 6), a = (insn & (1 << 29));
546 target += (uint32_t) dc->pc;
547 if (cond == 0x0) {
548 /* unconditional not taken */
549 if (a) {
550 dc->pc = dc->npc + 4;
551 dc->npc = dc->pc + 4;
552 } else {
553 dc->pc = dc->npc;
554 dc->npc = dc->pc + 4;
555 }
556 } else if (cond == 0x8) {
557 /* unconditional taken */
558 if (a) {
72cbca10 559 dc->pc = target;
cf495bcf
FB		 560 dc->npc = dc->pc + 4;
561 } else {
562 dc->pc = dc->npc;
72cbca10 563 dc->npc = target;
cf495bcf
FB		 564 }
565 } else {
72cbca10 566 flush_T2(dc);
cf495bcf
FB		 567 gen_cond(cond);
568 if (a) {
72cbca10 569 gen_op_branch_a((long)dc->tb, target, dc->npc);
cf495bcf 570 dc->is_br = 1;
cf495bcf
FB		 571 } else {
572 dc->pc = dc->npc;
72cbca10
FB		 573 dc->jump_pc[0] = target;
574 dc->jump_pc[1] = dc->npc + 4;
575 dc->npc = JUMP_PC;
cf495bcf
FB		 576 }
577 }
7a3f1944
FB		 578}
579
e8af50a3
FB		 580static void do_fbranch(DisasContext * dc, uint32_t target, uint32_t insn)
581{
582 unsigned int cond = GET_FIELD(insn, 3, 6), a = (insn & (1 << 29));
583 target += (uint32_t) dc->pc;
584 if (cond == 0x0) {
585 /* unconditional not taken */
586 if (a) {
587 dc->pc = dc->npc + 4;
588 dc->npc = dc->pc + 4;
589 } else {
590 dc->pc = dc->npc;
591 dc->npc = dc->pc + 4;
592 }
593 } else if (cond == 0x8) {
594 /* unconditional taken */
595 if (a) {
596 dc->pc = target;
597 dc->npc = dc->pc + 4;
598 } else {
599 dc->pc = dc->npc;
600 dc->npc = target;
601 }
602 } else {
603 flush_T2(dc);
604 gen_fcond(cond);
605 if (a) {
606 gen_op_branch_a((long)dc->tb, target, dc->npc);
607 dc->is_br = 1;
608 } else {
609 dc->pc = dc->npc;
610 dc->jump_pc[0] = target;
611 dc->jump_pc[1] = dc->npc + 4;
612 dc->npc = JUMP_PC;
613 }
614 }
615}
616
617static void gen_debug(DisasContext *s, uint32_t pc)
618{
619 gen_op_jmp_im(pc);
620 gen_op_debug();
621 s->is_br = 1;
622}
623
cf495bcf 624#define GET_FIELDs(x,a,b) sign_extend (GET_FIELD(x,a,b), (b) - (a) + 1)
7a3f1944 625
cf495bcf 626static int sign_extend(int x, int len)
7a3f1944 627{
cf495bcf
FB		 628 len = 32 - len;
629 return (x << len) >> len;
7a3f1944
FB		 630}
631
cf495bcf
FB		 632static void disas_sparc_insn(DisasContext * dc)
633{
634 unsigned int insn, opc, rs1, rs2, rd;
7a3f1944 635
72cbca10 636 insn = ldl_code((uint8_t *)dc->pc);
cf495bcf 637 opc = GET_FIELD(insn, 0, 1);
7a3f1944 638
cf495bcf
FB		 639 rd = GET_FIELD(insn, 2, 6);
640 switch (opc) {
641 case 0: /* branches/sethi */
642 {
643 unsigned int xop = GET_FIELD(insn, 7, 9);
644 int target;
645 target = GET_FIELD(insn, 10, 31);
646 switch (xop) {
647 case 0x0:
648 case 0x1: /* UNIMPL */
e8af50a3 649 default:
cf495bcf
FB		 650 goto illegal_insn;
651 case 0x2: /* BN+x */
7a3f1944 652 {
cf495bcf
FB		 653 target <<= 2;
654 target = sign_extend(target, 22);
655 do_branch(dc, target, insn);
656 goto jmp_insn;
7a3f1944 657 }
e8af50a3
FB		 658 case 0x6: /* FBN+x */
659 {
660 target <<= 2;
661 target = sign_extend(target, 22);
662 do_fbranch(dc, target, insn);
663 goto jmp_insn;
664 }
cf495bcf
FB		 665 case 0x4: /* SETHI */
666 gen_movl_imm_T0(target << 10);
667 gen_movl_T0_reg(rd);
668 break;
669 case 0x5: /*CBN+x */
670 break;
671 }
672 break;
673 }
674 case 1:
675 /*CALL*/ {
676 unsigned int target = GET_FIELDs(insn, 2, 31) << 2;
677
678 gen_op_movl_T0_im((long) (dc->pc));
679 gen_movl_T0_reg(15);
72cbca10 680 target = dc->pc + target;
cf495bcf 681 dc->pc = dc->npc;
72cbca10 682 dc->npc = target;
cf495bcf
FB		 683 }
684 goto jmp_insn;
685 case 2: /* FPU & Logical Operations */
686 {
687 unsigned int xop = GET_FIELD(insn, 7, 12);
688 if (xop == 0x3a) { /* generate trap */
689 int cond;
690 rs1 = GET_FIELD(insn, 13, 17);
691 gen_movl_reg_T0(rs1);
692 if (IS_IMM) {
e8af50a3
FB		 693 rs2 = GET_FIELD(insn, 25, 31);
694 if (rs2 != 0) {
695 gen_movl_imm_T1(rs2);
696 gen_op_add_T1_T0();
697 }
cf495bcf
FB		 698 } else {
699 rs2 = GET_FIELD(insn, 27, 31);
700 gen_movl_reg_T1(rs2);
e8af50a3 701 gen_op_add_T1_T0();
cf495bcf 702 }
cf495bcf
FB		 703 save_state(dc);
704 cond = GET_FIELD(insn, 3, 6);
705 if (cond == 0x8) {
706 gen_op_trap_T0();
707 dc->is_br = 1;
708 goto jmp_insn;
709 } else {
710 gen_op_trapcc_T0();
711 }
712 } else if (xop == 0x28) {
713 rs1 = GET_FIELD(insn, 13, 17);
714 switch(rs1) {
715 case 0: /* rdy */
716 gen_op_rdy();
717 gen_movl_T0_reg(rd);
718 break;
e8af50a3
FB		 719 case 15: /* stbar */
720 break; /* no effect? */
cf495bcf
FB		 721 default:
722 goto illegal_insn;
723 }
e8af50a3
FB		 724#if !defined(CONFIG_USER_ONLY)
725 } else if (xop == 0x29) {
726 if (!supervisor(dc))
727 goto priv_insn;
728 gen_op_rdpsr();
729 gen_movl_T0_reg(rd);
730 break;
731 } else if (xop == 0x2a) {
732 if (!supervisor(dc))
733 goto priv_insn;
734 gen_op_rdwim();
735 gen_movl_T0_reg(rd);
736 break;
737 } else if (xop == 0x2b) {
738 if (!supervisor(dc))
739 goto priv_insn;
740 gen_op_rdtbr();
741 gen_movl_T0_reg(rd);
742 break;
743#endif
cf495bcf 744 } else if (xop == 0x34 || xop == 0x35) { /* FPU Operations */
e8af50a3
FB		 745 rs1 = GET_FIELD(insn, 13, 17);
746 rs2 = GET_FIELD(insn, 27, 31);
747 xop = GET_FIELD(insn, 18, 26);
748 switch (xop) {
749 case 0x1: /* fmovs */
750 gen_op_load_fpr_FT0(rs2);
751 gen_op_store_FT0_fpr(rd);
752 break;
753 case 0x5: /* fnegs */
754 gen_op_load_fpr_FT1(rs2);
755 gen_op_fnegs();
756 gen_op_store_FT0_fpr(rd);
757 break;
758 case 0x9: /* fabss */
759 gen_op_load_fpr_FT1(rs2);
760 gen_op_fabss();
761 gen_op_store_FT0_fpr(rd);
762 break;
763 case 0x29: /* fsqrts */
764 gen_op_load_fpr_FT1(rs2);
765 gen_op_fsqrts();
766 gen_op_store_FT0_fpr(rd);
767 break;
768 case 0x2a: /* fsqrtd */
769 gen_op_load_fpr_DT1(rs2);
770 gen_op_fsqrtd();
771 gen_op_store_DT0_fpr(rd);
772 break;
773 case 0x41:
774 gen_op_load_fpr_FT0(rs1);
775 gen_op_load_fpr_FT1(rs2);
776 gen_op_fadds();
777 gen_op_store_FT0_fpr(rd);
778 break;
779 case 0x42:
780 gen_op_load_fpr_DT0(rs1);
781 gen_op_load_fpr_DT1(rs2);
782 gen_op_faddd();
783 gen_op_store_DT0_fpr(rd);
784 break;
785 case 0x45:
786 gen_op_load_fpr_FT0(rs1);
787 gen_op_load_fpr_FT1(rs2);
788 gen_op_fsubs();
789 gen_op_store_FT0_fpr(rd);
790 break;
791 case 0x46:
792 gen_op_load_fpr_DT0(rs1);
793 gen_op_load_fpr_DT1(rs2);
794 gen_op_fsubd();
795 gen_op_store_DT0_fpr(rd);
796 break;
797 case 0x49:
798 gen_op_load_fpr_FT0(rs1);
799 gen_op_load_fpr_FT1(rs2);
800 gen_op_fmuls();
801 gen_op_store_FT0_fpr(rd);
802 break;
803 case 0x4a:
804 gen_op_load_fpr_DT0(rs1);
805 gen_op_load_fpr_DT1(rs2);
806 gen_op_fmuld();
807 gen_op_store_DT0_fpr(rd);
808 break;
809 case 0x4d:
810 gen_op_load_fpr_FT0(rs1);
811 gen_op_load_fpr_FT1(rs2);
812 gen_op_fdivs();
813 gen_op_store_FT0_fpr(rd);
814 break;
815 case 0x4e:
816 gen_op_load_fpr_DT0(rs1);
817 gen_op_load_fpr_DT1(rs2);
818 gen_op_fdivd();
819 gen_op_store_DT0_fpr(rd);
820 break;
821 case 0x51:
822 gen_op_load_fpr_FT0(rs1);
823 gen_op_load_fpr_FT1(rs2);
824 gen_op_fcmps();
825 break;
826 case 0x52:
827 gen_op_load_fpr_DT0(rs1);
828 gen_op_load_fpr_DT1(rs2);
829 gen_op_fcmpd();
830 break;
831 case 0x55: /* fcmpes */
832 gen_op_load_fpr_FT0(rs1);
833 gen_op_load_fpr_FT1(rs2);
834 gen_op_fcmps(); /* XXX */
835 break;
836 case 0x56: /* fcmped */
837 gen_op_load_fpr_DT0(rs1);
838 gen_op_load_fpr_DT1(rs2);
839 gen_op_fcmpd(); /* XXX */
840 break;
841 case 0x69:
842 gen_op_load_fpr_FT0(rs1);
843 gen_op_load_fpr_FT1(rs2);
844 gen_op_fsmuld();
845 gen_op_store_DT0_fpr(rd);
846 break;
847 case 0xc4:
848 gen_op_load_fpr_FT1(rs2);
849 gen_op_fitos();
850 gen_op_store_FT0_fpr(rd);
851 break;
852 case 0xc6:
853 gen_op_load_fpr_DT1(rs2);
854 gen_op_fdtos();
855 gen_op_store_FT0_fpr(rd);
856 break;
857 case 0xc8:
858 gen_op_load_fpr_FT1(rs2);
859 gen_op_fitod();
860 gen_op_store_DT0_fpr(rd);
861 break;
862 case 0xc9:
863 gen_op_load_fpr_FT1(rs2);
864 gen_op_fstod();
865 gen_op_store_DT0_fpr(rd);
866 break;
867 case 0xd1:
868 gen_op_load_fpr_FT1(rs2);
869 gen_op_fstoi();
870 gen_op_store_FT0_fpr(rd);
871 break;
872 case 0xd2:
873 gen_op_load_fpr_DT1(rs2);
874 gen_op_fdtoi();
875 gen_op_store_FT0_fpr(rd);
876 break;
877 default:
878 goto illegal_insn;
879 }
cf495bcf
FB		 880 } else {
881 rs1 = GET_FIELD(insn, 13, 17);
882 gen_movl_reg_T0(rs1);
883 if (IS_IMM) { /* immediate */
884 rs2 = GET_FIELDs(insn, 19, 31);
885 gen_movl_imm_T1(rs2);
886 } else { /* register */
887 rs2 = GET_FIELD(insn, 27, 31);
888 gen_movl_reg_T1(rs2);
889 }
890 if (xop < 0x20) {
891 switch (xop & ~0x10) {
892 case 0x0:
893 if (xop & 0x10)
894 gen_op_add_T1_T0_cc();
895 else
896 gen_op_add_T1_T0();
897 break;
898 case 0x1:
899 gen_op_and_T1_T0();
900 if (xop & 0x10)
901 gen_op_logic_T0_cc();
902 break;
903 case 0x2:
904 gen_op_or_T1_T0();
905 if (xop & 0x10)
906 gen_op_logic_T0_cc();
907 break;
908 case 0x3:
909 gen_op_xor_T1_T0();
910 if (xop & 0x10)
911 gen_op_logic_T0_cc();
912 break;
913 case 0x4:
914 if (xop & 0x10)
915 gen_op_sub_T1_T0_cc();
916 else
917 gen_op_sub_T1_T0();
918 break;
919 case 0x5:
920 gen_op_andn_T1_T0();
921 if (xop & 0x10)
922 gen_op_logic_T0_cc();
923 break;
924 case 0x6:
925 gen_op_orn_T1_T0();
926 if (xop & 0x10)
927 gen_op_logic_T0_cc();
928 break;
929 case 0x7:
930 gen_op_xnor_T1_T0();
931 if (xop & 0x10)
932 gen_op_logic_T0_cc();
933 break;
934 case 0x8:
935 gen_op_addx_T1_T0();
936 if (xop & 0x10)
937 gen_op_set_flags();
938 break;
939 case 0xa:
940 gen_op_umul_T1_T0();
941 if (xop & 0x10)
942 gen_op_logic_T0_cc();
943 break;
944 case 0xb:
945 gen_op_smul_T1_T0();
946 if (xop & 0x10)
947 gen_op_logic_T0_cc();
948 break;
949 case 0xc:
950 gen_op_subx_T1_T0();
951 if (xop & 0x10)
952 gen_op_set_flags();
953 break;
954 case 0xe:
955 gen_op_udiv_T1_T0();
956 if (xop & 0x10)
957 gen_op_div_cc();
958 break;
959 case 0xf:
960 gen_op_sdiv_T1_T0();
961 if (xop & 0x10)
962 gen_op_div_cc();
963 break;
964 default:
965 goto illegal_insn;
966 }
967 gen_movl_T0_reg(rd);
968 } else {
969 switch (xop) {
970 case 0x24: /* mulscc */
971 gen_op_mulscc_T1_T0();
972 gen_movl_T0_reg(rd);
973 break;
974 case 0x25: /* SLL */
975 gen_op_sll();
976 gen_movl_T0_reg(rd);
977 break;
978 case 0x26:
979 gen_op_srl();
980 gen_movl_T0_reg(rd);
981 break;
982 case 0x27:
983 gen_op_sra();
984 gen_movl_T0_reg(rd);
985 break;
986 case 0x30:
987 {
988 gen_op_xor_T1_T0();
989 switch(rd) {
990 case 0:
991 gen_op_wry();
992 break;
993 default:
994 goto illegal_insn;
995 }
996 }
997 break;
e8af50a3
FB		 998#if !defined(CONFIG_USER_ONLY)
999 case 0x31:
1000 {
1001 if (!supervisor(dc))
1002 goto priv_insn;
1003 gen_op_xor_T1_T0();
1004 gen_op_wrpsr();
1005 }
1006 break;
1007 case 0x32:
1008 {
1009 if (!supervisor(dc))
1010 goto priv_insn;
1011 gen_op_xor_T1_T0();
1012 gen_op_wrwim();
1013 }
1014 break;
1015 case 0x33:
1016 {
1017 if (!supervisor(dc))
1018 goto priv_insn;
1019 gen_op_xor_T1_T0();
1020 gen_op_wrtbr();
1021 }
1022 break;
1023#endif
cf495bcf
FB		 1024 case 0x38: /* jmpl */
1025 {
1026 gen_op_add_T1_T0();
1027 gen_op_movl_npc_T0();
1028 if (rd != 0) {
1029 gen_op_movl_T0_im((long) (dc->pc));
1030 gen_movl_T0_reg(rd);
1031 }
1032 dc->pc = dc->npc;
72cbca10 1033 dc->npc = DYNAMIC_PC;
cf495bcf
FB		 1034 }
1035 goto jmp_insn;
e8af50a3
FB		 1036#if !defined(CONFIG_USER_ONLY)
1037 case 0x39: /* rett */
1038 {
1039 if (!supervisor(dc))
1040 goto priv_insn;
1041 gen_op_add_T1_T0();
1042 gen_op_movl_npc_T0();
1043 gen_op_rett();
1044#if 0
1045 dc->pc = dc->npc;
1046 dc->npc = DYNAMIC_PC;
1047#endif
1048 }
1049#if 0
1050 goto jmp_insn;
1051#endif
1052 break;
1053#endif
cf495bcf 1054 case 0x3b: /* flush */
658138bc
FB		 1055 gen_op_add_T1_T0();
1056 gen_op_flush_T0();
cf495bcf
FB		 1057 break;
1058 case 0x3c: /* save */
1059 save_state(dc);
1060 gen_op_add_T1_T0();
1061 gen_op_save();
1062 gen_movl_T0_reg(rd);
1063 break;
1064 case 0x3d: /* restore */
1065 save_state(dc);
1066 gen_op_add_T1_T0();
1067 gen_op_restore();
1068 gen_movl_T0_reg(rd);
1069 break;
1070 default:
1071 goto illegal_insn;
1072 }
1073 }
1074 }
1075 break;
1076 }
1077 case 3: /* load/store instructions */
1078 {
1079 unsigned int xop = GET_FIELD(insn, 7, 12);
1080 rs1 = GET_FIELD(insn, 13, 17);
1081 gen_movl_reg_T0(rs1);
1082 if (IS_IMM) { /* immediate */
1083 rs2 = GET_FIELDs(insn, 19, 31);
e8af50a3
FB		 1084 if (rs2 != 0) {
1085 gen_movl_imm_T1(rs2);
1086 gen_op_add_T1_T0();
1087 }
cf495bcf
FB		 1088 } else { /* register */
1089 rs2 = GET_FIELD(insn, 27, 31);
1090 gen_movl_reg_T1(rs2);
e8af50a3 1091 gen_op_add_T1_T0();
cf495bcf 1092 }
e8af50a3
FB		 1093 if (xop < 4 || (xop > 7 && xop < 0x14) || \
1094 (xop > 0x17 && xop < 0x20)) {
cf495bcf
FB		 1095 switch (xop) {
1096 case 0x0: /* load word */
e8af50a3 1097 gen_op_ldst(ld);
cf495bcf
FB		 1098 break;
1099 case 0x1: /* load unsigned byte */
e8af50a3 1100 gen_op_ldst(ldub);
cf495bcf
FB		 1101 break;
1102 case 0x2: /* load unsigned halfword */
e8af50a3 1103 gen_op_ldst(lduh);
cf495bcf
FB		 1104 break;
1105 case 0x3: /* load double word */
e8af50a3 1106 gen_op_ldst(ldd);
cf495bcf
FB		 1107 gen_movl_T0_reg(rd + 1);
1108 break;
1109 case 0x9: /* load signed byte */
e8af50a3 1110 gen_op_ldst(ldsb);
cf495bcf
FB		 1111 break;
1112 case 0xa: /* load signed halfword */
e8af50a3 1113 gen_op_ldst(ldsh);
cf495bcf
FB		 1114 break;
1115 case 0xd: /* ldstub -- XXX: should be atomically */
e8af50a3 1116 gen_op_ldst(ldstub);
cf495bcf
FB		 1117 break;
1118 case 0x0f: /* swap register with memory. Also atomically */
e8af50a3
FB		 1119 gen_op_ldst(swap);
1120 break;
1121 case 0x10: /* load word alternate */
1122 if (!supervisor(dc))
1123 goto priv_insn;
1124 gen_op_lda(insn, 1, 4, 0);
1125 break;
1126 case 0x11: /* load unsigned byte alternate */
1127 if (!supervisor(dc))
1128 goto priv_insn;
1129 gen_op_lduba(insn, 1, 1, 0);
1130 break;
1131 case 0x12: /* load unsigned halfword alternate */
1132 if (!supervisor(dc))
1133 goto priv_insn;
1134 gen_op_lduha(insn, 1, 2, 0);
1135 break;
1136 case 0x13: /* load double word alternate */
1137 if (!supervisor(dc))
1138 goto priv_insn;
1139 gen_op_ldda(insn, 1, 8, 0);
1140 gen_movl_T0_reg(rd + 1);
1141 break;
1142 case 0x19: /* load signed byte alternate */
1143 if (!supervisor(dc))
1144 goto priv_insn;
1145 gen_op_ldsba(insn, 1, 1, 1);
1146 break;
1147 case 0x1a: /* load signed halfword alternate */
1148 if (!supervisor(dc))
1149 goto priv_insn;
1150 gen_op_ldsha(insn, 1, 2 ,1);
1151 break;
1152 case 0x1d: /* ldstuba -- XXX: should be atomically */
1153 if (!supervisor(dc))
1154 goto priv_insn;
1155 gen_op_ldstuba(insn, 1, 1, 0);
1156 break;
1157 case 0x1f: /* swap reg with alt. memory. Also atomically */
1158 if (!supervisor(dc))
1159 goto priv_insn;
1160 gen_op_swapa(insn, 1, 4, 0);
cf495bcf 1161 break;
7a3f1944 1162 }
cf495bcf 1163 gen_movl_T1_reg(rd);
e8af50a3
FB		 1164 } else if (xop >= 0x20 && xop < 0x24) {
1165 switch (xop) {
1166 case 0x20: /* load fpreg */
1167 gen_op_ldst(ldf);
1168 gen_op_store_FT0_fpr(rd);
1169 break;
1170 case 0x21: /* load fsr */
1171 gen_op_ldfsr();
1172 break;
1173 case 0x23: /* load double fpreg */
1174 gen_op_ldst(lddf);
1175 gen_op_store_DT0_fpr(rd);
1176 break;
1177 }
1178 } else if (xop < 8 || (xop >= 0x14 && xop < 0x18)) {
cf495bcf
FB		 1179 gen_movl_reg_T1(rd);
1180 switch (xop) {
1181 case 0x4:
e8af50a3 1182 gen_op_ldst(st);
cf495bcf
FB		 1183 break;
1184 case 0x5:
e8af50a3 1185 gen_op_ldst(stb);
cf495bcf
FB		 1186 break;
1187 case 0x6:
e8af50a3 1188 gen_op_ldst(sth);
cf495bcf
FB		 1189 break;
1190 case 0x7:
72cbca10 1191 flush_T2(dc);
cf495bcf 1192 gen_movl_reg_T2(rd + 1);
e8af50a3
FB		 1193 gen_op_ldst(std);
1194 break;
1195 case 0x14:
1196 if (!supervisor(dc))
1197 goto priv_insn;
1198 gen_op_sta(insn, 0, 4, 0);
1199 break;
1200 case 0x15:
1201 if (!supervisor(dc))
1202 goto priv_insn;
1203 gen_op_stba(insn, 0, 1, 0);
1204 break;
1205 case 0x16:
1206 if (!supervisor(dc))
1207 goto priv_insn;
1208 gen_op_stha(insn, 0, 2, 0);
1209 break;
1210 case 0x17:
1211 if (!supervisor(dc))
1212 goto priv_insn;
1213 flush_T2(dc);
1214 gen_movl_reg_T2(rd + 1);
1215 gen_op_stda(insn, 0, 8, 0);
cf495bcf 1216 break;
7a3f1944 1217 }
e8af50a3
FB		 1218 } else if (xop > 0x23 && xop < 0x28) {
1219 switch (xop) {
1220 case 0x24:
1221 gen_op_load_fpr_FT0(rd);
1222 gen_op_ldst(stf);
1223 break;
1224 case 0x25:
1225 gen_op_stfsr();
1226 break;
1227 case 0x27:
1228 gen_op_load_fpr_DT0(rd);
1229 gen_op_ldst(stdf);
1230 break;
1231 }
1232 } else if (xop > 0x33 && xop < 0x38) {
1233 /* Co-processor */
1234 }
7a3f1944 1235 }
cf495bcf
FB		 1236 }
1237 /* default case for non jump instructions */
72cbca10
FB		 1238 if (dc->npc == DYNAMIC_PC) {
1239 dc->pc = DYNAMIC_PC;
1240 gen_op_next_insn();
1241 } else if (dc->npc == JUMP_PC) {
1242 /* we can do a static jump */
1243 gen_op_branch2((long)dc->tb, dc->jump_pc[0], dc->jump_pc[1]);
1244 dc->is_br = 1;
1245 } else {
cf495bcf
FB		 1246 dc->pc = dc->npc;
1247 dc->npc = dc->npc + 4;
cf495bcf
FB		 1248 }
1249 jmp_insn:;
1250 return;
1251 illegal_insn:
72cbca10 1252 save_state(dc);
cf495bcf
FB		 1253 gen_op_exception(TT_ILL_INSN);
1254 dc->is_br = 1;
e8af50a3
FB		 1255 return;
1256 priv_insn:
1257 save_state(dc);
1258 gen_op_exception(TT_PRIV_INSN);
1259 dc->is_br = 1;
7a3f1944
FB		 1260}
1261
cf495bcf 1262static inline int gen_intermediate_code_internal(TranslationBlock * tb,
e8af50a3 1263 int spc, CPUSPARCState *env)
7a3f1944 1264{
72cbca10 1265 target_ulong pc_start, last_pc;
cf495bcf
FB		 1266 uint16_t *gen_opc_end;
1267 DisasContext dc1, *dc = &dc1;
e8af50a3 1268 int j, lj = -1;
cf495bcf
FB		 1269
1270 memset(dc, 0, sizeof(DisasContext));
cf495bcf 1271 dc->tb = tb;
72cbca10 1272 pc_start = tb->pc;
cf495bcf 1273 dc->pc = pc_start;
72cbca10 1274 dc->npc = (target_ulong) tb->cs_base;
e8af50a3
FB		 1275#if defined(CONFIG_USER_ONLY)
1276 dc->mem_idx = 0;
1277#else
1278 dc->mem_idx = ((env->psrs) != 0);
1279#endif
cf495bcf
FB		 1280 gen_opc_ptr = gen_opc_buf;
1281 gen_opc_end = gen_opc_buf + OPC_MAX_SIZE;
1282 gen_opparam_ptr = gen_opparam_buf;
1283
1284 do {
e8af50a3
FB		 1285 if (env->nb_breakpoints > 0) {
1286 for(j = 0; j < env->nb_breakpoints; j++) {
1287 if (env->breakpoints[j] == dc->pc) {
1288 gen_debug(dc, dc->pc);
1289 break;
1290 }
1291 }
1292 }
1293 if (spc) {
1294 if (loglevel > 0)
1295 fprintf(logfile, "Search PC...\n");
1296 j = gen_opc_ptr - gen_opc_buf;
1297 if (lj < j) {
1298 lj++;
1299 while (lj < j)
1300 gen_opc_instr_start[lj++] = 0;
1301 gen_opc_pc[lj] = dc->pc;
1302 gen_opc_npc[lj] = dc->npc;
1303 gen_opc_instr_start[lj] = 1;
1304 }
1305 }
cf495bcf
FB		 1306 last_pc = dc->pc;
1307 disas_sparc_insn(dc);
1308 if (dc->is_br)
1309 break;
1310 /* if the next PC is different, we abort now */
1311 if (dc->pc != (last_pc + 4))
1312 break;
1313 } while ((gen_opc_ptr < gen_opc_end) &&
1314 (dc->pc - pc_start) < (TARGET_PAGE_SIZE - 32));
72cbca10
FB		 1315 if (!dc->is_br) {
1316 if (dc->pc != DYNAMIC_PC &&
1317 (dc->npc != DYNAMIC_PC && dc->npc != JUMP_PC)) {
1318 /* static PC and NPC: we can use direct chaining */
1319 gen_op_branch((long)tb, dc->pc, dc->npc);
1320 } else {
1321 if (dc->pc != DYNAMIC_PC)
1322 gen_op_jmp_im(dc->pc);
1323 save_npc(dc);
1324 gen_op_movl_T0_0();
1325 gen_op_exit_tb();
1326 }
1327 }
cf495bcf 1328 *gen_opc_ptr = INDEX_op_end;
e8af50a3
FB		 1329 if (spc) {
1330 j = gen_opc_ptr - gen_opc_buf;
1331 lj++;
1332 while (lj <= j)
1333 gen_opc_instr_start[lj++] = 0;
1334 tb->size = 0;
1335#if 0
1336 if (loglevel > 0) {
1337 page_dump(logfile);
1338 }
1339#endif
1340 } else {
1341 tb->size = dc->npc - pc_start;
1342 }
7a3f1944 1343#ifdef DEBUG_DISAS
e19e89a5 1344 if (loglevel & CPU_LOG_TB_IN_ASM) {
cf495bcf 1345 fprintf(logfile, "--------------\n");
72cbca10
FB		 1346 fprintf(logfile, "IN: %s\n", lookup_symbol((uint8_t *)pc_start));
1347 disas(logfile, (uint8_t *)pc_start, last_pc + 4 - pc_start, 0, 0);
cf495bcf 1348 fprintf(logfile, "\n");
e19e89a5
FB		 1349 if (loglevel & CPU_LOG_TB_OP) {
1350 fprintf(logfile, "OP:\n");
1351 dump_ops(gen_opc_buf, gen_opparam_buf);
1352 fprintf(logfile, "\n");
1353 }
cf495bcf 1354 }
7a3f1944 1355#endif
cf495bcf 1356 return 0;
7a3f1944
FB		 1357}
1358
cf495bcf 1359int gen_intermediate_code(CPUSPARCState * env, TranslationBlock * tb)
7a3f1944 1360{
e8af50a3 1361 return gen_intermediate_code_internal(tb, 0, env);
7a3f1944
FB		 1362}
1363
cf495bcf 1364int gen_intermediate_code_pc(CPUSPARCState * env, TranslationBlock * tb)
7a3f1944 1365{
e8af50a3 1366 return gen_intermediate_code_internal(tb, 1, env);
7a3f1944
FB		 1367}
1368
cf495bcf 1369CPUSPARCState *cpu_sparc_init(void)
7a3f1944 1370{
cf495bcf
FB		 1371 CPUSPARCState *env;
1372
1373 cpu_exec_init();
1374
1375 if (!(env = malloc(sizeof(CPUSPARCState))))
1376 return (NULL);
1377 memset(env, 0, sizeof(*env));
1378 env->cwp = 0;
1379 env->wim = 1;
1380 env->regwptr = env->regbase + (env->cwp * 16);
e8af50a3 1381#if defined(CONFIG_USER_ONLY)
cf495bcf 1382 env->user_mode_only = 1;
e8af50a3
FB		 1383#else
1384 /* Emulate Prom */
1385 env->psrs = 1;
1386 env->pc = 0x4000;
1387 env->npc = env->pc + 4;
1388 env->mmuregs[0] = (0x10<<24) | MMU_E; /* Impl 1, ver 0, MMU Enabled */
1389 env->mmuregs[1] = 0x3000 >> 4; /* MMU Context table */
1390#endif
7496f526 1391 cpu_single_env = env;
cf495bcf 1392 return (env);
7a3f1944
FB		 1393}
1394
1395#define GET_FLAG(a,b) ((env->psr & a)?b:'-')
1396
7fe48483
FB		 1397void cpu_dump_state(CPUState *env, FILE *f,
1398 int (*cpu_fprintf)(FILE *f, const char *fmt, ...),
1399 int flags)
7a3f1944 1400{
cf495bcf
FB		 1401 int i, x;
1402
7fe48483
FB		 1403 cpu_fprintf(f, "pc: 0x%08x npc: 0x%08x\n", (int) env->pc, (int) env->npc);
1404 cpu_fprintf(f, "General Registers:\n");
cf495bcf 1405 for (i = 0; i < 4; i++)
7fe48483
FB		 1406 cpu_fprintf(f, "%%g%c: 0x%08x\t", i + '0', env->gregs[i]);
1407 cpu_fprintf(f, "\n");
cf495bcf 1408 for (; i < 8; i++)
7fe48483
FB		 1409 cpu_fprintf(f, "%%g%c: 0x%08x\t", i + '0', env->gregs[i]);
1410 cpu_fprintf(f, "\nCurrent Register Window:\n");
cf495bcf
FB		 1411 for (x = 0; x < 3; x++) {
1412 for (i = 0; i < 4; i++)
7fe48483 1413 cpu_fprintf(f, "%%%c%d: 0x%08x\t",
cf495bcf
FB		 1414 (x == 0 ? 'o' : (x == 1 ? 'l' : 'i')), i,
1415 env->regwptr[i + x * 8]);
7fe48483 1416 cpu_fprintf(f, "\n");
cf495bcf 1417 for (; i < 8; i++)
7fe48483 1418 cpu_fprintf(f, "%%%c%d: 0x%08x\t",
cf495bcf
FB		 1419 (x == 0 ? 'o' : x == 1 ? 'l' : 'i'), i,
1420 env->regwptr[i + x * 8]);
7fe48483 1421 cpu_fprintf(f, "\n");
cf495bcf 1422 }
7fe48483 1423 cpu_fprintf(f, "\nFloating Point Registers:\n");
e8af50a3
FB		 1424 for (i = 0; i < 32; i++) {
1425 if ((i & 3) == 0)
7fe48483
FB		 1426 cpu_fprintf(f, "%%f%02d:", i);
1427 cpu_fprintf(f, " %016lf", env->fpr[i]);
e8af50a3 1428 if ((i & 3) == 3)
7fe48483 1429 cpu_fprintf(f, "\n");
e8af50a3 1430 }
7fe48483 1431 cpu_fprintf(f, "psr: 0x%08x -> %c%c%c%c %c%c%c wim: 0x%08x\n", GET_PSR(env),
cf495bcf
FB		 1432 GET_FLAG(PSR_ZERO, 'Z'), GET_FLAG(PSR_OVF, 'V'),
1433 GET_FLAG(PSR_NEG, 'N'), GET_FLAG(PSR_CARRY, 'C'),
e8af50a3
FB		 1434 env->psrs?'S':'-', env->psrps?'P':'-',
1435 env->psret?'E':'-', env->wim);
7fe48483 1436 cpu_fprintf(f, "fsr: 0x%08x\n", env->fsr);
7a3f1944 1437}
edfcbd99
FB		 1438
1439target_ulong cpu_get_phys_page_debug(CPUState *env, target_ulong addr)
1440{
1441 return addr;
1442}
658138bc
FB		 1443
1444void helper_flush(target_ulong addr)
1445{
1446 addr &= ~7;
1447 tb_invalidate_page_range(addr, addr + 8);
1448}
Mirror of https://git.qemu.org/git/qemu.git