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1 | /* | |
2 | * Copyright (c) 2016 Rockchip, Inc. | |
3 | * Authors: Daniel Meng <daniel.meng@rock-chips.com> | |
4 | * | |
5 | * SPDX-License-Identifier: GPL-2.0+ | |
6 | */ | |
7 | #include <common.h> | |
8 | #include <dm.h> | |
9 | #include <fdtdec.h> | |
10 | #include <libfdt.h> | |
11 | #include <malloc.h> | |
12 | #include <usb.h> | |
13 | #include <watchdog.h> | |
14 | #include <asm/gpio.h> | |
15 | #include <linux/errno.h> | |
16 | #include <linux/compat.h> | |
17 | #include <linux/usb/dwc3.h> | |
18 | ||
19 | #include "xhci.h" | |
20 | ||
21 | DECLARE_GLOBAL_DATA_PTR; | |
22 | ||
23 | struct rockchip_xhci_platdata { | |
24 | fdt_addr_t hcd_base; | |
25 | fdt_addr_t phy_base; | |
26 | struct gpio_desc vbus_gpio; | |
27 | }; | |
28 | ||
29 | /* | |
30 | * Contains pointers to register base addresses | |
31 | * for the usb controller. | |
32 | */ | |
33 | struct rockchip_xhci { | |
34 | struct usb_platdata usb_plat; | |
35 | struct xhci_ctrl ctrl; | |
36 | struct xhci_hccr *hcd; | |
37 | struct dwc3 *dwc3_reg; | |
38 | }; | |
39 | ||
40 | static int xhci_usb_ofdata_to_platdata(struct udevice *dev) | |
41 | { | |
42 | struct rockchip_xhci_platdata *plat = dev_get_platdata(dev); | |
43 | struct udevice *child; | |
44 | int ret = 0; | |
45 | ||
46 | /* | |
47 | * Get the base address for XHCI controller from the device node | |
48 | */ | |
49 | plat->hcd_base = devfdt_get_addr(dev); | |
50 | if (plat->hcd_base == FDT_ADDR_T_NONE) { | |
51 | debug("Can't get the XHCI register base address\n"); | |
52 | return -ENXIO; | |
53 | } | |
54 | ||
55 | /* Get the base address for usbphy from the device node */ | |
56 | for (device_find_first_child(dev, &child); child; | |
57 | device_find_next_child(&child)) { | |
58 | if (!of_device_is_compatible(child, "rockchip,rk3399-usb3-phy")) | |
59 | continue; | |
60 | plat->phy_base = devfdt_get_addr(child); | |
61 | break; | |
62 | } | |
63 | ||
64 | if (plat->phy_base == FDT_ADDR_T_NONE) { | |
65 | debug("Can't get the usbphy register address\n"); | |
66 | return -ENXIO; | |
67 | } | |
68 | ||
69 | /* Vbus gpio */ | |
70 | ret = gpio_request_by_name(dev, "rockchip,vbus-gpio", 0, | |
71 | &plat->vbus_gpio, GPIOD_IS_OUT); | |
72 | if (ret) | |
73 | debug("rockchip,vbus-gpio node missing!"); | |
74 | ||
75 | return 0; | |
76 | } | |
77 | ||
78 | /* | |
79 | * rockchip_dwc3_phy_setup() - Configure USB PHY Interface of DWC3 Core | |
80 | * @dwc: Pointer to our controller context structure | |
81 | * @dev: Pointer to ulcass device | |
82 | */ | |
83 | static void rockchip_dwc3_phy_setup(struct dwc3 *dwc3_reg, | |
84 | struct udevice *dev) | |
85 | { | |
86 | u32 reg; | |
87 | const void *blob = gd->fdt_blob; | |
88 | u32 utmi_bits; | |
89 | ||
90 | /* Set dwc3 usb2 phy config */ | |
91 | reg = readl(&dwc3_reg->g_usb2phycfg[0]); | |
92 | ||
93 | if (fdtdec_get_bool(blob, dev_of_offset(dev), | |
94 | "snps,dis-enblslpm-quirk")) | |
95 | reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM; | |
96 | ||
97 | utmi_bits = fdtdec_get_int(blob, dev_of_offset(dev), | |
98 | "snps,phyif-utmi-bits", -1); | |
99 | if (utmi_bits == 16) { | |
100 | reg |= DWC3_GUSB2PHYCFG_PHYIF; | |
101 | reg &= ~DWC3_GUSB2PHYCFG_USBTRDTIM_MASK; | |
102 | reg |= DWC3_GUSB2PHYCFG_USBTRDTIM_16BIT; | |
103 | } else if (utmi_bits == 8) { | |
104 | reg &= ~DWC3_GUSB2PHYCFG_PHYIF; | |
105 | reg &= ~DWC3_GUSB2PHYCFG_USBTRDTIM_MASK; | |
106 | reg |= DWC3_GUSB2PHYCFG_USBTRDTIM_8BIT; | |
107 | } | |
108 | ||
109 | if (fdtdec_get_bool(blob, dev_of_offset(dev), | |
110 | "snps,dis-u2-freeclk-exists-quirk")) | |
111 | reg &= ~DWC3_GUSB2PHYCFG_U2_FREECLK_EXISTS; | |
112 | ||
113 | if (fdtdec_get_bool(blob, dev_of_offset(dev), | |
114 | "snps,dis-u2-susphy-quirk")) | |
115 | reg &= ~DWC3_GUSB2PHYCFG_SUSPHY; | |
116 | ||
117 | writel(reg, &dwc3_reg->g_usb2phycfg[0]); | |
118 | } | |
119 | ||
120 | static int rockchip_xhci_core_init(struct rockchip_xhci *rkxhci, | |
121 | struct udevice *dev) | |
122 | { | |
123 | int ret; | |
124 | ||
125 | ret = dwc3_core_init(rkxhci->dwc3_reg); | |
126 | if (ret) { | |
127 | debug("failed to initialize core\n"); | |
128 | return ret; | |
129 | } | |
130 | ||
131 | rockchip_dwc3_phy_setup(rkxhci->dwc3_reg, dev); | |
132 | ||
133 | /* We are hard-coding DWC3 core to Host Mode */ | |
134 | dwc3_set_mode(rkxhci->dwc3_reg, DWC3_GCTL_PRTCAP_HOST); | |
135 | ||
136 | return 0; | |
137 | } | |
138 | ||
139 | static int rockchip_xhci_core_exit(struct rockchip_xhci *rkxhci) | |
140 | { | |
141 | return 0; | |
142 | } | |
143 | ||
144 | static int xhci_usb_probe(struct udevice *dev) | |
145 | { | |
146 | struct rockchip_xhci_platdata *plat = dev_get_platdata(dev); | |
147 | struct rockchip_xhci *ctx = dev_get_priv(dev); | |
148 | struct xhci_hcor *hcor; | |
149 | int ret; | |
150 | ||
151 | ctx->hcd = (struct xhci_hccr *)plat->hcd_base; | |
152 | ctx->dwc3_reg = (struct dwc3 *)((char *)(ctx->hcd) + DWC3_REG_OFFSET); | |
153 | hcor = (struct xhci_hcor *)((uint64_t)ctx->hcd + | |
154 | HC_LENGTH(xhci_readl(&ctx->hcd->cr_capbase))); | |
155 | ||
156 | /* setup the Vbus gpio here */ | |
157 | if (dm_gpio_is_valid(&plat->vbus_gpio)) | |
158 | dm_gpio_set_value(&plat->vbus_gpio, 1); | |
159 | ||
160 | ret = rockchip_xhci_core_init(ctx, dev); | |
161 | if (ret) { | |
162 | debug("XHCI: failed to initialize controller\n"); | |
163 | return ret; | |
164 | } | |
165 | ||
166 | return xhci_register(dev, ctx->hcd, hcor); | |
167 | } | |
168 | ||
169 | static int xhci_usb_remove(struct udevice *dev) | |
170 | { | |
171 | struct rockchip_xhci *ctx = dev_get_priv(dev); | |
172 | int ret; | |
173 | ||
174 | ret = xhci_deregister(dev); | |
175 | if (ret) | |
176 | return ret; | |
177 | ret = rockchip_xhci_core_exit(ctx); | |
178 | if (ret) | |
179 | return ret; | |
180 | ||
181 | return 0; | |
182 | } | |
183 | ||
184 | static const struct udevice_id xhci_usb_ids[] = { | |
185 | { .compatible = "rockchip,rk3399-xhci" }, | |
186 | { } | |
187 | }; | |
188 | ||
189 | U_BOOT_DRIVER(usb_xhci) = { | |
190 | .name = "xhci_rockchip", | |
191 | .id = UCLASS_USB, | |
192 | .of_match = xhci_usb_ids, | |
193 | .ofdata_to_platdata = xhci_usb_ofdata_to_platdata, | |
194 | .probe = xhci_usb_probe, | |
195 | .remove = xhci_usb_remove, | |
196 | .ops = &xhci_usb_ops, | |
197 | .bind = dm_scan_fdt_dev, | |
198 | .platdata_auto_alloc_size = sizeof(struct rockchip_xhci_platdata), | |
199 | .priv_auto_alloc_size = sizeof(struct rockchip_xhci), | |
200 | .flags = DM_FLAG_ALLOC_PRIV_DMA, | |
201 | }; | |
202 | ||
203 | static const struct udevice_id usb_phy_ids[] = { | |
204 | { .compatible = "rockchip,rk3399-usb3-phy" }, | |
205 | { } | |
206 | }; | |
207 | ||
208 | U_BOOT_DRIVER(usb_phy) = { | |
209 | .name = "usb_phy_rockchip", | |
210 | .of_match = usb_phy_ids, | |
211 | }; |