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1 | /* | |
2 | * VT82C686B south bridge support | |
3 | * | |
4 | * Copyright (c) 2008 yajin (yajin@vm-kernel.org) | |
5 | * Copyright (c) 2009 chenming (chenming@rdc.faw.com.cn) | |
6 | * Copyright (c) 2010 Huacai Chen (zltjiangshi@gmail.com) | |
7 | * This code is licensed under the GNU GPL v2. | |
8 | * | |
9 | * Contributions after 2012-01-13 are licensed under the terms of the | |
10 | * GNU GPL, version 2 or (at your option) any later version. | |
11 | * | |
12 | * VT8231 south bridge support and general clean up to allow it | |
13 | * Copyright (c) 2018-2020 BALATON Zoltan | |
14 | */ | |
15 | ||
16 | #include "qemu/osdep.h" | |
17 | #include "hw/isa/vt82c686.h" | |
18 | #include "hw/pci/pci.h" | |
19 | #include "hw/qdev-properties.h" | |
20 | #include "hw/ide/pci.h" | |
21 | #include "hw/isa/isa.h" | |
22 | #include "hw/isa/superio.h" | |
23 | #include "hw/intc/i8259.h" | |
24 | #include "hw/irq.h" | |
25 | #include "hw/dma/i8257.h" | |
26 | #include "hw/usb/hcd-uhci.h" | |
27 | #include "hw/timer/i8254.h" | |
28 | #include "hw/rtc/mc146818rtc.h" | |
29 | #include "migration/vmstate.h" | |
30 | #include "hw/isa/apm.h" | |
31 | #include "hw/acpi/acpi.h" | |
32 | #include "hw/i2c/pm_smbus.h" | |
33 | #include "qapi/error.h" | |
34 | #include "qemu/log.h" | |
35 | #include "qemu/module.h" | |
36 | #include "qemu/range.h" | |
37 | #include "qemu/timer.h" | |
38 | #include "trace.h" | |
39 | ||
40 | #define TYPE_VIA_PM "via-pm" | |
41 | OBJECT_DECLARE_SIMPLE_TYPE(ViaPMState, VIA_PM) | |
42 | ||
43 | struct ViaPMState { | |
44 | PCIDevice dev; | |
45 | MemoryRegion io; | |
46 | ACPIREGS ar; | |
47 | APMState apm; | |
48 | PMSMBus smb; | |
49 | }; | |
50 | ||
51 | static void pm_io_space_update(ViaPMState *s) | |
52 | { | |
53 | uint32_t pmbase = pci_get_long(s->dev.config + 0x48) & 0xff80UL; | |
54 | ||
55 | memory_region_transaction_begin(); | |
56 | memory_region_set_address(&s->io, pmbase); | |
57 | memory_region_set_enabled(&s->io, s->dev.config[0x41] & BIT(7)); | |
58 | memory_region_transaction_commit(); | |
59 | } | |
60 | ||
61 | static void smb_io_space_update(ViaPMState *s) | |
62 | { | |
63 | uint32_t smbase = pci_get_long(s->dev.config + 0x90) & 0xfff0UL; | |
64 | ||
65 | memory_region_transaction_begin(); | |
66 | memory_region_set_address(&s->smb.io, smbase); | |
67 | memory_region_set_enabled(&s->smb.io, s->dev.config[0xd2] & BIT(0)); | |
68 | memory_region_transaction_commit(); | |
69 | } | |
70 | ||
71 | static int vmstate_acpi_post_load(void *opaque, int version_id) | |
72 | { | |
73 | ViaPMState *s = opaque; | |
74 | ||
75 | pm_io_space_update(s); | |
76 | smb_io_space_update(s); | |
77 | return 0; | |
78 | } | |
79 | ||
80 | static const VMStateDescription vmstate_acpi = { | |
81 | .name = "vt82c686b_pm", | |
82 | .version_id = 1, | |
83 | .minimum_version_id = 1, | |
84 | .post_load = vmstate_acpi_post_load, | |
85 | .fields = (VMStateField[]) { | |
86 | VMSTATE_PCI_DEVICE(dev, ViaPMState), | |
87 | VMSTATE_UINT16(ar.pm1.evt.sts, ViaPMState), | |
88 | VMSTATE_UINT16(ar.pm1.evt.en, ViaPMState), | |
89 | VMSTATE_UINT16(ar.pm1.cnt.cnt, ViaPMState), | |
90 | VMSTATE_STRUCT(apm, ViaPMState, 0, vmstate_apm, APMState), | |
91 | VMSTATE_TIMER_PTR(ar.tmr.timer, ViaPMState), | |
92 | VMSTATE_INT64(ar.tmr.overflow_time, ViaPMState), | |
93 | VMSTATE_END_OF_LIST() | |
94 | } | |
95 | }; | |
96 | ||
97 | static void pm_write_config(PCIDevice *d, uint32_t addr, uint32_t val, int len) | |
98 | { | |
99 | ViaPMState *s = VIA_PM(d); | |
100 | ||
101 | trace_via_pm_write(addr, val, len); | |
102 | pci_default_write_config(d, addr, val, len); | |
103 | if (ranges_overlap(addr, len, 0x48, 4)) { | |
104 | uint32_t v = pci_get_long(s->dev.config + 0x48); | |
105 | pci_set_long(s->dev.config + 0x48, (v & 0xff80UL) | 1); | |
106 | } | |
107 | if (range_covers_byte(addr, len, 0x41)) { | |
108 | pm_io_space_update(s); | |
109 | } | |
110 | if (ranges_overlap(addr, len, 0x90, 4)) { | |
111 | uint32_t v = pci_get_long(s->dev.config + 0x90); | |
112 | pci_set_long(s->dev.config + 0x90, (v & 0xfff0UL) | 1); | |
113 | } | |
114 | if (range_covers_byte(addr, len, 0xd2)) { | |
115 | s->dev.config[0xd2] &= 0xf; | |
116 | smb_io_space_update(s); | |
117 | } | |
118 | } | |
119 | ||
120 | static void pm_io_write(void *op, hwaddr addr, uint64_t data, unsigned size) | |
121 | { | |
122 | trace_via_pm_io_write(addr, data, size); | |
123 | } | |
124 | ||
125 | static uint64_t pm_io_read(void *op, hwaddr addr, unsigned size) | |
126 | { | |
127 | trace_via_pm_io_read(addr, 0, size); | |
128 | return 0; | |
129 | } | |
130 | ||
131 | static const MemoryRegionOps pm_io_ops = { | |
132 | .read = pm_io_read, | |
133 | .write = pm_io_write, | |
134 | .endianness = DEVICE_NATIVE_ENDIAN, | |
135 | .impl = { | |
136 | .min_access_size = 1, | |
137 | .max_access_size = 1, | |
138 | }, | |
139 | }; | |
140 | ||
141 | static void pm_update_sci(ViaPMState *s) | |
142 | { | |
143 | int sci_level, pmsts; | |
144 | ||
145 | pmsts = acpi_pm1_evt_get_sts(&s->ar); | |
146 | sci_level = (((pmsts & s->ar.pm1.evt.en) & | |
147 | (ACPI_BITMASK_RT_CLOCK_ENABLE | | |
148 | ACPI_BITMASK_POWER_BUTTON_ENABLE | | |
149 | ACPI_BITMASK_GLOBAL_LOCK_ENABLE | | |
150 | ACPI_BITMASK_TIMER_ENABLE)) != 0); | |
151 | if (pci_get_byte(s->dev.config + PCI_INTERRUPT_PIN)) { | |
152 | /* | |
153 | * FIXME: | |
154 | * Fix device model that realizes this PM device and remove | |
155 | * this work around. | |
156 | * The device model should wire SCI and setup | |
157 | * PCI_INTERRUPT_PIN properly. | |
158 | * If PIN# = 0(interrupt pin isn't used), don't raise SCI as | |
159 | * work around. | |
160 | */ | |
161 | pci_set_irq(&s->dev, sci_level); | |
162 | } | |
163 | /* schedule a timer interruption if needed */ | |
164 | acpi_pm_tmr_update(&s->ar, (s->ar.pm1.evt.en & ACPI_BITMASK_TIMER_ENABLE) && | |
165 | !(pmsts & ACPI_BITMASK_TIMER_STATUS)); | |
166 | } | |
167 | ||
168 | static void pm_tmr_timer(ACPIREGS *ar) | |
169 | { | |
170 | ViaPMState *s = container_of(ar, ViaPMState, ar); | |
171 | pm_update_sci(s); | |
172 | } | |
173 | ||
174 | static void via_pm_reset(DeviceState *d) | |
175 | { | |
176 | ViaPMState *s = VIA_PM(d); | |
177 | ||
178 | memset(s->dev.config + PCI_CONFIG_HEADER_SIZE, 0, | |
179 | PCI_CONFIG_SPACE_SIZE - PCI_CONFIG_HEADER_SIZE); | |
180 | /* Power Management IO base */ | |
181 | pci_set_long(s->dev.config + 0x48, 1); | |
182 | /* SMBus IO base */ | |
183 | pci_set_long(s->dev.config + 0x90, 1); | |
184 | ||
185 | acpi_pm1_evt_reset(&s->ar); | |
186 | acpi_pm1_cnt_reset(&s->ar); | |
187 | acpi_pm_tmr_reset(&s->ar); | |
188 | pm_update_sci(s); | |
189 | ||
190 | pm_io_space_update(s); | |
191 | smb_io_space_update(s); | |
192 | } | |
193 | ||
194 | static void via_pm_realize(PCIDevice *dev, Error **errp) | |
195 | { | |
196 | ViaPMState *s = VIA_PM(dev); | |
197 | ||
198 | pci_set_word(dev->config + PCI_STATUS, PCI_STATUS_FAST_BACK | | |
199 | PCI_STATUS_DEVSEL_MEDIUM); | |
200 | ||
201 | pm_smbus_init(DEVICE(s), &s->smb, false); | |
202 | memory_region_add_subregion(pci_address_space_io(dev), 0, &s->smb.io); | |
203 | memory_region_set_enabled(&s->smb.io, false); | |
204 | ||
205 | apm_init(dev, &s->apm, NULL, s); | |
206 | ||
207 | memory_region_init_io(&s->io, OBJECT(dev), &pm_io_ops, s, "via-pm", 128); | |
208 | memory_region_add_subregion(pci_address_space_io(dev), 0, &s->io); | |
209 | memory_region_set_enabled(&s->io, false); | |
210 | ||
211 | acpi_pm_tmr_init(&s->ar, pm_tmr_timer, &s->io); | |
212 | acpi_pm1_evt_init(&s->ar, pm_tmr_timer, &s->io); | |
213 | acpi_pm1_cnt_init(&s->ar, &s->io, false, false, 2, false); | |
214 | } | |
215 | ||
216 | typedef struct via_pm_init_info { | |
217 | uint16_t device_id; | |
218 | } ViaPMInitInfo; | |
219 | ||
220 | static void via_pm_class_init(ObjectClass *klass, void *data) | |
221 | { | |
222 | DeviceClass *dc = DEVICE_CLASS(klass); | |
223 | PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); | |
224 | ViaPMInitInfo *info = data; | |
225 | ||
226 | k->realize = via_pm_realize; | |
227 | k->config_write = pm_write_config; | |
228 | k->vendor_id = PCI_VENDOR_ID_VIA; | |
229 | k->device_id = info->device_id; | |
230 | k->class_id = PCI_CLASS_BRIDGE_OTHER; | |
231 | k->revision = 0x40; | |
232 | dc->reset = via_pm_reset; | |
233 | /* Reason: part of VIA south bridge, does not exist stand alone */ | |
234 | dc->user_creatable = false; | |
235 | dc->vmsd = &vmstate_acpi; | |
236 | } | |
237 | ||
238 | static const TypeInfo via_pm_info = { | |
239 | .name = TYPE_VIA_PM, | |
240 | .parent = TYPE_PCI_DEVICE, | |
241 | .instance_size = sizeof(ViaPMState), | |
242 | .abstract = true, | |
243 | .interfaces = (InterfaceInfo[]) { | |
244 | { INTERFACE_CONVENTIONAL_PCI_DEVICE }, | |
245 | { }, | |
246 | }, | |
247 | }; | |
248 | ||
249 | static const ViaPMInitInfo vt82c686b_pm_init_info = { | |
250 | .device_id = PCI_DEVICE_ID_VIA_82C686B_PM, | |
251 | }; | |
252 | ||
253 | #define TYPE_VT82C686B_PM "vt82c686b-pm" | |
254 | ||
255 | static const TypeInfo vt82c686b_pm_info = { | |
256 | .name = TYPE_VT82C686B_PM, | |
257 | .parent = TYPE_VIA_PM, | |
258 | .class_init = via_pm_class_init, | |
259 | .class_data = (void *)&vt82c686b_pm_init_info, | |
260 | }; | |
261 | ||
262 | static const ViaPMInitInfo vt8231_pm_init_info = { | |
263 | .device_id = PCI_DEVICE_ID_VIA_8231_PM, | |
264 | }; | |
265 | ||
266 | #define TYPE_VT8231_PM "vt8231-pm" | |
267 | ||
268 | static const TypeInfo vt8231_pm_info = { | |
269 | .name = TYPE_VT8231_PM, | |
270 | .parent = TYPE_VIA_PM, | |
271 | .class_init = via_pm_class_init, | |
272 | .class_data = (void *)&vt8231_pm_init_info, | |
273 | }; | |
274 | ||
275 | ||
276 | #define TYPE_VIA_SUPERIO "via-superio" | |
277 | OBJECT_DECLARE_SIMPLE_TYPE(ViaSuperIOState, VIA_SUPERIO) | |
278 | ||
279 | struct ViaSuperIOState { | |
280 | ISASuperIODevice superio; | |
281 | uint8_t regs[0x100]; | |
282 | const MemoryRegionOps *io_ops; | |
283 | MemoryRegion io; | |
284 | }; | |
285 | ||
286 | static inline void via_superio_io_enable(ViaSuperIOState *s, bool enable) | |
287 | { | |
288 | memory_region_set_enabled(&s->io, enable); | |
289 | } | |
290 | ||
291 | static void via_superio_realize(DeviceState *d, Error **errp) | |
292 | { | |
293 | ViaSuperIOState *s = VIA_SUPERIO(d); | |
294 | ISASuperIOClass *ic = ISA_SUPERIO_GET_CLASS(s); | |
295 | Error *local_err = NULL; | |
296 | ||
297 | assert(s->io_ops); | |
298 | ic->parent_realize(d, &local_err); | |
299 | if (local_err) { | |
300 | error_propagate(errp, local_err); | |
301 | return; | |
302 | } | |
303 | memory_region_init_io(&s->io, OBJECT(d), s->io_ops, s, "via-superio", 2); | |
304 | memory_region_set_enabled(&s->io, false); | |
305 | /* The floppy also uses 0x3f0 and 0x3f1 but this seems to work anyway */ | |
306 | memory_region_add_subregion(isa_address_space_io(ISA_DEVICE(s)), 0x3f0, | |
307 | &s->io); | |
308 | } | |
309 | ||
310 | static uint64_t via_superio_cfg_read(void *opaque, hwaddr addr, unsigned size) | |
311 | { | |
312 | ViaSuperIOState *sc = opaque; | |
313 | uint8_t idx = sc->regs[0]; | |
314 | uint8_t val = sc->regs[idx]; | |
315 | ||
316 | if (addr == 0) { | |
317 | return idx; | |
318 | } | |
319 | if (addr == 1 && idx == 0) { | |
320 | val = 0; /* reading reg 0 where we store index value */ | |
321 | } | |
322 | trace_via_superio_read(idx, val); | |
323 | return val; | |
324 | } | |
325 | ||
326 | static void via_superio_class_init(ObjectClass *klass, void *data) | |
327 | { | |
328 | DeviceClass *dc = DEVICE_CLASS(klass); | |
329 | ISASuperIOClass *sc = ISA_SUPERIO_CLASS(klass); | |
330 | ||
331 | sc->parent_realize = dc->realize; | |
332 | dc->realize = via_superio_realize; | |
333 | } | |
334 | ||
335 | static const TypeInfo via_superio_info = { | |
336 | .name = TYPE_VIA_SUPERIO, | |
337 | .parent = TYPE_ISA_SUPERIO, | |
338 | .instance_size = sizeof(ViaSuperIOState), | |
339 | .class_size = sizeof(ISASuperIOClass), | |
340 | .class_init = via_superio_class_init, | |
341 | .abstract = true, | |
342 | }; | |
343 | ||
344 | #define TYPE_VT82C686B_SUPERIO "vt82c686b-superio" | |
345 | ||
346 | static void vt82c686b_superio_cfg_write(void *opaque, hwaddr addr, | |
347 | uint64_t data, unsigned size) | |
348 | { | |
349 | ViaSuperIOState *sc = opaque; | |
350 | uint8_t idx = sc->regs[0]; | |
351 | ||
352 | if (addr == 0) { /* config index register */ | |
353 | sc->regs[0] = data; | |
354 | return; | |
355 | } | |
356 | ||
357 | /* config data register */ | |
358 | trace_via_superio_write(idx, data); | |
359 | switch (idx) { | |
360 | case 0x00 ... 0xdf: | |
361 | case 0xe4: | |
362 | case 0xe5: | |
363 | case 0xe9 ... 0xed: | |
364 | case 0xf3: | |
365 | case 0xf5: | |
366 | case 0xf7: | |
367 | case 0xf9 ... 0xfb: | |
368 | case 0xfd ... 0xff: | |
369 | /* ignore write to read only registers */ | |
370 | return; | |
371 | /* case 0xe6 ... 0xe8: Should set base port of parallel and serial */ | |
372 | default: | |
373 | qemu_log_mask(LOG_UNIMP, | |
374 | "via_superio_cfg: unimplemented register 0x%x\n", idx); | |
375 | break; | |
376 | } | |
377 | sc->regs[idx] = data; | |
378 | } | |
379 | ||
380 | static const MemoryRegionOps vt82c686b_superio_cfg_ops = { | |
381 | .read = via_superio_cfg_read, | |
382 | .write = vt82c686b_superio_cfg_write, | |
383 | .endianness = DEVICE_NATIVE_ENDIAN, | |
384 | .impl = { | |
385 | .min_access_size = 1, | |
386 | .max_access_size = 1, | |
387 | }, | |
388 | }; | |
389 | ||
390 | static void vt82c686b_superio_reset(DeviceState *dev) | |
391 | { | |
392 | ViaSuperIOState *s = VIA_SUPERIO(dev); | |
393 | ||
394 | memset(s->regs, 0, sizeof(s->regs)); | |
395 | /* Device ID */ | |
396 | vt82c686b_superio_cfg_write(s, 0, 0xe0, 1); | |
397 | vt82c686b_superio_cfg_write(s, 1, 0x3c, 1); | |
398 | /* Function select - all disabled */ | |
399 | vt82c686b_superio_cfg_write(s, 0, 0xe2, 1); | |
400 | vt82c686b_superio_cfg_write(s, 1, 0x03, 1); | |
401 | /* Floppy ctrl base addr 0x3f0-7 */ | |
402 | vt82c686b_superio_cfg_write(s, 0, 0xe3, 1); | |
403 | vt82c686b_superio_cfg_write(s, 1, 0xfc, 1); | |
404 | /* Parallel port base addr 0x378-f */ | |
405 | vt82c686b_superio_cfg_write(s, 0, 0xe6, 1); | |
406 | vt82c686b_superio_cfg_write(s, 1, 0xde, 1); | |
407 | /* Serial port 1 base addr 0x3f8-f */ | |
408 | vt82c686b_superio_cfg_write(s, 0, 0xe7, 1); | |
409 | vt82c686b_superio_cfg_write(s, 1, 0xfe, 1); | |
410 | /* Serial port 2 base addr 0x2f8-f */ | |
411 | vt82c686b_superio_cfg_write(s, 0, 0xe8, 1); | |
412 | vt82c686b_superio_cfg_write(s, 1, 0xbe, 1); | |
413 | ||
414 | vt82c686b_superio_cfg_write(s, 0, 0, 1); | |
415 | } | |
416 | ||
417 | static void vt82c686b_superio_init(Object *obj) | |
418 | { | |
419 | VIA_SUPERIO(obj)->io_ops = &vt82c686b_superio_cfg_ops; | |
420 | } | |
421 | ||
422 | static void vt82c686b_superio_class_init(ObjectClass *klass, void *data) | |
423 | { | |
424 | DeviceClass *dc = DEVICE_CLASS(klass); | |
425 | ISASuperIOClass *sc = ISA_SUPERIO_CLASS(klass); | |
426 | ||
427 | dc->reset = vt82c686b_superio_reset; | |
428 | sc->serial.count = 2; | |
429 | sc->parallel.count = 1; | |
430 | sc->ide.count = 0; /* emulated by via-ide */ | |
431 | sc->floppy.count = 1; | |
432 | } | |
433 | ||
434 | static const TypeInfo vt82c686b_superio_info = { | |
435 | .name = TYPE_VT82C686B_SUPERIO, | |
436 | .parent = TYPE_VIA_SUPERIO, | |
437 | .instance_size = sizeof(ViaSuperIOState), | |
438 | .instance_init = vt82c686b_superio_init, | |
439 | .class_size = sizeof(ISASuperIOClass), | |
440 | .class_init = vt82c686b_superio_class_init, | |
441 | }; | |
442 | ||
443 | ||
444 | #define TYPE_VT8231_SUPERIO "vt8231-superio" | |
445 | ||
446 | static void vt8231_superio_cfg_write(void *opaque, hwaddr addr, | |
447 | uint64_t data, unsigned size) | |
448 | { | |
449 | ViaSuperIOState *sc = opaque; | |
450 | uint8_t idx = sc->regs[0]; | |
451 | ||
452 | if (addr == 0) { /* config index register */ | |
453 | sc->regs[0] = data; | |
454 | return; | |
455 | } | |
456 | ||
457 | /* config data register */ | |
458 | trace_via_superio_write(idx, data); | |
459 | switch (idx) { | |
460 | case 0x00 ... 0xdf: | |
461 | case 0xe7 ... 0xef: | |
462 | case 0xf0 ... 0xf1: | |
463 | case 0xf5: | |
464 | case 0xf8: | |
465 | case 0xfd: | |
466 | /* ignore write to read only registers */ | |
467 | return; | |
468 | default: | |
469 | qemu_log_mask(LOG_UNIMP, | |
470 | "via_superio_cfg: unimplemented register 0x%x\n", idx); | |
471 | break; | |
472 | } | |
473 | sc->regs[idx] = data; | |
474 | } | |
475 | ||
476 | static const MemoryRegionOps vt8231_superio_cfg_ops = { | |
477 | .read = via_superio_cfg_read, | |
478 | .write = vt8231_superio_cfg_write, | |
479 | .endianness = DEVICE_NATIVE_ENDIAN, | |
480 | .impl = { | |
481 | .min_access_size = 1, | |
482 | .max_access_size = 1, | |
483 | }, | |
484 | }; | |
485 | ||
486 | static void vt8231_superio_reset(DeviceState *dev) | |
487 | { | |
488 | ViaSuperIOState *s = VIA_SUPERIO(dev); | |
489 | ||
490 | memset(s->regs, 0, sizeof(s->regs)); | |
491 | /* Device ID */ | |
492 | s->regs[0xf0] = 0x3c; | |
493 | /* Device revision */ | |
494 | s->regs[0xf1] = 0x01; | |
495 | /* Function select - all disabled */ | |
496 | vt8231_superio_cfg_write(s, 0, 0xf2, 1); | |
497 | vt8231_superio_cfg_write(s, 1, 0x03, 1); | |
498 | /* Serial port base addr */ | |
499 | vt8231_superio_cfg_write(s, 0, 0xf4, 1); | |
500 | vt8231_superio_cfg_write(s, 1, 0xfe, 1); | |
501 | /* Parallel port base addr */ | |
502 | vt8231_superio_cfg_write(s, 0, 0xf6, 1); | |
503 | vt8231_superio_cfg_write(s, 1, 0xde, 1); | |
504 | /* Floppy ctrl base addr */ | |
505 | vt8231_superio_cfg_write(s, 0, 0xf7, 1); | |
506 | vt8231_superio_cfg_write(s, 1, 0xfc, 1); | |
507 | ||
508 | vt8231_superio_cfg_write(s, 0, 0, 1); | |
509 | } | |
510 | ||
511 | static void vt8231_superio_init(Object *obj) | |
512 | { | |
513 | VIA_SUPERIO(obj)->io_ops = &vt8231_superio_cfg_ops; | |
514 | } | |
515 | ||
516 | static uint16_t vt8231_superio_serial_iobase(ISASuperIODevice *sio, | |
517 | uint8_t index) | |
518 | { | |
519 | return 0x2f8; /* FIXME: This should be settable via registers f2-f4 */ | |
520 | } | |
521 | ||
522 | static void vt8231_superio_class_init(ObjectClass *klass, void *data) | |
523 | { | |
524 | DeviceClass *dc = DEVICE_CLASS(klass); | |
525 | ISASuperIOClass *sc = ISA_SUPERIO_CLASS(klass); | |
526 | ||
527 | dc->reset = vt8231_superio_reset; | |
528 | sc->serial.count = 1; | |
529 | sc->serial.get_iobase = vt8231_superio_serial_iobase; | |
530 | sc->parallel.count = 1; | |
531 | sc->ide.count = 0; /* emulated by via-ide */ | |
532 | sc->floppy.count = 1; | |
533 | } | |
534 | ||
535 | static const TypeInfo vt8231_superio_info = { | |
536 | .name = TYPE_VT8231_SUPERIO, | |
537 | .parent = TYPE_VIA_SUPERIO, | |
538 | .instance_size = sizeof(ViaSuperIOState), | |
539 | .instance_init = vt8231_superio_init, | |
540 | .class_size = sizeof(ISASuperIOClass), | |
541 | .class_init = vt8231_superio_class_init, | |
542 | }; | |
543 | ||
544 | ||
545 | #define TYPE_VIA_ISA "via-isa" | |
546 | OBJECT_DECLARE_SIMPLE_TYPE(ViaISAState, VIA_ISA) | |
547 | ||
548 | struct ViaISAState { | |
549 | PCIDevice dev; | |
550 | qemu_irq cpu_intr; | |
551 | qemu_irq *isa_irqs_in; | |
552 | uint16_t irq_state[ISA_NUM_IRQS]; | |
553 | ViaSuperIOState via_sio; | |
554 | MC146818RtcState rtc; | |
555 | PCIIDEState ide; | |
556 | UHCIState uhci[2]; | |
557 | ViaPMState pm; | |
558 | ViaAC97State ac97; | |
559 | PCIDevice mc97; | |
560 | }; | |
561 | ||
562 | static const VMStateDescription vmstate_via = { | |
563 | .name = "via-isa", | |
564 | .version_id = 1, | |
565 | .minimum_version_id = 1, | |
566 | .fields = (VMStateField[]) { | |
567 | VMSTATE_PCI_DEVICE(dev, ViaISAState), | |
568 | VMSTATE_END_OF_LIST() | |
569 | } | |
570 | }; | |
571 | ||
572 | static void via_isa_init(Object *obj) | |
573 | { | |
574 | ViaISAState *s = VIA_ISA(obj); | |
575 | ||
576 | object_initialize_child(obj, "rtc", &s->rtc, TYPE_MC146818_RTC); | |
577 | object_initialize_child(obj, "ide", &s->ide, TYPE_VIA_IDE); | |
578 | object_initialize_child(obj, "uhci1", &s->uhci[0], TYPE_VT82C686B_USB_UHCI); | |
579 | object_initialize_child(obj, "uhci2", &s->uhci[1], TYPE_VT82C686B_USB_UHCI); | |
580 | object_initialize_child(obj, "ac97", &s->ac97, TYPE_VIA_AC97); | |
581 | object_initialize_child(obj, "mc97", &s->mc97, TYPE_VIA_MC97); | |
582 | } | |
583 | ||
584 | static const TypeInfo via_isa_info = { | |
585 | .name = TYPE_VIA_ISA, | |
586 | .parent = TYPE_PCI_DEVICE, | |
587 | .instance_size = sizeof(ViaISAState), | |
588 | .instance_init = via_isa_init, | |
589 | .abstract = true, | |
590 | .interfaces = (InterfaceInfo[]) { | |
591 | { INTERFACE_CONVENTIONAL_PCI_DEVICE }, | |
592 | { }, | |
593 | }, | |
594 | }; | |
595 | ||
596 | static int via_isa_get_pci_irq(const ViaISAState *s, int pin) | |
597 | { | |
598 | switch (pin) { | |
599 | case 0: | |
600 | return s->dev.config[0x55] >> 4; | |
601 | case 1: | |
602 | return s->dev.config[0x56] & 0xf; | |
603 | case 2: | |
604 | return s->dev.config[0x56] >> 4; | |
605 | case 3: | |
606 | return s->dev.config[0x57] >> 4; | |
607 | } | |
608 | return 0; | |
609 | } | |
610 | ||
611 | void via_isa_set_irq(PCIDevice *d, int pin, int level) | |
612 | { | |
613 | ViaISAState *s = VIA_ISA(pci_get_function_0(d)); | |
614 | uint8_t irq = d->config[PCI_INTERRUPT_LINE], max_irq = 15; | |
615 | int f = PCI_FUNC(d->devfn); | |
616 | uint16_t mask = BIT(f); | |
617 | ||
618 | switch (f) { | |
619 | case 0: /* PIRQ/PINT inputs */ | |
620 | irq = via_isa_get_pci_irq(s, pin); | |
621 | f = 8 + pin; /* Use function 8-11 for PCI interrupt inputs */ | |
622 | break; | |
623 | case 2: /* USB ports 0-1 */ | |
624 | case 3: /* USB ports 2-3 */ | |
625 | max_irq = 14; | |
626 | break; | |
627 | } | |
628 | ||
629 | /* Keep track of the state of all sources */ | |
630 | if (level) { | |
631 | s->irq_state[0] |= mask; | |
632 | } else { | |
633 | s->irq_state[0] &= ~mask; | |
634 | } | |
635 | if (irq == 0 || irq == 0xff) { | |
636 | return; /* disabled */ | |
637 | } | |
638 | if (unlikely(irq > max_irq || irq == 2)) { | |
639 | qemu_log_mask(LOG_GUEST_ERROR, "Invalid ISA IRQ routing %d for %d", | |
640 | irq, f); | |
641 | return; | |
642 | } | |
643 | /* Record source state at mapped IRQ */ | |
644 | if (level) { | |
645 | s->irq_state[irq] |= mask; | |
646 | } else { | |
647 | s->irq_state[irq] &= ~mask; | |
648 | } | |
649 | /* Make sure there are no stuck bits if mapping has changed */ | |
650 | s->irq_state[irq] &= s->irq_state[0]; | |
651 | /* ISA IRQ level is the OR of all sources routed to it */ | |
652 | qemu_set_irq(s->isa_irqs_in[irq], !!s->irq_state[irq]); | |
653 | } | |
654 | ||
655 | static void via_isa_pirq(void *opaque, int pin, int level) | |
656 | { | |
657 | via_isa_set_irq(opaque, pin, level); | |
658 | } | |
659 | ||
660 | static void via_isa_request_i8259_irq(void *opaque, int irq, int level) | |
661 | { | |
662 | ViaISAState *s = opaque; | |
663 | qemu_set_irq(s->cpu_intr, level); | |
664 | } | |
665 | ||
666 | static void via_isa_realize(PCIDevice *d, Error **errp) | |
667 | { | |
668 | ViaISAState *s = VIA_ISA(d); | |
669 | DeviceState *dev = DEVICE(d); | |
670 | PCIBus *pci_bus = pci_get_bus(d); | |
671 | qemu_irq *isa_irq; | |
672 | ISABus *isa_bus; | |
673 | int i; | |
674 | ||
675 | qdev_init_gpio_out(dev, &s->cpu_intr, 1); | |
676 | qdev_init_gpio_in_named(dev, via_isa_pirq, "pirq", PCI_NUM_PINS); | |
677 | isa_irq = qemu_allocate_irqs(via_isa_request_i8259_irq, s, 1); | |
678 | isa_bus = isa_bus_new(dev, pci_address_space(d), pci_address_space_io(d), | |
679 | errp); | |
680 | ||
681 | if (!isa_bus) { | |
682 | return; | |
683 | } | |
684 | ||
685 | s->isa_irqs_in = i8259_init(isa_bus, *isa_irq); | |
686 | isa_bus_register_input_irqs(isa_bus, s->isa_irqs_in); | |
687 | i8254_pit_init(isa_bus, 0x40, 0, NULL); | |
688 | i8257_dma_init(isa_bus, 0); | |
689 | ||
690 | /* RTC */ | |
691 | qdev_prop_set_int32(DEVICE(&s->rtc), "base_year", 2000); | |
692 | if (!qdev_realize(DEVICE(&s->rtc), BUS(isa_bus), errp)) { | |
693 | return; | |
694 | } | |
695 | isa_connect_gpio_out(ISA_DEVICE(&s->rtc), 0, s->rtc.isairq); | |
696 | ||
697 | for (i = 0; i < PCI_CONFIG_HEADER_SIZE; i++) { | |
698 | if (i < PCI_COMMAND || i >= PCI_REVISION_ID) { | |
699 | d->wmask[i] = 0; | |
700 | } | |
701 | } | |
702 | ||
703 | /* Super I/O */ | |
704 | if (!qdev_realize(DEVICE(&s->via_sio), BUS(isa_bus), errp)) { | |
705 | return; | |
706 | } | |
707 | ||
708 | /* Function 1: IDE */ | |
709 | qdev_prop_set_int32(DEVICE(&s->ide), "addr", d->devfn + 1); | |
710 | if (!qdev_realize(DEVICE(&s->ide), BUS(pci_bus), errp)) { | |
711 | return; | |
712 | } | |
713 | for (i = 0; i < 2; i++) { | |
714 | qdev_connect_gpio_out_named(DEVICE(&s->ide), "isa-irq", i, | |
715 | s->isa_irqs_in[14 + i]); | |
716 | } | |
717 | ||
718 | /* Functions 2-3: USB Ports */ | |
719 | for (i = 0; i < ARRAY_SIZE(s->uhci); i++) { | |
720 | qdev_prop_set_int32(DEVICE(&s->uhci[i]), "addr", d->devfn + 2 + i); | |
721 | if (!qdev_realize(DEVICE(&s->uhci[i]), BUS(pci_bus), errp)) { | |
722 | return; | |
723 | } | |
724 | } | |
725 | ||
726 | /* Function 4: Power Management */ | |
727 | qdev_prop_set_int32(DEVICE(&s->pm), "addr", d->devfn + 4); | |
728 | if (!qdev_realize(DEVICE(&s->pm), BUS(pci_bus), errp)) { | |
729 | return; | |
730 | } | |
731 | ||
732 | /* Function 5: AC97 Audio */ | |
733 | qdev_prop_set_int32(DEVICE(&s->ac97), "addr", d->devfn + 5); | |
734 | if (!qdev_realize(DEVICE(&s->ac97), BUS(pci_bus), errp)) { | |
735 | return; | |
736 | } | |
737 | ||
738 | /* Function 6: MC97 Modem */ | |
739 | qdev_prop_set_int32(DEVICE(&s->mc97), "addr", d->devfn + 6); | |
740 | if (!qdev_realize(DEVICE(&s->mc97), BUS(pci_bus), errp)) { | |
741 | return; | |
742 | } | |
743 | } | |
744 | ||
745 | /* TYPE_VT82C686B_ISA */ | |
746 | ||
747 | static void vt82c686b_write_config(PCIDevice *d, uint32_t addr, | |
748 | uint32_t val, int len) | |
749 | { | |
750 | ViaISAState *s = VIA_ISA(d); | |
751 | ||
752 | trace_via_isa_write(addr, val, len); | |
753 | pci_default_write_config(d, addr, val, len); | |
754 | if (addr == 0x85) { | |
755 | /* BIT(1): enable or disable superio config io ports */ | |
756 | via_superio_io_enable(&s->via_sio, val & BIT(1)); | |
757 | } | |
758 | } | |
759 | ||
760 | static void vt82c686b_isa_reset(DeviceState *dev) | |
761 | { | |
762 | ViaISAState *s = VIA_ISA(dev); | |
763 | uint8_t *pci_conf = s->dev.config; | |
764 | ||
765 | pci_set_long(pci_conf + PCI_CAPABILITY_LIST, 0x000000c0); | |
766 | pci_set_word(pci_conf + PCI_COMMAND, PCI_COMMAND_IO | PCI_COMMAND_MEMORY | | |
767 | PCI_COMMAND_MASTER | PCI_COMMAND_SPECIAL); | |
768 | pci_set_word(pci_conf + PCI_STATUS, PCI_STATUS_DEVSEL_MEDIUM); | |
769 | ||
770 | pci_conf[0x48] = 0x01; /* Miscellaneous Control 3 */ | |
771 | pci_conf[0x4a] = 0x04; /* IDE interrupt Routing */ | |
772 | pci_conf[0x4f] = 0x03; /* DMA/Master Mem Access Control 3 */ | |
773 | pci_conf[0x50] = 0x2d; /* PnP DMA Request Control */ | |
774 | pci_conf[0x59] = 0x04; | |
775 | pci_conf[0x5a] = 0x04; /* KBC/RTC Control*/ | |
776 | pci_conf[0x5f] = 0x04; | |
777 | pci_conf[0x77] = 0x10; /* GPIO Control 1/2/3/4 */ | |
778 | } | |
779 | ||
780 | static void vt82c686b_init(Object *obj) | |
781 | { | |
782 | ViaISAState *s = VIA_ISA(obj); | |
783 | ||
784 | object_initialize_child(obj, "sio", &s->via_sio, TYPE_VT82C686B_SUPERIO); | |
785 | object_initialize_child(obj, "pm", &s->pm, TYPE_VT82C686B_PM); | |
786 | } | |
787 | ||
788 | static void vt82c686b_class_init(ObjectClass *klass, void *data) | |
789 | { | |
790 | DeviceClass *dc = DEVICE_CLASS(klass); | |
791 | PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); | |
792 | ||
793 | k->realize = via_isa_realize; | |
794 | k->config_write = vt82c686b_write_config; | |
795 | k->vendor_id = PCI_VENDOR_ID_VIA; | |
796 | k->device_id = PCI_DEVICE_ID_VIA_82C686B_ISA; | |
797 | k->class_id = PCI_CLASS_BRIDGE_ISA; | |
798 | k->revision = 0x40; | |
799 | dc->reset = vt82c686b_isa_reset; | |
800 | dc->desc = "ISA bridge"; | |
801 | dc->vmsd = &vmstate_via; | |
802 | /* Reason: part of VIA VT82C686 southbridge, needs to be wired up */ | |
803 | dc->user_creatable = false; | |
804 | } | |
805 | ||
806 | static const TypeInfo vt82c686b_isa_info = { | |
807 | .name = TYPE_VT82C686B_ISA, | |
808 | .parent = TYPE_VIA_ISA, | |
809 | .instance_size = sizeof(ViaISAState), | |
810 | .instance_init = vt82c686b_init, | |
811 | .class_init = vt82c686b_class_init, | |
812 | }; | |
813 | ||
814 | /* TYPE_VT8231_ISA */ | |
815 | ||
816 | static void vt8231_write_config(PCIDevice *d, uint32_t addr, | |
817 | uint32_t val, int len) | |
818 | { | |
819 | ViaISAState *s = VIA_ISA(d); | |
820 | ||
821 | trace_via_isa_write(addr, val, len); | |
822 | pci_default_write_config(d, addr, val, len); | |
823 | if (addr == 0x50) { | |
824 | /* BIT(2): enable or disable superio config io ports */ | |
825 | via_superio_io_enable(&s->via_sio, val & BIT(2)); | |
826 | } | |
827 | } | |
828 | ||
829 | static void vt8231_isa_reset(DeviceState *dev) | |
830 | { | |
831 | ViaISAState *s = VIA_ISA(dev); | |
832 | uint8_t *pci_conf = s->dev.config; | |
833 | ||
834 | pci_set_long(pci_conf + PCI_CAPABILITY_LIST, 0x000000c0); | |
835 | pci_set_word(pci_conf + PCI_COMMAND, PCI_COMMAND_IO | PCI_COMMAND_MEMORY | | |
836 | PCI_COMMAND_MASTER | PCI_COMMAND_SPECIAL); | |
837 | pci_set_word(pci_conf + PCI_STATUS, PCI_STATUS_DEVSEL_MEDIUM); | |
838 | ||
839 | pci_conf[0x4c] = 0x04; /* IDE interrupt Routing */ | |
840 | pci_conf[0x58] = 0x40; /* Miscellaneous Control 0 */ | |
841 | pci_conf[0x67] = 0x08; /* Fast IR Config */ | |
842 | pci_conf[0x6b] = 0x01; /* Fast IR I/O Base */ | |
843 | } | |
844 | ||
845 | static void vt8231_init(Object *obj) | |
846 | { | |
847 | ViaISAState *s = VIA_ISA(obj); | |
848 | ||
849 | object_initialize_child(obj, "sio", &s->via_sio, TYPE_VT8231_SUPERIO); | |
850 | object_initialize_child(obj, "pm", &s->pm, TYPE_VT8231_PM); | |
851 | } | |
852 | ||
853 | static void vt8231_class_init(ObjectClass *klass, void *data) | |
854 | { | |
855 | DeviceClass *dc = DEVICE_CLASS(klass); | |
856 | PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); | |
857 | ||
858 | k->realize = via_isa_realize; | |
859 | k->config_write = vt8231_write_config; | |
860 | k->vendor_id = PCI_VENDOR_ID_VIA; | |
861 | k->device_id = PCI_DEVICE_ID_VIA_8231_ISA; | |
862 | k->class_id = PCI_CLASS_BRIDGE_ISA; | |
863 | k->revision = 0x10; | |
864 | dc->reset = vt8231_isa_reset; | |
865 | dc->desc = "ISA bridge"; | |
866 | dc->vmsd = &vmstate_via; | |
867 | /* Reason: part of VIA VT8231 southbridge, needs to be wired up */ | |
868 | dc->user_creatable = false; | |
869 | } | |
870 | ||
871 | static const TypeInfo vt8231_isa_info = { | |
872 | .name = TYPE_VT8231_ISA, | |
873 | .parent = TYPE_VIA_ISA, | |
874 | .instance_size = sizeof(ViaISAState), | |
875 | .instance_init = vt8231_init, | |
876 | .class_init = vt8231_class_init, | |
877 | }; | |
878 | ||
879 | ||
880 | static void vt82c686b_register_types(void) | |
881 | { | |
882 | type_register_static(&via_pm_info); | |
883 | type_register_static(&vt82c686b_pm_info); | |
884 | type_register_static(&vt8231_pm_info); | |
885 | type_register_static(&via_superio_info); | |
886 | type_register_static(&vt82c686b_superio_info); | |
887 | type_register_static(&vt8231_superio_info); | |
888 | type_register_static(&via_isa_info); | |
889 | type_register_static(&vt82c686b_isa_info); | |
890 | type_register_static(&vt8231_isa_info); | |
891 | } | |
892 | ||
893 | type_init(vt82c686b_register_types) |