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1 | /* | |
2 | * MCF547x_8x Internal Memory Map | |
3 | * | |
4 | * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. | |
5 | * TsiChung Liew (Tsi-Chung.Liew@freescale.com) | |
6 | * | |
7 | * See file CREDITS for list of people who contributed to this | |
8 | * project. | |
9 | * | |
10 | * This program is free software; you can redistribute it and/or | |
11 | * modify it under the terms of the GNU General Public License as | |
12 | * published by the Free Software Foundation; either version 2 of | |
13 | * the License, or (at your option) any later version. | |
14 | * | |
15 | * This program is distributed in the hope that it will be useful, | |
16 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
17 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
18 | * GNU General Public License for more details. | |
19 | * | |
20 | * You should have received a copy of the GNU General Public License | |
21 | * along with this program; if not, write to the Free Software | |
22 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
23 | * MA 02111-1307 USA | |
24 | */ | |
25 | ||
26 | #ifndef __IMMAP_547x_8x__ | |
27 | #define __IMMAP_547x_8x__ | |
28 | ||
29 | #define MMAP_SIU (CONFIG_SYS_MBAR + 0x00000000) | |
30 | #define MMAP_SDRAM (CONFIG_SYS_MBAR + 0x00000100) | |
31 | #define MMAP_XARB (CONFIG_SYS_MBAR + 0x00000240) | |
32 | #define MMAP_FBCS (CONFIG_SYS_MBAR + 0x00000500) | |
33 | #define MMAP_INTC0 (CONFIG_SYS_MBAR + 0x00000700) | |
34 | #define MMAP_GPTMR (CONFIG_SYS_MBAR + 0x00000800) | |
35 | #define MMAP_SLT0 (CONFIG_SYS_MBAR + 0x00000900) | |
36 | #define MMAP_SLT1 (CONFIG_SYS_MBAR + 0x00000910) | |
37 | #define MMAP_GPIO (CONFIG_SYS_MBAR + 0x00000A00) | |
38 | #define MMAP_PCI (CONFIG_SYS_MBAR + 0x00000B00) | |
39 | #define MMAP_PCIARB (CONFIG_SYS_MBAR + 0x00000C00) | |
40 | #define MMAP_EXTDMA (CONFIG_SYS_MBAR + 0x00000D00) | |
41 | #define MMAP_EPORT (CONFIG_SYS_MBAR + 0x00000F00) | |
42 | #define MMAP_CTM (CONFIG_SYS_MBAR + 0x00007F00) | |
43 | #define MMAP_MCDMA (CONFIG_SYS_MBAR + 0x00008000) | |
44 | #define MMAP_SCPCI (CONFIG_SYS_MBAR + 0x00008400) | |
45 | #define MMAP_UART0 (CONFIG_SYS_MBAR + 0x00008600) | |
46 | #define MMAP_UART1 (CONFIG_SYS_MBAR + 0x00008700) | |
47 | #define MMAP_UART2 (CONFIG_SYS_MBAR + 0x00008800) | |
48 | #define MMAP_UART3 (CONFIG_SYS_MBAR + 0x00008900) | |
49 | #define MMAP_DSPI (CONFIG_SYS_MBAR + 0x00008A00) | |
50 | #define MMAP_I2C (CONFIG_SYS_MBAR + 0x00008F00) | |
51 | #define MMAP_FEC0 (CONFIG_SYS_MBAR + 0x00009000) | |
52 | #define MMAP_FEC1 (CONFIG_SYS_MBAR + 0x00009800) | |
53 | #define MMAP_CAN0 (CONFIG_SYS_MBAR + 0x0000A000) | |
54 | #define MMAP_CAN1 (CONFIG_SYS_MBAR + 0x0000A800) | |
55 | #define MMAP_USBD (CONFIG_SYS_MBAR + 0x0000B000) | |
56 | #define MMAP_SRAM (CONFIG_SYS_MBAR + 0x00010000) | |
57 | #define MMAP_SRAMCFG (CONFIG_SYS_MBAR + 0x0001FF00) | |
58 | #define MMAP_SEC (CONFIG_SYS_MBAR + 0x00020000) | |
59 | ||
60 | #include <asm/coldfire/flexbus.h> | |
61 | ||
62 | typedef struct siu { | |
63 | u32 mbar; /* 0x00 */ | |
64 | u32 drv; /* 0x04 */ | |
65 | u32 rsvd1[2]; /* 0x08 - 0x1F */ | |
66 | u32 sbcr; /* 0x10 */ | |
67 | u32 rsvd2[3]; /* 0x14 - 0x1F */ | |
68 | u32 cs0cfg; /* 0x20 */ | |
69 | u32 cs1cfg; /* 0x24 */ | |
70 | u32 cs2cfg; /* 0x28 */ | |
71 | u32 cs3cfg; /* 0x2C */ | |
72 | u32 rsvd3[2]; /* 0x30 - 0x37 */ | |
73 | u32 secsacr; /* 0x38 */ | |
74 | u32 rsvd4[2]; /* 0x3C - 0x43 */ | |
75 | u32 rsr; /* 0x44 */ | |
76 | u32 rsvd5[2]; /* 0x48 - 0x4F */ | |
77 | u32 jtagid; /* 0x50 */ | |
78 | } siu_t; | |
79 | ||
80 | typedef struct sdram { | |
81 | u32 mode; /* 0x00 */ | |
82 | u32 ctrl; /* 0x04 */ | |
83 | u32 cfg1; /* 0x08 */ | |
84 | u32 cfg2; /* 0x0c */ | |
85 | } sdram_t; | |
86 | ||
87 | typedef struct xlb_arb { | |
88 | u32 cfg; /* 0x240 */ | |
89 | u32 ver; /* 0x244 */ | |
90 | u32 sr; /* 0x248 */ | |
91 | u32 imr; /* 0x24c */ | |
92 | u32 adrcap; /* 0x250 */ | |
93 | u32 sigcap; /* 0x254 */ | |
94 | u32 adrto; /* 0x258 */ | |
95 | u32 datto; /* 0x25c */ | |
96 | u32 busto; /* 0x260 */ | |
97 | u32 prien; /* 0x264 */ | |
98 | u32 pri; /* 0x268 */ | |
99 | } xlbarb_t; | |
100 | ||
101 | typedef struct int0_ctrl { | |
102 | u32 iprh0; /* 0x00 */ | |
103 | u32 iprl0; /* 0x04 */ | |
104 | u32 imrh0; /* 0x08 */ | |
105 | u32 imrl0; /* 0x0C */ | |
106 | u32 frch0; /* 0x10 */ | |
107 | u32 frcl0; /* 0x14 */ | |
108 | u8 irlr; /* 0x18 */ | |
109 | u8 iacklpr; /* 0x19 */ | |
110 | u16 res1; /* 0x1A - 0x1B */ | |
111 | u32 res2[9]; /* 0x1C - 0x3F */ | |
112 | u8 icr0[64]; /* 0x40 - 0x7F */ | |
113 | u32 res3[24]; /* 0x80 - 0xDF */ | |
114 | u8 swiack0; /* 0xE0 */ | |
115 | u8 res4[3]; /* 0xE1 - 0xE3 */ | |
116 | u8 Lniack0_1; /* 0xE4 */ | |
117 | u8 res5[3]; /* 0xE5 - 0xE7 */ | |
118 | u8 Lniack0_2; /* 0xE8 */ | |
119 | u8 res6[3]; /* 0xE9 - 0xEB */ | |
120 | u8 Lniack0_3; /* 0xEC */ | |
121 | u8 res7[3]; /* 0xED - 0xEF */ | |
122 | u8 Lniack0_4; /* 0xF0 */ | |
123 | u8 res8[3]; /* 0xF1 - 0xF3 */ | |
124 | u8 Lniack0_5; /* 0xF4 */ | |
125 | u8 res9[3]; /* 0xF5 - 0xF7 */ | |
126 | u8 Lniack0_6; /* 0xF8 */ | |
127 | u8 resa[3]; /* 0xF9 - 0xFB */ | |
128 | u8 Lniack0_7; /* 0xFC */ | |
129 | u8 resb[3]; /* 0xFD - 0xFF */ | |
130 | } int0_t; | |
131 | ||
132 | typedef struct gptmr { | |
133 | u8 ocpw; | |
134 | u8 octict; | |
135 | u8 ctrl; | |
136 | u8 mode; | |
137 | ||
138 | u16 pre; /* Prescale */ | |
139 | u16 cnt; | |
140 | ||
141 | u16 pwmwidth; | |
142 | u8 pwmop; /* Output Polarity */ | |
143 | u8 pwmld; /* Immediate Update */ | |
144 | ||
145 | u16 cap; /* Capture internal counter */ | |
146 | u8 ovfpin; /* Ovf and Pin */ | |
147 | u8 intr; /* Interrupts */ | |
148 | } gptmr_t; | |
149 | ||
150 | typedef struct slt { | |
151 | u32 tcnt; /* 0x00 */ | |
152 | u32 cr; /* 0x04 */ | |
153 | u32 cnt; /* 0x08 */ | |
154 | u32 sr; /* 0x0C */ | |
155 | } slt_t; | |
156 | ||
157 | typedef struct gpio { | |
158 | /* Port Output Data Registers */ | |
159 | u8 podr_fbctl; /*0x00 */ | |
160 | u8 podr_fbcs; /*0x01 */ | |
161 | u8 podr_dma; /*0x02 */ | |
162 | u8 rsvd1; /*0x03 */ | |
163 | u8 podr_fec0h; /*0x04 */ | |
164 | u8 podr_fec0l; /*0x05 */ | |
165 | u8 podr_fec1h; /*0x06 */ | |
166 | u8 podr_fec1l; /*0x07 */ | |
167 | u8 podr_feci2c; /*0x08 */ | |
168 | u8 podr_pcibg; /*0x09 */ | |
169 | u8 podr_pcibr; /*0x0A */ | |
170 | u8 rsvd2; /*0x0B */ | |
171 | u8 podr_psc3psc2; /*0x0C */ | |
172 | u8 podr_psc1psc0; /*0x0D */ | |
173 | u8 podr_dspi; /*0x0E */ | |
174 | u8 rsvd3; /*0x0F */ | |
175 | ||
176 | /* Port Data Direction Registers */ | |
177 | u8 pddr_fbctl; /*0x10 */ | |
178 | u8 pddr_fbcs; /*0x11 */ | |
179 | u8 pddr_dma; /*0x12 */ | |
180 | u8 rsvd4; /*0x13 */ | |
181 | u8 pddr_fec0h; /*0x14 */ | |
182 | u8 pddr_fec0l; /*0x15 */ | |
183 | u8 pddr_fec1h; /*0x16 */ | |
184 | u8 pddr_fec1l; /*0x17 */ | |
185 | u8 pddr_feci2c; /*0x18 */ | |
186 | u8 pddr_pcibg; /*0x19 */ | |
187 | u8 pddr_pcibr; /*0x1A */ | |
188 | u8 rsvd5; /*0x1B */ | |
189 | u8 pddr_psc3psc2; /*0x1C */ | |
190 | u8 pddr_psc1psc0; /*0x1D */ | |
191 | u8 pddr_dspi; /*0x1E */ | |
192 | u8 rsvd6; /*0x1F */ | |
193 | ||
194 | /* Port Pin Data/Set Data Registers */ | |
195 | u8 ppdsdr_fbctl; /*0x20 */ | |
196 | u8 ppdsdr_fbcs; /*0x21 */ | |
197 | u8 ppdsdr_dma; /*0x22 */ | |
198 | u8 rsvd7; /*0x23 */ | |
199 | u8 ppdsdr_fec0h; /*0x24 */ | |
200 | u8 ppdsdr_fec0l; /*0x25 */ | |
201 | u8 ppdsdr_fec1h; /*0x26 */ | |
202 | u8 ppdsdr_fec1l; /*0x27 */ | |
203 | u8 ppdsdr_feci2c; /*0x28 */ | |
204 | u8 ppdsdr_pcibg; /*0x29 */ | |
205 | u8 ppdsdr_pcibr; /*0x2A */ | |
206 | u8 rsvd8; /*0x2B */ | |
207 | u8 ppdsdr_psc3psc2; /*0x2C */ | |
208 | u8 ppdsdr_psc1psc0; /*0x2D */ | |
209 | u8 ppdsdr_dspi; /*0x2E */ | |
210 | u8 rsvd9; /*0x2F */ | |
211 | ||
212 | /* Port Clear Output Data Registers */ | |
213 | u8 pclrr_fbctl; /*0x30 */ | |
214 | u8 pclrr_fbcs; /*0x31 */ | |
215 | u8 pclrr_dma; /*0x32 */ | |
216 | u8 rsvd10; /*0x33 */ | |
217 | u8 pclrr_fec0h; /*0x34 */ | |
218 | u8 pclrr_fec0l; /*0x35 */ | |
219 | u8 pclrr_fec1h; /*0x36 */ | |
220 | u8 pclrr_fec1l; /*0x37 */ | |
221 | u8 pclrr_feci2c; /*0x38 */ | |
222 | u8 pclrr_pcibg; /*0x39 */ | |
223 | u8 pclrr_pcibr; /*0x3A */ | |
224 | u8 rsvd11; /*0x3B */ | |
225 | u8 pclrr_psc3psc2; /*0x3C */ | |
226 | u8 pclrr_psc1psc0; /*0x3D */ | |
227 | u8 pclrr_dspi; /*0x3E */ | |
228 | u8 rsvd12; /*0x3F */ | |
229 | ||
230 | /* Pin Assignment Registers */ | |
231 | u16 par_fbctl; /*0x40 */ | |
232 | u8 par_fbcs; /*0x42 */ | |
233 | u8 par_dma; /*0x43 */ | |
234 | u16 par_feci2cirq; /*0x44 */ | |
235 | u16 rsvd13; /*0x46 */ | |
236 | u16 par_pcibg; /*0x48 */ | |
237 | u16 par_pcibr; /*0x4A */ | |
238 | u8 par_psc3; /*0x4C */ | |
239 | u8 par_psc2; /*0x4D */ | |
240 | u8 par_psc1; /*0x4E */ | |
241 | u8 par_psc0; /*0x4F */ | |
242 | u16 par_dspi; /*0x50 */ | |
243 | u8 par_timer; /*0x52 */ | |
244 | u8 rsvd14; /*0x53 */ | |
245 | } gpio_t; | |
246 | ||
247 | typedef struct pci { | |
248 | u32 idr; /* 0x00 Device Id / Vendor Id */ | |
249 | u32 scr; /* 0x04 Status / command */ | |
250 | u32 ccrir; /* 0x08 Class Code / Revision Id */ | |
251 | u32 cr1; /* 0x0c Configuration 1 */ | |
252 | u32 bar0; /* 0x10 Base address register 0 */ | |
253 | u32 bar1; /* 0x14 Base address register 1 */ | |
254 | u32 bar2; /* 0x18 NA */ | |
255 | u32 bar3; /* 0x1c NA */ | |
256 | u32 bar4; /* 0x20 NA */ | |
257 | u32 bar5; /* 0x24 NA */ | |
258 | u32 ccpr; /* 0x28 Cardbus CIS Pointer */ | |
259 | u32 sid; /* 0x2c Subsystem ID / Subsystem Vendor ID */ | |
260 | u32 erbar; /* 0x30 Expansion ROM Base Address */ | |
261 | u32 cpr; /* 0x34 Capabilities Pointer */ | |
262 | u32 rsvd1; /* 0x38 */ | |
263 | u32 cr2; /* 0x3c Configuration 2 */ | |
264 | u32 rsvd2[8]; /* 0x40 - 0x5f */ | |
265 | ||
266 | /* General control / status registers */ | |
267 | u32 gscr; /* 0x60 Global Status / Control */ | |
268 | u32 tbatr0a; /* 0x64 Target Base Adr Translation 0 */ | |
269 | u32 tbatr1a; /* 0x68 Target Base Adr Translation 1 */ | |
270 | u32 tcr1; /* 0x6c Target Control 1 Register */ | |
271 | u32 iw0btar; /* 0x70 Initiator Win 0 Base/Translation adr */ | |
272 | u32 iw1btar; /* 0x74 Initiator Win 1 Base/Translation adr */ | |
273 | u32 iw2btar; /* 0x78 NA */ | |
274 | u32 rsvd3; /* 0x7c */ | |
275 | u32 iwcr; /* 0x80 Initiator Window Configuration */ | |
276 | u32 icr; /* 0x84 Initiator Control */ | |
277 | u32 isr; /* 0x88 Initiator Status */ | |
278 | u32 tcr2; /* 0x8c NA */ | |
279 | u32 tbatr0; /* 0x90 NA */ | |
280 | u32 tbatr1; /* 0x94 NA */ | |
281 | u32 tbatr2; /* 0x98 NA */ | |
282 | u32 tbatr3; /* 0x9c NA */ | |
283 | u32 tbatr4; /* 0xa0 NA */ | |
284 | u32 tbatr5; /* 0xa4 NA */ | |
285 | u32 intr; /* 0xa8 NA */ | |
286 | u32 rsvd4[19]; /* 0xac - 0xf7 */ | |
287 | u32 car; /* 0xf8 Configuration Address */ | |
288 | } pci_t; | |
289 | ||
290 | typedef struct pci_arbiter { | |
291 | /* Pci Arbiter Registers */ | |
292 | union { | |
293 | u32 acr; /* Arbiter Control */ | |
294 | u32 asr; /* Arbiter Status */ | |
295 | }; | |
296 | } pciarb_t; | |
297 | #endif /* __IMMAP_547x_8x__ */ |