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1 | /* | |
2 | * Copyright 2007, 2010-2011 Freescale Semiconductor, Inc. | |
3 | * | |
4 | * SPDX-License-Identifier: GPL-2.0+ | |
5 | */ | |
6 | ||
7 | /* | |
8 | * mpc8544ds board configuration file | |
9 | * | |
10 | */ | |
11 | #ifndef __CONFIG_H | |
12 | #define __CONFIG_H | |
13 | ||
14 | #ifndef CONFIG_SYS_TEXT_BASE | |
15 | #define CONFIG_SYS_TEXT_BASE 0xfff80000 | |
16 | #endif | |
17 | ||
18 | #define CONFIG_PCI1 1 /* PCI controller 1 */ | |
19 | #define CONFIG_PCIE1 1 /* PCIE controller 1 (slot 1) */ | |
20 | #define CONFIG_PCIE2 1 /* PCIE controller 2 (slot 2) */ | |
21 | #define CONFIG_PCIE3 1 /* PCIE controller 3 (ULI bridge) */ | |
22 | #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ | |
23 | #define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */ | |
24 | #define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */ | |
25 | #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ | |
26 | ||
27 | #define CONFIG_TSEC_ENET /* tsec ethernet support */ | |
28 | #define CONFIG_ENV_OVERWRITE | |
29 | #define CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */ | |
30 | ||
31 | #ifndef __ASSEMBLY__ | |
32 | extern unsigned long get_board_sys_clk(unsigned long dummy); | |
33 | #endif | |
34 | #define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) /* sysclk for MPC85xx */ | |
35 | ||
36 | /* | |
37 | * These can be toggled for performance analysis, otherwise use default. | |
38 | */ | |
39 | #define CONFIG_L2_CACHE /* toggle L2 cache */ | |
40 | #define CONFIG_BTB /* toggle branch predition */ | |
41 | ||
42 | /* | |
43 | * Only possible on E500 Version 2 or newer cores. | |
44 | */ | |
45 | #define CONFIG_ENABLE_36BIT_PHYS 1 | |
46 | ||
47 | #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ | |
48 | #define CONFIG_SYS_MEMTEST_END 0x00400000 | |
49 | #define CONFIG_PANIC_HANG /* do not reset board on panic */ | |
50 | ||
51 | #define CONFIG_SYS_CCSRBAR 0xe0000000 | |
52 | #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR | |
53 | ||
54 | /* DDR Setup */ | |
55 | #undef CONFIG_FSL_DDR_INTERACTIVE | |
56 | #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ | |
57 | #define CONFIG_DDR_SPD | |
58 | ||
59 | #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ | |
60 | #define CONFIG_MEM_INIT_VALUE 0xDeadBeef | |
61 | ||
62 | #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 | |
63 | #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE | |
64 | #define CONFIG_VERY_BIG_RAM | |
65 | ||
66 | #define CONFIG_DIMM_SLOTS_PER_CTLR 1 | |
67 | #define CONFIG_CHIP_SELECTS_PER_CTRL 2 | |
68 | ||
69 | /* I2C addresses of SPD EEPROMs */ | |
70 | #define SPD_EEPROM_ADDRESS 0x51 /* DDR DIMM */ | |
71 | ||
72 | /* Make sure required options are set */ | |
73 | #ifndef CONFIG_SPD_EEPROM | |
74 | #error ("CONFIG_SPD_EEPROM is required") | |
75 | #endif | |
76 | ||
77 | #undef CONFIG_CLOCKS_IN_MHZ | |
78 | ||
79 | /* | |
80 | * Memory map | |
81 | * | |
82 | * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable | |
83 | * | |
84 | * 0x8000_0000 0xbfff_ffff PCI Express Mem 1G non-cacheable | |
85 | * | |
86 | * 0xc000_0000 0xdfff_ffff PCI 512M non-cacheable | |
87 | * | |
88 | * 0xe000_0000 0xe00f_ffff CCSR 1M non-cacheable | |
89 | * 0xe100_0000 0xe3ff_ffff PCI IO range 4M non-cacheable | |
90 | * | |
91 | * Localbus cacheable | |
92 | * | |
93 | * 0xf000_0000 0xf3ff_ffff SDRAM 64M Cacheable | |
94 | * 0xf401_0000 0xf401_3fff L1 for stack 4K Cacheable TLB0 | |
95 | * | |
96 | * Localbus non-cacheable | |
97 | * | |
98 | * 0xf800_0000 0xf80f_ffff NVRAM/CADMUS (*) 1M non-cacheable | |
99 | * 0xff00_0000 0xff7f_ffff FLASH (2nd bank) 8M non-cacheable | |
100 | * 0xff80_0000 0xffff_ffff FLASH (boot bank) 8M non-cacheable | |
101 | * | |
102 | */ | |
103 | ||
104 | /* | |
105 | * Local Bus Definitions | |
106 | */ | |
107 | #define CONFIG_SYS_BOOT_BLOCK 0xfc000000 /* boot TLB */ | |
108 | ||
109 | #define CONFIG_SYS_FLASH_BASE 0xff800000 /* start of FLASH 8M */ | |
110 | ||
111 | #define CONFIG_SYS_BR0_PRELIM 0xff801001 | |
112 | #define CONFIG_SYS_BR1_PRELIM 0xfe801001 | |
113 | ||
114 | #define CONFIG_SYS_OR0_PRELIM 0xff806e65 | |
115 | #define CONFIG_SYS_OR1_PRELIM 0xff806e65 | |
116 | ||
117 | #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE} | |
118 | ||
119 | #define CONFIG_SYS_FLASH_QUIET_TEST | |
120 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ | |
121 | #define CONFIG_SYS_MAX_FLASH_SECT 128 /* sectors per device */ | |
122 | #undef CONFIG_SYS_FLASH_CHECKSUM | |
123 | #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ | |
124 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ | |
125 | #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ | |
126 | ||
127 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ | |
128 | ||
129 | #define CONFIG_FLASH_CFI_DRIVER | |
130 | #define CONFIG_SYS_FLASH_CFI | |
131 | #define CONFIG_SYS_FLASH_EMPTY_INFO | |
132 | ||
133 | #define CONFIG_SYS_LBC_NONCACHE_BASE 0xf8000000 | |
134 | ||
135 | #define CONFIG_SYS_BR2_PRELIM 0xf8201001 /* port size 16bit */ | |
136 | #define CONFIG_SYS_OR2_PRELIM 0xfff06ff7 /* 1MB Compact Flash area*/ | |
137 | ||
138 | #define CONFIG_SYS_BR3_PRELIM 0xf8100801 /* port size 8bit */ | |
139 | #define CONFIG_SYS_OR3_PRELIM 0xfff06ff7 /* 1MB PIXIS area*/ | |
140 | ||
141 | #define CONFIG_FSL_PIXIS 1 /* use common PIXIS code */ | |
142 | #define PIXIS_BASE 0xf8100000 /* PIXIS registers */ | |
143 | #define PIXIS_ID 0x0 /* Board ID at offset 0 */ | |
144 | #define PIXIS_VER 0x1 /* Board version at offset 1 */ | |
145 | #define PIXIS_PVER 0x2 /* PIXIS FPGA version at offset 2 */ | |
146 | #define PIXIS_RST 0x4 /* PIXIS Reset Control register */ | |
147 | #define PIXIS_AUX 0x6 /* PIXIS Auxiliary register; Scratch | |
148 | * register */ | |
149 | #define PIXIS_SPD 0x7 /* Register for SYSCLK speed */ | |
150 | #define PIXIS_VCTL 0x10 /* VELA Control Register */ | |
151 | #define PIXIS_VCFGEN0 0x12 /* VELA Config Enable 0 */ | |
152 | #define PIXIS_VCFGEN1 0x13 /* VELA Config Enable 1 */ | |
153 | #define PIXIS_VBOOT 0x16 /* VELA VBOOT Register */ | |
154 | #define PIXIS_VBOOT_FMAP 0x80 /* VBOOT - CFG_FLASHMAP */ | |
155 | #define PIXIS_VBOOT_FBANK 0x40 /* VBOOT - CFG_FLASHBANK */ | |
156 | #define PIXIS_VSPEED0 0x17 /* VELA VSpeed 0 */ | |
157 | #define PIXIS_VSPEED1 0x18 /* VELA VSpeed 1 */ | |
158 | #define PIXIS_VCLKH 0x19 /* VELA VCLKH register */ | |
159 | #define PIXIS_VCLKL 0x1A /* VELA VCLKL register */ | |
160 | #define PIXIS_VSPEED2 0x1d /* VELA VSpeed 2 */ | |
161 | #define CONFIG_SYS_PIXIS_VBOOT_MASK 0x40 /* Reset altbank mask*/ | |
162 | #define PIXIS_VSPEED2_TSEC1SER 0x2 | |
163 | #define PIXIS_VSPEED2_TSEC3SER 0x1 | |
164 | #define PIXIS_VCFGEN1_TSEC1SER 0x20 | |
165 | #define PIXIS_VCFGEN1_TSEC3SER 0x40 | |
166 | #define PIXIS_VSPEED2_MASK (PIXIS_VSPEED2_TSEC1SER|PIXIS_VSPEED2_TSEC3SER) | |
167 | #define PIXIS_VCFGEN1_MASK (PIXIS_VCFGEN1_TSEC1SER|PIXIS_VCFGEN1_TSEC3SER) | |
168 | ||
169 | #define CONFIG_SYS_INIT_RAM_LOCK 1 | |
170 | #define CONFIG_SYS_INIT_RAM_ADDR 0xf4010000 /* Initial L1 address */ | |
171 | #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* Size of used area in RAM */ | |
172 | ||
173 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) | |
174 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET | |
175 | ||
176 | #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ | |
177 | #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */ | |
178 | ||
179 | /* Serial Port - controlled on board with jumper J8 | |
180 | * open - index 2 | |
181 | * shorted - index 1 | |
182 | */ | |
183 | #define CONFIG_CONS_INDEX 1 | |
184 | #define CONFIG_SYS_NS16550_SERIAL | |
185 | #define CONFIG_SYS_NS16550_REG_SIZE 1 | |
186 | #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) | |
187 | ||
188 | #define CONFIG_SYS_BAUDRATE_TABLE \ | |
189 | {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} | |
190 | ||
191 | #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) | |
192 | #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) | |
193 | ||
194 | /* I2C */ | |
195 | #define CONFIG_SYS_I2C | |
196 | #define CONFIG_SYS_I2C_FSL | |
197 | #define CONFIG_SYS_FSL_I2C_SPEED 400000 | |
198 | #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F | |
199 | #define CONFIG_SYS_FSL_I2C_OFFSET 0x3100 | |
200 | #define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} } | |
201 | #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 | |
202 | ||
203 | /* | |
204 | * General PCI | |
205 | * Memory space is mapped 1-1, but I/O space must start from 0. | |
206 | */ | |
207 | #define CONFIG_SYS_PCIE_VIRT 0x80000000 /* 1G PCIE TLB */ | |
208 | #define CONFIG_SYS_PCIE_PHYS 0x80000000 /* 1G PCIE TLB */ | |
209 | #define CONFIG_SYS_PCI_VIRT 0xc0000000 /* 512M PCI TLB */ | |
210 | #define CONFIG_SYS_PCI_PHYS 0xc0000000 /* 512M PCI TLB */ | |
211 | ||
212 | #define CONFIG_SYS_PCI1_MEM_VIRT 0xc0000000 | |
213 | #define CONFIG_SYS_PCI1_MEM_BUS 0xc0000000 | |
214 | #define CONFIG_SYS_PCI1_MEM_PHYS 0xc0000000 | |
215 | #define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */ | |
216 | #define CONFIG_SYS_PCI1_IO_VIRT 0xe1000000 | |
217 | #define CONFIG_SYS_PCI1_IO_BUS 0x00000000 | |
218 | #define CONFIG_SYS_PCI1_IO_PHYS 0xe1000000 | |
219 | #define CONFIG_SYS_PCI1_IO_SIZE 0x00010000 /* 64k */ | |
220 | ||
221 | /* controller 2, Slot 1, tgtid 1, Base address 9000 */ | |
222 | #define CONFIG_SYS_PCIE2_NAME "Slot 1" | |
223 | #define CONFIG_SYS_PCIE2_MEM_VIRT 0x80000000 | |
224 | #define CONFIG_SYS_PCIE2_MEM_BUS 0x80000000 | |
225 | #define CONFIG_SYS_PCIE2_MEM_PHYS 0x80000000 | |
226 | #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ | |
227 | #define CONFIG_SYS_PCIE2_IO_VIRT 0xe1010000 | |
228 | #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 | |
229 | #define CONFIG_SYS_PCIE2_IO_PHYS 0xe1010000 | |
230 | #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ | |
231 | ||
232 | /* controller 1, Slot 2,tgtid 2, Base address a000 */ | |
233 | #define CONFIG_SYS_PCIE1_NAME "Slot 2" | |
234 | #define CONFIG_SYS_PCIE1_MEM_VIRT 0xa0000000 | |
235 | #define CONFIG_SYS_PCIE1_MEM_BUS 0xa0000000 | |
236 | #define CONFIG_SYS_PCIE1_MEM_PHYS 0xa0000000 | |
237 | #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */ | |
238 | #define CONFIG_SYS_PCIE1_IO_VIRT 0xe1020000 | |
239 | #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 | |
240 | #define CONFIG_SYS_PCIE1_IO_PHYS 0xe1020000 | |
241 | #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ | |
242 | ||
243 | /* controller 3, direct to uli, tgtid 3, Base address b000 */ | |
244 | #define CONFIG_SYS_PCIE3_NAME "ULI" | |
245 | #define CONFIG_SYS_PCIE3_MEM_VIRT 0xb0000000 | |
246 | #define CONFIG_SYS_PCIE3_MEM_BUS 0xb0000000 | |
247 | #define CONFIG_SYS_PCIE3_MEM_PHYS 0xb0000000 | |
248 | #define CONFIG_SYS_PCIE3_MEM_SIZE 0x00100000 /* 1M */ | |
249 | #define CONFIG_SYS_PCIE3_IO_VIRT 0xb0100000 /* reuse mem LAW */ | |
250 | #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 | |
251 | #define CONFIG_SYS_PCIE3_IO_PHYS 0xb0100000 /* reuse mem LAW */ | |
252 | #define CONFIG_SYS_PCIE3_IO_SIZE 0x00100000 /* 1M */ | |
253 | #define CONFIG_SYS_PCIE3_MEM_VIRT2 0xb0200000 | |
254 | #define CONFIG_SYS_PCIE3_MEM_BUS2 0xb0200000 | |
255 | #define CONFIG_SYS_PCIE3_MEM_PHYS2 0xb0200000 | |
256 | #define CONFIG_SYS_PCIE3_MEM_SIZE2 0x00200000 /* 1M */ | |
257 | ||
258 | #if defined(CONFIG_PCI) | |
259 | ||
260 | /*PCIE video card used*/ | |
261 | #define VIDEO_IO_OFFSET CONFIG_SYS_PCIE2_IO_VIRT | |
262 | ||
263 | /*PCI video card used*/ | |
264 | /*#define VIDEO_IO_OFFSET CONFIG_SYS_PCI1_IO_VIRT*/ | |
265 | ||
266 | /* video */ | |
267 | ||
268 | #if defined(CONFIG_VIDEO) | |
269 | #define CONFIG_BIOSEMU | |
270 | #define CONFIG_ATI_RADEON_FB | |
271 | #define CONFIG_VIDEO_LOGO | |
272 | #define CONFIG_SYS_ISA_IO_BASE_ADDRESS VIDEO_IO_OFFSET | |
273 | #endif | |
274 | ||
275 | #undef CONFIG_EEPRO100 | |
276 | #undef CONFIG_TULIP | |
277 | ||
278 | #ifndef CONFIG_PCI_PNP | |
279 | #define PCI_ENET0_IOADDR CONFIG_SYS_PCI1_IO_BUS | |
280 | #define PCI_ENET0_MEMADDR CONFIG_SYS_PCI1_IO_BUS | |
281 | #define PCI_IDSEL_NUMBER 0x11 /* IDSEL = AD11 */ | |
282 | #endif | |
283 | ||
284 | #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ | |
285 | ||
286 | #ifdef CONFIG_SCSI_AHCI | |
287 | #define CONFIG_LIBATA | |
288 | #define CONFIG_SATA_ULI5288 | |
289 | #define CONFIG_SYS_SCSI_MAX_SCSI_ID 4 | |
290 | #define CONFIG_SYS_SCSI_MAX_LUN 1 | |
291 | #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * CONFIG_SYS_SCSI_MAX_LUN) | |
292 | #define CONFIG_SYS_SCSI_MAXDEVICE CONFIG_SYS_SCSI_MAX_DEVICE | |
293 | #endif /* SCSCI */ | |
294 | ||
295 | #endif /* CONFIG_PCI */ | |
296 | ||
297 | #if defined(CONFIG_TSEC_ENET) | |
298 | ||
299 | #define CONFIG_MII 1 /* MII PHY management */ | |
300 | #define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */ | |
301 | #define CONFIG_TSEC1 1 | |
302 | #define CONFIG_TSEC1_NAME "eTSEC1" | |
303 | #define CONFIG_TSEC3 1 | |
304 | #define CONFIG_TSEC3_NAME "eTSEC3" | |
305 | ||
306 | #define CONFIG_PIXIS_SGMII_CMD | |
307 | #define CONFIG_FSL_SGMII_RISER 1 | |
308 | #define SGMII_RISER_PHY_OFFSET 0x1c | |
309 | ||
310 | #define TSEC1_PHY_ADDR 0 | |
311 | #define TSEC3_PHY_ADDR 1 | |
312 | ||
313 | #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) | |
314 | #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) | |
315 | ||
316 | #define TSEC1_PHYIDX 0 | |
317 | #define TSEC3_PHYIDX 0 | |
318 | ||
319 | #define CONFIG_ETHPRIME "eTSEC1" | |
320 | #endif /* CONFIG_TSEC_ENET */ | |
321 | ||
322 | /* | |
323 | * Environment | |
324 | */ | |
325 | #define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K (one sector) */ | |
326 | #if CONFIG_SYS_MONITOR_BASE > 0xfff80000 | |
327 | #define CONFIG_ENV_ADDR 0xfff80000 | |
328 | #else | |
329 | #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) | |
330 | #endif | |
331 | #define CONFIG_ENV_SIZE 0x2000 | |
332 | ||
333 | #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ | |
334 | #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ | |
335 | ||
336 | /* | |
337 | * BOOTP options | |
338 | */ | |
339 | #define CONFIG_BOOTP_BOOTFILESIZE | |
340 | #define CONFIG_BOOTP_BOOTPATH | |
341 | #define CONFIG_BOOTP_GATEWAY | |
342 | #define CONFIG_BOOTP_HOSTNAME | |
343 | ||
344 | /* | |
345 | * USB | |
346 | */ | |
347 | ||
348 | #ifdef CONFIG_USB_EHCI_HCD | |
349 | #define CONFIG_EHCI_HCD_INIT_AFTER_RESET | |
350 | #define CONFIG_PCI_EHCI_DEVICE 0 | |
351 | #endif | |
352 | ||
353 | #undef CONFIG_WATCHDOG /* watchdog disabled */ | |
354 | ||
355 | /* | |
356 | * Miscellaneous configurable options | |
357 | */ | |
358 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ | |
359 | #define CONFIG_CMDLINE_EDITING /* Command-line editing */ | |
360 | #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ | |
361 | #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ | |
362 | ||
363 | /* | |
364 | * For booting Linux, the board info and command line data | |
365 | * have to be in the first 64 MB of memory, since this is | |
366 | * the maximum mapped by the Linux kernel during initialization. | |
367 | */ | |
368 | #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/ | |
369 | #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ | |
370 | ||
371 | #if defined(CONFIG_CMD_KGDB) | |
372 | #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ | |
373 | #endif | |
374 | ||
375 | /* | |
376 | * Environment Configuration | |
377 | */ | |
378 | ||
379 | /* The mac addresses for all ethernet interface */ | |
380 | #if defined(CONFIG_TSEC_ENET) | |
381 | #define CONFIG_HAS_ETH0 | |
382 | #define CONFIG_HAS_ETH1 | |
383 | #endif | |
384 | ||
385 | #define CONFIG_IPADDR 192.168.1.251 | |
386 | ||
387 | #define CONFIG_HOSTNAME 8544ds_unknown | |
388 | #define CONFIG_ROOTPATH "/nfs/mpc85xx" | |
389 | #define CONFIG_BOOTFILE "8544ds/uImage.uboot" | |
390 | #define CONFIG_UBOOTPATH 8544ds/u-boot.bin /* TFTP server */ | |
391 | ||
392 | #define CONFIG_SERVERIP 192.168.1.1 | |
393 | #define CONFIG_GATEWAYIP 192.168.1.1 | |
394 | #define CONFIG_NETMASK 255.255.0.0 | |
395 | ||
396 | #define CONFIG_LOADADDR 1000000 /*default location for tftp and bootm*/ | |
397 | ||
398 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
399 | "netdev=eth0\0" \ | |
400 | "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ | |
401 | "tftpflash=tftpboot $loadaddr $uboot; " \ | |
402 | "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \ | |
403 | " +$filesize; " \ | |
404 | "erase " __stringify(CONFIG_SYS_TEXT_BASE) \ | |
405 | " +$filesize; " \ | |
406 | "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \ | |
407 | " $filesize; " \ | |
408 | "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \ | |
409 | " +$filesize; " \ | |
410 | "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \ | |
411 | " $filesize\0" \ | |
412 | "consoledev=ttyS0\0" \ | |
413 | "ramdiskaddr=2000000\0" \ | |
414 | "ramdiskfile=8544ds/ramdisk.uboot\0" \ | |
415 | "fdtaddr=1e00000\0" \ | |
416 | "fdtfile=8544ds/mpc8544ds.dtb\0" \ | |
417 | "bdev=sda3\0" | |
418 | ||
419 | #define CONFIG_NFSBOOTCOMMAND \ | |
420 | "setenv bootargs root=/dev/nfs rw " \ | |
421 | "nfsroot=$serverip:$rootpath " \ | |
422 | "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ | |
423 | "console=$consoledev,$baudrate $othbootargs;" \ | |
424 | "tftp $loadaddr $bootfile;" \ | |
425 | "tftp $fdtaddr $fdtfile;" \ | |
426 | "bootm $loadaddr - $fdtaddr" | |
427 | ||
428 | #define CONFIG_RAMBOOTCOMMAND \ | |
429 | "setenv bootargs root=/dev/ram rw " \ | |
430 | "console=$consoledev,$baudrate $othbootargs;" \ | |
431 | "tftp $ramdiskaddr $ramdiskfile;" \ | |
432 | "tftp $loadaddr $bootfile;" \ | |
433 | "tftp $fdtaddr $fdtfile;" \ | |
434 | "bootm $loadaddr $ramdiskaddr $fdtaddr" | |
435 | ||
436 | #define CONFIG_BOOTCOMMAND \ | |
437 | "setenv bootargs root=/dev/$bdev rw " \ | |
438 | "console=$consoledev,$baudrate $othbootargs;" \ | |
439 | "tftp $loadaddr $bootfile;" \ | |
440 | "tftp $fdtaddr $fdtfile;" \ | |
441 | "bootm $loadaddr - $fdtaddr" | |
442 | ||
443 | #endif /* __CONFIG_H */ |