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1 | /* | |
2 | * Configuation settings for the Renesas Solutions r0p7734 board | |
3 | * | |
4 | * Copyright (C) 2010, 2011 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> | |
5 | * | |
6 | * SPDX-License-Identifier: GPL-2.0+ | |
7 | */ | |
8 | ||
9 | #ifndef __R0P7734_H | |
10 | #define __R0P7734_H | |
11 | ||
12 | #define CONFIG_CPU_SH7734 1 | |
13 | #define CONFIG_R0P7734 1 | |
14 | #define CONFIG_400MHZ_MODE 1 | |
15 | /* #define CONFIG_533MHZ_MODE 1 */ | |
16 | ||
17 | #define CONFIG_SYS_TEXT_BASE 0x8FFC0000 | |
18 | ||
19 | #define CONFIG_CMD_SDRAM | |
20 | ||
21 | #define CONFIG_BOOTARGS "console=ttySC3,115200" | |
22 | ||
23 | #define CONFIG_DISPLAY_BOARDINFO | |
24 | #undef CONFIG_SHOW_BOOT_PROGRESS | |
25 | ||
26 | /* Ether */ | |
27 | #define CONFIG_SH_ETHER 1 | |
28 | #define CONFIG_SH_ETHER_USE_PORT (0) | |
29 | #define CONFIG_SH_ETHER_PHY_ADDR (0x0) | |
30 | #define CONFIG_PHYLIB | |
31 | #define CONFIG_PHY_SMSC 1 | |
32 | #define CONFIG_BITBANGMII | |
33 | #define CONFIG_BITBANGMII_MULTI | |
34 | #define CONFIG_SH_ETHER_SH7734_MII (0x00) /* MII */ | |
35 | #define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_MII | |
36 | #ifndef CONFIG_SH_ETHER | |
37 | # define CONFIG_SMC911X | |
38 | # define CONFIG_SMC911X_16_BIT | |
39 | # define CONFIG_SMC911X_BASE (0x84000000) | |
40 | #endif | |
41 | ||
42 | /* undef to save memory */ | |
43 | #define CONFIG_SYS_LONGHELP | |
44 | /* Monitor Command Prompt */ | |
45 | /* Buffer size for input from the Console */ | |
46 | #define CONFIG_SYS_CBSIZE 256 | |
47 | /* Buffer size for Console output */ | |
48 | #define CONFIG_SYS_PBSIZE 256 | |
49 | /* max args accepted for monitor commands */ | |
50 | #define CONFIG_SYS_MAXARGS 16 | |
51 | /* Buffer size for Boot Arguments passed to kernel */ | |
52 | #define CONFIG_SYS_BARGSIZE 512 | |
53 | /* List of legal baudrate settings for this board */ | |
54 | #define CONFIG_SYS_BAUDRATE_TABLE { 115200 } | |
55 | ||
56 | /* SCIF */ | |
57 | #define CONFIG_SCIF_CONSOLE 1 | |
58 | #define CONFIG_SCIF 1 | |
59 | #define CONFIG_CONS_SCIF3 1 | |
60 | ||
61 | /* Suppress display of console information at boot */ | |
62 | ||
63 | /* SDRAM */ | |
64 | #define CONFIG_SYS_SDRAM_BASE (0x88000000) | |
65 | #define CONFIG_SYS_SDRAM_SIZE (128 * 1024 * 1024) | |
66 | #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 16 * 1024 * 1024) | |
67 | ||
68 | #define CONFIG_SYS_MEMTEST_START (CONFIG_SYS_SDRAM_BASE) | |
69 | #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 100 * 1024 * 1024) | |
70 | /* Enable alternate, more extensive, memory test */ | |
71 | #undef CONFIG_SYS_ALT_MEMTEST | |
72 | /* Scratch address used by the alternate memory test */ | |
73 | #undef CONFIG_SYS_MEMTEST_SCRATCH | |
74 | ||
75 | /* Enable temporary baudrate change while serial download */ | |
76 | #undef CONFIG_SYS_LOADS_BAUD_CHANGE | |
77 | ||
78 | /* FLASH */ | |
79 | #define CONFIG_FLASH_CFI_DRIVER 1 | |
80 | #define CONFIG_SYS_FLASH_CFI | |
81 | #undef CONFIG_SYS_FLASH_QUIET_TEST | |
82 | #define CONFIG_SYS_FLASH_EMPTY_INFO | |
83 | #define CONFIG_SYS_FLASH_BASE (0xA0000000) | |
84 | #define CONFIG_SYS_MAX_FLASH_SECT 512 | |
85 | ||
86 | /* if you use all NOR Flash , you change dip-switch. Please see Manual. */ | |
87 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 | |
88 | #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } | |
89 | ||
90 | /* Timeout for Flash erase operations (in ms) */ | |
91 | #define CONFIG_SYS_FLASH_ERASE_TOUT (3 * 1000) | |
92 | /* Timeout for Flash write operations (in ms) */ | |
93 | #define CONFIG_SYS_FLASH_WRITE_TOUT (3 * 1000) | |
94 | /* Timeout for Flash set sector lock bit operations (in ms) */ | |
95 | #define CONFIG_SYS_FLASH_LOCK_TOUT (3 * 1000) | |
96 | /* Timeout for Flash clear lock bit operations (in ms) */ | |
97 | #define CONFIG_SYS_FLASH_UNLOCK_TOUT (3 * 1000) | |
98 | ||
99 | /* | |
100 | * Use hardware flash sectors protection instead | |
101 | * of U-Boot software protection | |
102 | */ | |
103 | #undef CONFIG_SYS_FLASH_PROTECTION | |
104 | #undef CONFIG_SYS_DIRECT_FLASH_TFTP | |
105 | ||
106 | /* Address of u-boot image in Flash (NOT run time address in SDRAM) ?!? */ | |
107 | #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE) | |
108 | /* Monitor size */ | |
109 | #define CONFIG_SYS_MONITOR_LEN (256 * 1024) | |
110 | /* Size of DRAM reserved for malloc() use */ | |
111 | #define CONFIG_SYS_MALLOC_LEN (256 * 1024) | |
112 | #define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024) | |
113 | ||
114 | /* ENV setting */ | |
115 | #define CONFIG_ENV_OVERWRITE 1 | |
116 | #define CONFIG_ENV_SECT_SIZE (128 * 1024) | |
117 | #define CONFIG_ENV_SIZE (CONFIG_ENV_SECT_SIZE) | |
118 | #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_LEN) | |
119 | /* Offset of env Flash sector relative to CONFIG_SYS_FLASH_BASE */ | |
120 | #define CONFIG_ENV_OFFSET (CONFIG_ENV_ADDR - CONFIG_SYS_FLASH_BASE) | |
121 | #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SECT_SIZE) | |
122 | ||
123 | /* Board Clock */ | |
124 | #if defined(CONFIG_400MHZ_MODE) | |
125 | #define CONFIG_SYS_CLK_FREQ 50000000 | |
126 | #else | |
127 | #define CONFIG_SYS_CLK_FREQ 44444444 | |
128 | #endif | |
129 | #define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ | |
130 | #define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ | |
131 | #define CONFIG_SYS_TMU_CLK_DIV 4 | |
132 | ||
133 | #endif /* __R0P7734_H */ |