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1 | /* run front end support for arm | |
2 | Copyright (C) 1995-1997, 2000-2002, 2007-2012 Free Software | |
3 | Foundation, Inc. | |
4 | ||
5 | This file is part of ARM SIM. | |
6 | ||
7 | This program is free software; you can redistribute it and/or modify | |
8 | it under the terms of the GNU General Public License as published by | |
9 | the Free Software Foundation; either version 3 of the License, or | |
10 | (at your option) any later version. | |
11 | ||
12 | This program is distributed in the hope that it will be useful, | |
13 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | GNU General Public License for more details. | |
16 | ||
17 | You should have received a copy of the GNU General Public License | |
18 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ | |
19 | ||
20 | /* This file provides the interface between the simulator and | |
21 | run.c and gdb (when the simulator is linked with gdb). | |
22 | All simulator interaction should go through this file. */ | |
23 | ||
24 | #include "config.h" | |
25 | #include <stdio.h> | |
26 | #include <stdarg.h> | |
27 | #include <string.h> | |
28 | #include <bfd.h> | |
29 | #include <signal.h> | |
30 | #include "gdb/callback.h" | |
31 | #include "gdb/remote-sim.h" | |
32 | #include "armdefs.h" | |
33 | #include "armemu.h" | |
34 | #include "dbg_rdi.h" | |
35 | #include "ansidecl.h" | |
36 | #include "sim-utils.h" | |
37 | #include "run-sim.h" | |
38 | #include "gdb/sim-arm.h" | |
39 | #include "gdb/signals.h" | |
40 | ||
41 | host_callback *sim_callback; | |
42 | ||
43 | static struct ARMul_State *state; | |
44 | ||
45 | /* Who is using the simulator. */ | |
46 | static SIM_OPEN_KIND sim_kind; | |
47 | ||
48 | /* argv[0] */ | |
49 | static char *myname; | |
50 | ||
51 | /* Memory size in bytes. */ | |
52 | static int mem_size = (1 << 21); | |
53 | ||
54 | /* Non-zero to display start up banner, and maybe other things. */ | |
55 | static int verbosity; | |
56 | ||
57 | /* Non-zero to set big endian mode. */ | |
58 | static int big_endian; | |
59 | ||
60 | int stop_simulator; | |
61 | ||
62 | /* Cirrus DSP registers. | |
63 | ||
64 | We need to define these registers outside of maverick.c because | |
65 | maverick.c might not be linked in unless --target=arm9e-* in which | |
66 | case wrapper.c will not compile because it tries to access Cirrus | |
67 | registers. This should all go away once we get the Cirrus and ARM | |
68 | Coprocessor to coexist in armcopro.c-- aldyh. */ | |
69 | ||
70 | struct maverick_regs | |
71 | { | |
72 | union | |
73 | { | |
74 | int i; | |
75 | float f; | |
76 | } upper; | |
77 | ||
78 | union | |
79 | { | |
80 | int i; | |
81 | float f; | |
82 | } lower; | |
83 | }; | |
84 | ||
85 | union maverick_acc_regs | |
86 | { | |
87 | long double ld; /* Acc registers are 72-bits. */ | |
88 | }; | |
89 | ||
90 | struct maverick_regs DSPregs[16]; | |
91 | union maverick_acc_regs DSPacc[4]; | |
92 | ARMword DSPsc; | |
93 | ||
94 | static void | |
95 | init () | |
96 | { | |
97 | static int done; | |
98 | ||
99 | if (!done) | |
100 | { | |
101 | ARMul_EmulateInit (); | |
102 | state = ARMul_NewState (); | |
103 | state->bigendSig = (big_endian ? HIGH : LOW); | |
104 | ARMul_MemoryInit (state, mem_size); | |
105 | ARMul_OSInit (state); | |
106 | state->verbose = verbosity; | |
107 | done = 1; | |
108 | } | |
109 | } | |
110 | ||
111 | /* Set verbosity level of simulator. | |
112 | This is not intended to produce detailed tracing or debugging information. | |
113 | Just summaries. */ | |
114 | /* FIXME: common/run.c doesn't do this yet. */ | |
115 | ||
116 | void | |
117 | sim_set_verbose (v) | |
118 | int v; | |
119 | { | |
120 | verbosity = v; | |
121 | } | |
122 | ||
123 | /* Set the memory size to SIZE bytes. | |
124 | Must be called before initializing simulator. */ | |
125 | /* FIXME: Rename to sim_set_mem_size. */ | |
126 | ||
127 | void | |
128 | sim_size (size) | |
129 | int size; | |
130 | { | |
131 | mem_size = size; | |
132 | } | |
133 | ||
134 | void | |
135 | ARMul_ConsolePrint VPARAMS ((ARMul_State * state, | |
136 | const char * format, | |
137 | ...)) | |
138 | { | |
139 | va_list ap; | |
140 | ||
141 | if (state->verbose) | |
142 | { | |
143 | va_start (ap, format); | |
144 | vprintf (format, ap); | |
145 | va_end (ap); | |
146 | } | |
147 | } | |
148 | ||
149 | ARMword | |
150 | ARMul_Debug (state, pc, instr) | |
151 | ARMul_State * state ATTRIBUTE_UNUSED; | |
152 | ARMword pc ATTRIBUTE_UNUSED; | |
153 | ARMword instr ATTRIBUTE_UNUSED; | |
154 | { | |
155 | return 0; | |
156 | } | |
157 | ||
158 | int | |
159 | sim_write (sd, addr, buffer, size) | |
160 | SIM_DESC sd ATTRIBUTE_UNUSED; | |
161 | SIM_ADDR addr; | |
162 | const unsigned char * buffer; | |
163 | int size; | |
164 | { | |
165 | int i; | |
166 | ||
167 | init (); | |
168 | ||
169 | for (i = 0; i < size; i++) | |
170 | ARMul_SafeWriteByte (state, addr + i, buffer[i]); | |
171 | ||
172 | return size; | |
173 | } | |
174 | ||
175 | int | |
176 | sim_read (sd, addr, buffer, size) | |
177 | SIM_DESC sd ATTRIBUTE_UNUSED; | |
178 | SIM_ADDR addr; | |
179 | unsigned char * buffer; | |
180 | int size; | |
181 | { | |
182 | int i; | |
183 | ||
184 | init (); | |
185 | ||
186 | for (i = 0; i < size; i++) | |
187 | buffer[i] = ARMul_SafeReadByte (state, addr + i); | |
188 | ||
189 | return size; | |
190 | } | |
191 | ||
192 | int | |
193 | sim_trace (sd) | |
194 | SIM_DESC sd ATTRIBUTE_UNUSED; | |
195 | { | |
196 | (*sim_callback->printf_filtered) | |
197 | (sim_callback, | |
198 | "This simulator does not support tracing\n"); | |
199 | return 1; | |
200 | } | |
201 | ||
202 | int | |
203 | sim_stop (sd) | |
204 | SIM_DESC sd ATTRIBUTE_UNUSED; | |
205 | { | |
206 | state->Emulate = STOP; | |
207 | stop_simulator = 1; | |
208 | return 1; | |
209 | } | |
210 | ||
211 | void | |
212 | sim_resume (sd, step, siggnal) | |
213 | SIM_DESC sd ATTRIBUTE_UNUSED; | |
214 | int step; | |
215 | int siggnal ATTRIBUTE_UNUSED; | |
216 | { | |
217 | state->EndCondition = 0; | |
218 | stop_simulator = 0; | |
219 | ||
220 | if (step) | |
221 | { | |
222 | state->Reg[15] = ARMul_DoInstr (state); | |
223 | if (state->EndCondition == 0) | |
224 | state->EndCondition = RDIError_BreakpointReached; | |
225 | } | |
226 | else | |
227 | { | |
228 | state->NextInstr = RESUME; /* treat as PC change */ | |
229 | state->Reg[15] = ARMul_DoProg (state); | |
230 | } | |
231 | ||
232 | FLUSHPIPE; | |
233 | } | |
234 | ||
235 | SIM_RC | |
236 | sim_create_inferior (sd, abfd, argv, env) | |
237 | SIM_DESC sd ATTRIBUTE_UNUSED; | |
238 | struct bfd * abfd; | |
239 | char ** argv; | |
240 | char ** env; | |
241 | { | |
242 | int argvlen = 0; | |
243 | int mach; | |
244 | char **arg; | |
245 | ||
246 | if (abfd != NULL) | |
247 | ARMul_SetPC (state, bfd_get_start_address (abfd)); | |
248 | else | |
249 | ARMul_SetPC (state, 0); /* ??? */ | |
250 | ||
251 | mach = bfd_get_mach (abfd); | |
252 | ||
253 | switch (mach) | |
254 | { | |
255 | default: | |
256 | (*sim_callback->printf_filtered) | |
257 | (sim_callback, | |
258 | "Unknown machine type '%d'; please update sim_create_inferior.\n", | |
259 | mach); | |
260 | /* fall through */ | |
261 | ||
262 | case 0: | |
263 | /* We wouldn't set the machine type with earlier toolchains, so we | |
264 | explicitly select a processor capable of supporting all ARMs in | |
265 | 32bit mode. */ | |
266 | /* We choose the XScale rather than the iWMMXt, because the iWMMXt | |
267 | removes the FPE emulator, since it conflicts with its coprocessors. | |
268 | For the most generic ARM support, we want the FPE emulator in place. */ | |
269 | case bfd_mach_arm_XScale: | |
270 | ARMul_SelectProcessor (state, ARM_v5_Prop | ARM_v5e_Prop | ARM_XScale_Prop | ARM_v6_Prop); | |
271 | break; | |
272 | ||
273 | case bfd_mach_arm_iWMMXt: | |
274 | { | |
275 | extern int SWI_vector_installed; | |
276 | ARMword i; | |
277 | ||
278 | if (! SWI_vector_installed) | |
279 | { | |
280 | /* Intialise the hardware vectors to zero. */ | |
281 | if (! SWI_vector_installed) | |
282 | for (i = ARMul_ResetV; i <= ARMFIQV; i += 4) | |
283 | ARMul_WriteWord (state, i, 0); | |
284 | ||
285 | /* ARM_WriteWord will have detected the write to the SWI vector, | |
286 | but we want SWI_vector_installed to remain at 0 so that thumb | |
287 | mode breakpoints will work. */ | |
288 | SWI_vector_installed = 0; | |
289 | } | |
290 | } | |
291 | ARMul_SelectProcessor (state, ARM_v5_Prop | ARM_v5e_Prop | ARM_XScale_Prop | ARM_iWMMXt_Prop); | |
292 | break; | |
293 | ||
294 | case bfd_mach_arm_ep9312: | |
295 | ARMul_SelectProcessor (state, ARM_v4_Prop | ARM_ep9312_Prop); | |
296 | break; | |
297 | ||
298 | case bfd_mach_arm_5: | |
299 | if (bfd_family_coff (abfd)) | |
300 | { | |
301 | /* This is a special case in order to support COFF based ARM toolchains. | |
302 | The COFF header does not have enough room to store all the different | |
303 | kinds of ARM cpu, so the XScale, v5T and v5TE architectures all default | |
304 | to v5. (See coff_set_flags() in bdf/coffcode.h). So if we see a v5 | |
305 | machine type here, we assume it could be any of the above architectures | |
306 | and so select the most feature-full. */ | |
307 | ARMul_SelectProcessor (state, ARM_v5_Prop | ARM_v5e_Prop | ARM_XScale_Prop); | |
308 | break; | |
309 | } | |
310 | /* Otherwise drop through. */ | |
311 | ||
312 | case bfd_mach_arm_5T: | |
313 | ARMul_SelectProcessor (state, ARM_v5_Prop); | |
314 | break; | |
315 | ||
316 | case bfd_mach_arm_5TE: | |
317 | ARMul_SelectProcessor (state, ARM_v5_Prop | ARM_v5e_Prop); | |
318 | break; | |
319 | ||
320 | case bfd_mach_arm_4: | |
321 | case bfd_mach_arm_4T: | |
322 | ARMul_SelectProcessor (state, ARM_v4_Prop); | |
323 | break; | |
324 | ||
325 | case bfd_mach_arm_3: | |
326 | case bfd_mach_arm_3M: | |
327 | ARMul_SelectProcessor (state, ARM_Lock_Prop); | |
328 | break; | |
329 | ||
330 | case bfd_mach_arm_2: | |
331 | case bfd_mach_arm_2a: | |
332 | ARMul_SelectProcessor (state, ARM_Fix26_Prop); | |
333 | break; | |
334 | } | |
335 | ||
336 | if ( mach != bfd_mach_arm_3 | |
337 | && mach != bfd_mach_arm_3M | |
338 | && mach != bfd_mach_arm_2 | |
339 | && mach != bfd_mach_arm_2a) | |
340 | { | |
341 | /* Reset mode to ARM. A gdb user may rerun a program that had entered | |
342 | THUMB mode from the start and cause the ARM-mode startup code to be | |
343 | executed in THUMB mode. */ | |
344 | ARMul_SetCPSR (state, SVC32MODE); | |
345 | } | |
346 | ||
347 | if (argv != NULL) | |
348 | { | |
349 | /* Set up the command line by laboriously stringing together | |
350 | the environment carefully picked apart by our caller. */ | |
351 | ||
352 | /* Free any old stuff. */ | |
353 | if (state->CommandLine != NULL) | |
354 | { | |
355 | free (state->CommandLine); | |
356 | state->CommandLine = NULL; | |
357 | } | |
358 | ||
359 | /* See how much we need. */ | |
360 | for (arg = argv; *arg != NULL; arg++) | |
361 | argvlen += strlen (*arg) + 1; | |
362 | ||
363 | /* Allocate it. */ | |
364 | state->CommandLine = malloc (argvlen + 1); | |
365 | if (state->CommandLine != NULL) | |
366 | { | |
367 | arg = argv; | |
368 | state->CommandLine[0] = '\0'; | |
369 | ||
370 | for (arg = argv; *arg != NULL; arg++) | |
371 | { | |
372 | strcat (state->CommandLine, *arg); | |
373 | strcat (state->CommandLine, " "); | |
374 | } | |
375 | } | |
376 | } | |
377 | ||
378 | if (env != NULL) | |
379 | { | |
380 | /* Now see if there's a MEMSIZE spec in the environment. */ | |
381 | while (*env) | |
382 | { | |
383 | if (strncmp (*env, "MEMSIZE=", sizeof ("MEMSIZE=") - 1) == 0) | |
384 | { | |
385 | char *end_of_num; | |
386 | ||
387 | /* Set up memory limit. */ | |
388 | state->MemSize = | |
389 | strtoul (*env + sizeof ("MEMSIZE=") - 1, &end_of_num, 0); | |
390 | } | |
391 | env++; | |
392 | } | |
393 | } | |
394 | ||
395 | return SIM_RC_OK; | |
396 | } | |
397 | ||
398 | void | |
399 | sim_info (sd, verbose) | |
400 | SIM_DESC sd ATTRIBUTE_UNUSED; | |
401 | int verbose ATTRIBUTE_UNUSED; | |
402 | { | |
403 | } | |
404 | ||
405 | static int | |
406 | frommem (state, memory) | |
407 | struct ARMul_State *state; | |
408 | unsigned char *memory; | |
409 | { | |
410 | if (state->bigendSig == HIGH) | |
411 | return (memory[0] << 24) | (memory[1] << 16) | |
412 | | (memory[2] << 8) | (memory[3] << 0); | |
413 | else | |
414 | return (memory[3] << 24) | (memory[2] << 16) | |
415 | | (memory[1] << 8) | (memory[0] << 0); | |
416 | } | |
417 | ||
418 | static void | |
419 | tomem (state, memory, val) | |
420 | struct ARMul_State *state; | |
421 | unsigned char *memory; | |
422 | int val; | |
423 | { | |
424 | if (state->bigendSig == HIGH) | |
425 | { | |
426 | memory[0] = val >> 24; | |
427 | memory[1] = val >> 16; | |
428 | memory[2] = val >> 8; | |
429 | memory[3] = val >> 0; | |
430 | } | |
431 | else | |
432 | { | |
433 | memory[3] = val >> 24; | |
434 | memory[2] = val >> 16; | |
435 | memory[1] = val >> 8; | |
436 | memory[0] = val >> 0; | |
437 | } | |
438 | } | |
439 | ||
440 | int | |
441 | sim_store_register (sd, rn, memory, length) | |
442 | SIM_DESC sd ATTRIBUTE_UNUSED; | |
443 | int rn; | |
444 | unsigned char *memory; | |
445 | int length ATTRIBUTE_UNUSED; | |
446 | { | |
447 | init (); | |
448 | ||
449 | switch ((enum sim_arm_regs) rn) | |
450 | { | |
451 | case SIM_ARM_R0_REGNUM: | |
452 | case SIM_ARM_R1_REGNUM: | |
453 | case SIM_ARM_R2_REGNUM: | |
454 | case SIM_ARM_R3_REGNUM: | |
455 | case SIM_ARM_R4_REGNUM: | |
456 | case SIM_ARM_R5_REGNUM: | |
457 | case SIM_ARM_R6_REGNUM: | |
458 | case SIM_ARM_R7_REGNUM: | |
459 | case SIM_ARM_R8_REGNUM: | |
460 | case SIM_ARM_R9_REGNUM: | |
461 | case SIM_ARM_R10_REGNUM: | |
462 | case SIM_ARM_R11_REGNUM: | |
463 | case SIM_ARM_R12_REGNUM: | |
464 | case SIM_ARM_R13_REGNUM: | |
465 | case SIM_ARM_R14_REGNUM: | |
466 | case SIM_ARM_R15_REGNUM: /* PC */ | |
467 | case SIM_ARM_FP0_REGNUM: | |
468 | case SIM_ARM_FP1_REGNUM: | |
469 | case SIM_ARM_FP2_REGNUM: | |
470 | case SIM_ARM_FP3_REGNUM: | |
471 | case SIM_ARM_FP4_REGNUM: | |
472 | case SIM_ARM_FP5_REGNUM: | |
473 | case SIM_ARM_FP6_REGNUM: | |
474 | case SIM_ARM_FP7_REGNUM: | |
475 | case SIM_ARM_FPS_REGNUM: | |
476 | ARMul_SetReg (state, state->Mode, rn, frommem (state, memory)); | |
477 | break; | |
478 | ||
479 | case SIM_ARM_PS_REGNUM: | |
480 | state->Cpsr = frommem (state, memory); | |
481 | ARMul_CPSRAltered (state); | |
482 | break; | |
483 | ||
484 | case SIM_ARM_MAVERIC_COP0R0_REGNUM: | |
485 | case SIM_ARM_MAVERIC_COP0R1_REGNUM: | |
486 | case SIM_ARM_MAVERIC_COP0R2_REGNUM: | |
487 | case SIM_ARM_MAVERIC_COP0R3_REGNUM: | |
488 | case SIM_ARM_MAVERIC_COP0R4_REGNUM: | |
489 | case SIM_ARM_MAVERIC_COP0R5_REGNUM: | |
490 | case SIM_ARM_MAVERIC_COP0R6_REGNUM: | |
491 | case SIM_ARM_MAVERIC_COP0R7_REGNUM: | |
492 | case SIM_ARM_MAVERIC_COP0R8_REGNUM: | |
493 | case SIM_ARM_MAVERIC_COP0R9_REGNUM: | |
494 | case SIM_ARM_MAVERIC_COP0R10_REGNUM: | |
495 | case SIM_ARM_MAVERIC_COP0R11_REGNUM: | |
496 | case SIM_ARM_MAVERIC_COP0R12_REGNUM: | |
497 | case SIM_ARM_MAVERIC_COP0R13_REGNUM: | |
498 | case SIM_ARM_MAVERIC_COP0R14_REGNUM: | |
499 | case SIM_ARM_MAVERIC_COP0R15_REGNUM: | |
500 | memcpy (& DSPregs [rn - SIM_ARM_MAVERIC_COP0R0_REGNUM], | |
501 | memory, sizeof (struct maverick_regs)); | |
502 | return sizeof (struct maverick_regs); | |
503 | ||
504 | case SIM_ARM_MAVERIC_DSPSC_REGNUM: | |
505 | memcpy (&DSPsc, memory, sizeof DSPsc); | |
506 | return sizeof DSPsc; | |
507 | ||
508 | case SIM_ARM_IWMMXT_COP0R0_REGNUM: | |
509 | case SIM_ARM_IWMMXT_COP0R1_REGNUM: | |
510 | case SIM_ARM_IWMMXT_COP0R2_REGNUM: | |
511 | case SIM_ARM_IWMMXT_COP0R3_REGNUM: | |
512 | case SIM_ARM_IWMMXT_COP0R4_REGNUM: | |
513 | case SIM_ARM_IWMMXT_COP0R5_REGNUM: | |
514 | case SIM_ARM_IWMMXT_COP0R6_REGNUM: | |
515 | case SIM_ARM_IWMMXT_COP0R7_REGNUM: | |
516 | case SIM_ARM_IWMMXT_COP0R8_REGNUM: | |
517 | case SIM_ARM_IWMMXT_COP0R9_REGNUM: | |
518 | case SIM_ARM_IWMMXT_COP0R10_REGNUM: | |
519 | case SIM_ARM_IWMMXT_COP0R11_REGNUM: | |
520 | case SIM_ARM_IWMMXT_COP0R12_REGNUM: | |
521 | case SIM_ARM_IWMMXT_COP0R13_REGNUM: | |
522 | case SIM_ARM_IWMMXT_COP0R14_REGNUM: | |
523 | case SIM_ARM_IWMMXT_COP0R15_REGNUM: | |
524 | case SIM_ARM_IWMMXT_COP1R0_REGNUM: | |
525 | case SIM_ARM_IWMMXT_COP1R1_REGNUM: | |
526 | case SIM_ARM_IWMMXT_COP1R2_REGNUM: | |
527 | case SIM_ARM_IWMMXT_COP1R3_REGNUM: | |
528 | case SIM_ARM_IWMMXT_COP1R4_REGNUM: | |
529 | case SIM_ARM_IWMMXT_COP1R5_REGNUM: | |
530 | case SIM_ARM_IWMMXT_COP1R6_REGNUM: | |
531 | case SIM_ARM_IWMMXT_COP1R7_REGNUM: | |
532 | case SIM_ARM_IWMMXT_COP1R8_REGNUM: | |
533 | case SIM_ARM_IWMMXT_COP1R9_REGNUM: | |
534 | case SIM_ARM_IWMMXT_COP1R10_REGNUM: | |
535 | case SIM_ARM_IWMMXT_COP1R11_REGNUM: | |
536 | case SIM_ARM_IWMMXT_COP1R12_REGNUM: | |
537 | case SIM_ARM_IWMMXT_COP1R13_REGNUM: | |
538 | case SIM_ARM_IWMMXT_COP1R14_REGNUM: | |
539 | case SIM_ARM_IWMMXT_COP1R15_REGNUM: | |
540 | return Store_Iwmmxt_Register (rn - SIM_ARM_IWMMXT_COP0R0_REGNUM, memory); | |
541 | ||
542 | default: | |
543 | return 0; | |
544 | } | |
545 | ||
546 | return -1; | |
547 | } | |
548 | ||
549 | int | |
550 | sim_fetch_register (sd, rn, memory, length) | |
551 | SIM_DESC sd ATTRIBUTE_UNUSED; | |
552 | int rn; | |
553 | unsigned char *memory; | |
554 | int length ATTRIBUTE_UNUSED; | |
555 | { | |
556 | ARMword regval; | |
557 | ||
558 | init (); | |
559 | ||
560 | switch ((enum sim_arm_regs) rn) | |
561 | { | |
562 | case SIM_ARM_R0_REGNUM: | |
563 | case SIM_ARM_R1_REGNUM: | |
564 | case SIM_ARM_R2_REGNUM: | |
565 | case SIM_ARM_R3_REGNUM: | |
566 | case SIM_ARM_R4_REGNUM: | |
567 | case SIM_ARM_R5_REGNUM: | |
568 | case SIM_ARM_R6_REGNUM: | |
569 | case SIM_ARM_R7_REGNUM: | |
570 | case SIM_ARM_R8_REGNUM: | |
571 | case SIM_ARM_R9_REGNUM: | |
572 | case SIM_ARM_R10_REGNUM: | |
573 | case SIM_ARM_R11_REGNUM: | |
574 | case SIM_ARM_R12_REGNUM: | |
575 | case SIM_ARM_R13_REGNUM: | |
576 | case SIM_ARM_R14_REGNUM: | |
577 | case SIM_ARM_R15_REGNUM: /* PC */ | |
578 | regval = ARMul_GetReg (state, state->Mode, rn); | |
579 | break; | |
580 | ||
581 | case SIM_ARM_FP0_REGNUM: | |
582 | case SIM_ARM_FP1_REGNUM: | |
583 | case SIM_ARM_FP2_REGNUM: | |
584 | case SIM_ARM_FP3_REGNUM: | |
585 | case SIM_ARM_FP4_REGNUM: | |
586 | case SIM_ARM_FP5_REGNUM: | |
587 | case SIM_ARM_FP6_REGNUM: | |
588 | case SIM_ARM_FP7_REGNUM: | |
589 | case SIM_ARM_FPS_REGNUM: | |
590 | memset (memory, 0, length); | |
591 | return 0; | |
592 | ||
593 | case SIM_ARM_PS_REGNUM: | |
594 | regval = ARMul_GetCPSR (state); | |
595 | break; | |
596 | ||
597 | case SIM_ARM_MAVERIC_COP0R0_REGNUM: | |
598 | case SIM_ARM_MAVERIC_COP0R1_REGNUM: | |
599 | case SIM_ARM_MAVERIC_COP0R2_REGNUM: | |
600 | case SIM_ARM_MAVERIC_COP0R3_REGNUM: | |
601 | case SIM_ARM_MAVERIC_COP0R4_REGNUM: | |
602 | case SIM_ARM_MAVERIC_COP0R5_REGNUM: | |
603 | case SIM_ARM_MAVERIC_COP0R6_REGNUM: | |
604 | case SIM_ARM_MAVERIC_COP0R7_REGNUM: | |
605 | case SIM_ARM_MAVERIC_COP0R8_REGNUM: | |
606 | case SIM_ARM_MAVERIC_COP0R9_REGNUM: | |
607 | case SIM_ARM_MAVERIC_COP0R10_REGNUM: | |
608 | case SIM_ARM_MAVERIC_COP0R11_REGNUM: | |
609 | case SIM_ARM_MAVERIC_COP0R12_REGNUM: | |
610 | case SIM_ARM_MAVERIC_COP0R13_REGNUM: | |
611 | case SIM_ARM_MAVERIC_COP0R14_REGNUM: | |
612 | case SIM_ARM_MAVERIC_COP0R15_REGNUM: | |
613 | memcpy (memory, & DSPregs [rn - SIM_ARM_MAVERIC_COP0R0_REGNUM], | |
614 | sizeof (struct maverick_regs)); | |
615 | return sizeof (struct maverick_regs); | |
616 | ||
617 | case SIM_ARM_MAVERIC_DSPSC_REGNUM: | |
618 | memcpy (memory, & DSPsc, sizeof DSPsc); | |
619 | return sizeof DSPsc; | |
620 | ||
621 | case SIM_ARM_IWMMXT_COP0R0_REGNUM: | |
622 | case SIM_ARM_IWMMXT_COP0R1_REGNUM: | |
623 | case SIM_ARM_IWMMXT_COP0R2_REGNUM: | |
624 | case SIM_ARM_IWMMXT_COP0R3_REGNUM: | |
625 | case SIM_ARM_IWMMXT_COP0R4_REGNUM: | |
626 | case SIM_ARM_IWMMXT_COP0R5_REGNUM: | |
627 | case SIM_ARM_IWMMXT_COP0R6_REGNUM: | |
628 | case SIM_ARM_IWMMXT_COP0R7_REGNUM: | |
629 | case SIM_ARM_IWMMXT_COP0R8_REGNUM: | |
630 | case SIM_ARM_IWMMXT_COP0R9_REGNUM: | |
631 | case SIM_ARM_IWMMXT_COP0R10_REGNUM: | |
632 | case SIM_ARM_IWMMXT_COP0R11_REGNUM: | |
633 | case SIM_ARM_IWMMXT_COP0R12_REGNUM: | |
634 | case SIM_ARM_IWMMXT_COP0R13_REGNUM: | |
635 | case SIM_ARM_IWMMXT_COP0R14_REGNUM: | |
636 | case SIM_ARM_IWMMXT_COP0R15_REGNUM: | |
637 | case SIM_ARM_IWMMXT_COP1R0_REGNUM: | |
638 | case SIM_ARM_IWMMXT_COP1R1_REGNUM: | |
639 | case SIM_ARM_IWMMXT_COP1R2_REGNUM: | |
640 | case SIM_ARM_IWMMXT_COP1R3_REGNUM: | |
641 | case SIM_ARM_IWMMXT_COP1R4_REGNUM: | |
642 | case SIM_ARM_IWMMXT_COP1R5_REGNUM: | |
643 | case SIM_ARM_IWMMXT_COP1R6_REGNUM: | |
644 | case SIM_ARM_IWMMXT_COP1R7_REGNUM: | |
645 | case SIM_ARM_IWMMXT_COP1R8_REGNUM: | |
646 | case SIM_ARM_IWMMXT_COP1R9_REGNUM: | |
647 | case SIM_ARM_IWMMXT_COP1R10_REGNUM: | |
648 | case SIM_ARM_IWMMXT_COP1R11_REGNUM: | |
649 | case SIM_ARM_IWMMXT_COP1R12_REGNUM: | |
650 | case SIM_ARM_IWMMXT_COP1R13_REGNUM: | |
651 | case SIM_ARM_IWMMXT_COP1R14_REGNUM: | |
652 | case SIM_ARM_IWMMXT_COP1R15_REGNUM: | |
653 | return Fetch_Iwmmxt_Register (rn - SIM_ARM_IWMMXT_COP0R0_REGNUM, memory); | |
654 | ||
655 | default: | |
656 | return 0; | |
657 | } | |
658 | ||
659 | while (length) | |
660 | { | |
661 | tomem (state, memory, regval); | |
662 | ||
663 | length -= 4; | |
664 | memory += 4; | |
665 | regval = 0; | |
666 | } | |
667 | ||
668 | return -1; | |
669 | } | |
670 | ||
671 | #ifdef SIM_TARGET_SWITCHES | |
672 | ||
673 | static void sim_target_parse_arg_array PARAMS ((char **)); | |
674 | ||
675 | typedef struct | |
676 | { | |
677 | char * swi_option; | |
678 | unsigned int swi_mask; | |
679 | } swi_options; | |
680 | ||
681 | #define SWI_SWITCH "--swi-support" | |
682 | ||
683 | static swi_options options[] = | |
684 | { | |
685 | { "none", 0 }, | |
686 | { "demon", SWI_MASK_DEMON }, | |
687 | { "angel", SWI_MASK_ANGEL }, | |
688 | { "redboot", SWI_MASK_REDBOOT }, | |
689 | { "all", -1 }, | |
690 | { "NONE", 0 }, | |
691 | { "DEMON", SWI_MASK_DEMON }, | |
692 | { "ANGEL", SWI_MASK_ANGEL }, | |
693 | { "REDBOOT", SWI_MASK_REDBOOT }, | |
694 | { "ALL", -1 } | |
695 | }; | |
696 | ||
697 | ||
698 | int | |
699 | sim_target_parse_command_line (argc, argv) | |
700 | int argc; | |
701 | char ** argv; | |
702 | { | |
703 | int i; | |
704 | ||
705 | for (i = 1; i < argc; i++) | |
706 | { | |
707 | char * ptr = argv[i]; | |
708 | int arg; | |
709 | ||
710 | if ((ptr == NULL) || (* ptr != '-')) | |
711 | break; | |
712 | ||
713 | if (strncmp (ptr, SWI_SWITCH, sizeof SWI_SWITCH - 1) != 0) | |
714 | continue; | |
715 | ||
716 | if (ptr[sizeof SWI_SWITCH - 1] == 0) | |
717 | { | |
718 | /* Remove this option from the argv array. */ | |
719 | for (arg = i; arg < argc; arg ++) | |
720 | argv[arg] = argv[arg + 1]; | |
721 | argc --; | |
722 | ||
723 | ptr = argv[i]; | |
724 | } | |
725 | else | |
726 | ptr += sizeof SWI_SWITCH; | |
727 | ||
728 | swi_mask = 0; | |
729 | ||
730 | while (* ptr) | |
731 | { | |
732 | int i; | |
733 | ||
734 | for (i = sizeof options / sizeof options[0]; i--;) | |
735 | if (strncmp (ptr, options[i].swi_option, | |
736 | strlen (options[i].swi_option)) == 0) | |
737 | { | |
738 | swi_mask |= options[i].swi_mask; | |
739 | ptr += strlen (options[i].swi_option); | |
740 | ||
741 | if (* ptr == ',') | |
742 | ++ ptr; | |
743 | ||
744 | break; | |
745 | } | |
746 | ||
747 | if (i < 0) | |
748 | break; | |
749 | } | |
750 | ||
751 | if (* ptr != 0) | |
752 | fprintf (stderr, "Ignoring swi options: %s\n", ptr); | |
753 | ||
754 | /* Remove this option from the argv array. */ | |
755 | for (arg = i; arg < argc; arg ++) | |
756 | argv[arg] = argv[arg + 1]; | |
757 | argc --; | |
758 | i --; | |
759 | } | |
760 | return argc; | |
761 | } | |
762 | ||
763 | static void | |
764 | sim_target_parse_arg_array (argv) | |
765 | char ** argv; | |
766 | { | |
767 | int i; | |
768 | ||
769 | for (i = 0; argv[i]; i++) | |
770 | ; | |
771 | ||
772 | sim_target_parse_command_line (i, argv); | |
773 | } | |
774 | ||
775 | void | |
776 | sim_target_display_usage (help) | |
777 | int help; | |
778 | { | |
779 | FILE *stream = help ? stdout : stderr; | |
780 | ||
781 | fprintf (stream, "%s=<list> Comma seperated list of SWI protocols to supoport.\n\ | |
782 | This list can contain: NONE, DEMON, ANGEL, REDBOOT and/or ALL.\n", | |
783 | SWI_SWITCH); | |
784 | } | |
785 | #endif | |
786 | ||
787 | SIM_DESC | |
788 | sim_open (kind, ptr, abfd, argv) | |
789 | SIM_OPEN_KIND kind; | |
790 | host_callback *ptr; | |
791 | struct bfd *abfd; | |
792 | char **argv; | |
793 | { | |
794 | sim_kind = kind; | |
795 | if (myname) free (myname); | |
796 | myname = (char *) xstrdup (argv[0]); | |
797 | sim_callback = ptr; | |
798 | ||
799 | #ifdef SIM_TARGET_SWITCHES | |
800 | sim_target_parse_arg_array (argv); | |
801 | #endif | |
802 | ||
803 | /* Decide upon the endian-ness of the processor. | |
804 | If we can, get the information from the bfd itself. | |
805 | Otherwise look to see if we have been given a command | |
806 | line switch that tells us. Otherwise default to little endian. */ | |
807 | if (abfd != NULL) | |
808 | big_endian = bfd_big_endian (abfd); | |
809 | else if (argv[1] != NULL) | |
810 | { | |
811 | int i; | |
812 | ||
813 | /* Scan for endian-ness and memory-size switches. */ | |
814 | for (i = 0; (argv[i] != NULL) && (argv[i][0] != 0); i++) | |
815 | if (argv[i][0] == '-' && argv[i][1] == 'E') | |
816 | { | |
817 | char c; | |
818 | ||
819 | if ((c = argv[i][2]) == 0) | |
820 | { | |
821 | ++i; | |
822 | c = argv[i][0]; | |
823 | } | |
824 | ||
825 | switch (c) | |
826 | { | |
827 | case 0: | |
828 | sim_callback->printf_filtered | |
829 | (sim_callback, "No argument to -E option provided\n"); | |
830 | break; | |
831 | ||
832 | case 'b': | |
833 | case 'B': | |
834 | big_endian = 1; | |
835 | break; | |
836 | ||
837 | case 'l': | |
838 | case 'L': | |
839 | big_endian = 0; | |
840 | break; | |
841 | ||
842 | default: | |
843 | sim_callback->printf_filtered | |
844 | (sim_callback, "Unrecognised argument to -E option\n"); | |
845 | break; | |
846 | } | |
847 | } | |
848 | else if (argv[i][0] == '-' && argv[i][1] == 'm') | |
849 | { | |
850 | if (argv[i][2] != '\0') | |
851 | sim_size (atoi (&argv[i][2])); | |
852 | else if (argv[i + 1] != NULL) | |
853 | { | |
854 | sim_size (atoi (argv[i + 1])); | |
855 | i++; | |
856 | } | |
857 | else | |
858 | { | |
859 | sim_callback->printf_filtered (sim_callback, | |
860 | "Missing argument to -m option\n"); | |
861 | return NULL; | |
862 | } | |
863 | ||
864 | } | |
865 | } | |
866 | ||
867 | return (SIM_DESC) 1; | |
868 | } | |
869 | ||
870 | void | |
871 | sim_close (sd, quitting) | |
872 | SIM_DESC sd ATTRIBUTE_UNUSED; | |
873 | int quitting ATTRIBUTE_UNUSED; | |
874 | { | |
875 | if (myname) | |
876 | free (myname); | |
877 | myname = NULL; | |
878 | } | |
879 | ||
880 | SIM_RC | |
881 | sim_load (sd, prog, abfd, from_tty) | |
882 | SIM_DESC sd; | |
883 | char *prog; | |
884 | bfd *abfd; | |
885 | int from_tty ATTRIBUTE_UNUSED; | |
886 | { | |
887 | bfd *prog_bfd; | |
888 | ||
889 | prog_bfd = sim_load_file (sd, myname, sim_callback, prog, abfd, | |
890 | sim_kind == SIM_OPEN_DEBUG, 0, sim_write); | |
891 | if (prog_bfd == NULL) | |
892 | return SIM_RC_FAIL; | |
893 | ARMul_SetPC (state, bfd_get_start_address (prog_bfd)); | |
894 | if (abfd == NULL) | |
895 | bfd_close (prog_bfd); | |
896 | return SIM_RC_OK; | |
897 | } | |
898 | ||
899 | void | |
900 | sim_stop_reason (sd, reason, sigrc) | |
901 | SIM_DESC sd ATTRIBUTE_UNUSED; | |
902 | enum sim_stop *reason; | |
903 | int *sigrc; | |
904 | { | |
905 | if (stop_simulator) | |
906 | { | |
907 | *reason = sim_stopped; | |
908 | *sigrc = GDB_SIGNAL_INT; | |
909 | } | |
910 | else if (state->EndCondition == 0) | |
911 | { | |
912 | *reason = sim_exited; | |
913 | *sigrc = state->Reg[0] & 255; | |
914 | } | |
915 | else | |
916 | { | |
917 | *reason = sim_stopped; | |
918 | if (state->EndCondition == RDIError_BreakpointReached) | |
919 | *sigrc = GDB_SIGNAL_TRAP; | |
920 | else if ( state->EndCondition == RDIError_DataAbort | |
921 | || state->EndCondition == RDIError_AddressException) | |
922 | *sigrc = GDB_SIGNAL_BUS; | |
923 | else | |
924 | *sigrc = 0; | |
925 | } | |
926 | } | |
927 | ||
928 | void | |
929 | sim_do_command (sd, cmd) | |
930 | SIM_DESC sd ATTRIBUTE_UNUSED; | |
931 | char *cmd ATTRIBUTE_UNUSED; | |
932 | { | |
933 | (*sim_callback->printf_filtered) | |
934 | (sim_callback, | |
935 | "This simulator does not accept any commands.\n"); | |
936 | } | |
937 | ||
938 | void | |
939 | sim_set_callbacks (ptr) | |
940 | host_callback *ptr; | |
941 | { | |
942 | sim_callback = ptr; | |
943 | } | |
944 | ||
945 | char ** | |
946 | sim_complete_command (SIM_DESC sd, char *text, char *word) | |
947 | { | |
948 | return NULL; | |
949 | } |