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1 | #include "config.h" | |
2 | ||
3 | #include <signal.h> | |
4 | #include <errno.h> | |
5 | #include <sys/types.h> | |
6 | #include <sys/stat.h> | |
7 | #ifdef HAVE_UNISTD_H | |
8 | #include <unistd.h> | |
9 | #endif | |
10 | ||
11 | #include "d10v_sim.h" | |
12 | #include "simops.h" | |
13 | #include "sys/syscall.h" | |
14 | ||
15 | extern char *strrchr (); | |
16 | ||
17 | enum op_types { | |
18 | OP_VOID, | |
19 | OP_REG, | |
20 | OP_REG_OUTPUT, | |
21 | OP_DREG, | |
22 | OP_DREG_OUTPUT, | |
23 | OP_ACCUM, | |
24 | OP_ACCUM_OUTPUT, | |
25 | OP_ACCUM_REVERSE, | |
26 | OP_CR, | |
27 | OP_CR_OUTPUT, | |
28 | OP_CR_REVERSE, | |
29 | OP_FLAG, | |
30 | OP_FLAG_OUTPUT, | |
31 | OP_CONSTANT16, | |
32 | OP_CONSTANT8, | |
33 | OP_CONSTANT3, | |
34 | OP_CONSTANT4, | |
35 | OP_MEMREF, | |
36 | OP_MEMREF2, | |
37 | OP_POSTDEC, | |
38 | OP_POSTINC, | |
39 | OP_PREDEC, | |
40 | OP_R0, | |
41 | OP_R1, | |
42 | OP_R2, | |
43 | OP_R0R1 | |
44 | }; | |
45 | ||
46 | ||
47 | void | |
48 | move_to_cr (int cr, reg_t val) | |
49 | { | |
50 | switch (cr) | |
51 | { | |
52 | case PSW_CR: | |
53 | State.SM = (val & PSW_SM_BIT) != 0; | |
54 | State.EA = (val & PSW_EA_BIT) != 0; | |
55 | State.DB = (val & PSW_DB_BIT) != 0; | |
56 | State.DM = (val & PSW_DM_BIT) != 0; | |
57 | State.IE = (val & PSW_IE_BIT) != 0; | |
58 | State.RP = (val & PSW_RP_BIT) != 0; | |
59 | State.MD = (val & PSW_MD_BIT) != 0; | |
60 | State.FX = (val & PSW_FX_BIT) != 0; | |
61 | State.ST = (val & PSW_ST_BIT) != 0; | |
62 | State.F0 = (val & PSW_F0_BIT) != 0; | |
63 | State.F1 = (val & PSW_F1_BIT) != 0; | |
64 | State.C = (val & PSW_C_BIT) != 0; | |
65 | if (State.ST && !State.FX) | |
66 | { | |
67 | (*d10v_callback->printf_filtered) | |
68 | (d10v_callback, | |
69 | "ERROR at PC 0x%x: ST can only be set when FX is set.\n", | |
70 | PC<<2); | |
71 | State.exception = SIGILL; | |
72 | } | |
73 | State.cregs[PSW_CR] = (val & ~0x4032); | |
74 | break; | |
75 | case BPSW_CR: | |
76 | State.cregs[BPSW_CR] = (val & ~0x4032); | |
77 | break; | |
78 | case MOD_S_CR: | |
79 | case MOD_E_CR: | |
80 | State.cregs[cr] = (val & ~0x1); | |
81 | break; | |
82 | default: | |
83 | State.cregs[cr] = val; | |
84 | break; | |
85 | } | |
86 | } | |
87 | ||
88 | reg_t | |
89 | move_from_cr (int cr) | |
90 | { | |
91 | reg_t val = 0; | |
92 | switch (cr) | |
93 | { | |
94 | case PSW_CR: | |
95 | if (State.SM) val |= PSW_SM_BIT; | |
96 | if (State.EA) val |= PSW_EA_BIT; | |
97 | if (State.DB) val |= PSW_DB_BIT; | |
98 | if (State.DM) val |= PSW_DM_BIT; | |
99 | if (State.IE) val |= PSW_IE_BIT; | |
100 | if (State.RP) val |= PSW_RP_BIT; | |
101 | if (State.MD) val |= PSW_MD_BIT; | |
102 | if (State.FX) val |= PSW_FX_BIT; | |
103 | if (State.ST) val |= PSW_ST_BIT; | |
104 | if (State.F0) val |= PSW_F0_BIT; | |
105 | if (State.F1) val |= PSW_F1_BIT; | |
106 | if (State.C) val |= PSW_C_BIT; | |
107 | break; | |
108 | default: | |
109 | val = State.cregs[cr]; | |
110 | break; | |
111 | } | |
112 | return val; | |
113 | } | |
114 | ||
115 | ||
116 | #ifdef DEBUG | |
117 | static void trace_input_func PARAMS ((char *name, | |
118 | enum op_types in1, | |
119 | enum op_types in2, | |
120 | enum op_types in3)); | |
121 | ||
122 | #define trace_input(name, in1, in2, in3) do { if (d10v_debug) trace_input_func (name, in1, in2, in3); } while (0) | |
123 | ||
124 | static void trace_output_func PARAMS ((enum op_types result)); | |
125 | ||
126 | #define trace_output(result) do { if (d10v_debug) trace_output_func (result); } while (0) | |
127 | ||
128 | #ifndef SIZE_INSTRUCTION | |
129 | #define SIZE_INSTRUCTION 8 | |
130 | #endif | |
131 | ||
132 | #ifndef SIZE_OPERANDS | |
133 | #define SIZE_OPERANDS 18 | |
134 | #endif | |
135 | ||
136 | #ifndef SIZE_VALUES | |
137 | #define SIZE_VALUES 13 | |
138 | #endif | |
139 | ||
140 | #ifndef SIZE_LOCATION | |
141 | #define SIZE_LOCATION 20 | |
142 | #endif | |
143 | ||
144 | #ifndef SIZE_PC | |
145 | #define SIZE_PC 6 | |
146 | #endif | |
147 | ||
148 | #ifndef SIZE_LINE_NUMBER | |
149 | #define SIZE_LINE_NUMBER 4 | |
150 | #endif | |
151 | ||
152 | static void | |
153 | trace_input_func (name, in1, in2, in3) | |
154 | char *name; | |
155 | enum op_types in1; | |
156 | enum op_types in2; | |
157 | enum op_types in3; | |
158 | { | |
159 | char *comma; | |
160 | enum op_types in[3]; | |
161 | int i; | |
162 | char buf[1024]; | |
163 | char *p; | |
164 | long tmp; | |
165 | char *type; | |
166 | const char *filename; | |
167 | const char *functionname; | |
168 | unsigned int linenumber; | |
169 | bfd_vma byte_pc; | |
170 | ||
171 | if ((d10v_debug & DEBUG_TRACE) == 0) | |
172 | return; | |
173 | ||
174 | switch (State.ins_type) | |
175 | { | |
176 | default: | |
177 | case INS_UNKNOWN: type = " ?"; break; | |
178 | case INS_LEFT: type = " L"; break; | |
179 | case INS_RIGHT: type = " R"; break; | |
180 | case INS_LEFT_PARALLEL: type = "*L"; break; | |
181 | case INS_RIGHT_PARALLEL: type = "*R"; break; | |
182 | case INS_LEFT_COND_TEST: type = "?L"; break; | |
183 | case INS_RIGHT_COND_TEST: type = "?R"; break; | |
184 | case INS_LEFT_COND_EXE: type = "&L"; break; | |
185 | case INS_RIGHT_COND_EXE: type = "&R"; break; | |
186 | case INS_LONG: type = " B"; break; | |
187 | } | |
188 | ||
189 | if ((d10v_debug & DEBUG_LINE_NUMBER) == 0) | |
190 | (*d10v_callback->printf_filtered) (d10v_callback, | |
191 | "0x%.*x %s: %-*s ", | |
192 | SIZE_PC, (unsigned)PC, | |
193 | type, | |
194 | SIZE_INSTRUCTION, name); | |
195 | ||
196 | else | |
197 | { | |
198 | buf[0] = '\0'; | |
199 | byte_pc = decode_pc (); | |
200 | if (text && byte_pc >= text_start && byte_pc < text_end) | |
201 | { | |
202 | filename = (const char *)0; | |
203 | functionname = (const char *)0; | |
204 | linenumber = 0; | |
205 | if (bfd_find_nearest_line (prog_bfd, text, (struct symbol_cache_entry **)0, byte_pc - text_start, | |
206 | &filename, &functionname, &linenumber)) | |
207 | { | |
208 | p = buf; | |
209 | if (linenumber) | |
210 | { | |
211 | sprintf (p, "#%-*d ", SIZE_LINE_NUMBER, linenumber); | |
212 | p += strlen (p); | |
213 | } | |
214 | else | |
215 | { | |
216 | sprintf (p, "%-*s ", SIZE_LINE_NUMBER+1, "---"); | |
217 | p += SIZE_LINE_NUMBER+2; | |
218 | } | |
219 | ||
220 | if (functionname) | |
221 | { | |
222 | sprintf (p, "%s ", functionname); | |
223 | p += strlen (p); | |
224 | } | |
225 | else if (filename) | |
226 | { | |
227 | char *q = strrchr (filename, '/'); | |
228 | sprintf (p, "%s ", (q) ? q+1 : filename); | |
229 | p += strlen (p); | |
230 | } | |
231 | ||
232 | if (*p == ' ') | |
233 | *p = '\0'; | |
234 | } | |
235 | } | |
236 | ||
237 | (*d10v_callback->printf_filtered) (d10v_callback, | |
238 | "0x%.*x %s: %-*.*s %-*s ", | |
239 | SIZE_PC, (unsigned)PC, | |
240 | type, | |
241 | SIZE_LOCATION, SIZE_LOCATION, buf, | |
242 | SIZE_INSTRUCTION, name); | |
243 | } | |
244 | ||
245 | in[0] = in1; | |
246 | in[1] = in2; | |
247 | in[2] = in3; | |
248 | comma = ""; | |
249 | p = buf; | |
250 | for (i = 0; i < 3; i++) | |
251 | { | |
252 | switch (in[i]) | |
253 | { | |
254 | case OP_VOID: | |
255 | case OP_R0: | |
256 | case OP_R1: | |
257 | case OP_R2: | |
258 | case OP_R0R1: | |
259 | break; | |
260 | ||
261 | case OP_REG: | |
262 | case OP_REG_OUTPUT: | |
263 | case OP_DREG: | |
264 | case OP_DREG_OUTPUT: | |
265 | sprintf (p, "%sr%d", comma, OP[i]); | |
266 | p += strlen (p); | |
267 | comma = ","; | |
268 | break; | |
269 | ||
270 | case OP_CR: | |
271 | case OP_CR_OUTPUT: | |
272 | case OP_CR_REVERSE: | |
273 | sprintf (p, "%scr%d", comma, OP[i]); | |
274 | p += strlen (p); | |
275 | comma = ","; | |
276 | break; | |
277 | ||
278 | case OP_ACCUM: | |
279 | case OP_ACCUM_OUTPUT: | |
280 | case OP_ACCUM_REVERSE: | |
281 | sprintf (p, "%sa%d", comma, OP[i]); | |
282 | p += strlen (p); | |
283 | comma = ","; | |
284 | break; | |
285 | ||
286 | case OP_CONSTANT16: | |
287 | sprintf (p, "%s%d", comma, OP[i]); | |
288 | p += strlen (p); | |
289 | comma = ","; | |
290 | break; | |
291 | ||
292 | case OP_CONSTANT8: | |
293 | sprintf (p, "%s%d", comma, SEXT8(OP[i])); | |
294 | p += strlen (p); | |
295 | comma = ","; | |
296 | break; | |
297 | ||
298 | case OP_CONSTANT4: | |
299 | sprintf (p, "%s%d", comma, SEXT4(OP[i])); | |
300 | p += strlen (p); | |
301 | comma = ","; | |
302 | break; | |
303 | ||
304 | case OP_CONSTANT3: | |
305 | sprintf (p, "%s%d", comma, SEXT3(OP[i])); | |
306 | p += strlen (p); | |
307 | comma = ","; | |
308 | break; | |
309 | ||
310 | case OP_MEMREF: | |
311 | sprintf (p, "%s@r%d", comma, OP[i]); | |
312 | p += strlen (p); | |
313 | comma = ","; | |
314 | break; | |
315 | ||
316 | case OP_MEMREF2: | |
317 | sprintf (p, "%s@(%d,r%d)", comma, (int16)OP[i], OP[i+1]); | |
318 | p += strlen (p); | |
319 | comma = ","; | |
320 | break; | |
321 | ||
322 | case OP_POSTINC: | |
323 | sprintf (p, "%s@r%d+", comma, OP[i]); | |
324 | p += strlen (p); | |
325 | comma = ","; | |
326 | break; | |
327 | ||
328 | case OP_POSTDEC: | |
329 | sprintf (p, "%s@r%d-", comma, OP[i]); | |
330 | p += strlen (p); | |
331 | comma = ","; | |
332 | break; | |
333 | ||
334 | case OP_PREDEC: | |
335 | sprintf (p, "%s@-r%d", comma, OP[i]); | |
336 | p += strlen (p); | |
337 | comma = ","; | |
338 | break; | |
339 | ||
340 | case OP_FLAG: | |
341 | case OP_FLAG_OUTPUT: | |
342 | if (OP[i] == 0) | |
343 | sprintf (p, "%sf0", comma); | |
344 | ||
345 | else if (OP[i] == 1) | |
346 | sprintf (p, "%sf1", comma); | |
347 | ||
348 | else | |
349 | sprintf (p, "%sc", comma); | |
350 | ||
351 | p += strlen (p); | |
352 | comma = ","; | |
353 | break; | |
354 | } | |
355 | } | |
356 | ||
357 | if ((d10v_debug & DEBUG_VALUES) == 0) | |
358 | { | |
359 | *p++ = '\n'; | |
360 | *p = '\0'; | |
361 | (*d10v_callback->printf_filtered) (d10v_callback, "%s", buf); | |
362 | } | |
363 | else | |
364 | { | |
365 | *p = '\0'; | |
366 | (*d10v_callback->printf_filtered) (d10v_callback, "%-*s", SIZE_OPERANDS, buf); | |
367 | ||
368 | p = buf; | |
369 | for (i = 0; i < 3; i++) | |
370 | { | |
371 | buf[0] = '\0'; | |
372 | switch (in[i]) | |
373 | { | |
374 | case OP_VOID: | |
375 | (*d10v_callback->printf_filtered) (d10v_callback, "%*s", SIZE_VALUES, ""); | |
376 | break; | |
377 | ||
378 | case OP_REG_OUTPUT: | |
379 | case OP_DREG_OUTPUT: | |
380 | case OP_CR_OUTPUT: | |
381 | case OP_ACCUM_OUTPUT: | |
382 | case OP_FLAG_OUTPUT: | |
383 | (*d10v_callback->printf_filtered) (d10v_callback, "%*s", SIZE_VALUES, "---"); | |
384 | break; | |
385 | ||
386 | case OP_REG: | |
387 | case OP_MEMREF: | |
388 | case OP_POSTDEC: | |
389 | case OP_POSTINC: | |
390 | case OP_PREDEC: | |
391 | (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "", | |
392 | (uint16)State.regs[OP[i]]); | |
393 | break; | |
394 | ||
395 | case OP_DREG: | |
396 | tmp = (long)((((uint32) State.regs[OP[i]]) << 16) | ((uint32) State.regs[OP[i]+1])); | |
397 | (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.8lx", SIZE_VALUES-10, "", tmp); | |
398 | break; | |
399 | ||
400 | case OP_CR: | |
401 | case OP_CR_REVERSE: | |
402 | (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "", | |
403 | (uint16)State.cregs[OP[i]]); | |
404 | break; | |
405 | ||
406 | case OP_ACCUM: | |
407 | case OP_ACCUM_REVERSE: | |
408 | (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.2x%.8lx", SIZE_VALUES-12, "", | |
409 | ((int)(State.a[OP[i]] >> 32) & 0xff), | |
410 | ((unsigned long)State.a[OP[i]]) & 0xffffffff); | |
411 | break; | |
412 | ||
413 | case OP_CONSTANT16: | |
414 | (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "", | |
415 | (uint16)OP[i]); | |
416 | break; | |
417 | ||
418 | case OP_CONSTANT4: | |
419 | (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "", | |
420 | (uint16)SEXT4(OP[i])); | |
421 | break; | |
422 | ||
423 | case OP_CONSTANT8: | |
424 | (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "", | |
425 | (uint16)SEXT8(OP[i])); | |
426 | break; | |
427 | ||
428 | case OP_CONSTANT3: | |
429 | (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "", | |
430 | (uint16)SEXT3(OP[i])); | |
431 | break; | |
432 | ||
433 | case OP_FLAG: | |
434 | if (OP[i] == 0) | |
435 | (*d10v_callback->printf_filtered) (d10v_callback, "%*sF0 = %d", SIZE_VALUES-6, "", | |
436 | State.F0 != 0); | |
437 | ||
438 | else if (OP[i] == 1) | |
439 | (*d10v_callback->printf_filtered) (d10v_callback, "%*sF1 = %d", SIZE_VALUES-6, "", | |
440 | State.F1 != 0); | |
441 | ||
442 | else | |
443 | (*d10v_callback->printf_filtered) (d10v_callback, "%*sC = %d", SIZE_VALUES-5, "", | |
444 | State.C != 0); | |
445 | ||
446 | break; | |
447 | ||
448 | case OP_MEMREF2: | |
449 | (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "", | |
450 | (uint16)OP[i]); | |
451 | (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "", | |
452 | (uint16)State.regs[OP[++i]]); | |
453 | break; | |
454 | ||
455 | case OP_R0: | |
456 | (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "", | |
457 | (uint16)State.regs[0]); | |
458 | break; | |
459 | ||
460 | case OP_R1: | |
461 | (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "", | |
462 | (uint16)State.regs[1]); | |
463 | break; | |
464 | ||
465 | case OP_R2: | |
466 | (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "", | |
467 | (uint16)State.regs[2]); | |
468 | break; | |
469 | ||
470 | case OP_R0R1: | |
471 | (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "", | |
472 | (uint16)State.regs[0]); | |
473 | (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "", | |
474 | (uint16)State.regs[1]); | |
475 | i++; | |
476 | break; | |
477 | } | |
478 | } | |
479 | } | |
480 | ||
481 | (*d10v_callback->flush_stdout) (d10v_callback); | |
482 | } | |
483 | ||
484 | static void | |
485 | trace_output_func (result) | |
486 | enum op_types result; | |
487 | { | |
488 | if ((d10v_debug & (DEBUG_TRACE | DEBUG_VALUES)) == (DEBUG_TRACE | DEBUG_VALUES)) | |
489 | { | |
490 | long tmp; | |
491 | ||
492 | switch (result) | |
493 | { | |
494 | default: | |
495 | putchar ('\n'); | |
496 | break; | |
497 | ||
498 | case OP_REG: | |
499 | case OP_REG_OUTPUT: | |
500 | (*d10v_callback->printf_filtered) (d10v_callback, " :: %*s0x%.4x F0=%d F1=%d C=%d\n", SIZE_VALUES-6, "", | |
501 | (uint16)State.regs[OP[0]], | |
502 | State.F0 != 0, State.F1 != 0, State.C != 0); | |
503 | break; | |
504 | ||
505 | case OP_DREG: | |
506 | case OP_DREG_OUTPUT: | |
507 | tmp = (long)((((uint32) State.regs[OP[0]]) << 16) | ((uint32) State.regs[OP[0]+1])); | |
508 | (*d10v_callback->printf_filtered) (d10v_callback, " :: %*s0x%.8lx F0=%d F1=%d C=%d\n", SIZE_VALUES-10, "", tmp, | |
509 | State.F0 != 0, State.F1 != 0, State.C != 0); | |
510 | break; | |
511 | ||
512 | case OP_CR: | |
513 | case OP_CR_OUTPUT: | |
514 | (*d10v_callback->printf_filtered) (d10v_callback, " :: %*s0x%.4x F0=%d F1=%d C=%d\n", SIZE_VALUES-6, "", | |
515 | (uint16)State.cregs[OP[0]], | |
516 | State.F0 != 0, State.F1 != 0, State.C != 0); | |
517 | break; | |
518 | ||
519 | case OP_CR_REVERSE: | |
520 | (*d10v_callback->printf_filtered) (d10v_callback, " :: %*s0x%.4x F0=%d F1=%d C=%d\n", SIZE_VALUES-6, "", | |
521 | (uint16)State.cregs[OP[1]], | |
522 | State.F0 != 0, State.F1 != 0, State.C != 0); | |
523 | break; | |
524 | ||
525 | case OP_ACCUM: | |
526 | case OP_ACCUM_OUTPUT: | |
527 | (*d10v_callback->printf_filtered) (d10v_callback, " :: %*s0x%.2x%.8lx F0=%d F1=%d C=%d\n", SIZE_VALUES-12, "", | |
528 | ((int)(State.a[OP[0]] >> 32) & 0xff), | |
529 | ((unsigned long)State.a[OP[0]]) & 0xffffffff, | |
530 | State.F0 != 0, State.F1 != 0, State.C != 0); | |
531 | break; | |
532 | ||
533 | case OP_ACCUM_REVERSE: | |
534 | (*d10v_callback->printf_filtered) (d10v_callback, " :: %*s0x%.2x%.8lx F0=%d F1=%d C=%d\n", SIZE_VALUES-12, "", | |
535 | ((int)(State.a[OP[1]] >> 32) & 0xff), | |
536 | ((unsigned long)State.a[OP[1]]) & 0xffffffff, | |
537 | State.F0 != 0, State.F1 != 0, State.C != 0); | |
538 | break; | |
539 | ||
540 | case OP_FLAG: | |
541 | case OP_FLAG_OUTPUT: | |
542 | (*d10v_callback->printf_filtered) (d10v_callback, " :: %*s F0=%d F1=%d C=%d\n", SIZE_VALUES, "", | |
543 | State.F0 != 0, State.F1 != 0, State.C != 0); | |
544 | break; | |
545 | ||
546 | case OP_R0: | |
547 | (*d10v_callback->printf_filtered) (d10v_callback, " :: %*s0x%.4x F0=%d F1=%d C=%d\n", SIZE_VALUES-6, "", | |
548 | (uint16)State.regs[0], | |
549 | State.F0 != 0, State.F1 != 0, State.C != 0); | |
550 | break; | |
551 | ||
552 | case OP_R0R1: | |
553 | (*d10v_callback->printf_filtered) (d10v_callback, " :: %*s0x%.4x%.4x F0=%d F1=%d C=%d\n", SIZE_VALUES-10, "", | |
554 | (uint16)State.regs[0], (uint16)State.regs[1], | |
555 | State.F0 != 0, State.F1 != 0, State.C != 0); | |
556 | break; | |
557 | } | |
558 | } | |
559 | ||
560 | (*d10v_callback->flush_stdout) (d10v_callback); | |
561 | } | |
562 | ||
563 | #else | |
564 | #define trace_input(NAME, IN1, IN2, IN3) | |
565 | #define trace_output(RESULT) | |
566 | #endif | |
567 | ||
568 | /* abs */ | |
569 | void | |
570 | OP_4607 () | |
571 | { | |
572 | trace_input ("abs", OP_REG, OP_VOID, OP_VOID); | |
573 | State.F1 = State.F0; | |
574 | if ((int16)(State.regs[OP[0]]) < 0) | |
575 | { | |
576 | State.regs[OP[0]] = -(int16)(State.regs[OP[0]]); | |
577 | State.F0 = 1; | |
578 | } | |
579 | else | |
580 | State.F0 = 0; | |
581 | trace_output (OP_REG); | |
582 | } | |
583 | ||
584 | /* abs */ | |
585 | void | |
586 | OP_5607 () | |
587 | { | |
588 | int64 tmp; | |
589 | ||
590 | trace_input ("abs", OP_ACCUM, OP_VOID, OP_VOID); | |
591 | State.F1 = State.F0; | |
592 | State.a[OP[0]] = SEXT40(State.a[OP[0]]); | |
593 | ||
594 | if (State.a[OP[0]] < 0 ) | |
595 | { | |
596 | tmp = -State.a[OP[0]]; | |
597 | if (State.ST) | |
598 | { | |
599 | if (tmp > MAX32) | |
600 | State.a[OP[0]] = MAX32; | |
601 | else if (tmp < MIN32) | |
602 | State.a[OP[0]] = MIN32; | |
603 | else | |
604 | State.a[OP[0]] = tmp & MASK40; | |
605 | } | |
606 | else | |
607 | State.a[OP[0]] = tmp & MASK40; | |
608 | State.F0 = 1; | |
609 | } | |
610 | else | |
611 | State.F0 = 0; | |
612 | trace_output (OP_ACCUM); | |
613 | } | |
614 | ||
615 | /* add */ | |
616 | void | |
617 | OP_200 () | |
618 | { | |
619 | uint16 tmp = State.regs[OP[0]]; | |
620 | trace_input ("add", OP_REG, OP_REG, OP_VOID); | |
621 | State.regs[OP[0]] += State.regs[OP[1]]; | |
622 | if ( tmp > State.regs[OP[0]]) | |
623 | State.C = 1; | |
624 | else | |
625 | State.C = 0; | |
626 | trace_output (OP_REG); | |
627 | } | |
628 | ||
629 | /* add */ | |
630 | void | |
631 | OP_1201 () | |
632 | { | |
633 | int64 tmp; | |
634 | tmp = SEXT40(State.a[OP[0]]) + (SEXT16 (State.regs[OP[1]]) << 16 | State.regs[OP[1]+1]); | |
635 | ||
636 | trace_input ("add", OP_ACCUM, OP_REG, OP_VOID); | |
637 | if (State.ST) | |
638 | { | |
639 | if ( tmp > MAX32) | |
640 | State.a[OP[0]] = MAX32; | |
641 | else if ( tmp < MIN32) | |
642 | State.a[OP[0]] = MIN32; | |
643 | else | |
644 | State.a[OP[0]] = tmp & MASK40; | |
645 | } | |
646 | else | |
647 | State.a[OP[0]] = tmp & MASK40; | |
648 | trace_output (OP_ACCUM); | |
649 | } | |
650 | ||
651 | /* add */ | |
652 | void | |
653 | OP_1203 () | |
654 | { | |
655 | int64 tmp; | |
656 | tmp = SEXT40(State.a[OP[0]]) + SEXT40(State.a[OP[1]]); | |
657 | ||
658 | trace_input ("add", OP_ACCUM, OP_ACCUM, OP_VOID); | |
659 | if (State.ST) | |
660 | { | |
661 | if (tmp > MAX32) | |
662 | State.a[OP[0]] = MAX32; | |
663 | else if ( tmp < MIN32) | |
664 | State.a[OP[0]] = MIN32; | |
665 | else | |
666 | State.a[OP[0]] = tmp & MASK40; | |
667 | } | |
668 | else | |
669 | State.a[OP[0]] = tmp & MASK40; | |
670 | trace_output (OP_ACCUM); | |
671 | } | |
672 | ||
673 | /* add2w */ | |
674 | void | |
675 | OP_1200 () | |
676 | { | |
677 | uint32 tmp; | |
678 | uint32 a = (State.regs[OP[0]]) << 16 | State.regs[OP[0]+1]; | |
679 | uint32 b = (State.regs[OP[1]]) << 16 | State.regs[OP[1]+1]; | |
680 | ||
681 | trace_input ("add2w", OP_DREG, OP_DREG, OP_VOID); | |
682 | tmp = a + b; | |
683 | State.C = (tmp < a); | |
684 | State.regs[OP[0]] = tmp >> 16; | |
685 | State.regs[OP[0]+1] = tmp & 0xFFFF; | |
686 | trace_output (OP_DREG); | |
687 | } | |
688 | ||
689 | /* add3 */ | |
690 | void | |
691 | OP_1000000 () | |
692 | { | |
693 | uint16 tmp = State.regs[OP[1]]; | |
694 | State.regs[OP[0]] = tmp + OP[2]; | |
695 | ||
696 | trace_input ("add3", OP_REG_OUTPUT, OP_REG, OP_CONSTANT16); | |
697 | State.C = (State.regs[OP[0]] < tmp); | |
698 | trace_output (OP_REG); | |
699 | } | |
700 | ||
701 | /* addac3 */ | |
702 | void | |
703 | OP_17000200 () | |
704 | { | |
705 | int64 tmp; | |
706 | tmp = SEXT40(State.a[OP[2]]) + SEXT40 ((State.regs[OP[1]] << 16) | State.regs[OP[1]+1]); | |
707 | ||
708 | trace_input ("addac3", OP_DREG_OUTPUT, OP_DREG, OP_ACCUM); | |
709 | State.regs[OP[0]] = (tmp >> 16) & 0xffff; | |
710 | State.regs[OP[0]+1] = tmp & 0xffff; | |
711 | trace_output (OP_DREG); | |
712 | } | |
713 | ||
714 | /* addac3 */ | |
715 | void | |
716 | OP_17000202 () | |
717 | { | |
718 | int64 tmp; | |
719 | tmp = SEXT40(State.a[OP[1]]) + SEXT40(State.a[OP[2]]); | |
720 | ||
721 | trace_input ("addac3", OP_DREG_OUTPUT, OP_ACCUM, OP_ACCUM); | |
722 | State.regs[OP[0]] = (tmp >> 16) & 0xffff; | |
723 | State.regs[OP[0]+1] = tmp & 0xffff; | |
724 | trace_output (OP_DREG); | |
725 | } | |
726 | ||
727 | /* addac3s */ | |
728 | void | |
729 | OP_17001200 () | |
730 | { | |
731 | int64 tmp; | |
732 | State.F1 = State.F0; | |
733 | ||
734 | trace_input ("addac3s", OP_DREG_OUTPUT, OP_DREG, OP_ACCUM); | |
735 | tmp = SEXT40(State.a[OP[2]]) + SEXT40 ((State.regs[OP[1]] << 16) | State.regs[OP[1]+1]); | |
736 | if ( tmp > MAX32) | |
737 | { | |
738 | State.regs[OP[0]] = 0x7fff; | |
739 | State.regs[OP[0]+1] = 0xffff; | |
740 | State.F0 = 1; | |
741 | } | |
742 | else if (tmp < MIN32) | |
743 | { | |
744 | State.regs[OP[0]] = 0x8000; | |
745 | State.regs[OP[0]+1] = 0; | |
746 | State.F0 = 1; | |
747 | } | |
748 | else | |
749 | { | |
750 | State.regs[OP[0]] = (tmp >> 16) & 0xffff; | |
751 | State.regs[OP[0]+1] = tmp & 0xffff; | |
752 | State.F0 = 0; | |
753 | } | |
754 | trace_output (OP_DREG); | |
755 | } | |
756 | ||
757 | /* addac3s */ | |
758 | void | |
759 | OP_17001202 () | |
760 | { | |
761 | int64 tmp; | |
762 | State.F1 = State.F0; | |
763 | ||
764 | trace_input ("addac3s", OP_DREG_OUTPUT, OP_ACCUM, OP_ACCUM); | |
765 | tmp = SEXT40(State.a[OP[1]]) + SEXT40(State.a[OP[2]]); | |
766 | if ( tmp > MAX32) | |
767 | { | |
768 | State.regs[OP[0]] = 0x7fff; | |
769 | State.regs[OP[0]+1] = 0xffff; | |
770 | State.F0 = 1; | |
771 | } | |
772 | else if (tmp < MIN32) | |
773 | { | |
774 | State.regs[OP[0]] = 0x8000; | |
775 | State.regs[OP[0]+1] = 0; | |
776 | State.F0 = 1; | |
777 | } | |
778 | else | |
779 | { | |
780 | State.regs[OP[0]] = (tmp >> 16) & 0xffff; | |
781 | State.regs[OP[0]+1] = tmp & 0xffff; | |
782 | State.F0 = 0; | |
783 | } | |
784 | trace_output (OP_DREG); | |
785 | } | |
786 | ||
787 | /* addi */ | |
788 | void | |
789 | OP_201 () | |
790 | { | |
791 | uint tmp = State.regs[OP[0]]; | |
792 | if (OP[1] == 0) | |
793 | OP[1] = 16; | |
794 | ||
795 | trace_input ("addi", OP_REG, OP_CONSTANT16, OP_VOID); | |
796 | State.regs[OP[0]] += OP[1]; | |
797 | State.C = (State.regs[OP[0]] < tmp); | |
798 | trace_output (OP_REG); | |
799 | } | |
800 | ||
801 | /* and */ | |
802 | void | |
803 | OP_C00 () | |
804 | { | |
805 | trace_input ("and", OP_REG, OP_REG, OP_VOID); | |
806 | State.regs[OP[0]] &= State.regs[OP[1]]; | |
807 | trace_output (OP_REG); | |
808 | } | |
809 | ||
810 | /* and3 */ | |
811 | void | |
812 | OP_6000000 () | |
813 | { | |
814 | trace_input ("and3", OP_REG_OUTPUT, OP_REG, OP_CONSTANT16); | |
815 | State.regs[OP[0]] = State.regs[OP[1]] & OP[2]; | |
816 | trace_output (OP_REG); | |
817 | } | |
818 | ||
819 | /* bclri */ | |
820 | void | |
821 | OP_C01 () | |
822 | { | |
823 | trace_input ("bclri", OP_REG, OP_CONSTANT16, OP_VOID); | |
824 | State.regs[OP[0]] &= ~(0x8000 >> OP[1]); | |
825 | trace_output (OP_REG); | |
826 | } | |
827 | ||
828 | /* bl.s */ | |
829 | void | |
830 | OP_4900 () | |
831 | { | |
832 | trace_input ("bl.s", OP_CONSTANT8, OP_R0, OP_R1); | |
833 | State.regs[13] = PC+1; | |
834 | JMP( PC + SEXT8 (OP[0])); | |
835 | trace_output (OP_VOID); | |
836 | } | |
837 | ||
838 | /* bl.l */ | |
839 | void | |
840 | OP_24800000 () | |
841 | { | |
842 | trace_input ("bl.l", OP_CONSTANT16, OP_R0, OP_R1); | |
843 | State.regs[13] = PC+1; | |
844 | JMP (PC + OP[0]); | |
845 | trace_output (OP_VOID); | |
846 | } | |
847 | ||
848 | /* bnoti */ | |
849 | void | |
850 | OP_A01 () | |
851 | { | |
852 | trace_input ("bnoti", OP_REG, OP_CONSTANT16, OP_VOID); | |
853 | State.regs[OP[0]] ^= 0x8000 >> OP[1]; | |
854 | trace_output (OP_REG); | |
855 | } | |
856 | ||
857 | /* bra.s */ | |
858 | void | |
859 | OP_4800 () | |
860 | { | |
861 | trace_input ("bra.s", OP_CONSTANT8, OP_VOID, OP_VOID); | |
862 | JMP (PC + SEXT8 (OP[0])); | |
863 | trace_output (OP_VOID); | |
864 | } | |
865 | ||
866 | /* bra.l */ | |
867 | void | |
868 | OP_24000000 () | |
869 | { | |
870 | trace_input ("bra.l", OP_CONSTANT16, OP_VOID, OP_VOID); | |
871 | JMP (PC + OP[0]); | |
872 | trace_output (OP_VOID); | |
873 | } | |
874 | ||
875 | /* brf0f.s */ | |
876 | void | |
877 | OP_4A00 () | |
878 | { | |
879 | trace_input ("brf0f.s", OP_CONSTANT8, OP_VOID, OP_VOID); | |
880 | if (State.F0 == 0) | |
881 | JMP (PC + SEXT8 (OP[0])); | |
882 | trace_output (OP_FLAG); | |
883 | } | |
884 | ||
885 | /* brf0f.l */ | |
886 | void | |
887 | OP_25000000 () | |
888 | { | |
889 | trace_input ("brf0f.l", OP_CONSTANT16, OP_VOID, OP_VOID); | |
890 | if (State.F0 == 0) | |
891 | JMP (PC + OP[0]); | |
892 | trace_output (OP_FLAG); | |
893 | } | |
894 | ||
895 | /* brf0t.s */ | |
896 | void | |
897 | OP_4B00 () | |
898 | { | |
899 | trace_input ("brf0t.s", OP_CONSTANT8, OP_VOID, OP_VOID); | |
900 | if (State.F0) | |
901 | JMP (PC + SEXT8 (OP[0])); | |
902 | trace_output (OP_FLAG); | |
903 | } | |
904 | ||
905 | /* brf0t.l */ | |
906 | void | |
907 | OP_25800000 () | |
908 | { | |
909 | trace_input ("brf0t.l", OP_CONSTANT16, OP_VOID, OP_VOID); | |
910 | if (State.F0) | |
911 | JMP (PC + OP[0]); | |
912 | trace_output (OP_FLAG); | |
913 | } | |
914 | ||
915 | /* bseti */ | |
916 | void | |
917 | OP_801 () | |
918 | { | |
919 | trace_input ("bseti", OP_REG, OP_CONSTANT16, OP_VOID); | |
920 | State.regs[OP[0]] |= 0x8000 >> OP[1]; | |
921 | trace_output (OP_REG); | |
922 | } | |
923 | ||
924 | /* btsti */ | |
925 | void | |
926 | OP_E01 () | |
927 | { | |
928 | trace_input ("btsti", OP_REG, OP_CONSTANT16, OP_VOID); | |
929 | State.F1 = State.F0; | |
930 | State.F0 = (State.regs[OP[0]] & (0x8000 >> OP[1])) ? 1 : 0; | |
931 | trace_output (OP_FLAG); | |
932 | } | |
933 | ||
934 | /* clrac */ | |
935 | void | |
936 | OP_5601 () | |
937 | { | |
938 | trace_input ("clrac", OP_ACCUM_OUTPUT, OP_VOID, OP_VOID); | |
939 | State.a[OP[0]] = 0; | |
940 | trace_output (OP_ACCUM); | |
941 | } | |
942 | ||
943 | /* cmp */ | |
944 | void | |
945 | OP_600 () | |
946 | { | |
947 | trace_input ("cmp", OP_REG, OP_REG, OP_VOID); | |
948 | State.F1 = State.F0; | |
949 | State.F0 = ((int16)(State.regs[OP[0]]) < (int16)(State.regs[OP[1]])) ? 1 : 0; | |
950 | trace_output (OP_FLAG); | |
951 | } | |
952 | ||
953 | /* cmp */ | |
954 | void | |
955 | OP_1603 () | |
956 | { | |
957 | trace_input ("cmp", OP_ACCUM, OP_ACCUM, OP_VOID); | |
958 | State.F1 = State.F0; | |
959 | State.F0 = (SEXT40(State.a[OP[0]]) < SEXT40(State.a[OP[1]])) ? 1 : 0; | |
960 | trace_output (OP_FLAG); | |
961 | } | |
962 | ||
963 | /* cmpeq */ | |
964 | void | |
965 | OP_400 () | |
966 | { | |
967 | trace_input ("cmpeq", OP_REG, OP_REG, OP_VOID); | |
968 | State.F1 = State.F0; | |
969 | State.F0 = (State.regs[OP[0]] == State.regs[OP[1]]) ? 1 : 0; | |
970 | trace_output (OP_FLAG); | |
971 | } | |
972 | ||
973 | /* cmpeq */ | |
974 | void | |
975 | OP_1403 () | |
976 | { | |
977 | trace_input ("cmpeq", OP_ACCUM, OP_ACCUM, OP_VOID); | |
978 | State.F1 = State.F0; | |
979 | State.F0 = ((State.a[OP[0]] & MASK40) == (State.a[OP[1]] & MASK40)) ? 1 : 0; | |
980 | trace_output (OP_FLAG); | |
981 | } | |
982 | ||
983 | /* cmpeqi.s */ | |
984 | void | |
985 | OP_401 () | |
986 | { | |
987 | trace_input ("cmpeqi.s", OP_REG, OP_CONSTANT4, OP_VOID); | |
988 | State.F1 = State.F0; | |
989 | State.F0 = (State.regs[OP[0]] == (reg_t)SEXT4(OP[1])) ? 1 : 0; | |
990 | trace_output (OP_FLAG); | |
991 | } | |
992 | ||
993 | /* cmpeqi.l */ | |
994 | void | |
995 | OP_2000000 () | |
996 | { | |
997 | trace_input ("cmpeqi.l", OP_REG, OP_CONSTANT16, OP_VOID); | |
998 | State.F1 = State.F0; | |
999 | State.F0 = (State.regs[OP[0]] == (reg_t)OP[1]) ? 1 : 0; | |
1000 | trace_output (OP_FLAG); | |
1001 | } | |
1002 | ||
1003 | /* cmpi.s */ | |
1004 | void | |
1005 | OP_601 () | |
1006 | { | |
1007 | trace_input ("cmpi.s", OP_REG, OP_CONSTANT4, OP_VOID); | |
1008 | State.F1 = State.F0; | |
1009 | State.F0 = ((int16)(State.regs[OP[0]]) < (int16)SEXT4(OP[1])) ? 1 : 0; | |
1010 | trace_output (OP_FLAG); | |
1011 | } | |
1012 | ||
1013 | /* cmpi.l */ | |
1014 | void | |
1015 | OP_3000000 () | |
1016 | { | |
1017 | trace_input ("cmpi.l", OP_REG, OP_CONSTANT16, OP_VOID); | |
1018 | State.F1 = State.F0; | |
1019 | State.F0 = ((int16)(State.regs[OP[0]]) < (int16)(OP[1])) ? 1 : 0; | |
1020 | trace_output (OP_FLAG); | |
1021 | } | |
1022 | ||
1023 | /* cmpu */ | |
1024 | void | |
1025 | OP_4600 () | |
1026 | { | |
1027 | trace_input ("cmpu", OP_REG, OP_REG, OP_VOID); | |
1028 | State.F1 = State.F0; | |
1029 | State.F0 = (State.regs[OP[0]] < State.regs[OP[1]]) ? 1 : 0; | |
1030 | trace_output (OP_FLAG); | |
1031 | } | |
1032 | ||
1033 | /* cmpui */ | |
1034 | void | |
1035 | OP_23000000 () | |
1036 | { | |
1037 | trace_input ("cmpui", OP_REG, OP_CONSTANT16, OP_VOID); | |
1038 | State.F1 = State.F0; | |
1039 | State.F0 = (State.regs[OP[0]] < (reg_t)OP[1]) ? 1 : 0; | |
1040 | trace_output (OP_FLAG); | |
1041 | } | |
1042 | ||
1043 | /* cpfg */ | |
1044 | void | |
1045 | OP_4E09 () | |
1046 | { | |
1047 | uint8 *src, *dst; | |
1048 | ||
1049 | trace_input ("cpfg", OP_FLAG_OUTPUT, OP_FLAG, OP_VOID); | |
1050 | if (OP[0] == 0) | |
1051 | dst = &State.F0; | |
1052 | else | |
1053 | dst = &State.F1; | |
1054 | ||
1055 | if (OP[1] == 0) | |
1056 | src = &State.F0; | |
1057 | else if (OP[1] == 1) | |
1058 | src = &State.F1; | |
1059 | else | |
1060 | src = &State.C; | |
1061 | ||
1062 | *dst = *src; | |
1063 | trace_output (OP_FLAG); | |
1064 | } | |
1065 | ||
1066 | /* dbt */ | |
1067 | void | |
1068 | OP_5F20 () | |
1069 | { | |
1070 | /* d10v_callback->printf_filtered(d10v_callback, "***** DBT ***** PC=%x\n",PC); */ | |
1071 | State.exception = SIGTRAP; | |
1072 | } | |
1073 | ||
1074 | /* divs */ | |
1075 | void | |
1076 | OP_14002800 () | |
1077 | { | |
1078 | uint16 foo, tmp, tmpf; | |
1079 | ||
1080 | trace_input ("divs", OP_DREG, OP_REG, OP_VOID); | |
1081 | foo = (State.regs[OP[0]] << 1) | (State.regs[OP[0]+1] >> 15); | |
1082 | tmp = (int16)foo - (int16)(State.regs[OP[1]]); | |
1083 | tmpf = (foo >= State.regs[OP[1]]) ? 1 : 0; | |
1084 | State.regs[OP[0]] = (tmpf == 1) ? tmp : foo; | |
1085 | State.regs[OP[0]+1] = (State.regs[OP[0]+1] << 1) | tmpf; | |
1086 | trace_output (OP_DREG); | |
1087 | } | |
1088 | ||
1089 | /* exef0f */ | |
1090 | void | |
1091 | OP_4E04 () | |
1092 | { | |
1093 | trace_input ("exef0f", OP_VOID, OP_VOID, OP_VOID); | |
1094 | State.exe = (State.F0 == 0); | |
1095 | trace_output (OP_FLAG); | |
1096 | } | |
1097 | ||
1098 | /* exef0t */ | |
1099 | void | |
1100 | OP_4E24 () | |
1101 | { | |
1102 | trace_input ("exef0t", OP_VOID, OP_VOID, OP_VOID); | |
1103 | State.exe = (State.F0 != 0); | |
1104 | trace_output (OP_FLAG); | |
1105 | } | |
1106 | ||
1107 | /* exef1f */ | |
1108 | void | |
1109 | OP_4E40 () | |
1110 | { | |
1111 | trace_input ("exef1f", OP_VOID, OP_VOID, OP_VOID); | |
1112 | State.exe = (State.F1 == 0); | |
1113 | trace_output (OP_FLAG); | |
1114 | } | |
1115 | ||
1116 | /* exef1t */ | |
1117 | void | |
1118 | OP_4E42 () | |
1119 | { | |
1120 | trace_input ("exef1t", OP_VOID, OP_VOID, OP_VOID); | |
1121 | State.exe = (State.F1 != 0); | |
1122 | trace_output (OP_FLAG); | |
1123 | } | |
1124 | ||
1125 | /* exefaf */ | |
1126 | void | |
1127 | OP_4E00 () | |
1128 | { | |
1129 | trace_input ("exefaf", OP_VOID, OP_VOID, OP_VOID); | |
1130 | State.exe = (State.F0 == 0) & (State.F1 == 0); | |
1131 | trace_output (OP_FLAG); | |
1132 | } | |
1133 | ||
1134 | /* exefat */ | |
1135 | void | |
1136 | OP_4E02 () | |
1137 | { | |
1138 | trace_input ("exefat", OP_VOID, OP_VOID, OP_VOID); | |
1139 | State.exe = (State.F0 == 0) & (State.F1 != 0); | |
1140 | trace_output (OP_FLAG); | |
1141 | } | |
1142 | ||
1143 | /* exetaf */ | |
1144 | void | |
1145 | OP_4E20 () | |
1146 | { | |
1147 | trace_input ("exetaf", OP_VOID, OP_VOID, OP_VOID); | |
1148 | State.exe = (State.F0 != 0) & (State.F1 == 0); | |
1149 | trace_output (OP_FLAG); | |
1150 | } | |
1151 | ||
1152 | /* exetat */ | |
1153 | void | |
1154 | OP_4E22 () | |
1155 | { | |
1156 | trace_input ("exetat", OP_VOID, OP_VOID, OP_VOID); | |
1157 | State.exe = (State.F0 != 0) & (State.F1 != 0); | |
1158 | trace_output (OP_FLAG); | |
1159 | } | |
1160 | ||
1161 | /* exp */ | |
1162 | void | |
1163 | OP_15002A00 () | |
1164 | { | |
1165 | uint32 tmp, foo; | |
1166 | int i; | |
1167 | ||
1168 | trace_input ("exp", OP_REG_OUTPUT, OP_DREG, OP_VOID); | |
1169 | if (((int16)State.regs[OP[1]]) >= 0) | |
1170 | tmp = (State.regs[OP[1]] << 16) | State.regs[OP[1]+1]; | |
1171 | else | |
1172 | tmp = ~((State.regs[OP[1]] << 16) | State.regs[OP[1]+1]); | |
1173 | ||
1174 | foo = 0x40000000; | |
1175 | for (i=1;i<17;i++) | |
1176 | { | |
1177 | if (tmp & foo) | |
1178 | { | |
1179 | State.regs[OP[0]] = i-1; | |
1180 | trace_output (OP_REG); | |
1181 | return; | |
1182 | } | |
1183 | foo >>= 1; | |
1184 | } | |
1185 | State.regs[OP[0]] = 16; | |
1186 | trace_output (OP_REG); | |
1187 | } | |
1188 | ||
1189 | /* exp */ | |
1190 | void | |
1191 | OP_15002A02 () | |
1192 | { | |
1193 | int64 tmp, foo; | |
1194 | int i; | |
1195 | ||
1196 | trace_input ("exp", OP_REG_OUTPUT, OP_ACCUM, OP_VOID); | |
1197 | tmp = SEXT40(State.a[OP[1]]); | |
1198 | if (tmp < 0) | |
1199 | tmp = ~tmp & MASK40; | |
1200 | ||
1201 | foo = 0x4000000000LL; | |
1202 | for (i=1;i<25;i++) | |
1203 | { | |
1204 | if (tmp & foo) | |
1205 | { | |
1206 | State.regs[OP[0]] = i-9; | |
1207 | trace_output (OP_REG); | |
1208 | return; | |
1209 | } | |
1210 | foo >>= 1; | |
1211 | } | |
1212 | State.regs[OP[0]] = 16; | |
1213 | trace_output (OP_REG); | |
1214 | } | |
1215 | ||
1216 | /* jl */ | |
1217 | void | |
1218 | OP_4D00 () | |
1219 | { | |
1220 | trace_input ("jl", OP_REG, OP_R0, OP_R1); | |
1221 | State.regs[13] = PC+1; | |
1222 | JMP (State.regs[OP[0]]); | |
1223 | trace_output (OP_VOID); | |
1224 | } | |
1225 | ||
1226 | /* jmp */ | |
1227 | void | |
1228 | OP_4C00 () | |
1229 | { | |
1230 | trace_input ("jmp", OP_REG, | |
1231 | (OP[0] == 13) ? OP_R0 : OP_VOID, | |
1232 | (OP[0] == 13) ? OP_R1 : OP_VOID); | |
1233 | ||
1234 | JMP (State.regs[OP[0]]); | |
1235 | trace_output (OP_VOID); | |
1236 | } | |
1237 | ||
1238 | /* ld */ | |
1239 | void | |
1240 | OP_30000000 () | |
1241 | { | |
1242 | trace_input ("ld", OP_REG_OUTPUT, OP_MEMREF2, OP_VOID); | |
1243 | State.regs[OP[0]] = RW (OP[1] + State.regs[OP[2]]); | |
1244 | trace_output (OP_REG); | |
1245 | } | |
1246 | ||
1247 | /* ld */ | |
1248 | void | |
1249 | OP_6401 () | |
1250 | { | |
1251 | trace_input ("ld", OP_REG_OUTPUT, OP_POSTDEC, OP_VOID); | |
1252 | State.regs[OP[0]] = RW (State.regs[OP[1]]); | |
1253 | INC_ADDR(State.regs[OP[1]],-2); | |
1254 | trace_output (OP_REG); | |
1255 | } | |
1256 | ||
1257 | /* ld */ | |
1258 | void | |
1259 | OP_6001 () | |
1260 | { | |
1261 | trace_input ("ld", OP_REG_OUTPUT, OP_POSTINC, OP_VOID); | |
1262 | State.regs[OP[0]] = RW (State.regs[OP[1]]); | |
1263 | INC_ADDR(State.regs[OP[1]],2); | |
1264 | trace_output (OP_REG); | |
1265 | } | |
1266 | ||
1267 | /* ld */ | |
1268 | void | |
1269 | OP_6000 () | |
1270 | { | |
1271 | trace_input ("ld", OP_REG_OUTPUT, OP_MEMREF, OP_VOID); | |
1272 | State.regs[OP[0]] = RW (State.regs[OP[1]]); | |
1273 | trace_output (OP_REG); | |
1274 | } | |
1275 | ||
1276 | /* ld2w */ | |
1277 | void | |
1278 | OP_31000000 () | |
1279 | { | |
1280 | uint16 addr = State.regs[OP[2]]; | |
1281 | trace_input ("ld2w", OP_REG_OUTPUT, OP_MEMREF2, OP_VOID); | |
1282 | State.regs[OP[0]] = RW (OP[1] + addr); | |
1283 | State.regs[OP[0]+1] = RW (OP[1] + addr + 2); | |
1284 | trace_output (OP_DREG); | |
1285 | } | |
1286 | ||
1287 | /* ld2w */ | |
1288 | void | |
1289 | OP_6601 () | |
1290 | { | |
1291 | uint16 addr = State.regs[OP[1]]; | |
1292 | trace_input ("ld2w", OP_REG_OUTPUT, OP_POSTDEC, OP_VOID); | |
1293 | State.regs[OP[0]] = RW (addr); | |
1294 | State.regs[OP[0]+1] = RW (addr+2); | |
1295 | INC_ADDR(State.regs[OP[1]],-4); | |
1296 | trace_output (OP_DREG); | |
1297 | } | |
1298 | ||
1299 | /* ld2w */ | |
1300 | void | |
1301 | OP_6201 () | |
1302 | { | |
1303 | uint16 addr = State.regs[OP[1]]; | |
1304 | trace_input ("ld2w", OP_REG_OUTPUT, OP_POSTINC, OP_VOID); | |
1305 | State.regs[OP[0]] = RW (addr); | |
1306 | State.regs[OP[0]+1] = RW (addr+2); | |
1307 | INC_ADDR(State.regs[OP[1]],4); | |
1308 | trace_output (OP_DREG); | |
1309 | } | |
1310 | ||
1311 | /* ld2w */ | |
1312 | void | |
1313 | OP_6200 () | |
1314 | { | |
1315 | uint16 addr = State.regs[OP[1]]; | |
1316 | trace_input ("ld2w", OP_REG_OUTPUT, OP_MEMREF, OP_VOID); | |
1317 | State.regs[OP[0]] = RW (addr); | |
1318 | State.regs[OP[0]+1] = RW (addr+2); | |
1319 | trace_output (OP_DREG); | |
1320 | } | |
1321 | ||
1322 | /* ldb */ | |
1323 | void | |
1324 | OP_38000000 () | |
1325 | { | |
1326 | trace_input ("ldb", OP_REG_OUTPUT, OP_MEMREF2, OP_VOID); | |
1327 | State.regs[OP[0]] = SEXT8 (RB (OP[1] + State.regs[OP[2]])); | |
1328 | trace_output (OP_REG); | |
1329 | } | |
1330 | ||
1331 | /* ldb */ | |
1332 | void | |
1333 | OP_7000 () | |
1334 | { | |
1335 | trace_input ("ldb", OP_REG_OUTPUT, OP_MEMREF, OP_VOID); | |
1336 | State.regs[OP[0]] = SEXT8 (RB (State.regs[OP[1]])); | |
1337 | trace_output (OP_REG); | |
1338 | } | |
1339 | ||
1340 | /* ldi.s */ | |
1341 | void | |
1342 | OP_4001 () | |
1343 | { | |
1344 | trace_input ("ldi.s", OP_REG_OUTPUT, OP_CONSTANT4, OP_VOID); | |
1345 | State.regs[OP[0]] = SEXT4(OP[1]); | |
1346 | trace_output (OP_REG); | |
1347 | } | |
1348 | ||
1349 | /* ldi.l */ | |
1350 | void | |
1351 | OP_20000000 () | |
1352 | { | |
1353 | trace_input ("ldi.l", OP_REG_OUTPUT, OP_CONSTANT16, OP_VOID); | |
1354 | State.regs[OP[0]] = OP[1]; | |
1355 | trace_output (OP_REG); | |
1356 | } | |
1357 | ||
1358 | /* ldub */ | |
1359 | void | |
1360 | OP_39000000 () | |
1361 | { | |
1362 | trace_input ("ldub", OP_REG_OUTPUT, OP_MEMREF2, OP_VOID); | |
1363 | State.regs[OP[0]] = RB (OP[1] + State.regs[OP[2]]); | |
1364 | trace_output (OP_REG); | |
1365 | } | |
1366 | ||
1367 | /* ldub */ | |
1368 | void | |
1369 | OP_7200 () | |
1370 | { | |
1371 | trace_input ("ldub", OP_REG_OUTPUT, OP_MEMREF, OP_VOID); | |
1372 | State.regs[OP[0]] = RB (State.regs[OP[1]]); | |
1373 | trace_output (OP_REG); | |
1374 | } | |
1375 | ||
1376 | /* mac */ | |
1377 | void | |
1378 | OP_2A00 () | |
1379 | { | |
1380 | int64 tmp; | |
1381 | ||
1382 | trace_input ("mac", OP_ACCUM, OP_REG, OP_REG); | |
1383 | tmp = SEXT40 ((int16)(State.regs[OP[1]]) * (int16)(State.regs[OP[2]])); | |
1384 | ||
1385 | if (State.FX) | |
1386 | tmp = SEXT40( (tmp << 1) & MASK40); | |
1387 | ||
1388 | if (State.ST && tmp > MAX32) | |
1389 | tmp = MAX32; | |
1390 | ||
1391 | tmp += SEXT40(State.a[OP[0]]); | |
1392 | if (State.ST) | |
1393 | { | |
1394 | if (tmp > MAX32) | |
1395 | State.a[OP[0]] = MAX32; | |
1396 | else if (tmp < MIN32) | |
1397 | State.a[OP[0]] = MIN32; | |
1398 | else | |
1399 | State.a[OP[0]] = tmp & MASK40; | |
1400 | } | |
1401 | else | |
1402 | State.a[OP[0]] = tmp & MASK40; | |
1403 | trace_output (OP_ACCUM); | |
1404 | } | |
1405 | ||
1406 | /* macsu */ | |
1407 | void | |
1408 | OP_1A00 () | |
1409 | { | |
1410 | int64 tmp; | |
1411 | ||
1412 | trace_input ("macsu", OP_ACCUM, OP_REG, OP_REG); | |
1413 | tmp = SEXT40 ((int16)State.regs[OP[1]] * State.regs[OP[2]]); | |
1414 | if (State.FX) | |
1415 | tmp = SEXT40( (tmp << 1) & MASK40); | |
1416 | ||
1417 | State.a[OP[0]] = (SEXT40 (State.a[OP[0]]) + tmp) & MASK40; | |
1418 | trace_output (OP_ACCUM); | |
1419 | } | |
1420 | ||
1421 | /* macu */ | |
1422 | void | |
1423 | OP_3A00 () | |
1424 | { | |
1425 | uint64 tmp; | |
1426 | uint32 src1; | |
1427 | uint32 src2; | |
1428 | ||
1429 | trace_input ("macu", OP_ACCUM, OP_REG, OP_REG); | |
1430 | src1 = (uint16) State.regs[OP[1]]; | |
1431 | src2 = (uint16) State.regs[OP[2]]; | |
1432 | tmp = src1 * src2; | |
1433 | if (State.FX) | |
1434 | tmp = (tmp << 1); | |
1435 | State.a[OP[0]] = (State.a[OP[0]] + tmp) & MASK40; | |
1436 | trace_output (OP_ACCUM); | |
1437 | } | |
1438 | ||
1439 | /* max */ | |
1440 | void | |
1441 | OP_2600 () | |
1442 | { | |
1443 | trace_input ("max", OP_REG, OP_REG, OP_VOID); | |
1444 | State.F1 = State.F0; | |
1445 | if ((int16)State.regs[OP[1]] > (int16)State.regs[OP[0]]) | |
1446 | { | |
1447 | State.regs[OP[0]] = State.regs[OP[1]]; | |
1448 | State.F0 = 1; | |
1449 | } | |
1450 | else | |
1451 | State.F0 = 0; | |
1452 | trace_output (OP_REG); | |
1453 | } | |
1454 | ||
1455 | /* max */ | |
1456 | void | |
1457 | OP_3600 () | |
1458 | { | |
1459 | int64 tmp; | |
1460 | ||
1461 | trace_input ("max", OP_ACCUM, OP_DREG, OP_VOID); | |
1462 | State.F1 = State.F0; | |
1463 | tmp = SEXT16 (State.regs[OP[1]]) << 16 | State.regs[OP[1]+1]; | |
1464 | if (tmp > SEXT40(State.a[OP[0]])) | |
1465 | { | |
1466 | State.a[OP[0]] = tmp & MASK40; | |
1467 | State.F0 = 1; | |
1468 | } | |
1469 | else | |
1470 | State.F0 = 0; | |
1471 | trace_output (OP_ACCUM); | |
1472 | } | |
1473 | ||
1474 | /* max */ | |
1475 | void | |
1476 | OP_3602 () | |
1477 | { | |
1478 | trace_input ("max", OP_ACCUM, OP_ACCUM, OP_VOID); | |
1479 | State.F1 = State.F0; | |
1480 | if (SEXT40(State.a[OP[1]]) > SEXT40(State.a[OP[0]])) | |
1481 | { | |
1482 | State.a[OP[0]] = State.a[OP[1]]; | |
1483 | State.F0 = 1; | |
1484 | } | |
1485 | else | |
1486 | State.F0 = 0; | |
1487 | trace_output (OP_ACCUM); | |
1488 | } | |
1489 | ||
1490 | ||
1491 | /* min */ | |
1492 | void | |
1493 | OP_2601 () | |
1494 | { | |
1495 | trace_input ("min", OP_REG, OP_REG, OP_VOID); | |
1496 | State.F1 = State.F0; | |
1497 | if ((int16)State.regs[OP[1]] < (int16)State.regs[OP[0]]) | |
1498 | { | |
1499 | State.regs[OP[0]] = State.regs[OP[1]]; | |
1500 | State.F0 = 1; | |
1501 | } | |
1502 | else | |
1503 | State.F0 = 0; | |
1504 | trace_output (OP_REG); | |
1505 | } | |
1506 | ||
1507 | /* min */ | |
1508 | void | |
1509 | OP_3601 () | |
1510 | { | |
1511 | int64 tmp; | |
1512 | ||
1513 | trace_input ("min", OP_ACCUM, OP_DREG, OP_VOID); | |
1514 | State.F1 = State.F0; | |
1515 | tmp = SEXT16 (State.regs[OP[1]]) << 16 | State.regs[OP[1]+1]; | |
1516 | if (tmp < SEXT40(State.a[OP[0]])) | |
1517 | { | |
1518 | State.a[OP[0]] = tmp & MASK40; | |
1519 | State.F0 = 1; | |
1520 | } | |
1521 | else | |
1522 | State.F0 = 0; | |
1523 | trace_output (OP_ACCUM); | |
1524 | } | |
1525 | ||
1526 | /* min */ | |
1527 | void | |
1528 | OP_3603 () | |
1529 | { | |
1530 | trace_input ("min", OP_ACCUM, OP_ACCUM, OP_VOID); | |
1531 | State.F1 = State.F0; | |
1532 | if (SEXT40(State.a[OP[1]]) < SEXT40(State.a[OP[0]])) | |
1533 | { | |
1534 | State.a[OP[0]] = State.a[OP[1]]; | |
1535 | State.F0 = 1; | |
1536 | } | |
1537 | else | |
1538 | State.F0 = 0; | |
1539 | trace_output (OP_ACCUM); | |
1540 | } | |
1541 | ||
1542 | /* msb */ | |
1543 | void | |
1544 | OP_2800 () | |
1545 | { | |
1546 | int64 tmp; | |
1547 | ||
1548 | trace_input ("msb", OP_ACCUM, OP_REG, OP_REG); | |
1549 | tmp = SEXT40 ((int16)(State.regs[OP[1]]) * (int16)(State.regs[OP[2]])); | |
1550 | ||
1551 | if (State.FX) | |
1552 | tmp = SEXT40 ((tmp << 1) & MASK40); | |
1553 | ||
1554 | if (State.ST && tmp > MAX32) | |
1555 | tmp = MAX32; | |
1556 | ||
1557 | tmp = SEXT40(State.a[OP[0]]) - tmp; | |
1558 | if (State.ST) | |
1559 | { | |
1560 | if (tmp > MAX32) | |
1561 | State.a[OP[0]] = MAX32; | |
1562 | else if (tmp < MIN32) | |
1563 | State.a[OP[0]] = MIN32; | |
1564 | else | |
1565 | State.a[OP[0]] = tmp & MASK40; | |
1566 | } | |
1567 | else | |
1568 | State.a[OP[0]] = tmp & MASK40; | |
1569 | trace_output (OP_ACCUM); | |
1570 | } | |
1571 | ||
1572 | /* msbsu */ | |
1573 | void | |
1574 | OP_1800 () | |
1575 | { | |
1576 | int64 tmp; | |
1577 | ||
1578 | trace_input ("msbsu", OP_ACCUM, OP_REG, OP_REG); | |
1579 | tmp = SEXT40 ((int16)State.regs[OP[1]] * State.regs[OP[2]]); | |
1580 | if (State.FX) | |
1581 | tmp = SEXT40( (tmp << 1) & MASK40); | |
1582 | ||
1583 | State.a[OP[0]] = (SEXT40 (State.a[OP[0]]) - tmp) & MASK40; | |
1584 | trace_output (OP_ACCUM); | |
1585 | } | |
1586 | ||
1587 | /* msbu */ | |
1588 | void | |
1589 | OP_3800 () | |
1590 | { | |
1591 | uint64 tmp; | |
1592 | uint32 src1; | |
1593 | uint32 src2; | |
1594 | ||
1595 | trace_input ("msbu", OP_ACCUM, OP_REG, OP_REG); | |
1596 | src1 = (uint16) State.regs[OP[1]]; | |
1597 | src2 = (uint16) State.regs[OP[2]]; | |
1598 | tmp = src1 * src2; | |
1599 | if (State.FX) | |
1600 | tmp = (tmp << 1); | |
1601 | ||
1602 | State.a[OP[0]] = (State.a[OP[0]] - tmp) & MASK40; | |
1603 | trace_output (OP_ACCUM); | |
1604 | } | |
1605 | ||
1606 | /* mul */ | |
1607 | void | |
1608 | OP_2E00 () | |
1609 | { | |
1610 | trace_input ("mul", OP_REG, OP_REG, OP_VOID); | |
1611 | State.regs[OP[0]] *= State.regs[OP[1]]; | |
1612 | trace_output (OP_REG); | |
1613 | } | |
1614 | ||
1615 | /* mulx */ | |
1616 | void | |
1617 | OP_2C00 () | |
1618 | { | |
1619 | int64 tmp; | |
1620 | ||
1621 | trace_input ("mulx", OP_ACCUM_OUTPUT, OP_REG, OP_REG); | |
1622 | tmp = SEXT40 ((int16)(State.regs[OP[1]]) * (int16)(State.regs[OP[2]])); | |
1623 | ||
1624 | if (State.FX) | |
1625 | tmp = SEXT40 ((tmp << 1) & MASK40); | |
1626 | ||
1627 | if (State.ST && tmp > MAX32) | |
1628 | State.a[OP[0]] = MAX32; | |
1629 | else | |
1630 | State.a[OP[0]] = tmp & MASK40; | |
1631 | trace_output (OP_ACCUM); | |
1632 | } | |
1633 | ||
1634 | /* mulxsu */ | |
1635 | void | |
1636 | OP_1C00 () | |
1637 | { | |
1638 | int64 tmp; | |
1639 | ||
1640 | trace_input ("mulxsu", OP_ACCUM_OUTPUT, OP_REG, OP_REG); | |
1641 | tmp = SEXT40 ((int16)(State.regs[OP[1]]) * State.regs[OP[2]]); | |
1642 | ||
1643 | if (State.FX) | |
1644 | tmp <<= 1; | |
1645 | ||
1646 | State.a[OP[0]] = tmp & MASK40; | |
1647 | trace_output (OP_ACCUM); | |
1648 | } | |
1649 | ||
1650 | /* mulxu */ | |
1651 | void | |
1652 | OP_3C00 () | |
1653 | { | |
1654 | uint64 tmp; | |
1655 | uint32 src1; | |
1656 | uint32 src2; | |
1657 | ||
1658 | trace_input ("mulxu", OP_ACCUM_OUTPUT, OP_REG, OP_REG); | |
1659 | src1 = (uint16) State.regs[OP[1]]; | |
1660 | src2 = (uint16) State.regs[OP[2]]; | |
1661 | tmp = src1 * src2; | |
1662 | if (State.FX) | |
1663 | tmp <<= 1; | |
1664 | ||
1665 | State.a[OP[0]] = tmp & MASK40; | |
1666 | trace_output (OP_ACCUM); | |
1667 | } | |
1668 | ||
1669 | /* mv */ | |
1670 | void | |
1671 | OP_4000 () | |
1672 | { | |
1673 | trace_input ("mv", OP_REG_OUTPUT, OP_REG, OP_VOID); | |
1674 | State.regs[OP[0]] = State.regs[OP[1]]; | |
1675 | trace_output (OP_REG); | |
1676 | } | |
1677 | ||
1678 | /* mv2w */ | |
1679 | void | |
1680 | OP_5000 () | |
1681 | { | |
1682 | trace_input ("mv2w", OP_DREG_OUTPUT, OP_DREG, OP_VOID); | |
1683 | State.regs[OP[0]] = State.regs[OP[1]]; | |
1684 | State.regs[OP[0]+1] = State.regs[OP[1]+1]; | |
1685 | trace_output (OP_DREG); | |
1686 | } | |
1687 | ||
1688 | /* mv2wfac */ | |
1689 | void | |
1690 | OP_3E00 () | |
1691 | { | |
1692 | trace_input ("mv2wfac", OP_DREG_OUTPUT, OP_ACCUM, OP_VOID); | |
1693 | State.regs[OP[0]] = (State.a[OP[1]] >> 16) & 0xffff; | |
1694 | State.regs[OP[0]+1] = State.a[OP[1]] & 0xffff; | |
1695 | trace_output (OP_DREG); | |
1696 | } | |
1697 | ||
1698 | /* mv2wtac */ | |
1699 | void | |
1700 | OP_3E01 () | |
1701 | { | |
1702 | trace_input ("mv2wtac", OP_DREG, OP_ACCUM_OUTPUT, OP_VOID); | |
1703 | State.a[OP[1]] = (SEXT16 (State.regs[OP[0]]) << 16 | State.regs[OP[0]+1]) & MASK40; | |
1704 | trace_output (OP_ACCUM_REVERSE); | |
1705 | } | |
1706 | ||
1707 | /* mvac */ | |
1708 | void | |
1709 | OP_3E03 () | |
1710 | { | |
1711 | trace_input ("mvac", OP_ACCUM_OUTPUT, OP_ACCUM, OP_VOID); | |
1712 | State.a[OP[0]] = State.a[OP[1]]; | |
1713 | trace_output (OP_ACCUM); | |
1714 | } | |
1715 | ||
1716 | /* mvb */ | |
1717 | void | |
1718 | OP_5400 () | |
1719 | { | |
1720 | trace_input ("mvb", OP_REG_OUTPUT, OP_REG, OP_VOID); | |
1721 | State.regs[OP[0]] = SEXT8 (State.regs[OP[1]] & 0xff); | |
1722 | trace_output (OP_REG); | |
1723 | } | |
1724 | ||
1725 | /* mvf0f */ | |
1726 | void | |
1727 | OP_4400 () | |
1728 | { | |
1729 | trace_input ("mf0f", OP_REG_OUTPUT, OP_REG, OP_VOID); | |
1730 | if (State.F0 == 0) | |
1731 | State.regs[OP[0]] = State.regs[OP[1]]; | |
1732 | trace_output (OP_REG); | |
1733 | } | |
1734 | ||
1735 | /* mvf0t */ | |
1736 | void | |
1737 | OP_4401 () | |
1738 | { | |
1739 | trace_input ("mf0t", OP_REG_OUTPUT, OP_REG, OP_VOID); | |
1740 | if (State.F0) | |
1741 | State.regs[OP[0]] = State.regs[OP[1]]; | |
1742 | trace_output (OP_REG); | |
1743 | } | |
1744 | ||
1745 | /* mvfacg */ | |
1746 | void | |
1747 | OP_1E04 () | |
1748 | { | |
1749 | trace_input ("mvfacg", OP_REG_OUTPUT, OP_ACCUM, OP_VOID); | |
1750 | State.regs[OP[0]] = (State.a[OP[1]] >> 32) & 0xff; | |
1751 | trace_output (OP_ACCUM); | |
1752 | } | |
1753 | ||
1754 | /* mvfachi */ | |
1755 | void | |
1756 | OP_1E00 () | |
1757 | { | |
1758 | trace_input ("mvfachi", OP_REG_OUTPUT, OP_ACCUM, OP_VOID); | |
1759 | State.regs[OP[0]] = (State.a[OP[1]] >> 16) & 0xffff; | |
1760 | trace_output (OP_REG); | |
1761 | } | |
1762 | ||
1763 | /* mvfaclo */ | |
1764 | void | |
1765 | OP_1E02 () | |
1766 | { | |
1767 | trace_input ("mvfaclo", OP_REG_OUTPUT, OP_ACCUM, OP_VOID); | |
1768 | State.regs[OP[0]] = State.a[OP[1]] & 0xffff; | |
1769 | trace_output (OP_REG); | |
1770 | } | |
1771 | ||
1772 | /* mvfc */ | |
1773 | void | |
1774 | OP_5200 () | |
1775 | { | |
1776 | trace_input ("mvfc", OP_REG_OUTPUT, OP_CR, OP_VOID); | |
1777 | State.regs[OP[0]] = move_from_cr (OP[1]); | |
1778 | trace_output (OP_REG); | |
1779 | } | |
1780 | ||
1781 | /* mvtacg */ | |
1782 | void | |
1783 | OP_1E41 () | |
1784 | { | |
1785 | trace_input ("mvtacg", OP_REG, OP_ACCUM, OP_VOID); | |
1786 | State.a[OP[1]] &= MASK32; | |
1787 | State.a[OP[1]] |= (int64)(State.regs[OP[0]] & 0xff) << 32; | |
1788 | trace_output (OP_ACCUM_REVERSE); | |
1789 | } | |
1790 | ||
1791 | /* mvtachi */ | |
1792 | void | |
1793 | OP_1E01 () | |
1794 | { | |
1795 | uint16 tmp; | |
1796 | ||
1797 | trace_input ("mvtachi", OP_REG, OP_ACCUM, OP_VOID); | |
1798 | tmp = State.a[OP[1]] & 0xffff; | |
1799 | State.a[OP[1]] = (SEXT16 (State.regs[OP[0]]) << 16 | tmp) & MASK40; | |
1800 | trace_output (OP_ACCUM_REVERSE); | |
1801 | } | |
1802 | ||
1803 | /* mvtaclo */ | |
1804 | void | |
1805 | OP_1E21 () | |
1806 | { | |
1807 | trace_input ("mvtaclo", OP_REG, OP_ACCUM, OP_VOID); | |
1808 | State.a[OP[1]] = (SEXT16 (State.regs[OP[0]])) & MASK40; | |
1809 | trace_output (OP_ACCUM_REVERSE); | |
1810 | } | |
1811 | ||
1812 | /* mvtc */ | |
1813 | void | |
1814 | OP_5600 () | |
1815 | { | |
1816 | trace_input ("mvtc", OP_REG, OP_CR_OUTPUT, OP_VOID); | |
1817 | move_to_cr (OP[1], State.regs[OP[0]]); | |
1818 | trace_output (OP_CR_REVERSE); | |
1819 | } | |
1820 | ||
1821 | /* mvub */ | |
1822 | void | |
1823 | OP_5401 () | |
1824 | { | |
1825 | trace_input ("mvub", OP_REG_OUTPUT, OP_REG, OP_VOID); | |
1826 | State.regs[OP[0]] = State.regs[OP[1]] & 0xff; | |
1827 | trace_output (OP_REG); | |
1828 | } | |
1829 | ||
1830 | /* neg */ | |
1831 | void | |
1832 | OP_4605 () | |
1833 | { | |
1834 | trace_input ("neg", OP_REG, OP_VOID, OP_VOID); | |
1835 | State.regs[OP[0]] = 0 - State.regs[OP[0]]; | |
1836 | trace_output (OP_REG); | |
1837 | } | |
1838 | ||
1839 | /* neg */ | |
1840 | void | |
1841 | OP_5605 () | |
1842 | { | |
1843 | int64 tmp; | |
1844 | ||
1845 | trace_input ("neg", OP_ACCUM, OP_VOID, OP_VOID); | |
1846 | tmp = -SEXT40(State.a[OP[0]]); | |
1847 | if (State.ST) | |
1848 | { | |
1849 | if ( tmp > MAX32) | |
1850 | State.a[OP[0]] = MAX32; | |
1851 | else if (tmp < MIN32) | |
1852 | State.a[OP[0]] = MIN32; | |
1853 | else | |
1854 | State.a[OP[0]] = tmp & MASK40; | |
1855 | } | |
1856 | else | |
1857 | State.a[OP[0]] = tmp & MASK40; | |
1858 | trace_output (OP_ACCUM); | |
1859 | } | |
1860 | ||
1861 | ||
1862 | /* nop */ | |
1863 | void | |
1864 | OP_5E00 () | |
1865 | { | |
1866 | trace_input ("nop", OP_VOID, OP_VOID, OP_VOID); | |
1867 | ||
1868 | ins_type_counters[ (int)State.ins_type ]--; /* don't count nops as normal instructions */ | |
1869 | switch (State.ins_type) | |
1870 | { | |
1871 | default: | |
1872 | ins_type_counters[ (int)INS_UNKNOWN ]++; | |
1873 | break; | |
1874 | ||
1875 | case INS_LEFT_PARALLEL: | |
1876 | /* Don't count a parallel op that includes a NOP as a true parallel op */ | |
1877 | ins_type_counters[ (int)INS_RIGHT_PARALLEL ]--; | |
1878 | ins_type_counters[ (int)INS_RIGHT ]++; | |
1879 | ins_type_counters[ (int)INS_LEFT_NOPS ]++; | |
1880 | break; | |
1881 | ||
1882 | case INS_LEFT: | |
1883 | case INS_LEFT_COND_EXE: | |
1884 | ins_type_counters[ (int)INS_LEFT_NOPS ]++; | |
1885 | break; | |
1886 | ||
1887 | case INS_RIGHT_PARALLEL: | |
1888 | /* Don't count a parallel op that includes a NOP as a true parallel op */ | |
1889 | ins_type_counters[ (int)INS_LEFT_PARALLEL ]--; | |
1890 | ins_type_counters[ (int)INS_LEFT ]++; | |
1891 | ins_type_counters[ (int)INS_RIGHT_NOPS ]++; | |
1892 | break; | |
1893 | ||
1894 | case INS_RIGHT: | |
1895 | case INS_RIGHT_COND_EXE: | |
1896 | ins_type_counters[ (int)INS_RIGHT_NOPS ]++; | |
1897 | break; | |
1898 | } | |
1899 | ||
1900 | trace_output (OP_VOID); | |
1901 | } | |
1902 | ||
1903 | /* not */ | |
1904 | void | |
1905 | OP_4603 () | |
1906 | { | |
1907 | trace_input ("not", OP_REG, OP_VOID, OP_VOID); | |
1908 | State.regs[OP[0]] = ~(State.regs[OP[0]]); | |
1909 | trace_output (OP_REG); | |
1910 | } | |
1911 | ||
1912 | /* or */ | |
1913 | void | |
1914 | OP_800 () | |
1915 | { | |
1916 | trace_input ("or", OP_REG, OP_REG, OP_VOID); | |
1917 | State.regs[OP[0]] |= State.regs[OP[1]]; | |
1918 | trace_output (OP_REG); | |
1919 | } | |
1920 | ||
1921 | /* or3 */ | |
1922 | void | |
1923 | OP_4000000 () | |
1924 | { | |
1925 | trace_input ("or3", OP_REG_OUTPUT, OP_REG, OP_CONSTANT16); | |
1926 | State.regs[OP[0]] = State.regs[OP[1]] | OP[2]; | |
1927 | trace_output (OP_REG); | |
1928 | } | |
1929 | ||
1930 | /* rac */ | |
1931 | void | |
1932 | OP_5201 () | |
1933 | { | |
1934 | int64 tmp; | |
1935 | int shift = SEXT3 (OP[2]); | |
1936 | ||
1937 | trace_input ("rac", OP_DREG_OUTPUT, OP_ACCUM, OP_CONSTANT3); | |
1938 | if (OP[1] != 0) | |
1939 | { | |
1940 | (*d10v_callback->printf_filtered) (d10v_callback, | |
1941 | "ERROR at PC 0x%x: instruction only valid for A0\n", | |
1942 | PC<<2); | |
1943 | State.exception = SIGILL; | |
1944 | } | |
1945 | ||
1946 | State.F1 = State.F0; | |
1947 | tmp = SEXT56 ((State.a[0] << 16) | (State.a[1] & 0xffff)); | |
1948 | if (shift >=0) | |
1949 | tmp <<= shift; | |
1950 | else | |
1951 | tmp >>= -shift; | |
1952 | tmp += 0x8000; | |
1953 | tmp >>= 16; /* look at bits 0:43 */ | |
1954 | if (tmp > SEXT44 (SIGNED64 (0x0007fffffff))) | |
1955 | { | |
1956 | State.regs[OP[0]] = 0x7fff; | |
1957 | State.regs[OP[0]+1] = 0xffff; | |
1958 | State.F0 = 1; | |
1959 | } | |
1960 | else if (tmp < SEXT44 (SIGNED64 (0xfff80000000))) | |
1961 | { | |
1962 | State.regs[OP[0]] = 0x8000; | |
1963 | State.regs[OP[0]+1] = 0; | |
1964 | State.F0 = 1; | |
1965 | } | |
1966 | else | |
1967 | { | |
1968 | State.regs[OP[0]] = (tmp >> 16) & 0xffff; | |
1969 | State.regs[OP[0]+1] = tmp & 0xffff; | |
1970 | State.F0 = 0; | |
1971 | } | |
1972 | trace_output (OP_DREG); | |
1973 | } | |
1974 | ||
1975 | /* rachi */ | |
1976 | void | |
1977 | OP_4201 () | |
1978 | { | |
1979 | signed64 tmp; | |
1980 | int shift = SEXT3 (OP[2]); | |
1981 | ||
1982 | trace_input ("rachi", OP_REG_OUTPUT, OP_ACCUM, OP_CONSTANT3); | |
1983 | State.F1 = State.F0; | |
1984 | if (shift >=0) | |
1985 | tmp = SEXT40 (State.a[OP[1]]) << shift; | |
1986 | else | |
1987 | tmp = SEXT40 (State.a[OP[1]]) >> -shift; | |
1988 | tmp += 0x8000; | |
1989 | ||
1990 | if (tmp > SEXT44 (SIGNED64 (0x0007fffffff))) | |
1991 | { | |
1992 | State.regs[OP[0]] = 0x7fff; | |
1993 | State.F0 = 1; | |
1994 | } | |
1995 | else if (tmp < SEXT44 (SIGNED64 (0xfff80000000))) | |
1996 | { | |
1997 | State.regs[OP[0]] = 0x8000; | |
1998 | State.F0 = 1; | |
1999 | } | |
2000 | else | |
2001 | { | |
2002 | State.regs[OP[0]] = (tmp >> 16) & 0xffff; | |
2003 | State.F0 = 0; | |
2004 | } | |
2005 | trace_output (OP_REG); | |
2006 | } | |
2007 | ||
2008 | /* rep */ | |
2009 | void | |
2010 | OP_27000000 () | |
2011 | { | |
2012 | trace_input ("rep", OP_REG, OP_CONSTANT16, OP_VOID); | |
2013 | RPT_S = PC + 1; | |
2014 | RPT_E = PC + OP[1]; | |
2015 | RPT_C = State.regs[OP[0]]; | |
2016 | State.RP = 1; | |
2017 | if (RPT_C == 0) | |
2018 | { | |
2019 | (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: rep with count=0 is illegal.\n"); | |
2020 | State.exception = SIGILL; | |
2021 | } | |
2022 | if (OP[1] < 4) | |
2023 | { | |
2024 | (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: rep must include at least 4 instructions.\n"); | |
2025 | State.exception = SIGILL; | |
2026 | } | |
2027 | trace_output (OP_VOID); | |
2028 | } | |
2029 | ||
2030 | /* repi */ | |
2031 | void | |
2032 | OP_2F000000 () | |
2033 | { | |
2034 | trace_input ("repi", OP_CONSTANT16, OP_CONSTANT16, OP_VOID); | |
2035 | RPT_S = PC + 1; | |
2036 | RPT_E = PC + OP[1]; | |
2037 | RPT_C = OP[0]; | |
2038 | State.RP = 1; | |
2039 | if (RPT_C == 0) | |
2040 | { | |
2041 | (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: repi with count=0 is illegal.\n"); | |
2042 | State.exception = SIGILL; | |
2043 | } | |
2044 | if (OP[1] < 4) | |
2045 | { | |
2046 | (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: repi must include at least 4 instructions.\n"); | |
2047 | State.exception = SIGILL; | |
2048 | } | |
2049 | trace_output (OP_VOID); | |
2050 | } | |
2051 | ||
2052 | /* rtd */ | |
2053 | void | |
2054 | OP_5F60 () | |
2055 | { | |
2056 | d10v_callback->printf_filtered(d10v_callback, "ERROR: rtd - NOT IMPLEMENTED\n"); | |
2057 | State.exception = SIGILL; | |
2058 | } | |
2059 | ||
2060 | /* rte */ | |
2061 | void | |
2062 | OP_5F40 () | |
2063 | { | |
2064 | trace_input ("rte", OP_VOID, OP_VOID, OP_VOID); | |
2065 | move_to_cr (PSW_CR, BPSW); | |
2066 | JMP(BPC); | |
2067 | trace_output (OP_VOID); | |
2068 | } | |
2069 | ||
2070 | /* sadd */ | |
2071 | void | |
2072 | OP_1223 () | |
2073 | { | |
2074 | int64 tmp; | |
2075 | ||
2076 | trace_input ("sadd", OP_ACCUM, OP_ACCUM, OP_VOID); | |
2077 | tmp = SEXT40(State.a[OP[0]]) + (SEXT40(State.a[OP[1]]) >> 16); | |
2078 | if (State.ST) | |
2079 | { | |
2080 | if (tmp > MAX32) | |
2081 | State.a[OP[0]] = MAX32; | |
2082 | else if (tmp < MIN32) | |
2083 | State.a[OP[0]] = MIN32; | |
2084 | else | |
2085 | State.a[OP[0]] = tmp & MASK40; | |
2086 | } | |
2087 | else | |
2088 | State.a[OP[0]] = tmp & MASK40; | |
2089 | trace_output (OP_ACCUM); | |
2090 | } | |
2091 | ||
2092 | /* setf0f */ | |
2093 | void | |
2094 | OP_4611 () | |
2095 | { | |
2096 | trace_input ("setf0f", OP_REG_OUTPUT, OP_VOID, OP_VOID); | |
2097 | State.regs[OP[0]] = (State.F0 == 0) ? 1 : 0; | |
2098 | trace_output (OP_REG); | |
2099 | } | |
2100 | ||
2101 | /* setf0t */ | |
2102 | void | |
2103 | OP_4613 () | |
2104 | { | |
2105 | trace_input ("setf0t", OP_REG_OUTPUT, OP_VOID, OP_VOID); | |
2106 | State.regs[OP[0]] = (State.F0 == 1) ? 1 : 0; | |
2107 | trace_output (OP_REG); | |
2108 | } | |
2109 | ||
2110 | /* sleep */ | |
2111 | void | |
2112 | OP_5FC0 () | |
2113 | { | |
2114 | trace_input ("sleep", OP_VOID, OP_VOID, OP_VOID); | |
2115 | State.IE = 1; | |
2116 | trace_output (OP_VOID); | |
2117 | } | |
2118 | ||
2119 | /* sll */ | |
2120 | void | |
2121 | OP_2200 () | |
2122 | { | |
2123 | trace_input ("sll", OP_REG, OP_REG, OP_VOID); | |
2124 | State.regs[OP[0]] <<= (State.regs[OP[1]] & 0xf); | |
2125 | trace_output (OP_REG); | |
2126 | } | |
2127 | ||
2128 | /* sll */ | |
2129 | void | |
2130 | OP_3200 () | |
2131 | { | |
2132 | int64 tmp; | |
2133 | trace_input ("sll", OP_ACCUM, OP_REG, OP_VOID); | |
2134 | if ((State.regs[OP[1]] & 31) <= 16) | |
2135 | tmp = SEXT40 (State.a[OP[0]]) << (State.regs[OP[1]] & 31); | |
2136 | else | |
2137 | { | |
2138 | (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: shift value %d too large.\n", State.regs[OP[1]] & 31); | |
2139 | State.exception = SIGILL; | |
2140 | return; | |
2141 | } | |
2142 | ||
2143 | if (State.ST) | |
2144 | { | |
2145 | if (tmp > MAX32) | |
2146 | State.a[OP[0]] = MAX32; | |
2147 | else if (tmp < 0xffffff80000000LL) | |
2148 | State.a[OP[0]] = MIN32; | |
2149 | else | |
2150 | State.a[OP[0]] = tmp & MASK40; | |
2151 | } | |
2152 | else | |
2153 | State.a[OP[0]] = tmp & MASK40; | |
2154 | trace_output (OP_ACCUM); | |
2155 | } | |
2156 | ||
2157 | /* slli */ | |
2158 | void | |
2159 | OP_2201 () | |
2160 | { | |
2161 | trace_input ("slli", OP_REG, OP_CONSTANT16, OP_VOID); | |
2162 | State.regs[OP[0]] <<= OP[1]; | |
2163 | trace_output (OP_REG); | |
2164 | } | |
2165 | ||
2166 | /* slli */ | |
2167 | void | |
2168 | OP_3201 () | |
2169 | { | |
2170 | int64 tmp; | |
2171 | ||
2172 | if (OP[1] == 0) | |
2173 | OP[1] = 16; | |
2174 | ||
2175 | trace_input ("slli", OP_ACCUM, OP_CONSTANT16, OP_VOID); | |
2176 | tmp = SEXT40(State.a[OP[0]]) << OP[1]; | |
2177 | ||
2178 | if (State.ST) | |
2179 | { | |
2180 | if (tmp > MAX32) | |
2181 | State.a[OP[0]] = MAX32; | |
2182 | else if (tmp < 0xffffff80000000LL) | |
2183 | State.a[OP[0]] = MIN32; | |
2184 | else | |
2185 | State.a[OP[0]] = tmp & MASK40; | |
2186 | } | |
2187 | else | |
2188 | State.a[OP[0]] = tmp & MASK40; | |
2189 | trace_output (OP_ACCUM); | |
2190 | } | |
2191 | ||
2192 | /* slx */ | |
2193 | void | |
2194 | OP_460B () | |
2195 | { | |
2196 | trace_input ("slx", OP_REG, OP_FLAG, OP_VOID); | |
2197 | State.regs[OP[0]] = (State.regs[OP[0]] << 1) | State.F0; | |
2198 | trace_output (OP_REG); | |
2199 | } | |
2200 | ||
2201 | /* sra */ | |
2202 | void | |
2203 | OP_2400 () | |
2204 | { | |
2205 | trace_input ("sra", OP_REG, OP_REG, OP_VOID); | |
2206 | State.regs[OP[0]] = ((int16)(State.regs[OP[0]])) >> (State.regs[OP[1]] & 0xf); | |
2207 | trace_output (OP_REG); | |
2208 | } | |
2209 | ||
2210 | /* sra */ | |
2211 | void | |
2212 | OP_3400 () | |
2213 | { | |
2214 | trace_input ("sra", OP_ACCUM, OP_REG, OP_VOID); | |
2215 | if ((State.regs[OP[1]] & 31) <= 16) | |
2216 | State.a[OP[0]] = (SEXT40(State.a[OP[0]]) >> (State.regs[OP[1]] & 31)) & MASK40; | |
2217 | else | |
2218 | { | |
2219 | (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: shift value %d too large.\n", State.regs[OP[1]] & 31); | |
2220 | State.exception = SIGILL; | |
2221 | return; | |
2222 | } | |
2223 | ||
2224 | trace_output (OP_ACCUM); | |
2225 | } | |
2226 | ||
2227 | /* srai */ | |
2228 | void | |
2229 | OP_2401 () | |
2230 | { | |
2231 | trace_input ("srai", OP_REG, OP_CONSTANT16, OP_VOID); | |
2232 | State.regs[OP[0]] = ((int16)(State.regs[OP[0]])) >> OP[1]; | |
2233 | trace_output (OP_REG); | |
2234 | } | |
2235 | ||
2236 | /* srai */ | |
2237 | void | |
2238 | OP_3401 () | |
2239 | { | |
2240 | if (OP[1] == 0) | |
2241 | OP[1] = 16; | |
2242 | ||
2243 | trace_input ("srai", OP_ACCUM, OP_CONSTANT16, OP_VOID); | |
2244 | State.a[OP[0]] = (SEXT40(State.a[OP[0]]) >> OP[1]) & MASK40; | |
2245 | trace_output (OP_ACCUM); | |
2246 | } | |
2247 | ||
2248 | /* srl */ | |
2249 | void | |
2250 | OP_2000 () | |
2251 | { | |
2252 | trace_input ("srl", OP_REG, OP_REG, OP_VOID); | |
2253 | State.regs[OP[0]] >>= (State.regs[OP[1]] & 0xf); | |
2254 | trace_output (OP_REG); | |
2255 | } | |
2256 | ||
2257 | /* srl */ | |
2258 | void | |
2259 | OP_3000 () | |
2260 | { | |
2261 | trace_input ("srl", OP_ACCUM, OP_REG, OP_VOID); | |
2262 | if ((State.regs[OP[1]] & 31) <= 16) | |
2263 | State.a[OP[0]] = (uint64)((State.a[OP[0]] & MASK40) >> (State.regs[OP[1]] & 31)); | |
2264 | else | |
2265 | { | |
2266 | (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: shift value %d too large.\n", State.regs[OP[1]] & 31); | |
2267 | State.exception = SIGILL; | |
2268 | return; | |
2269 | } | |
2270 | ||
2271 | trace_output (OP_ACCUM); | |
2272 | } | |
2273 | ||
2274 | /* srli */ | |
2275 | void | |
2276 | OP_2001 () | |
2277 | { | |
2278 | trace_input ("srli", OP_REG, OP_CONSTANT16, OP_VOID); | |
2279 | State.regs[OP[0]] >>= OP[1]; | |
2280 | trace_output (OP_REG); | |
2281 | } | |
2282 | ||
2283 | /* srli */ | |
2284 | void | |
2285 | OP_3001 () | |
2286 | { | |
2287 | if (OP[1] == 0) | |
2288 | OP[1] = 16; | |
2289 | ||
2290 | trace_input ("srli", OP_ACCUM, OP_CONSTANT16, OP_VOID); | |
2291 | State.a[OP[0]] = (uint64)(State.a[OP[0]] & MASK40) >> OP[1]; | |
2292 | trace_output (OP_ACCUM); | |
2293 | } | |
2294 | ||
2295 | /* srx */ | |
2296 | void | |
2297 | OP_4609 () | |
2298 | { | |
2299 | uint16 tmp; | |
2300 | ||
2301 | trace_input ("srx", OP_REG, OP_FLAG, OP_VOID); | |
2302 | tmp = State.F0 << 15; | |
2303 | State.regs[OP[0]] = (State.regs[OP[0]] >> 1) | tmp; | |
2304 | trace_output (OP_REG); | |
2305 | } | |
2306 | ||
2307 | /* st */ | |
2308 | void | |
2309 | OP_34000000 () | |
2310 | { | |
2311 | trace_input ("st", OP_REG, OP_MEMREF2, OP_VOID); | |
2312 | SW (OP[1] + State.regs[OP[2]], State.regs[OP[0]]); | |
2313 | trace_output (OP_VOID); | |
2314 | } | |
2315 | ||
2316 | /* st */ | |
2317 | void | |
2318 | OP_6800 () | |
2319 | { | |
2320 | trace_input ("st", OP_REG, OP_MEMREF, OP_VOID); | |
2321 | SW (State.regs[OP[1]], State.regs[OP[0]]); | |
2322 | trace_output (OP_VOID); | |
2323 | } | |
2324 | ||
2325 | /* st */ | |
2326 | void | |
2327 | OP_6C1F () | |
2328 | { | |
2329 | trace_input ("st", OP_REG, OP_PREDEC, OP_VOID); | |
2330 | if ( OP[1] != 15 ) | |
2331 | { | |
2332 | (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: cannot pre-decrement any registers but r15 (SP).\n"); | |
2333 | State.exception = SIGILL; | |
2334 | return; | |
2335 | } | |
2336 | State.regs[OP[1]] -= 2; | |
2337 | SW (State.regs[OP[1]], State.regs[OP[0]]); | |
2338 | trace_output (OP_VOID); | |
2339 | } | |
2340 | ||
2341 | /* st */ | |
2342 | void | |
2343 | OP_6801 () | |
2344 | { | |
2345 | trace_input ("st", OP_REG, OP_POSTINC, OP_VOID); | |
2346 | SW (State.regs[OP[1]], State.regs[OP[0]]); | |
2347 | INC_ADDR (State.regs[OP[1]],2); | |
2348 | trace_output (OP_VOID); | |
2349 | } | |
2350 | ||
2351 | /* st */ | |
2352 | void | |
2353 | OP_6C01 () | |
2354 | { | |
2355 | trace_input ("st", OP_REG, OP_POSTDEC, OP_VOID); | |
2356 | if ( OP[1] == 15 ) | |
2357 | { | |
2358 | (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: cannot post-decrement register r15 (SP).\n"); | |
2359 | State.exception = SIGILL; | |
2360 | return; | |
2361 | } | |
2362 | SW (State.regs[OP[1]], State.regs[OP[0]]); | |
2363 | INC_ADDR (State.regs[OP[1]],-2); | |
2364 | trace_output (OP_VOID); | |
2365 | } | |
2366 | ||
2367 | /* st2w */ | |
2368 | void | |
2369 | OP_35000000 () | |
2370 | { | |
2371 | trace_input ("st2w", OP_DREG, OP_MEMREF2, OP_VOID); | |
2372 | SW (State.regs[OP[2]]+OP[1], State.regs[OP[0]]); | |
2373 | SW (State.regs[OP[2]]+OP[1]+2, State.regs[OP[0]+1]); | |
2374 | trace_output (OP_VOID); | |
2375 | } | |
2376 | ||
2377 | /* st2w */ | |
2378 | void | |
2379 | OP_6A00 () | |
2380 | { | |
2381 | trace_input ("st2w", OP_DREG, OP_MEMREF, OP_VOID); | |
2382 | SW (State.regs[OP[1]], State.regs[OP[0]]); | |
2383 | SW (State.regs[OP[1]]+2, State.regs[OP[0]+1]); | |
2384 | trace_output (OP_VOID); | |
2385 | } | |
2386 | ||
2387 | /* st2w */ | |
2388 | void | |
2389 | OP_6E1F () | |
2390 | { | |
2391 | trace_input ("st2w", OP_DREG, OP_PREDEC, OP_VOID); | |
2392 | if ( OP[1] != 15 ) | |
2393 | { | |
2394 | (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: cannot pre-decrement any registers but r15 (SP).\n"); | |
2395 | State.exception = SIGILL; | |
2396 | return; | |
2397 | } | |
2398 | State.regs[OP[1]] -= 4; | |
2399 | SW (State.regs[OP[1]], State.regs[OP[0]]); | |
2400 | SW (State.regs[OP[1]]+2, State.regs[OP[0]+1]); | |
2401 | trace_output (OP_VOID); | |
2402 | } | |
2403 | ||
2404 | /* st2w */ | |
2405 | void | |
2406 | OP_6A01 () | |
2407 | { | |
2408 | trace_input ("st2w", OP_DREG, OP_POSTINC, OP_VOID); | |
2409 | SW (State.regs[OP[1]], State.regs[OP[0]]); | |
2410 | SW (State.regs[OP[1]]+2, State.regs[OP[0]+1]); | |
2411 | INC_ADDR (State.regs[OP[1]],4); | |
2412 | trace_output (OP_VOID); | |
2413 | } | |
2414 | ||
2415 | /* st2w */ | |
2416 | void | |
2417 | OP_6E01 () | |
2418 | { | |
2419 | trace_input ("st2w", OP_DREG, OP_POSTDEC, OP_VOID); | |
2420 | if ( OP[1] == 15 ) | |
2421 | { | |
2422 | (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: cannot post-decrement register r15 (SP).\n"); | |
2423 | State.exception = SIGILL; | |
2424 | return; | |
2425 | } | |
2426 | SW (State.regs[OP[1]], State.regs[OP[0]]); | |
2427 | SW (State.regs[OP[1]]+2, State.regs[OP[0]+1]); | |
2428 | INC_ADDR (State.regs[OP[1]],-4); | |
2429 | trace_output (OP_VOID); | |
2430 | } | |
2431 | ||
2432 | /* stb */ | |
2433 | void | |
2434 | OP_3C000000 () | |
2435 | { | |
2436 | trace_input ("stb", OP_REG, OP_MEMREF2, OP_VOID); | |
2437 | SB (State.regs[OP[2]]+OP[1], State.regs[OP[0]]); | |
2438 | trace_output (OP_VOID); | |
2439 | } | |
2440 | ||
2441 | /* stb */ | |
2442 | void | |
2443 | OP_7800 () | |
2444 | { | |
2445 | trace_input ("stb", OP_REG, OP_MEMREF, OP_VOID); | |
2446 | SB (State.regs[OP[1]], State.regs[OP[0]]); | |
2447 | trace_output (OP_VOID); | |
2448 | } | |
2449 | ||
2450 | /* stop */ | |
2451 | void | |
2452 | OP_5FE0 () | |
2453 | { | |
2454 | trace_input ("stop", OP_VOID, OP_VOID, OP_VOID); | |
2455 | State.exception = SIG_D10V_STOP; | |
2456 | trace_output (OP_VOID); | |
2457 | } | |
2458 | ||
2459 | /* sub */ | |
2460 | void | |
2461 | OP_0 () | |
2462 | { | |
2463 | uint16 tmp; | |
2464 | ||
2465 | trace_input ("sub", OP_REG, OP_REG, OP_VOID); | |
2466 | /* see ../common/sim-alu.h for a more extensive discussion on how to | |
2467 | compute the carry/overflow bits. */ | |
2468 | tmp = State.regs[OP[0]] - State.regs[OP[1]]; | |
2469 | State.C = ((uint16) State.regs[OP[0]] >= (uint16) State.regs[OP[1]]); | |
2470 | State.regs[OP[0]] = tmp; | |
2471 | trace_output (OP_REG); | |
2472 | } | |
2473 | ||
2474 | /* sub */ | |
2475 | void | |
2476 | OP_1001 () | |
2477 | { | |
2478 | int64 tmp; | |
2479 | ||
2480 | trace_input ("sub", OP_ACCUM, OP_DREG, OP_VOID); | |
2481 | tmp = SEXT40(State.a[OP[0]]) - (SEXT16 (State.regs[OP[1]]) << 16 | State.regs[OP[1]+1]); | |
2482 | if (State.ST) | |
2483 | { | |
2484 | if ( tmp > MAX32) | |
2485 | State.a[OP[0]] = MAX32; | |
2486 | else if ( tmp < MIN32) | |
2487 | State.a[OP[0]] = MIN32; | |
2488 | else | |
2489 | State.a[OP[0]] = tmp & MASK40; | |
2490 | } | |
2491 | else | |
2492 | State.a[OP[0]] = tmp & MASK40; | |
2493 | ||
2494 | trace_output (OP_ACCUM); | |
2495 | } | |
2496 | ||
2497 | /* sub */ | |
2498 | ||
2499 | void | |
2500 | OP_1003 () | |
2501 | { | |
2502 | int64 tmp; | |
2503 | ||
2504 | trace_input ("sub", OP_ACCUM, OP_ACCUM, OP_VOID); | |
2505 | tmp = SEXT40(State.a[OP[0]]) - SEXT40(State.a[OP[1]]); | |
2506 | if (State.ST) | |
2507 | { | |
2508 | if (tmp > MAX32) | |
2509 | State.a[OP[0]] = MAX32; | |
2510 | else if ( tmp < MIN32) | |
2511 | State.a[OP[0]] = MIN32; | |
2512 | else | |
2513 | State.a[OP[0]] = tmp & MASK40; | |
2514 | } | |
2515 | else | |
2516 | State.a[OP[0]] = tmp & MASK40; | |
2517 | ||
2518 | trace_output (OP_ACCUM); | |
2519 | } | |
2520 | ||
2521 | /* sub2w */ | |
2522 | void | |
2523 | OP_1000 () | |
2524 | { | |
2525 | uint32 tmp,a,b; | |
2526 | ||
2527 | trace_input ("sub2w", OP_DREG, OP_DREG, OP_VOID); | |
2528 | a = (uint32)((State.regs[OP[0]] << 16) | State.regs[OP[0]+1]); | |
2529 | b = (uint32)((State.regs[OP[1]] << 16) | State.regs[OP[1]+1]); | |
2530 | /* see ../common/sim-alu.h for a more extensive discussion on how to | |
2531 | compute the carry/overflow bits */ | |
2532 | tmp = a - b; | |
2533 | State.C = (a >= b); | |
2534 | State.regs[OP[0]] = (tmp >> 16) & 0xffff; | |
2535 | State.regs[OP[0]+1] = tmp & 0xffff; | |
2536 | trace_output (OP_DREG); | |
2537 | } | |
2538 | ||
2539 | /* subac3 */ | |
2540 | void | |
2541 | OP_17000000 () | |
2542 | { | |
2543 | int64 tmp; | |
2544 | ||
2545 | trace_input ("subac3", OP_DREG_OUTPUT, OP_DREG, OP_ACCUM); | |
2546 | tmp = SEXT40 ((State.regs[OP[1]] << 16) | State.regs[OP[1]+1]) - SEXT40 (State.a[OP[2]]); | |
2547 | State.regs[OP[0]] = (tmp >> 16) & 0xffff; | |
2548 | State.regs[OP[0]+1] = tmp & 0xffff; | |
2549 | trace_output (OP_DREG); | |
2550 | } | |
2551 | ||
2552 | /* subac3 */ | |
2553 | void | |
2554 | OP_17000002 () | |
2555 | { | |
2556 | int64 tmp; | |
2557 | ||
2558 | trace_input ("subac3", OP_DREG_OUTPUT, OP_ACCUM, OP_ACCUM); | |
2559 | tmp = SEXT40(State.a[OP[1]]) - SEXT40(State.a[OP[2]]); | |
2560 | State.regs[OP[0]] = (tmp >> 16) & 0xffff; | |
2561 | State.regs[OP[0]+1] = tmp & 0xffff; | |
2562 | trace_output (OP_DREG); | |
2563 | } | |
2564 | ||
2565 | /* subac3s */ | |
2566 | void | |
2567 | OP_17001000 () | |
2568 | { | |
2569 | int64 tmp; | |
2570 | ||
2571 | trace_input ("subac3s", OP_DREG_OUTPUT, OP_DREG, OP_ACCUM); | |
2572 | State.F1 = State.F0; | |
2573 | tmp = SEXT40 ((State.regs[OP[1]] << 16) | State.regs[OP[1]+1]) - SEXT40(State.a[OP[2]]); | |
2574 | if ( tmp > MAX32) | |
2575 | { | |
2576 | State.regs[OP[0]] = 0x7fff; | |
2577 | State.regs[OP[0]+1] = 0xffff; | |
2578 | State.F0 = 1; | |
2579 | } | |
2580 | else if (tmp < MIN32) | |
2581 | { | |
2582 | State.regs[OP[0]] = 0x8000; | |
2583 | State.regs[OP[0]+1] = 0; | |
2584 | State.F0 = 1; | |
2585 | } | |
2586 | else | |
2587 | { | |
2588 | State.regs[OP[0]] = (tmp >> 16) & 0xffff; | |
2589 | State.regs[OP[0]+1] = tmp & 0xffff; | |
2590 | State.F0 = 0; | |
2591 | } | |
2592 | trace_output (OP_DREG); | |
2593 | } | |
2594 | ||
2595 | /* subac3s */ | |
2596 | void | |
2597 | OP_17001002 () | |
2598 | { | |
2599 | int64 tmp; | |
2600 | ||
2601 | trace_input ("subac3s", OP_DREG_OUTPUT, OP_ACCUM, OP_ACCUM); | |
2602 | State.F1 = State.F0; | |
2603 | tmp = SEXT40(State.a[OP[1]]) - SEXT40(State.a[OP[2]]); | |
2604 | if ( tmp > MAX32) | |
2605 | { | |
2606 | State.regs[OP[0]] = 0x7fff; | |
2607 | State.regs[OP[0]+1] = 0xffff; | |
2608 | State.F0 = 1; | |
2609 | } | |
2610 | else if (tmp < MIN32) | |
2611 | { | |
2612 | State.regs[OP[0]] = 0x8000; | |
2613 | State.regs[OP[0]+1] = 0; | |
2614 | State.F0 = 1; | |
2615 | } | |
2616 | else | |
2617 | { | |
2618 | State.regs[OP[0]] = (tmp >> 16) & 0xffff; | |
2619 | State.regs[OP[0]+1] = tmp & 0xffff; | |
2620 | State.F0 = 0; | |
2621 | } | |
2622 | trace_output (OP_DREG); | |
2623 | } | |
2624 | ||
2625 | /* subi */ | |
2626 | void | |
2627 | OP_1 () | |
2628 | { | |
2629 | unsigned tmp; | |
2630 | if (OP[1] == 0) | |
2631 | OP[1] = 16; | |
2632 | ||
2633 | trace_input ("subi", OP_REG, OP_CONSTANT16, OP_VOID); | |
2634 | /* see ../common/sim-alu.h for a more extensive discussion on how to | |
2635 | compute the carry/overflow bits. */ | |
2636 | /* since OP[1] is never <= 0, -OP[1] == ~OP[1]+1 can never overflow */ | |
2637 | tmp = ((unsigned)(unsigned16) State.regs[OP[0]] | |
2638 | + (unsigned)(unsigned16) ( - OP[1])); | |
2639 | State.C = (tmp >= (1 << 16)); | |
2640 | State.regs[OP[0]] = tmp; | |
2641 | trace_output (OP_REG); | |
2642 | } | |
2643 | ||
2644 | /* trap */ | |
2645 | void | |
2646 | OP_5F00 () | |
2647 | { | |
2648 | trace_input ("trap", OP_CONSTANT4, OP_VOID, OP_VOID); | |
2649 | trace_output (OP_VOID); | |
2650 | ||
2651 | switch (OP[0]) | |
2652 | { | |
2653 | default: | |
2654 | { | |
2655 | uint16 vec = OP[0] + TRAP_VECTOR_START; | |
2656 | BPC = PC + 1; | |
2657 | move_to_cr (BPSW_CR, PSW); | |
2658 | move_to_cr (PSW_CR, PSW & PSW_SM_BIT); | |
2659 | JMP (vec); | |
2660 | } | |
2661 | break; | |
2662 | case 15: /* new system call trap */ | |
2663 | /* Trap 15 is used for simulating low-level I/O */ | |
2664 | { | |
2665 | errno = 0; | |
2666 | ||
2667 | /* Registers passed to trap 0 */ | |
2668 | ||
2669 | #define FUNC State.regs[4] /* function number */ | |
2670 | #define PARM1 State.regs[0] /* optional parm 1 */ | |
2671 | #define PARM2 State.regs[1] /* optional parm 2 */ | |
2672 | #define PARM3 State.regs[2] /* optional parm 3 */ | |
2673 | #define PARM4 State.regs[3] /* optional parm 3 */ | |
2674 | ||
2675 | /* Registers set by trap 0 */ | |
2676 | ||
2677 | #define RETVAL State.regs[0] /* return value */ | |
2678 | #define RETVAL_HIGH State.regs[0] /* return value */ | |
2679 | #define RETVAL_LOW State.regs[1] /* return value */ | |
2680 | #define RETERR State.regs[4] /* return error code */ | |
2681 | ||
2682 | /* Turn a pointer in a register into a pointer into real memory. */ | |
2683 | ||
2684 | #define MEMPTR(x) ((char *)(dmem_addr(x))) | |
2685 | ||
2686 | switch (FUNC) | |
2687 | { | |
2688 | #if !defined(__GO32__) && !defined(_WIN32) | |
2689 | case SYS_fork: | |
2690 | RETVAL = fork (); | |
2691 | trace_input ("<fork>", OP_VOID, OP_VOID, OP_VOID); | |
2692 | trace_output (OP_R0); | |
2693 | break; | |
2694 | ||
2695 | case SYS_getpid: | |
2696 | trace_input ("<getpid>", OP_VOID, OP_VOID, OP_VOID); | |
2697 | RETVAL = getpid (); | |
2698 | trace_output (OP_R0); | |
2699 | break; | |
2700 | ||
2701 | case SYS_kill: | |
2702 | trace_input ("<kill>", OP_REG, OP_REG, OP_VOID); | |
2703 | if (PARM1 == getpid ()) | |
2704 | { | |
2705 | trace_output (OP_VOID); | |
2706 | State.exception = PARM2; | |
2707 | } | |
2708 | else | |
2709 | { | |
2710 | int os_sig = -1; | |
2711 | switch (PARM2) | |
2712 | { | |
2713 | #ifdef SIGHUP | |
2714 | case 1: os_sig = SIGHUP; break; | |
2715 | #endif | |
2716 | #ifdef SIGINT | |
2717 | case 2: os_sig = SIGINT; break; | |
2718 | #endif | |
2719 | #ifdef SIGQUIT | |
2720 | case 3: os_sig = SIGQUIT; break; | |
2721 | #endif | |
2722 | #ifdef SIGILL | |
2723 | case 4: os_sig = SIGILL; break; | |
2724 | #endif | |
2725 | #ifdef SIGTRAP | |
2726 | case 5: os_sig = SIGTRAP; break; | |
2727 | #endif | |
2728 | #ifdef SIGABRT | |
2729 | case 6: os_sig = SIGABRT; break; | |
2730 | #elif defined(SIGIOT) | |
2731 | case 6: os_sig = SIGIOT; break; | |
2732 | #endif | |
2733 | #ifdef SIGEMT | |
2734 | case 7: os_sig = SIGEMT; break; | |
2735 | #endif | |
2736 | #ifdef SIGFPE | |
2737 | case 8: os_sig = SIGFPE; break; | |
2738 | #endif | |
2739 | #ifdef SIGKILL | |
2740 | case 9: os_sig = SIGKILL; break; | |
2741 | #endif | |
2742 | #ifdef SIGBUS | |
2743 | case 10: os_sig = SIGBUS; break; | |
2744 | #endif | |
2745 | #ifdef SIGSEGV | |
2746 | case 11: os_sig = SIGSEGV; break; | |
2747 | #endif | |
2748 | #ifdef SIGSYS | |
2749 | case 12: os_sig = SIGSYS; break; | |
2750 | #endif | |
2751 | #ifdef SIGPIPE | |
2752 | case 13: os_sig = SIGPIPE; break; | |
2753 | #endif | |
2754 | #ifdef SIGALRM | |
2755 | case 14: os_sig = SIGALRM; break; | |
2756 | #endif | |
2757 | #ifdef SIGTERM | |
2758 | case 15: os_sig = SIGTERM; break; | |
2759 | #endif | |
2760 | #ifdef SIGURG | |
2761 | case 16: os_sig = SIGURG; break; | |
2762 | #endif | |
2763 | #ifdef SIGSTOP | |
2764 | case 17: os_sig = SIGSTOP; break; | |
2765 | #endif | |
2766 | #ifdef SIGTSTP | |
2767 | case 18: os_sig = SIGTSTP; break; | |
2768 | #endif | |
2769 | #ifdef SIGCONT | |
2770 | case 19: os_sig = SIGCONT; break; | |
2771 | #endif | |
2772 | #ifdef SIGCHLD | |
2773 | case 20: os_sig = SIGCHLD; break; | |
2774 | #elif defined(SIGCLD) | |
2775 | case 20: os_sig = SIGCLD; break; | |
2776 | #endif | |
2777 | #ifdef SIGTTIN | |
2778 | case 21: os_sig = SIGTTIN; break; | |
2779 | #endif | |
2780 | #ifdef SIGTTOU | |
2781 | case 22: os_sig = SIGTTOU; break; | |
2782 | #endif | |
2783 | #ifdef SIGIO | |
2784 | case 23: os_sig = SIGIO; break; | |
2785 | #elif defined (SIGPOLL) | |
2786 | case 23: os_sig = SIGPOLL; break; | |
2787 | #endif | |
2788 | #ifdef SIGXCPU | |
2789 | case 24: os_sig = SIGXCPU; break; | |
2790 | #endif | |
2791 | #ifdef SIGXFSZ | |
2792 | case 25: os_sig = SIGXFSZ; break; | |
2793 | #endif | |
2794 | #ifdef SIGVTALRM | |
2795 | case 26: os_sig = SIGVTALRM; break; | |
2796 | #endif | |
2797 | #ifdef SIGPROF | |
2798 | case 27: os_sig = SIGPROF; break; | |
2799 | #endif | |
2800 | #ifdef SIGWINCH | |
2801 | case 28: os_sig = SIGWINCH; break; | |
2802 | #endif | |
2803 | #ifdef SIGLOST | |
2804 | case 29: os_sig = SIGLOST; break; | |
2805 | #endif | |
2806 | #ifdef SIGUSR1 | |
2807 | case 30: os_sig = SIGUSR1; break; | |
2808 | #endif | |
2809 | #ifdef SIGUSR2 | |
2810 | case 31: os_sig = SIGUSR2; break; | |
2811 | #endif | |
2812 | } | |
2813 | ||
2814 | if (os_sig == -1) | |
2815 | { | |
2816 | trace_output (OP_VOID); | |
2817 | (*d10v_callback->printf_filtered) (d10v_callback, "Unknown signal %d\n", PARM2); | |
2818 | (*d10v_callback->flush_stdout) (d10v_callback); | |
2819 | State.exception = SIGILL; | |
2820 | } | |
2821 | else | |
2822 | { | |
2823 | RETVAL = kill (PARM1, PARM2); | |
2824 | trace_output (OP_R0); | |
2825 | } | |
2826 | } | |
2827 | break; | |
2828 | ||
2829 | case SYS_execve: | |
2830 | RETVAL = execve (MEMPTR (PARM1), (char **) MEMPTR (PARM2), | |
2831 | (char **)MEMPTR (PARM3)); | |
2832 | trace_input ("<execve>", OP_R0, OP_R1, OP_R2); | |
2833 | trace_output (OP_R0); | |
2834 | break; | |
2835 | ||
2836 | #ifdef SYS_execv | |
2837 | case SYS_execv: | |
2838 | RETVAL = execve (MEMPTR (PARM1), (char **) MEMPTR (PARM2), NULL); | |
2839 | trace_input ("<execv>", OP_R0, OP_R1, OP_VOID); | |
2840 | trace_output (OP_R0); | |
2841 | break; | |
2842 | #endif | |
2843 | ||
2844 | case SYS_pipe: | |
2845 | { | |
2846 | reg_t buf; | |
2847 | int host_fd[2]; | |
2848 | ||
2849 | buf = PARM1; | |
2850 | RETVAL = pipe (host_fd); | |
2851 | SW (buf, host_fd[0]); | |
2852 | buf += sizeof(uint16); | |
2853 | SW (buf, host_fd[1]); | |
2854 | trace_input ("<pipe>", OP_R0, OP_VOID, OP_VOID); | |
2855 | trace_output (OP_R0); | |
2856 | } | |
2857 | break; | |
2858 | ||
2859 | #ifdef SYS_wait | |
2860 | case SYS_wait: | |
2861 | { | |
2862 | int status; | |
2863 | ||
2864 | RETVAL = wait (&status); | |
2865 | if (PARM1) | |
2866 | SW (PARM1, status); | |
2867 | trace_input ("<wait>", OP_R0, OP_VOID, OP_VOID); | |
2868 | trace_output (OP_R0); | |
2869 | } | |
2870 | break; | |
2871 | #endif | |
2872 | #else | |
2873 | case SYS_getpid: | |
2874 | trace_input ("<getpid>", OP_VOID, OP_VOID, OP_VOID); | |
2875 | RETVAL = 1; | |
2876 | trace_output (OP_R0); | |
2877 | break; | |
2878 | ||
2879 | case SYS_kill: | |
2880 | trace_input ("<kill>", OP_REG, OP_REG, OP_VOID); | |
2881 | trace_output (OP_VOID); | |
2882 | State.exception = PARM2; | |
2883 | break; | |
2884 | #endif | |
2885 | ||
2886 | case SYS_read: | |
2887 | RETVAL = d10v_callback->read (d10v_callback, PARM1, MEMPTR (PARM2), | |
2888 | PARM3); | |
2889 | trace_input ("<read>", OP_R0, OP_R1, OP_R2); | |
2890 | trace_output (OP_R0); | |
2891 | break; | |
2892 | ||
2893 | case SYS_write: | |
2894 | if (PARM1 == 1) | |
2895 | RETVAL = (int)d10v_callback->write_stdout (d10v_callback, | |
2896 | MEMPTR (PARM2), PARM3); | |
2897 | else | |
2898 | RETVAL = (int)d10v_callback->write (d10v_callback, PARM1, | |
2899 | MEMPTR (PARM2), PARM3); | |
2900 | trace_input ("<write>", OP_R0, OP_R1, OP_R2); | |
2901 | trace_output (OP_R0); | |
2902 | break; | |
2903 | ||
2904 | case SYS_lseek: | |
2905 | { | |
2906 | unsigned long ret = d10v_callback->lseek (d10v_callback, PARM1, | |
2907 | (((unsigned long)PARM2) << 16) || (unsigned long)PARM3, | |
2908 | PARM4); | |
2909 | RETVAL_HIGH = ret >> 16; | |
2910 | RETVAL_LOW = ret & 0xffff; | |
2911 | } | |
2912 | trace_input ("<lseek>", OP_R0, OP_R1, OP_R2); | |
2913 | trace_output (OP_R0R1); | |
2914 | break; | |
2915 | ||
2916 | case SYS_close: | |
2917 | RETVAL = d10v_callback->close (d10v_callback, PARM1); | |
2918 | trace_input ("<close>", OP_R0, OP_VOID, OP_VOID); | |
2919 | trace_output (OP_R0); | |
2920 | break; | |
2921 | ||
2922 | case SYS_open: | |
2923 | RETVAL = d10v_callback->open (d10v_callback, MEMPTR (PARM1), PARM2); | |
2924 | trace_input ("<open>", OP_R0, OP_R1, OP_R2); | |
2925 | trace_output (OP_R0); | |
2926 | trace_input ("<open>", OP_R0, OP_R1, OP_R2); | |
2927 | trace_output (OP_R0); | |
2928 | break; | |
2929 | ||
2930 | case SYS_exit: | |
2931 | State.exception = SIG_D10V_EXIT; | |
2932 | trace_input ("<exit>", OP_R0, OP_VOID, OP_VOID); | |
2933 | trace_output (OP_VOID); | |
2934 | break; | |
2935 | ||
2936 | case SYS_stat: | |
2937 | /* stat system call */ | |
2938 | { | |
2939 | struct stat host_stat; | |
2940 | reg_t buf; | |
2941 | ||
2942 | RETVAL = stat (MEMPTR (PARM1), &host_stat); | |
2943 | ||
2944 | buf = PARM2; | |
2945 | ||
2946 | /* The hard-coded offsets and sizes were determined by using | |
2947 | * the D10V compiler on a test program that used struct stat. | |
2948 | */ | |
2949 | SW (buf, host_stat.st_dev); | |
2950 | SW (buf+2, host_stat.st_ino); | |
2951 | SW (buf+4, host_stat.st_mode); | |
2952 | SW (buf+6, host_stat.st_nlink); | |
2953 | SW (buf+8, host_stat.st_uid); | |
2954 | SW (buf+10, host_stat.st_gid); | |
2955 | SW (buf+12, host_stat.st_rdev); | |
2956 | SLW (buf+16, host_stat.st_size); | |
2957 | SLW (buf+20, host_stat.st_atime); | |
2958 | SLW (buf+28, host_stat.st_mtime); | |
2959 | SLW (buf+36, host_stat.st_ctime); | |
2960 | } | |
2961 | trace_input ("<stat>", OP_R0, OP_R1, OP_VOID); | |
2962 | trace_output (OP_R0); | |
2963 | break; | |
2964 | ||
2965 | case SYS_chown: | |
2966 | RETVAL = chown (MEMPTR (PARM1), PARM2, PARM3); | |
2967 | trace_input ("<chown>", OP_R0, OP_R1, OP_R2); | |
2968 | trace_output (OP_R0); | |
2969 | break; | |
2970 | ||
2971 | case SYS_chmod: | |
2972 | RETVAL = chmod (MEMPTR (PARM1), PARM2); | |
2973 | trace_input ("<chmod>", OP_R0, OP_R1, OP_R2); | |
2974 | trace_output (OP_R0); | |
2975 | break; | |
2976 | ||
2977 | #ifdef SYS_utime | |
2978 | case SYS_utime: | |
2979 | /* Cast the second argument to void *, to avoid type mismatch | |
2980 | if a prototype is present. */ | |
2981 | RETVAL = utime (MEMPTR (PARM1), (void *) MEMPTR (PARM2)); | |
2982 | trace_input ("<utime>", OP_R0, OP_R1, OP_R2); | |
2983 | trace_output (OP_R0); | |
2984 | break; | |
2985 | #endif | |
2986 | ||
2987 | #ifdef SYS_time | |
2988 | case SYS_time: | |
2989 | { | |
2990 | unsigned long ret = time (PARM1 ? MEMPTR (PARM1) : NULL); | |
2991 | RETVAL_HIGH = ret >> 16; | |
2992 | RETVAL_LOW = ret & 0xffff; | |
2993 | } | |
2994 | trace_input ("<time>", OP_R0, OP_R1, OP_R2); | |
2995 | trace_output (OP_R0R1); | |
2996 | break; | |
2997 | #endif | |
2998 | ||
2999 | default: | |
3000 | abort (); | |
3001 | } | |
3002 | RETERR = (RETVAL == (uint16) -1) ? d10v_callback->get_errno(d10v_callback) : 0; | |
3003 | break; | |
3004 | } | |
3005 | } | |
3006 | } | |
3007 | ||
3008 | /* tst0i */ | |
3009 | void | |
3010 | OP_7000000 () | |
3011 | { | |
3012 | trace_input ("tst0i", OP_REG, OP_CONSTANT16, OP_VOID); | |
3013 | State.F1 = State.F0; | |
3014 | State.F0 = (State.regs[OP[0]] & OP[1]) ? 1 : 0; | |
3015 | trace_output (OP_FLAG); | |
3016 | } | |
3017 | ||
3018 | /* tst1i */ | |
3019 | void | |
3020 | OP_F000000 () | |
3021 | { | |
3022 | trace_input ("tst1i", OP_REG, OP_CONSTANT16, OP_VOID); | |
3023 | State.F1 = State.F0; | |
3024 | State.F0 = (~(State.regs[OP[0]]) & OP[1]) ? 1 : 0; | |
3025 | trace_output (OP_FLAG); | |
3026 | } | |
3027 | ||
3028 | /* wait */ | |
3029 | void | |
3030 | OP_5F80 () | |
3031 | { | |
3032 | trace_input ("wait", OP_VOID, OP_VOID, OP_VOID); | |
3033 | State.IE = 1; | |
3034 | trace_output (OP_VOID); | |
3035 | } | |
3036 | ||
3037 | /* xor */ | |
3038 | void | |
3039 | OP_A00 () | |
3040 | { | |
3041 | trace_input ("xor", OP_REG, OP_REG, OP_VOID); | |
3042 | State.regs[OP[0]] ^= State.regs[OP[1]]; | |
3043 | trace_output (OP_REG); | |
3044 | } | |
3045 | ||
3046 | /* xor3 */ | |
3047 | void | |
3048 | OP_5000000 () | |
3049 | { | |
3050 | trace_input ("xor3", OP_REG_OUTPUT, OP_REG, OP_CONSTANT16); | |
3051 | State.regs[OP[0]] = State.regs[OP[1]] ^ OP[2]; | |
3052 | trace_output (OP_REG); | |
3053 | } | |
3054 |