arch/arc/cpu/arc700/cache.c

   1 /*
   2  * Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved.
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 #include <config.h>
   8 #include <asm/arcregs.h>
   9
  10 /* Bit values in IC_CTRL */
  11 #define IC_CTRL_CACHE_DISABLE   (1 << 0)
  12
  13 /* Bit values in DC_CTRL */
  14 #define DC_CTRL_CACHE_DISABLE   (1 << 0)
  15 #define DC_CTRL_INV_MODE_FLUSH  (1 << 6)
  16 #define DC_CTRL_FLUSH_STATUS    (1 << 8)
  17
  18 int icache_status(void)
  19 {
  20         return (read_aux_reg(ARC_AUX_IC_CTRL) & IC_CTRL_CACHE_DISABLE) !=
  21                IC_CTRL_CACHE_DISABLE;
  22 }
  23
  24 void icache_enable(void)
  25 {
  26         write_aux_reg(ARC_AUX_IC_CTRL, read_aux_reg(ARC_AUX_IC_CTRL) &
  27                       ~IC_CTRL_CACHE_DISABLE);
  28 }
  29
  30 void icache_disable(void)
  31 {
  32         write_aux_reg(ARC_AUX_IC_CTRL, read_aux_reg(ARC_AUX_IC_CTRL) |
  33                       IC_CTRL_CACHE_DISABLE);
  34 }
  35
  36 void invalidate_icache_all(void)
  37 {
  38 #ifndef CONFIG_SYS_ICACHE_OFF
  39         /* Any write to IC_IVIC register triggers invalidation of entire I$ */
  40         write_aux_reg(ARC_AUX_IC_IVIC, 1);
  41 #endif /* CONFIG_SYS_ICACHE_OFF */
  42 }
  43
  44 int dcache_status(void)
  45 {
  46         return (read_aux_reg(ARC_AUX_DC_CTRL) & DC_CTRL_CACHE_DISABLE) !=
  47                 DC_CTRL_CACHE_DISABLE;
  48 }
  49
  50 void dcache_enable(void)
  51 {
  52         write_aux_reg(ARC_AUX_DC_CTRL, read_aux_reg(ARC_AUX_DC_CTRL) &
  53                       ~(DC_CTRL_INV_MODE_FLUSH | DC_CTRL_CACHE_DISABLE));
  54 }
  55
  56 void dcache_disable(void)
  57 {
  58         write_aux_reg(ARC_AUX_DC_CTRL, read_aux_reg(ARC_AUX_DC_CTRL) |
  59                       DC_CTRL_CACHE_DISABLE);
  60 }
  61
  62 void flush_dcache_all(void)
  63 {
  64         /* Do flush of entire cache */
  65         write_aux_reg(ARC_AUX_DC_FLSH, 1);
  66
  67         /* Wait flush end */
  68         while (read_aux_reg(ARC_AUX_DC_CTRL) & DC_CTRL_FLUSH_STATUS)
  69                 ;
  70 }
  71
  72 #ifndef CONFIG_SYS_DCACHE_OFF
  73 static void dcache_flush_line(unsigned addr)
  74 {
  75 #if (CONFIG_ARC_MMU_VER > 2)
  76         write_aux_reg(ARC_AUX_DC_PTAG, addr);
  77 #endif
  78         write_aux_reg(ARC_AUX_DC_FLDL, addr);
  79
  80         /* Wait flush end */
  81         while (read_aux_reg(ARC_AUX_DC_CTRL) & DC_CTRL_FLUSH_STATUS)
  82                 ;
  83
  84 #ifndef CONFIG_SYS_ICACHE_OFF
  85         /*
  86          * Invalidate I$ for addresses range just flushed from D$.
  87          * If we try to execute data flushed above it will be valid/correct
  88          */
  89 #if (CONFIG_ARC_MMU_VER > 2)
  90         write_aux_reg(ARC_AUX_IC_PTAG, addr);
  91 #endif
  92         write_aux_reg(ARC_AUX_IC_IVIL, addr);
  93 #endif /* CONFIG_SYS_ICACHE_OFF */
  94 }
  95 #endif /* CONFIG_SYS_DCACHE_OFF */
  96
  97 void flush_dcache_range(unsigned long start, unsigned long end)
  98 {
  99 #ifndef CONFIG_SYS_DCACHE_OFF
 100         unsigned int addr;
 101
 102         start = start & (~(CONFIG_SYS_CACHELINE_SIZE - 1));
 103         end = end & (~(CONFIG_SYS_CACHELINE_SIZE - 1));
 104
 105         for (addr = start; addr <= end; addr += CONFIG_SYS_CACHELINE_SIZE)
 106                 dcache_flush_line(addr);
 107 #endif /* CONFIG_SYS_DCACHE_OFF */
 108 }
 109
 110 void invalidate_dcache_range(unsigned long start, unsigned long end)
 111 {
 112 #ifndef CONFIG_SYS_DCACHE_OFF
 113         unsigned int addr;
 114
 115         start = start & (~(CONFIG_SYS_CACHELINE_SIZE - 1));
 116         end = end & (~(CONFIG_SYS_CACHELINE_SIZE - 1));
 117
 118         for (addr = start; addr <= end; addr += CONFIG_SYS_CACHELINE_SIZE) {
 119 #if (CONFIG_ARC_MMU_VER > 2)
 120                 write_aux_reg(ARC_AUX_DC_PTAG, addr);
 121 #endif
 122                 write_aux_reg(ARC_AUX_DC_IVDL, addr);
 123         }
 124 #endif /* CONFIG_SYS_DCACHE_OFF */
 125 }
 126
 127 void invalidate_dcache_all(void)
 128 {
 129 #ifndef CONFIG_SYS_DCACHE_OFF
 130         /* Write 1 to DC_IVDC register triggers invalidation of entire D$ */
 131         write_aux_reg(ARC_AUX_DC_IVDC, 1);
 132 #endif /* CONFIG_SYS_DCACHE_OFF */
 133 }
 134
 135 void flush_cache(unsigned long start, unsigned long size)
 136 {
 137         flush_dcache_range(start, start + size);
 138 }