arch/arc/include/asm/io.h

   1 /*
   2  * Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved.
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 #ifndef __ASM_ARC_IO_H
   8 #define __ASM_ARC_IO_H
   9
  10 #include <linux/types.h>
  11 #include <asm/byteorder.h>
  12
  13 #ifdef CONFIG_ISA_ARCV2
  14
  15 /*
  16  * ARCv2 based HS38 cores are in-order issue, but still weakly ordered
  17  * due to micro-arch buffering/queuing of load/store, cache hit vs. miss ...
  18  *
  19  * Explicit barrier provided by DMB instruction
  20  *  - Operand supports fine grained load/store/load+store semantics
  21  *  - Ensures that selected memory operation issued before it will complete
  22  *    before any subsequent memory operation of same type
  23  *  - DMB guarantees SMP as well as local barrier semantics
  24  *    (asm-generic/barrier.h ensures sane smp_*mb if not defined here, i.e.
  25  *    UP: barrier(), SMP: smp_*mb == *mb)
  26  *  - DSYNC provides DMB+completion_of_cache_bpu_maintenance_ops hence not needed
  27  *    in the general case. Plus it only provides full barrier.
  28  */
  29
  30 #define mb()    asm volatile("dmb 3\n" : : : "memory")
  31 #define rmb()   asm volatile("dmb 1\n" : : : "memory")
  32 #define wmb()   asm volatile("dmb 2\n" : : : "memory")
  33
  34 #else
  35
  36 /*
  37  * ARCompact based cores (ARC700) only have SYNC instruction which is super
  38  * heavy weight as it flushes the pipeline as well.
  39  * There are no real SMP implementations of such cores.
  40  */
  41
  42 #define mb()    asm volatile("sync\n" : : : "memory")
  43 #endif
  44
  45 #ifdef CONFIG_ISA_ARCV2
  46 #define __iormb()               rmb()
  47 #define __iowmb()               wmb()
  48 #else
  49 #define __iormb()               do { } while (0)
  50 #define __iowmb()               do { } while (0)
  51 #endif
  52
  53 /*
  54  * Given a physical address and a length, return a virtual address
  55  * that can be used to access the memory range with the caching
  56  * properties specified by "flags".
  57  */
  58 #define MAP_NOCACHE     (0)
  59 #define MAP_WRCOMBINE   (0)
  60 #define MAP_WRBACK      (0)
  61 #define MAP_WRTHROUGH   (0)
  62
  63 static inline void *
  64 map_physmem(phys_addr_t paddr, unsigned long len, unsigned long flags)
  65 {
  66         return (void *)((unsigned long)paddr);
  67 }
  68
  69 /*
  70  * Take down a mapping set up by map_physmem().
  71  */
  72 static inline void unmap_physmem(void *vaddr, unsigned long flags)
  73 {
  74
  75 }
  76
  77 static inline void sync(void)
  78 {
  79         /* Not yet implemented */
  80 }
  81
  82 static inline u8 __raw_readb(const volatile void __iomem *addr)
  83 {
  84         u8 b;
  85
  86         __asm__ __volatile__("ldb%U1    %0, %1\n"
  87                              : "=r" (b)
  88                              : "m" (*(volatile u8 __force *)addr)
  89                              : "memory");
  90         return b;
  91 }
  92
  93 static inline u16 __raw_readw(const volatile void __iomem *addr)
  94 {
  95         u16 s;
  96
  97         __asm__ __volatile__("ldw%U1    %0, %1\n"
  98                              : "=r" (s)
  99                              : "m" (*(volatile u16 __force *)addr)
 100                              : "memory");
 101         return s;
 102 }
 103
 104 static inline u32 __raw_readl(const volatile void __iomem *addr)
 105 {
 106         u32 w;
 107
 108         __asm__ __volatile__("ld%U1     %0, %1\n"
 109                              : "=r" (w)
 110                              : "m" (*(volatile u32 __force *)addr)
 111                              : "memory");
 112         return w;
 113 }
 114
 115 static inline void __raw_writeb(u8 b, volatile void __iomem *addr)
 116 {
 117         __asm__ __volatile__("stb%U1    %0, %1\n"
 118                              :
 119                              : "r" (b), "m" (*(volatile u8 __force *)addr)
 120                              : "memory");
 121 }
 122
 123 static inline void __raw_writew(u16 s, volatile void __iomem *addr)
 124 {
 125         __asm__ __volatile__("stw%U1    %0, %1\n"
 126                              :
 127                              : "r" (s), "m" (*(volatile u16 __force *)addr)
 128                              : "memory");
 129 }
 130
 131 static inline void __raw_writel(u32 w, volatile void __iomem *addr)
 132 {
 133         __asm__ __volatile__("st%U1     %0, %1\n"
 134                              :
 135                              : "r" (w), "m" (*(volatile u32 __force *)addr)
 136                              : "memory");
 137 }
 138
 139 static inline int __raw_readsb(unsigned int addr, void *data, int bytelen)
 140 {
 141         __asm__ __volatile__ ("1:ld.di  r8, [r0]\n"
 142                               "sub.f    r2, r2, 1\n"
 143                               "bnz.d    1b\n"
 144                               "stb.ab   r8, [r1, 1]\n"
 145                               :
 146                               : "r" (addr), "r" (data), "r" (bytelen)
 147                               : "r8");
 148         return bytelen;
 149 }
 150
 151 static inline int __raw_readsw(unsigned int addr, void *data, int wordlen)
 152 {
 153         __asm__ __volatile__ ("1:ld.di  r8, [r0]\n"
 154                               "sub.f    r2, r2, 1\n"
 155                               "bnz.d    1b\n"
 156                               "stw.ab   r8, [r1, 2]\n"
 157                               :
 158                               : "r" (addr), "r" (data), "r" (wordlen)
 159                               : "r8");
 160         return wordlen;
 161 }
 162
 163 static inline int __raw_readsl(unsigned int addr, void *data, int longlen)
 164 {
 165         __asm__ __volatile__ ("1:ld.di  r8, [r0]\n"
 166                               "sub.f    r2, r2, 1\n"
 167                               "bnz.d    1b\n"
 168                               "st.ab    r8, [r1, 4]\n"
 169                               :
 170                               : "r" (addr), "r" (data), "r" (longlen)
 171                               : "r8");
 172         return longlen;
 173 }
 174
 175 static inline int __raw_writesb(unsigned int addr, void *data, int bytelen)
 176 {
 177         __asm__ __volatile__ ("1:ldb.ab r8, [r1, 1]\n"
 178                               "sub.f    r2, r2, 1\n"
 179                               "bnz.d    1b\n"
 180                               "st.di    r8, [r0, 0]\n"
 181                               :
 182                               : "r" (addr), "r" (data), "r" (bytelen)
 183                               : "r8");
 184         return bytelen;
 185 }
 186
 187 static inline int __raw_writesw(unsigned int addr, void *data, int wordlen)
 188 {
 189         __asm__ __volatile__ ("1:ldw.ab r8, [r1, 2]\n"
 190                               "sub.f    r2, r2, 1\n"
 191                               "bnz.d    1b\n"
 192                               "st.ab.di r8, [r0, 0]\n"
 193                               :
 194                               : "r" (addr), "r" (data), "r" (wordlen)
 195                               : "r8");
 196         return wordlen;
 197 }
 198
 199 static inline int __raw_writesl(unsigned int addr, void *data, int longlen)
 200 {
 201         __asm__ __volatile__ ("1:ld.ab  r8, [r1, 4]\n"
 202                               "sub.f    r2, r2, 1\n"
 203                               "bnz.d    1b\n"
 204                               "st.ab.di r8, [r0, 0]\n"
 205                               :
 206                               : "r" (addr), "r" (data), "r" (longlen)
 207                               : "r8");
 208         return longlen;
 209 }
 210
 211 /*
 212  * MMIO can also get buffered/optimized in micro-arch, so barriers needed
 213  * Based on ARM model for the typical use case
 214  *
 215  *      <ST [DMA buffer]>
 216  *      <writel MMIO "go" reg>
 217  *  or:
 218  *      <readl MMIO "status" reg>
 219  *      <LD [DMA buffer]>
 220  *
 221  * http://lkml.kernel.org/r/20150622133656.GG1583@arm.com
 222  */
 223 #define readb(c)                ({ u8  __v = readb_relaxed(c); __iormb(); __v; })
 224 #define readw(c)                ({ u16 __v = readw_relaxed(c); __iormb(); __v; })
 225 #define readl(c)                ({ u32 __v = readl_relaxed(c); __iormb(); __v; })
 226
 227 #define writeb(v,c)             ({ __iowmb(); writeb_relaxed(v,c); })
 228 #define writew(v,c)             ({ __iowmb(); writew_relaxed(v,c); })
 229 #define writel(v,c)             ({ __iowmb(); writel_relaxed(v,c); })
 230
 231 /*
 232  * Relaxed API for drivers which can handle barrier ordering themselves
 233  *
 234  * Also these are defined to perform little endian accesses.
 235  * To provide the typical device register semantics of fixed endian,
 236  * swap the byte order for Big Endian
 237  *
 238  * http://lkml.kernel.org/r/201603100845.30602.arnd@arndb.de
 239  */
 240 #define readb_relaxed(c)        __raw_readb(c)
 241 #define readw_relaxed(c) ({ u16 __r = le16_to_cpu((__force __le16) \
 242                                         __raw_readw(c)); __r; })
 243 #define readl_relaxed(c) ({ u32 __r = le32_to_cpu((__force __le32) \
 244                                         __raw_readl(c)); __r; })
 245
 246 #define writeb_relaxed(v,c)     __raw_writeb(v,c)
 247 #define writew_relaxed(v,c)     __raw_writew((__force u16) cpu_to_le16(v),c)
 248 #define writel_relaxed(v,c)     __raw_writel((__force u32) cpu_to_le32(v),c)
 249
 250 #define out_arch(type, endian, a, v)    __raw_write##type(cpu_to_##endian(v), a)
 251 #define in_arch(type, endian, a)        endian##_to_cpu(__raw_read##type(a))
 252
 253 #define out_le32(a, v)  out_arch(l, le32, a, v)
 254 #define out_le16(a, v)  out_arch(w, le16, a, v)
 255
 256 #define in_le32(a)      in_arch(l, le32, a)
 257 #define in_le16(a)      in_arch(w, le16, a)
 258
 259 #define out_be32(a, v)  out_arch(l, be32, a, v)
 260 #define out_be16(a, v)  out_arch(w, be16, a, v)
 261
 262 #define in_be32(a)      in_arch(l, be32, a)
 263 #define in_be16(a)      in_arch(w, be16, a)
 264
 265 #define out_8(a, v)     __raw_writeb(v, a)
 266 #define in_8(a)         __raw_readb(a)
 267
 268 /*
 269  * Clear and set bits in one shot. These macros can be used to clear and
 270  * set multiple bits in a register using a single call. These macros can
 271  * also be used to set a multiple-bit bit pattern using a mask, by
 272  * specifying the mask in the 'clear' parameter and the new bit pattern
 273  * in the 'set' parameter.
 274  */
 275
 276 #define clrbits(type, addr, clear) \
 277         out_##type((addr), in_##type(addr) & ~(clear))
 278
 279 #define setbits(type, addr, set) \
 280         out_##type((addr), in_##type(addr) | (set))
 281
 282 #define clrsetbits(type, addr, clear, set) \
 283         out_##type((addr), (in_##type(addr) & ~(clear)) | (set))
 284
 285 #define clrbits_be32(addr, clear) clrbits(be32, addr, clear)
 286 #define setbits_be32(addr, set) setbits(be32, addr, set)
 287 #define clrsetbits_be32(addr, clear, set) clrsetbits(be32, addr, clear, set)
 288
 289 #define clrbits_le32(addr, clear) clrbits(le32, addr, clear)
 290 #define setbits_le32(addr, set) setbits(le32, addr, set)
 291 #define clrsetbits_le32(addr, clear, set) clrsetbits(le32, addr, clear, set)
 292
 293 #define clrbits_be16(addr, clear) clrbits(be16, addr, clear)
 294 #define setbits_be16(addr, set) setbits(be16, addr, set)
 295 #define clrsetbits_be16(addr, clear, set) clrsetbits(be16, addr, clear, set)
 296
 297 #define clrbits_le16(addr, clear) clrbits(le16, addr, clear)
 298 #define setbits_le16(addr, set) setbits(le16, addr, set)
 299 #define clrsetbits_le16(addr, clear, set) clrsetbits(le16, addr, clear, set)
 300
 301 #define clrbits_8(addr, clear) clrbits(8, addr, clear)
 302 #define setbits_8(addr, set) setbits(8, addr, set)
 303 #define clrsetbits_8(addr, clear, set) clrsetbits(8, addr, clear, set)
 304
 305 static inline phys_addr_t virt_to_phys(void *vaddr)
 306 {
 307         return (phys_addr_t)((unsigned long)vaddr);
 308 }
 309
 310 #endif  /* __ASM_ARC_IO_H */