arch/arm/Kconfig

   1 # SPDX-License-Identifier: GPL-2.0
   2 config ARM
   3         bool
   4         default y
   5         select ARCH_CLOCKSOURCE_DATA
   6         select ARCH_HAS_DEBUG_VIRTUAL
   7         select ARCH_HAS_DEVMEM_IS_ALLOWED
   8         select ARCH_HAS_ELF_RANDOMIZE
   9         select ARCH_HAS_SET_MEMORY
  10         select ARCH_HAS_STRICT_KERNEL_RWX if MMU && !XIP_KERNEL
  11         select ARCH_HAS_STRICT_MODULE_RWX if MMU
  12         select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
  13         select ARCH_HAVE_CUSTOM_GPIO_H
  14         select ARCH_HAS_GCOV_PROFILE_ALL
  15         select ARCH_MIGHT_HAVE_PC_PARPORT
  16         select ARCH_OPTIONAL_KERNEL_RWX if ARCH_HAS_STRICT_KERNEL_RWX
  17         select ARCH_OPTIONAL_KERNEL_RWX_DEFAULT if CPU_V7
  18         select ARCH_SUPPORTS_ATOMIC_RMW
  19         select ARCH_USE_BUILTIN_BSWAP
  20         select ARCH_USE_CMPXCHG_LOCKREF
  21         select ARCH_WANT_IPC_PARSE_VERSION
  22         select BUILDTIME_EXTABLE_SORT if MMU
  23         select CLONE_BACKWARDS
  24         select CPU_PM if (SUSPEND || CPU_IDLE)
  25         select DCACHE_WORD_ACCESS if HAVE_EFFICIENT_UNALIGNED_ACCESS
  26         select DMA_NOOP_OPS if !MMU
  27         select EDAC_SUPPORT
  28         select EDAC_ATOMIC_SCRUB
  29         select GENERIC_ALLOCATOR
  30         select GENERIC_ARCH_TOPOLOGY if ARM_CPU_TOPOLOGY
  31         select GENERIC_ATOMIC64 if (CPU_V7M || CPU_V6 || !CPU_32v6K || !AEABI)
  32         select GENERIC_CLOCKEVENTS_BROADCAST if SMP
  33         select GENERIC_CPU_AUTOPROBE
  34         select GENERIC_EARLY_IOREMAP
  35         select GENERIC_IDLE_POLL_SETUP
  36         select GENERIC_IRQ_PROBE
  37         select GENERIC_IRQ_SHOW
  38         select GENERIC_IRQ_SHOW_LEVEL
  39         select GENERIC_PCI_IOMAP
  40         select GENERIC_SCHED_CLOCK
  41         select GENERIC_SMP_IDLE_THREAD
  42         select GENERIC_STRNCPY_FROM_USER
  43         select GENERIC_STRNLEN_USER
  44         select HANDLE_DOMAIN_IRQ
  45         select HARDIRQS_SW_RESEND
  46         select HAVE_ARCH_AUDITSYSCALL if (AEABI && !OABI_COMPAT)
  47         select HAVE_ARCH_BITREVERSE if (CPU_32v7M || CPU_32v7) && !CPU_32v6
  48         select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL && !CPU_ENDIAN_BE32 && MMU
  49         select HAVE_ARCH_KGDB if !CPU_ENDIAN_BE32 && MMU
  50         select HAVE_ARCH_MMAP_RND_BITS if MMU
  51         select HAVE_ARCH_SECCOMP_FILTER if (AEABI && !OABI_COMPAT)
  52         select HAVE_ARCH_TRACEHOOK
  53         select HAVE_ARM_SMCCC if CPU_V7
  54         select HAVE_EBPF_JIT if !CPU_ENDIAN_BE32
  55         select HAVE_CC_STACKPROTECTOR
  56         select HAVE_CONTEXT_TRACKING
  57         select HAVE_C_RECORDMCOUNT
  58         select HAVE_DEBUG_KMEMLEAK
  59         select HAVE_DMA_API_DEBUG
  60         select HAVE_DMA_CONTIGUOUS if MMU
  61         select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL) && !CPU_ENDIAN_BE32 && MMU
  62         select HAVE_DYNAMIC_FTRACE_WITH_REGS if HAVE_DYNAMIC_FTRACE
  63         select HAVE_EFFICIENT_UNALIGNED_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && MMU
  64         select HAVE_EXIT_THREAD
  65         select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL)
  66         select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL)
  67         select HAVE_FUNCTION_TRACER if (!XIP_KERNEL)
  68         select HAVE_GCC_PLUGINS
  69         select HAVE_GENERIC_DMA_COHERENT
  70         select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7))
  71         select HAVE_IDE if PCI || ISA || PCMCIA
  72         select HAVE_IRQ_TIME_ACCOUNTING
  73         select HAVE_KERNEL_GZIP
  74         select HAVE_KERNEL_LZ4
  75         select HAVE_KERNEL_LZMA
  76         select HAVE_KERNEL_LZO
  77         select HAVE_KERNEL_XZ
  78         select HAVE_KPROBES if !XIP_KERNEL && !CPU_ENDIAN_BE32 && !CPU_V7M
  79         select HAVE_KRETPROBES if (HAVE_KPROBES)
  80         select HAVE_MEMBLOCK
  81         select HAVE_MOD_ARCH_SPECIFIC
  82         select HAVE_NMI
  83         select HAVE_OPROFILE if (HAVE_PERF_EVENTS)
  84         select HAVE_OPTPROBES if !THUMB2_KERNEL
  85         select HAVE_PERF_EVENTS
  86         select HAVE_PERF_REGS
  87         select HAVE_PERF_USER_STACK_DUMP
  88         select HAVE_RCU_TABLE_FREE if (SMP && ARM_LPAE)
  89         select HAVE_REGS_AND_STACK_ACCESS_API
  90         select HAVE_SYSCALL_TRACEPOINTS
  91         select HAVE_UID16
  92         select HAVE_VIRT_CPU_ACCOUNTING_GEN
  93         select IRQ_FORCED_THREADING
  94         select MODULES_USE_ELF_REL
  95         select NO_BOOTMEM
  96         select OF_EARLY_FLATTREE if OF
  97         select OF_RESERVED_MEM if OF
  98         select OLD_SIGACTION
  99         select OLD_SIGSUSPEND3
 100         select PERF_USE_VMALLOC
 101         select RTC_LIB
 102         select SYS_SUPPORTS_APM_EMULATION
 103         # Above selects are sorted alphabetically; please add new ones
 104         # according to that.  Thanks.
 105         help
 106           The ARM series is a line of low-power-consumption RISC chip designs
 107           licensed by ARM Ltd and targeted at embedded applications and
 108           handhelds such as the Compaq IPAQ.  ARM-based PCs are no longer
 109           manufactured, but legacy ARM-based PC hardware remains popular in
 110           Europe.  There is an ARM Linux project with a web page at
 111           <http://www.arm.linux.org.uk/>.
 112
 113 config ARM_HAS_SG_CHAIN
 114         select ARCH_HAS_SG_CHAIN
 115         bool
 116
 117 config NEED_SG_DMA_LENGTH
 118         bool
 119
 120 config ARM_DMA_USE_IOMMU
 121         bool
 122         select ARM_HAS_SG_CHAIN
 123         select NEED_SG_DMA_LENGTH
 124
 125 if ARM_DMA_USE_IOMMU
 126
 127 config ARM_DMA_IOMMU_ALIGNMENT
 128         int "Maximum PAGE_SIZE order of alignment for DMA IOMMU buffers"
 129         range 4 9
 130         default 8
 131         help
 132           DMA mapping framework by default aligns all buffers to the smallest
 133           PAGE_SIZE order which is greater than or equal to the requested buffer
 134           size. This works well for buffers up to a few hundreds kilobytes, but
 135           for larger buffers it just a waste of address space. Drivers which has
 136           relatively small addressing window (like 64Mib) might run out of
 137           virtual space with just a few allocations.
 138
 139           With this parameter you can specify the maximum PAGE_SIZE order for
 140           DMA IOMMU buffers. Larger buffers will be aligned only to this
 141           specified order. The order is expressed as a power of two multiplied
 142           by the PAGE_SIZE.
 143
 144 endif
 145
 146 config MIGHT_HAVE_PCI
 147         bool
 148
 149 config SYS_SUPPORTS_APM_EMULATION
 150         bool
 151
 152 config HAVE_TCM
 153         bool
 154         select GENERIC_ALLOCATOR
 155
 156 config HAVE_PROC_CPU
 157         bool
 158
 159 config NO_IOPORT_MAP
 160         bool
 161
 162 config EISA
 163         bool
 164         ---help---
 165           The Extended Industry Standard Architecture (EISA) bus was
 166           developed as an open alternative to the IBM MicroChannel bus.
 167
 168           The EISA bus provided some of the features of the IBM MicroChannel
 169           bus while maintaining backward compatibility with cards made for
 170           the older ISA bus.  The EISA bus saw limited use between 1988 and
 171           1995 when it was made obsolete by the PCI bus.
 172
 173           Say Y here if you are building a kernel for an EISA-based machine.
 174
 175           Otherwise, say N.
 176
 177 config SBUS
 178         bool
 179
 180 config STACKTRACE_SUPPORT
 181         bool
 182         default y
 183
 184 config LOCKDEP_SUPPORT
 185         bool
 186         default y
 187
 188 config TRACE_IRQFLAGS_SUPPORT
 189         bool
 190         default !CPU_V7M
 191
 192 config RWSEM_XCHGADD_ALGORITHM
 193         bool
 194         default y
 195
 196 config ARCH_HAS_ILOG2_U32
 197         bool
 198
 199 config ARCH_HAS_ILOG2_U64
 200         bool
 201
 202 config ARCH_HAS_BANDGAP
 203         bool
 204
 205 config FIX_EARLYCON_MEM
 206         def_bool y if MMU
 207
 208 config GENERIC_HWEIGHT
 209         bool
 210         default y
 211
 212 config GENERIC_CALIBRATE_DELAY
 213         bool
 214         default y
 215
 216 config ARCH_MAY_HAVE_PC_FDC
 217         bool
 218
 219 config ZONE_DMA
 220         bool
 221
 222 config NEED_DMA_MAP_STATE
 223        def_bool y
 224
 225 config ARCH_SUPPORTS_UPROBES
 226         def_bool y
 227
 228 config ARCH_HAS_DMA_SET_COHERENT_MASK
 229         bool
 230
 231 config GENERIC_ISA_DMA
 232         bool
 233
 234 config FIQ
 235         bool
 236
 237 config NEED_RET_TO_USER
 238         bool
 239
 240 config ARCH_MTD_XIP
 241         bool
 242
 243 config VECTORS_BASE
 244         hex
 245         default 0xffff0000 if MMU || CPU_HIGH_VECTOR
 246         default DRAM_BASE if REMAP_VECTORS_TO_RAM
 247         default 0x00000000
 248         help
 249           The base address of exception vectors.  This must be two pages
 250           in size.
 251
 252 config ARM_PATCH_PHYS_VIRT
 253         bool "Patch physical to virtual translations at runtime" if EMBEDDED
 254         default y
 255         depends on !XIP_KERNEL && MMU
 256         help
 257           Patch phys-to-virt and virt-to-phys translation functions at
 258           boot and module load time according to the position of the
 259           kernel in system memory.
 260
 261           This can only be used with non-XIP MMU kernels where the base
 262           of physical memory is at a 16MB boundary.
 263
 264           Only disable this option if you know that you do not require
 265           this feature (eg, building a kernel for a single machine) and
 266           you need to shrink the kernel to the minimal size.
 267
 268 config NEED_MACH_IO_H
 269         bool
 270         help
 271           Select this when mach/io.h is required to provide special
 272           definitions for this platform.  The need for mach/io.h should
 273           be avoided when possible.
 274
 275 config NEED_MACH_MEMORY_H
 276         bool
 277         help
 278           Select this when mach/memory.h is required to provide special
 279           definitions for this platform.  The need for mach/memory.h should
 280           be avoided when possible.
 281
 282 config PHYS_OFFSET
 283         hex "Physical address of main memory" if MMU
 284         depends on !ARM_PATCH_PHYS_VIRT
 285         default DRAM_BASE if !MMU
 286         default 0x00000000 if ARCH_EBSA110 || \
 287                         ARCH_FOOTBRIDGE || \
 288                         ARCH_INTEGRATOR || \
 289                         ARCH_IOP13XX || \
 290                         ARCH_KS8695 || \
 291                         ARCH_REALVIEW
 292         default 0x10000000 if ARCH_OMAP1 || ARCH_RPC
 293         default 0x20000000 if ARCH_S5PV210
 294         default 0xc0000000 if ARCH_SA1100
 295         help
 296           Please provide the physical address corresponding to the
 297           location of main memory in your system.
 298
 299 config GENERIC_BUG
 300         def_bool y
 301         depends on BUG
 302
 303 config PGTABLE_LEVELS
 304         int
 305         default 3 if ARM_LPAE
 306         default 2
 307
 308 source "init/Kconfig"
 309
 310 source "kernel/Kconfig.freezer"
 311
 312 menu "System Type"
 313
 314 config MMU
 315         bool "MMU-based Paged Memory Management Support"
 316         default y
 317         help
 318           Select if you want MMU-based virtualised addressing space
 319           support by paged memory management. If unsure, say 'Y'.
 320
 321 config ARCH_MMAP_RND_BITS_MIN
 322         default 8
 323
 324 config ARCH_MMAP_RND_BITS_MAX
 325         default 14 if PAGE_OFFSET=0x40000000
 326         default 15 if PAGE_OFFSET=0x80000000
 327         default 16
 328
 329 #
 330 # The "ARM system type" choice list is ordered alphabetically by option
 331 # text.  Please add new entries in the option alphabetic order.
 332 #
 333 choice
 334         prompt "ARM system type"
 335         default ARM_SINGLE_ARMV7M if !MMU
 336         default ARCH_MULTIPLATFORM if MMU
 337
 338 config ARCH_MULTIPLATFORM
 339         bool "Allow multiple platforms to be selected"
 340         depends on MMU
 341         select ARM_HAS_SG_CHAIN
 342         select ARM_PATCH_PHYS_VIRT
 343         select AUTO_ZRELADDR
 344         select TIMER_OF
 345         select COMMON_CLK
 346         select GENERIC_CLOCKEVENTS
 347         select MIGHT_HAVE_PCI
 348         select MULTI_IRQ_HANDLER
 349         select PCI_DOMAINS if PCI
 350         select SPARSE_IRQ
 351         select USE_OF
 352
 353 config ARM_SINGLE_ARMV7M
 354         bool "ARMv7-M based platforms (Cortex-M0/M3/M4)"
 355         depends on !MMU
 356         select ARM_NVIC
 357         select AUTO_ZRELADDR
 358         select TIMER_OF
 359         select COMMON_CLK
 360         select CPU_V7M
 361         select GENERIC_CLOCKEVENTS
 362         select NO_IOPORT_MAP
 363         select SPARSE_IRQ
 364         select USE_OF
 365
 366 config ARCH_EBSA110
 367         bool "EBSA-110"
 368         select ARCH_USES_GETTIMEOFFSET
 369         select CPU_SA110
 370         select ISA
 371         select NEED_MACH_IO_H
 372         select NEED_MACH_MEMORY_H
 373         select NO_IOPORT_MAP
 374         help
 375           This is an evaluation board for the StrongARM processor available
 376           from Digital. It has limited hardware on-board, including an
 377           Ethernet interface, two PCMCIA sockets, two serial ports and a
 378           parallel port.
 379
 380 config ARCH_EP93XX
 381         bool "EP93xx-based"
 382         select ARCH_HAS_HOLES_MEMORYMODEL
 383         select ARM_AMBA
 384         imply ARM_PATCH_PHYS_VIRT
 385         select ARM_VIC
 386         select AUTO_ZRELADDR
 387         select CLKDEV_LOOKUP
 388         select CLKSRC_MMIO
 389         select CPU_ARM920T
 390         select GENERIC_CLOCKEVENTS
 391         select GPIOLIB
 392         help
 393           This enables support for the Cirrus EP93xx series of CPUs.
 394
 395 config ARCH_FOOTBRIDGE
 396         bool "FootBridge"
 397         select CPU_SA110
 398         select FOOTBRIDGE
 399         select GENERIC_CLOCKEVENTS
 400         select HAVE_IDE
 401         select NEED_MACH_IO_H if !MMU
 402         select NEED_MACH_MEMORY_H
 403         help
 404           Support for systems based on the DC21285 companion chip
 405           ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
 406
 407 config ARCH_NETX
 408         bool "Hilscher NetX based"
 409         select ARM_VIC
 410         select CLKSRC_MMIO
 411         select CPU_ARM926T
 412         select GENERIC_CLOCKEVENTS
 413         help
 414           This enables support for systems based on the Hilscher NetX Soc
 415
 416 config ARCH_IOP13XX
 417         bool "IOP13xx-based"
 418         depends on MMU
 419         select CPU_XSC3
 420         select NEED_MACH_MEMORY_H
 421         select NEED_RET_TO_USER
 422         select PCI
 423         select PLAT_IOP
 424         select VMSPLIT_1G
 425         select SPARSE_IRQ
 426         help
 427           Support for Intel's IOP13XX (XScale) family of processors.
 428
 429 config ARCH_IOP32X
 430         bool "IOP32x-based"
 431         depends on MMU
 432         select CPU_XSCALE
 433         select GPIO_IOP
 434         select GPIOLIB
 435         select NEED_RET_TO_USER
 436         select PCI
 437         select PLAT_IOP
 438         help
 439           Support for Intel's 80219 and IOP32X (XScale) family of
 440           processors.
 441
 442 config ARCH_IOP33X
 443         bool "IOP33x-based"
 444         depends on MMU
 445         select CPU_XSCALE
 446         select GPIO_IOP
 447         select GPIOLIB
 448         select NEED_RET_TO_USER
 449         select PCI
 450         select PLAT_IOP
 451         help
 452           Support for Intel's IOP33X (XScale) family of processors.
 453
 454 config ARCH_IXP4XX
 455         bool "IXP4xx-based"
 456         depends on MMU
 457         select ARCH_HAS_DMA_SET_COHERENT_MASK
 458         select ARCH_SUPPORTS_BIG_ENDIAN
 459         select CLKSRC_MMIO
 460         select CPU_XSCALE
 461         select DMABOUNCE if PCI
 462         select GENERIC_CLOCKEVENTS
 463         select GPIOLIB
 464         select MIGHT_HAVE_PCI
 465         select NEED_MACH_IO_H
 466         select USB_EHCI_BIG_ENDIAN_DESC
 467         select USB_EHCI_BIG_ENDIAN_MMIO
 468         help
 469           Support for Intel's IXP4XX (XScale) family of processors.
 470
 471 config ARCH_DOVE
 472         bool "Marvell Dove"
 473         select CPU_PJ4
 474         select GENERIC_CLOCKEVENTS
 475         select GPIOLIB
 476         select MIGHT_HAVE_PCI
 477         select MULTI_IRQ_HANDLER
 478         select MVEBU_MBUS
 479         select PINCTRL
 480         select PINCTRL_DOVE
 481         select PLAT_ORION_LEGACY
 482         select SPARSE_IRQ
 483         select PM_GENERIC_DOMAINS if PM
 484         help
 485           Support for the Marvell Dove SoC 88AP510
 486
 487 config ARCH_KS8695
 488         bool "Micrel/Kendin KS8695"
 489         select CLKSRC_MMIO
 490         select CPU_ARM922T
 491         select GENERIC_CLOCKEVENTS
 492         select GPIOLIB
 493         select NEED_MACH_MEMORY_H
 494         help
 495           Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based
 496           System-on-Chip devices.
 497
 498 config ARCH_W90X900
 499         bool "Nuvoton W90X900 CPU"
 500         select CLKDEV_LOOKUP
 501         select CLKSRC_MMIO
 502         select CPU_ARM926T
 503         select GENERIC_CLOCKEVENTS
 504         select GPIOLIB
 505         help
 506           Support for Nuvoton (Winbond logic dept.) ARM9 processor,
 507           At present, the w90x900 has been renamed nuc900, regarding
 508           the ARM series product line, you can login the following
 509           link address to know more.
 510
 511           <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/
 512                 ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller>
 513
 514 config ARCH_LPC32XX
 515         bool "NXP LPC32XX"
 516         select ARM_AMBA
 517         select CLKDEV_LOOKUP
 518         select CLKSRC_LPC32XX
 519         select COMMON_CLK
 520         select CPU_ARM926T
 521         select GENERIC_CLOCKEVENTS
 522         select GPIOLIB
 523         select MULTI_IRQ_HANDLER
 524         select SPARSE_IRQ
 525         select USE_OF
 526         help
 527           Support for the NXP LPC32XX family of processors
 528
 529 config ARCH_PXA
 530         bool "PXA2xx/PXA3xx-based"
 531         depends on MMU
 532         select ARCH_MTD_XIP
 533         select ARM_CPU_SUSPEND if PM
 534         select AUTO_ZRELADDR
 535         select COMMON_CLK
 536         select CLKDEV_LOOKUP
 537         select CLKSRC_PXA
 538         select CLKSRC_MMIO
 539         select TIMER_OF
 540         select CPU_XSCALE if !CPU_XSC3
 541         select GENERIC_CLOCKEVENTS
 542         select GPIO_PXA
 543         select GPIOLIB
 544         select HAVE_IDE
 545         select IRQ_DOMAIN
 546         select MULTI_IRQ_HANDLER
 547         select PLAT_PXA
 548         select SPARSE_IRQ
 549         help
 550           Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
 551
 552 config ARCH_RPC
 553         bool "RiscPC"
 554         depends on MMU
 555         select ARCH_ACORN
 556         select ARCH_MAY_HAVE_PC_FDC
 557         select ARCH_SPARSEMEM_ENABLE
 558         select ARCH_USES_GETTIMEOFFSET
 559         select CPU_SA110
 560         select FIQ
 561         select HAVE_IDE
 562         select HAVE_PATA_PLATFORM
 563         select ISA_DMA_API
 564         select NEED_MACH_IO_H
 565         select NEED_MACH_MEMORY_H
 566         select NO_IOPORT_MAP
 567         help
 568           On the Acorn Risc-PC, Linux can support the internal IDE disk and
 569           CD-ROM interface, serial and parallel port, and the floppy drive.
 570
 571 config ARCH_SA1100
 572         bool "SA1100-based"
 573         select ARCH_MTD_XIP
 574         select ARCH_SPARSEMEM_ENABLE
 575         select CLKDEV_LOOKUP
 576         select CLKSRC_MMIO
 577         select CLKSRC_PXA
 578         select TIMER_OF if OF
 579         select CPU_FREQ
 580         select CPU_SA1100
 581         select GENERIC_CLOCKEVENTS
 582         select GPIOLIB
 583         select HAVE_IDE
 584         select IRQ_DOMAIN
 585         select ISA
 586         select MULTI_IRQ_HANDLER
 587         select NEED_MACH_MEMORY_H
 588         select SPARSE_IRQ
 589         help
 590           Support for StrongARM 11x0 based boards.
 591
 592 config ARCH_S3C24XX
 593         bool "Samsung S3C24XX SoCs"
 594         select ATAGS
 595         select CLKDEV_LOOKUP
 596         select CLKSRC_SAMSUNG_PWM
 597         select GENERIC_CLOCKEVENTS
 598         select GPIO_SAMSUNG
 599         select GPIOLIB
 600         select HAVE_S3C2410_I2C if I2C
 601         select HAVE_S3C2410_WATCHDOG if WATCHDOG
 602         select HAVE_S3C_RTC if RTC_CLASS
 603         select MULTI_IRQ_HANDLER
 604         select NEED_MACH_IO_H
 605         select S3C2410_WATCHDOG
 606         select SAMSUNG_ATAGS
 607         select WATCHDOG
 608         help
 609           Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443
 610           and S3C2450 SoCs based systems, such as the Simtec Electronics BAST
 611           (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or the
 612           Samsung SMDK2410 development board (and derivatives).
 613
 614 config ARCH_DAVINCI
 615         bool "TI DaVinci"
 616         select ARCH_HAS_HOLES_MEMORYMODEL
 617         select CLKDEV_LOOKUP
 618         select CPU_ARM926T
 619         select GENERIC_ALLOCATOR
 620         select GENERIC_CLOCKEVENTS
 621         select GENERIC_IRQ_CHIP
 622         select GPIOLIB
 623         select HAVE_IDE
 624         select USE_OF
 625         select ZONE_DMA
 626         help
 627           Support for TI's DaVinci platform.
 628
 629 config ARCH_OMAP1
 630         bool "TI OMAP1"
 631         depends on MMU
 632         select ARCH_HAS_HOLES_MEMORYMODEL
 633         select ARCH_OMAP
 634         select CLKDEV_LOOKUP
 635         select CLKSRC_MMIO
 636         select GENERIC_CLOCKEVENTS
 637         select GENERIC_IRQ_CHIP
 638         select GPIOLIB
 639         select HAVE_IDE
 640         select IRQ_DOMAIN
 641         select MULTI_IRQ_HANDLER
 642         select NEED_MACH_IO_H if PCCARD
 643         select NEED_MACH_MEMORY_H
 644         select SPARSE_IRQ
 645         help
 646           Support for older TI OMAP1 (omap7xx, omap15xx or omap16xx)
 647
 648 endchoice
 649
 650 menu "Multiple platform selection"
 651         depends on ARCH_MULTIPLATFORM
 652
 653 comment "CPU Core family selection"
 654
 655 config ARCH_MULTI_V4
 656         bool "ARMv4 based platforms (FA526)"
 657         depends on !ARCH_MULTI_V6_V7
 658         select ARCH_MULTI_V4_V5
 659         select CPU_FA526
 660
 661 config ARCH_MULTI_V4T
 662         bool "ARMv4T based platforms (ARM720T, ARM920T, ...)"
 663         depends on !ARCH_MULTI_V6_V7
 664         select ARCH_MULTI_V4_V5
 665         select CPU_ARM920T if !(CPU_ARM7TDMI || CPU_ARM720T || \
 666                 CPU_ARM740T || CPU_ARM9TDMI || CPU_ARM922T || \
 667                 CPU_ARM925T || CPU_ARM940T)
 668
 669 config ARCH_MULTI_V5
 670         bool "ARMv5 based platforms (ARM926T, XSCALE, PJ1, ...)"
 671         depends on !ARCH_MULTI_V6_V7
 672         select ARCH_MULTI_V4_V5
 673         select CPU_ARM926T if !(CPU_ARM946E || CPU_ARM1020 || \
 674                 CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || \
 675                 CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_FEROCEON)
 676
 677 config ARCH_MULTI_V4_V5
 678         bool
 679
 680 config ARCH_MULTI_V6
 681         bool "ARMv6 based platforms (ARM11)"
 682         select ARCH_MULTI_V6_V7
 683         select CPU_V6K
 684
 685 config ARCH_MULTI_V7
 686         bool "ARMv7 based platforms (Cortex-A, PJ4, Scorpion, Krait)"
 687         default y
 688         select ARCH_MULTI_V6_V7
 689         select CPU_V7
 690         select HAVE_SMP
 691
 692 config ARCH_MULTI_V6_V7
 693         bool
 694         select MIGHT_HAVE_CACHE_L2X0
 695
 696 config ARCH_MULTI_CPU_AUTO
 697         def_bool !(ARCH_MULTI_V4 || ARCH_MULTI_V4T || ARCH_MULTI_V6_V7)
 698         select ARCH_MULTI_V5
 699
 700 endmenu
 701
 702 config ARCH_VIRT
 703         bool "Dummy Virtual Machine"
 704         depends on ARCH_MULTI_V7
 705         select ARM_AMBA
 706         select ARM_GIC
 707         select ARM_GIC_V2M if PCI
 708         select ARM_GIC_V3
 709         select ARM_GIC_V3_ITS if PCI
 710         select ARM_PSCI
 711         select HAVE_ARM_ARCH_TIMER
 712
 713 #
 714 # This is sorted alphabetically by mach-* pathname.  However, plat-*
 715 # Kconfigs may be included either alphabetically (according to the
 716 # plat- suffix) or along side the corresponding mach-* source.
 717 #
 718 source "arch/arm/mach-mvebu/Kconfig"
 719
 720 source "arch/arm/mach-actions/Kconfig"
 721
 722 source "arch/arm/mach-alpine/Kconfig"
 723
 724 source "arch/arm/mach-artpec/Kconfig"
 725
 726 source "arch/arm/mach-asm9260/Kconfig"
 727
 728 source "arch/arm/mach-at91/Kconfig"
 729
 730 source "arch/arm/mach-axxia/Kconfig"
 731
 732 source "arch/arm/mach-bcm/Kconfig"
 733
 734 source "arch/arm/mach-berlin/Kconfig"
 735
 736 source "arch/arm/mach-clps711x/Kconfig"
 737
 738 source "arch/arm/mach-cns3xxx/Kconfig"
 739
 740 source "arch/arm/mach-davinci/Kconfig"
 741
 742 source "arch/arm/mach-digicolor/Kconfig"
 743
 744 source "arch/arm/mach-dove/Kconfig"
 745
 746 source "arch/arm/mach-ep93xx/Kconfig"
 747
 748 source "arch/arm/mach-footbridge/Kconfig"
 749
 750 source "arch/arm/mach-gemini/Kconfig"
 751
 752 source "arch/arm/mach-highbank/Kconfig"
 753
 754 source "arch/arm/mach-hisi/Kconfig"
 755
 756 source "arch/arm/mach-integrator/Kconfig"
 757
 758 source "arch/arm/mach-iop32x/Kconfig"
 759
 760 source "arch/arm/mach-iop33x/Kconfig"
 761
 762 source "arch/arm/mach-iop13xx/Kconfig"
 763
 764 source "arch/arm/mach-ixp4xx/Kconfig"
 765
 766 source "arch/arm/mach-keystone/Kconfig"
 767
 768 source "arch/arm/mach-ks8695/Kconfig"
 769
 770 source "arch/arm/mach-meson/Kconfig"
 771
 772 source "arch/arm/mach-moxart/Kconfig"
 773
 774 source "arch/arm/mach-aspeed/Kconfig"
 775
 776 source "arch/arm/mach-mv78xx0/Kconfig"
 777
 778 source "arch/arm/mach-imx/Kconfig"
 779
 780 source "arch/arm/mach-mediatek/Kconfig"
 781
 782 source "arch/arm/mach-mxs/Kconfig"
 783
 784 source "arch/arm/mach-netx/Kconfig"
 785
 786 source "arch/arm/mach-nomadik/Kconfig"
 787
 788 source "arch/arm/mach-nspire/Kconfig"
 789
 790 source "arch/arm/plat-omap/Kconfig"
 791
 792 source "arch/arm/mach-omap1/Kconfig"
 793
 794 source "arch/arm/mach-omap2/Kconfig"
 795
 796 source "arch/arm/mach-orion5x/Kconfig"
 797
 798 source "arch/arm/mach-picoxcell/Kconfig"
 799
 800 source "arch/arm/mach-pxa/Kconfig"
 801 source "arch/arm/plat-pxa/Kconfig"
 802
 803 source "arch/arm/mach-mmp/Kconfig"
 804
 805 source "arch/arm/mach-oxnas/Kconfig"
 806
 807 source "arch/arm/mach-qcom/Kconfig"
 808
 809 source "arch/arm/mach-realview/Kconfig"
 810
 811 source "arch/arm/mach-rockchip/Kconfig"
 812
 813 source "arch/arm/mach-sa1100/Kconfig"
 814
 815 source "arch/arm/mach-socfpga/Kconfig"
 816
 817 source "arch/arm/mach-spear/Kconfig"
 818
 819 source "arch/arm/mach-sti/Kconfig"
 820
 821 source "arch/arm/mach-stm32/Kconfig"
 822
 823 source "arch/arm/mach-s3c24xx/Kconfig"
 824
 825 source "arch/arm/mach-s3c64xx/Kconfig"
 826
 827 source "arch/arm/mach-s5pv210/Kconfig"
 828
 829 source "arch/arm/mach-exynos/Kconfig"
 830 source "arch/arm/plat-samsung/Kconfig"
 831
 832 source "arch/arm/mach-shmobile/Kconfig"
 833
 834 source "arch/arm/mach-sunxi/Kconfig"
 835
 836 source "arch/arm/mach-prima2/Kconfig"
 837
 838 source "arch/arm/mach-tango/Kconfig"
 839
 840 source "arch/arm/mach-tegra/Kconfig"
 841
 842 source "arch/arm/mach-u300/Kconfig"
 843
 844 source "arch/arm/mach-uniphier/Kconfig"
 845
 846 source "arch/arm/mach-ux500/Kconfig"
 847
 848 source "arch/arm/mach-versatile/Kconfig"
 849
 850 source "arch/arm/mach-vexpress/Kconfig"
 851 source "arch/arm/plat-versatile/Kconfig"
 852
 853 source "arch/arm/mach-vt8500/Kconfig"
 854
 855 source "arch/arm/mach-w90x900/Kconfig"
 856
 857 source "arch/arm/mach-zx/Kconfig"
 858
 859 source "arch/arm/mach-zynq/Kconfig"
 860
 861 # ARMv7-M architecture
 862 config ARCH_EFM32
 863         bool "Energy Micro efm32"
 864         depends on ARM_SINGLE_ARMV7M
 865         select GPIOLIB
 866         help
 867           Support for Energy Micro's (now Silicon Labs) efm32 Giant Gecko
 868           processors.
 869
 870 config ARCH_LPC18XX
 871         bool "NXP LPC18xx/LPC43xx"
 872         depends on ARM_SINGLE_ARMV7M
 873         select ARCH_HAS_RESET_CONTROLLER
 874         select ARM_AMBA
 875         select CLKSRC_LPC32XX
 876         select PINCTRL
 877         help
 878           Support for NXP's LPC18xx Cortex-M3 and LPC43xx Cortex-M4
 879           high performance microcontrollers.
 880
 881 config ARCH_MPS2
 882         bool "ARM MPS2 platform"
 883         depends on ARM_SINGLE_ARMV7M
 884         select ARM_AMBA
 885         select CLKSRC_MPS2
 886         help
 887           Support for Cortex-M Prototyping System (or V2M-MPS2) which comes
 888           with a range of available cores like Cortex-M3/M4/M7.
 889
 890           Please, note that depends which Application Note is used memory map
 891           for the platform may vary, so adjustment of RAM base might be needed.
 892
 893 # Definitions to make life easier
 894 config ARCH_ACORN
 895         bool
 896
 897 config PLAT_IOP
 898         bool
 899         select GENERIC_CLOCKEVENTS
 900
 901 config PLAT_ORION
 902         bool
 903         select CLKSRC_MMIO
 904         select COMMON_CLK
 905         select GENERIC_IRQ_CHIP
 906         select IRQ_DOMAIN
 907
 908 config PLAT_ORION_LEGACY
 909         bool
 910         select PLAT_ORION
 911
 912 config PLAT_PXA
 913         bool
 914
 915 config PLAT_VERSATILE
 916         bool
 917
 918 source "arch/arm/firmware/Kconfig"
 919
 920 source arch/arm/mm/Kconfig
 921
 922 config IWMMXT
 923         bool "Enable iWMMXt support"
 924         depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4 || CPU_PJ4B
 925         default y if PXA27x || PXA3xx || ARCH_MMP || CPU_PJ4 || CPU_PJ4B
 926         help
 927           Enable support for iWMMXt context switching at run time if
 928           running on a CPU that supports it.
 929
 930 config MULTI_IRQ_HANDLER
 931         bool
 932         help
 933           Allow each machine to specify it's own IRQ handler at run time.
 934
 935 if !MMU
 936 source "arch/arm/Kconfig-nommu"
 937 endif
 938
 939 config PJ4B_ERRATA_4742
 940         bool "PJ4B Errata 4742: IDLE Wake Up Commands can Cause the CPU Core to Cease Operation"
 941         depends on CPU_PJ4B && MACH_ARMADA_370
 942         default y
 943         help
 944           When coming out of either a Wait for Interrupt (WFI) or a Wait for
 945           Event (WFE) IDLE states, a specific timing sensitivity exists between
 946           the retiring WFI/WFE instructions and the newly issued subsequent
 947           instructions.  This sensitivity can result in a CPU hang scenario.
 948           Workaround:
 949           The software must insert either a Data Synchronization Barrier (DSB)
 950           or Data Memory Barrier (DMB) command immediately after the WFI/WFE
 951           instruction
 952
 953 config ARM_ERRATA_326103
 954         bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory"
 955         depends on CPU_V6
 956         help
 957           Executing a SWP instruction to read-only memory does not set bit 11
 958           of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to
 959           treat the access as a read, preventing a COW from occurring and
 960           causing the faulting task to livelock.
 961
 962 config ARM_ERRATA_411920
 963         bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
 964         depends on CPU_V6 || CPU_V6K
 965         help
 966           Invalidation of the Instruction Cache operation can
 967           fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
 968           It does not affect the MPCore. This option enables the ARM Ltd.
 969           recommended workaround.
 970
 971 config ARM_ERRATA_430973
 972         bool "ARM errata: Stale prediction on replaced interworking branch"
 973         depends on CPU_V7
 974         help
 975           This option enables the workaround for the 430973 Cortex-A8
 976           r1p* erratum. If a code sequence containing an ARM/Thumb
 977           interworking branch is replaced with another code sequence at the
 978           same virtual address, whether due to self-modifying code or virtual
 979           to physical address re-mapping, Cortex-A8 does not recover from the
 980           stale interworking branch prediction. This results in Cortex-A8
 981           executing the new code sequence in the incorrect ARM or Thumb state.
 982           The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
 983           and also flushes the branch target cache at every context switch.
 984           Note that setting specific bits in the ACTLR register may not be
 985           available in non-secure mode.
 986
 987 config ARM_ERRATA_458693
 988         bool "ARM errata: Processor deadlock when a false hazard is created"
 989         depends on CPU_V7
 990         depends on !ARCH_MULTIPLATFORM
 991         help
 992           This option enables the workaround for the 458693 Cortex-A8 (r2p0)
 993           erratum. For very specific sequences of memory operations, it is
 994           possible for a hazard condition intended for a cache line to instead
 995           be incorrectly associated with a different cache line. This false
 996           hazard might then cause a processor deadlock. The workaround enables
 997           the L1 caching of the NEON accesses and disables the PLD instruction
 998           in the ACTLR register. Note that setting specific bits in the ACTLR
 999           register may not be available in non-secure mode.
1000
1001 config ARM_ERRATA_460075
1002         bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
1003         depends on CPU_V7
1004         depends on !ARCH_MULTIPLATFORM
1005         help
1006           This option enables the workaround for the 460075 Cortex-A8 (r2p0)
1007           erratum. Any asynchronous access to the L2 cache may encounter a
1008           situation in which recent store transactions to the L2 cache are lost
1009           and overwritten with stale memory contents from external memory. The
1010           workaround disables the write-allocate mode for the L2 cache via the
1011           ACTLR register. Note that setting specific bits in the ACTLR register
1012           may not be available in non-secure mode.
1013
1014 config ARM_ERRATA_742230
1015         bool "ARM errata: DMB operation may be faulty"
1016         depends on CPU_V7 && SMP
1017         depends on !ARCH_MULTIPLATFORM
1018         help
1019           This option enables the workaround for the 742230 Cortex-A9
1020           (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
1021           between two write operations may not ensure the correct visibility
1022           ordering of the two writes. This workaround sets a specific bit in
1023           the diagnostic register of the Cortex-A9 which causes the DMB
1024           instruction to behave as a DSB, ensuring the correct behaviour of
1025           the two writes.
1026
1027 config ARM_ERRATA_742231
1028         bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
1029         depends on CPU_V7 && SMP
1030         depends on !ARCH_MULTIPLATFORM
1031         help
1032           This option enables the workaround for the 742231 Cortex-A9
1033           (r2p0..r2p2) erratum. Under certain conditions, specific to the
1034           Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
1035           accessing some data located in the same cache line, may get corrupted
1036           data due to bad handling of the address hazard when the line gets
1037           replaced from one of the CPUs at the same time as another CPU is
1038           accessing it. This workaround sets specific bits in the diagnostic
1039           register of the Cortex-A9 which reduces the linefill issuing
1040           capabilities of the processor.
1041
1042 config ARM_ERRATA_643719
1043         bool "ARM errata: LoUIS bit field in CLIDR register is incorrect"
1044         depends on CPU_V7 && SMP
1045         default y
1046         help
1047           This option enables the workaround for the 643719 Cortex-A9 (prior to
1048           r1p0) erratum. On affected cores the LoUIS bit field of the CLIDR
1049           register returns zero when it should return one. The workaround
1050           corrects this value, ensuring cache maintenance operations which use
1051           it behave as intended and avoiding data corruption.
1052
1053 config ARM_ERRATA_720789
1054         bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
1055         depends on CPU_V7
1056         help
1057           This option enables the workaround for the 720789 Cortex-A9 (prior to
1058           r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
1059           broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS.
1060           As a consequence of this erratum, some TLB entries which should be
1061           invalidated are not, resulting in an incoherency in the system page
1062           tables. The workaround changes the TLB flushing routines to invalidate
1063           entries regardless of the ASID.
1064
1065 config ARM_ERRATA_743622
1066         bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
1067         depends on CPU_V7
1068         depends on !ARCH_MULTIPLATFORM
1069         help
1070           This option enables the workaround for the 743622 Cortex-A9
1071           (r2p*) erratum. Under very rare conditions, a faulty
1072           optimisation in the Cortex-A9 Store Buffer may lead to data
1073           corruption. This workaround sets a specific bit in the diagnostic
1074           register of the Cortex-A9 which disables the Store Buffer
1075           optimisation, preventing the defect from occurring. This has no
1076           visible impact on the overall performance or power consumption of the
1077           processor.
1078
1079 config ARM_ERRATA_751472
1080         bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
1081         depends on CPU_V7
1082         depends on !ARCH_MULTIPLATFORM
1083         help
1084           This option enables the workaround for the 751472 Cortex-A9 (prior
1085           to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
1086           completion of a following broadcasted operation if the second
1087           operation is received by a CPU before the ICIALLUIS has completed,
1088           potentially leading to corrupted entries in the cache or TLB.
1089
1090 config ARM_ERRATA_754322
1091         bool "ARM errata: possible faulty MMU translations following an ASID switch"
1092         depends on CPU_V7
1093         help
1094           This option enables the workaround for the 754322 Cortex-A9 (r2p*,
1095           r3p*) erratum. A speculative memory access may cause a page table walk
1096           which starts prior to an ASID switch but completes afterwards. This
1097           can populate the micro-TLB with a stale entry which may be hit with
1098           the new ASID. This workaround places two dsb instructions in the mm
1099           switching code so that no page table walks can cross the ASID switch.
1100
1101 config ARM_ERRATA_754327
1102         bool "ARM errata: no automatic Store Buffer drain"
1103         depends on CPU_V7 && SMP
1104         help
1105           This option enables the workaround for the 754327 Cortex-A9 (prior to
1106           r2p0) erratum. The Store Buffer does not have any automatic draining
1107           mechanism and therefore a livelock may occur if an external agent
1108           continuously polls a memory location waiting to observe an update.
1109           This workaround defines cpu_relax() as smp_mb(), preventing correctly
1110           written polling loops from denying visibility of updates to memory.
1111
1112 config ARM_ERRATA_364296
1113         bool "ARM errata: Possible cache data corruption with hit-under-miss enabled"
1114         depends on CPU_V6
1115         help
1116           This options enables the workaround for the 364296 ARM1136
1117           r0p2 erratum (possible cache data corruption with
1118           hit-under-miss enabled). It sets the undocumented bit 31 in
1119           the auxiliary control register and the FI bit in the control
1120           register, thus disabling hit-under-miss without putting the
1121           processor into full low interrupt latency mode. ARM11MPCore
1122           is not affected.
1123
1124 config ARM_ERRATA_764369
1125         bool "ARM errata: Data cache line maintenance operation by MVA may not succeed"
1126         depends on CPU_V7 && SMP
1127         help
1128           This option enables the workaround for erratum 764369
1129           affecting Cortex-A9 MPCore with two or more processors (all
1130           current revisions). Under certain timing circumstances, a data
1131           cache line maintenance operation by MVA targeting an Inner
1132           Shareable memory region may fail to proceed up to either the
1133           Point of Coherency or to the Point of Unification of the
1134           system. This workaround adds a DSB instruction before the
1135           relevant cache maintenance functions and sets a specific bit
1136           in the diagnostic control register of the SCU.
1137
1138 config ARM_ERRATA_775420
1139        bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock"
1140        depends on CPU_V7
1141        help
1142          This option enables the workaround for the 775420 Cortex-A9 (r2p2,
1143          r2p6,r2p8,r2p10,r3p0) erratum. In case a date cache maintenance
1144          operation aborts with MMU exception, it might cause the processor
1145          to deadlock. This workaround puts DSB before executing ISB if
1146          an abort may occur on cache maintenance.
1147
1148 config ARM_ERRATA_798181
1149         bool "ARM errata: TLBI/DSB failure on Cortex-A15"
1150         depends on CPU_V7 && SMP
1151         help
1152           On Cortex-A15 (r0p0..r3p2) the TLBI*IS/DSB operations are not
1153           adequately shooting down all use of the old entries. This
1154           option enables the Linux kernel workaround for this erratum
1155           which sends an IPI to the CPUs that are running the same ASID
1156           as the one being invalidated.
1157
1158 config ARM_ERRATA_773022
1159         bool "ARM errata: incorrect instructions may be executed from loop buffer"
1160         depends on CPU_V7
1161         help
1162           This option enables the workaround for the 773022 Cortex-A15
1163           (up to r0p4) erratum. In certain rare sequences of code, the
1164           loop buffer may deliver incorrect instructions. This
1165           workaround disables the loop buffer to avoid the erratum.
1166
1167 config ARM_ERRATA_818325_852422
1168         bool "ARM errata: A12: some seqs of opposed cond code instrs => deadlock or corruption"
1169         depends on CPU_V7
1170         help
1171           This option enables the workaround for:
1172           - Cortex-A12 818325: Execution of an UNPREDICTABLE STR or STM
1173             instruction might deadlock.  Fixed in r0p1.
1174           - Cortex-A12 852422: Execution of a sequence of instructions might
1175             lead to either a data corruption or a CPU deadlock.  Not fixed in
1176             any Cortex-A12 cores yet.
1177           This workaround for all both errata involves setting bit[12] of the
1178           Feature Register. This bit disables an optimisation applied to a
1179           sequence of 2 instructions that use opposing condition codes.
1180
1181 config ARM_ERRATA_821420
1182         bool "ARM errata: A12: sequence of VMOV to core registers might lead to a dead lock"
1183         depends on CPU_V7
1184         help
1185           This option enables the workaround for the 821420 Cortex-A12
1186           (all revs) erratum. In very rare timing conditions, a sequence
1187           of VMOV to Core registers instructions, for which the second
1188           one is in the shadow of a branch or abort, can lead to a
1189           deadlock when the VMOV instructions are issued out-of-order.
1190
1191 config ARM_ERRATA_825619
1192         bool "ARM errata: A12: DMB NSHST/ISHST mixed ... might cause deadlock"
1193         depends on CPU_V7
1194         help
1195           This option enables the workaround for the 825619 Cortex-A12
1196           (all revs) erratum. Within rare timing constraints, executing a
1197           DMB NSHST or DMB ISHST instruction followed by a mix of Cacheable
1198           and Device/Strongly-Ordered loads and stores might cause deadlock
1199
1200 config ARM_ERRATA_852421
1201         bool "ARM errata: A17: DMB ST might fail to create order between stores"
1202         depends on CPU_V7
1203         help
1204           This option enables the workaround for the 852421 Cortex-A17
1205           (r1p0, r1p1, r1p2) erratum. Under very rare timing conditions,
1206           execution of a DMB ST instruction might fail to properly order
1207           stores from GroupA and stores from GroupB.
1208
1209 config ARM_ERRATA_852423
1210         bool "ARM errata: A17: some seqs of opposed cond code instrs => deadlock or corruption"
1211         depends on CPU_V7
1212         help
1213           This option enables the workaround for:
1214           - Cortex-A17 852423: Execution of a sequence of instructions might
1215             lead to either a data corruption or a CPU deadlock.  Not fixed in
1216             any Cortex-A17 cores yet.
1217           This is identical to Cortex-A12 erratum 852422.  It is a separate
1218           config option from the A12 erratum due to the way errata are checked
1219           for and handled.
1220
1221 endmenu
1222
1223 source "arch/arm/common/Kconfig"
1224
1225 menu "Bus support"
1226
1227 config ISA
1228         bool
1229         help
1230           Find out whether you have ISA slots on your motherboard.  ISA is the
1231           name of a bus system, i.e. the way the CPU talks to the other stuff
1232           inside your box.  Other bus systems are PCI, EISA, MicroChannel
1233           (MCA) or VESA.  ISA is an older system, now being displaced by PCI;
1234           newer boards don't support it.  If you have ISA, say Y, otherwise N.
1235
1236 # Select ISA DMA controller support
1237 config ISA_DMA
1238         bool
1239         select ISA_DMA_API
1240
1241 # Select ISA DMA interface
1242 config ISA_DMA_API
1243         bool
1244
1245 config PCI
1246         bool "PCI support" if MIGHT_HAVE_PCI
1247         help
1248           Find out whether you have a PCI motherboard. PCI is the name of a
1249           bus system, i.e. the way the CPU talks to the other stuff inside
1250           your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or
1251           VESA. If you have PCI, say Y, otherwise N.
1252
1253 config PCI_DOMAINS
1254         bool
1255         depends on PCI
1256
1257 config PCI_DOMAINS_GENERIC
1258         def_bool PCI_DOMAINS
1259
1260 config PCI_NANOENGINE
1261         bool "BSE nanoEngine PCI support"
1262         depends on SA1100_NANOENGINE
1263         help
1264           Enable PCI on the BSE nanoEngine board.
1265
1266 config PCI_SYSCALL
1267         def_bool PCI
1268
1269 config PCI_HOST_ITE8152
1270         bool
1271         depends on PCI && MACH_ARMCORE
1272         default y
1273         select DMABOUNCE
1274
1275 source "drivers/pci/Kconfig"
1276
1277 source "drivers/pcmcia/Kconfig"
1278
1279 endmenu
1280
1281 menu "Kernel Features"
1282
1283 config HAVE_SMP
1284         bool
1285         help
1286           This option should be selected by machines which have an SMP-
1287           capable CPU.
1288
1289           The only effect of this option is to make the SMP-related
1290           options available to the user for configuration.
1291
1292 config SMP
1293         bool "Symmetric Multi-Processing"
1294         depends on CPU_V6K || CPU_V7
1295         depends on GENERIC_CLOCKEVENTS
1296         depends on HAVE_SMP
1297         depends on MMU || ARM_MPU
1298         select IRQ_WORK
1299         help
1300           This enables support for systems with more than one CPU. If you have
1301           a system with only one CPU, say N. If you have a system with more
1302           than one CPU, say Y.
1303
1304           If you say N here, the kernel will run on uni- and multiprocessor
1305           machines, but will use only one CPU of a multiprocessor machine. If
1306           you say Y here, the kernel will run on many, but not all,
1307           uniprocessor machines. On a uniprocessor machine, the kernel
1308           will run faster if you say N here.
1309
1310           See also <file:Documentation/x86/i386/IO-APIC.txt>,
1311           <file:Documentation/nmi_watchdog.txt> and the SMP-HOWTO available at
1312           <http://tldp.org/HOWTO/SMP-HOWTO.html>.
1313
1314           If you don't know what to do here, say N.
1315
1316 config SMP_ON_UP
1317         bool "Allow booting SMP kernel on uniprocessor systems"
1318         depends on SMP && !XIP_KERNEL && MMU
1319         default y
1320         help
1321           SMP kernels contain instructions which fail on non-SMP processors.
1322           Enabling this option allows the kernel to modify itself to make
1323           these instructions safe.  Disabling it allows about 1K of space
1324           savings.
1325
1326           If you don't know what to do here, say Y.
1327
1328 config ARM_CPU_TOPOLOGY
1329         bool "Support cpu topology definition"
1330         depends on SMP && CPU_V7
1331         default y
1332         help
1333           Support ARM cpu topology definition. The MPIDR register defines
1334           affinity between processors which is then used to describe the cpu
1335           topology of an ARM System.
1336
1337 config SCHED_MC
1338         bool "Multi-core scheduler support"
1339         depends on ARM_CPU_TOPOLOGY
1340         help
1341           Multi-core scheduler support improves the CPU scheduler's decision
1342           making when dealing with multi-core CPU chips at a cost of slightly
1343           increased overhead in some places. If unsure say N here.
1344
1345 config SCHED_SMT
1346         bool "SMT scheduler support"
1347         depends on ARM_CPU_TOPOLOGY
1348         help
1349           Improves the CPU scheduler's decision making when dealing with
1350           MultiThreading at a cost of slightly increased overhead in some
1351           places. If unsure say N here.
1352
1353 config HAVE_ARM_SCU
1354         bool
1355         help
1356           This option enables support for the ARM system coherency unit
1357
1358 config HAVE_ARM_ARCH_TIMER
1359         bool "Architected timer support"
1360         depends on CPU_V7
1361         select ARM_ARCH_TIMER
1362         select GENERIC_CLOCKEVENTS
1363         help
1364           This option enables support for the ARM architected timer
1365
1366 config HAVE_ARM_TWD
1367         bool
1368         select TIMER_OF if OF
1369         help
1370           This options enables support for the ARM timer and watchdog unit
1371
1372 config MCPM
1373         bool "Multi-Cluster Power Management"
1374         depends on CPU_V7 && SMP
1375         help
1376           This option provides the common power management infrastructure
1377           for (multi-)cluster based systems, such as big.LITTLE based
1378           systems.
1379
1380 config MCPM_QUAD_CLUSTER
1381         bool
1382         depends on MCPM
1383         help
1384           To avoid wasting resources unnecessarily, MCPM only supports up
1385           to 2 clusters by default.
1386           Platforms with 3 or 4 clusters that use MCPM must select this
1387           option to allow the additional clusters to be managed.
1388
1389 config BIG_LITTLE
1390         bool "big.LITTLE support (Experimental)"
1391         depends on CPU_V7 && SMP
1392         select MCPM
1393         help
1394           This option enables support selections for the big.LITTLE
1395           system architecture.
1396
1397 config BL_SWITCHER
1398         bool "big.LITTLE switcher support"
1399         depends on BIG_LITTLE && MCPM && HOTPLUG_CPU && ARM_GIC
1400         select CPU_PM
1401         help
1402           The big.LITTLE "switcher" provides the core functionality to
1403           transparently handle transition between a cluster of A15's
1404           and a cluster of A7's in a big.LITTLE system.
1405
1406 config BL_SWITCHER_DUMMY_IF
1407         tristate "Simple big.LITTLE switcher user interface"
1408         depends on BL_SWITCHER && DEBUG_KERNEL
1409         help
1410           This is a simple and dummy char dev interface to control
1411           the big.LITTLE switcher core code.  It is meant for
1412           debugging purposes only.
1413
1414 choice
1415         prompt "Memory split"
1416         depends on MMU
1417         default VMSPLIT_3G
1418         help
1419           Select the desired split between kernel and user memory.
1420
1421           If you are not absolutely sure what you are doing, leave this
1422           option alone!
1423
1424         config VMSPLIT_3G
1425                 bool "3G/1G user/kernel split"
1426         config VMSPLIT_3G_OPT
1427                 depends on !ARM_LPAE
1428                 bool "3G/1G user/kernel split (for full 1G low memory)"
1429         config VMSPLIT_2G
1430                 bool "2G/2G user/kernel split"
1431         config VMSPLIT_1G
1432                 bool "1G/3G user/kernel split"
1433 endchoice
1434
1435 config PAGE_OFFSET
1436         hex
1437         default PHYS_OFFSET if !MMU
1438         default 0x40000000 if VMSPLIT_1G
1439         default 0x80000000 if VMSPLIT_2G
1440         default 0xB0000000 if VMSPLIT_3G_OPT
1441         default 0xC0000000
1442
1443 config NR_CPUS
1444         int "Maximum number of CPUs (2-32)"
1445         range 2 32
1446         depends on SMP
1447         default "4"
1448
1449 config HOTPLUG_CPU
1450         bool "Support for hot-pluggable CPUs"
1451         depends on SMP
1452         select GENERIC_IRQ_MIGRATION
1453         help
1454           Say Y here to experiment with turning CPUs off and on.  CPUs
1455           can be controlled through /sys/devices/system/cpu.
1456
1457 config ARM_PSCI
1458         bool "Support for the ARM Power State Coordination Interface (PSCI)"
1459         depends on HAVE_ARM_SMCCC
1460         select ARM_PSCI_FW
1461         help
1462           Say Y here if you want Linux to communicate with system firmware
1463           implementing the PSCI specification for CPU-centric power
1464           management operations described in ARM document number ARM DEN
1465           0022A ("Power State Coordination Interface System Software on
1466           ARM processors").
1467
1468 # The GPIO number here must be sorted by descending number. In case of
1469 # a multiplatform kernel, we just want the highest value required by the
1470 # selected platforms.
1471 config ARCH_NR_GPIO
1472         int
1473         default 2048 if ARCH_SOCFPGA
1474         default 1024 if ARCH_BRCMSTB || ARCH_SHMOBILE || ARCH_TEGRA || \
1475                 ARCH_ZYNQ
1476         default 512 if ARCH_EXYNOS || ARCH_KEYSTONE || SOC_OMAP5 || \
1477                 SOC_DRA7XX || ARCH_S3C24XX || ARCH_S3C64XX || ARCH_S5PV210
1478         default 416 if ARCH_SUNXI
1479         default 392 if ARCH_U8500
1480         default 352 if ARCH_VT8500
1481         default 288 if ARCH_ROCKCHIP
1482         default 264 if MACH_H4700
1483         default 0
1484         help
1485           Maximum number of GPIOs in the system.
1486
1487           If unsure, leave the default value.
1488
1489 source kernel/Kconfig.preempt
1490
1491 config HZ_FIXED
1492         int
1493         default 200 if ARCH_EBSA110
1494         default 128 if SOC_AT91RM9200
1495         default 0
1496
1497 choice
1498         depends on HZ_FIXED = 0
1499         prompt "Timer frequency"
1500
1501 config HZ_100
1502         bool "100 Hz"
1503
1504 config HZ_200
1505         bool "200 Hz"
1506
1507 config HZ_250
1508         bool "250 Hz"
1509
1510 config HZ_300
1511         bool "300 Hz"
1512
1513 config HZ_500
1514         bool "500 Hz"
1515
1516 config HZ_1000
1517         bool "1000 Hz"
1518
1519 endchoice
1520
1521 config HZ
1522         int
1523         default HZ_FIXED if HZ_FIXED != 0
1524         default 100 if HZ_100
1525         default 200 if HZ_200
1526         default 250 if HZ_250
1527         default 300 if HZ_300
1528         default 500 if HZ_500
1529         default 1000
1530
1531 config SCHED_HRTICK
1532         def_bool HIGH_RES_TIMERS
1533
1534 config THUMB2_KERNEL
1535         bool "Compile the kernel in Thumb-2 mode" if !CPU_THUMBONLY
1536         depends on (CPU_V7 || CPU_V7M) && !CPU_V6 && !CPU_V6K
1537         default y if CPU_THUMBONLY
1538         select ARM_UNWIND
1539         help
1540           By enabling this option, the kernel will be compiled in
1541           Thumb-2 mode.
1542
1543           If unsure, say N.
1544
1545 config THUMB2_AVOID_R_ARM_THM_JUMP11
1546         bool "Work around buggy Thumb-2 short branch relocations in gas"
1547         depends on THUMB2_KERNEL && MODULES
1548         default y
1549         help
1550           Various binutils versions can resolve Thumb-2 branches to
1551           locally-defined, preemptible global symbols as short-range "b.n"
1552           branch instructions.
1553
1554           This is a problem, because there's no guarantee the final
1555           destination of the symbol, or any candidate locations for a
1556           trampoline, are within range of the branch.  For this reason, the
1557           kernel does not support fixing up the R_ARM_THM_JUMP11 (102)
1558           relocation in modules at all, and it makes little sense to add
1559           support.
1560
1561           The symptom is that the kernel fails with an "unsupported
1562           relocation" error when loading some modules.
1563
1564           Until fixed tools are available, passing
1565           -fno-optimize-sibling-calls to gcc should prevent gcc generating
1566           code which hits this problem, at the cost of a bit of extra runtime
1567           stack usage in some cases.
1568
1569           The problem is described in more detail at:
1570               https://bugs.launchpad.net/binutils-linaro/+bug/725126
1571
1572           Only Thumb-2 kernels are affected.
1573
1574           Unless you are sure your tools don't have this problem, say Y.
1575
1576 config ARM_PATCH_IDIV
1577         bool "Runtime patch udiv/sdiv instructions into __aeabi_{u}idiv()"
1578         depends on CPU_32v7 && !XIP_KERNEL
1579         default y
1580         help
1581           The ARM compiler inserts calls to __aeabi_idiv() and
1582           __aeabi_uidiv() when it needs to perform division on signed
1583           and unsigned integers. Some v7 CPUs have support for the sdiv
1584           and udiv instructions that can be used to implement those
1585           functions.
1586
1587           Enabling this option allows the kernel to modify itself to
1588           replace the first two instructions of these library functions
1589           with the sdiv or udiv plus "bx lr" instructions when the CPU
1590           it is running on supports them. Typically this will be faster
1591           and less power intensive than running the original library
1592           code to do integer division.
1593
1594 config AEABI
1595         bool "Use the ARM EABI to compile the kernel" if !CPU_V7 && !CPU_V7M && !CPU_V6 && !CPU_V6K
1596         default CPU_V7 || CPU_V7M || CPU_V6 || CPU_V6K
1597         help
1598           This option allows for the kernel to be compiled using the latest
1599           ARM ABI (aka EABI).  This is only useful if you are using a user
1600           space environment that is also compiled with EABI.
1601
1602           Since there are major incompatibilities between the legacy ABI and
1603           EABI, especially with regard to structure member alignment, this
1604           option also changes the kernel syscall calling convention to
1605           disambiguate both ABIs and allow for backward compatibility support
1606           (selected with CONFIG_OABI_COMPAT).
1607
1608           To use this you need GCC version 4.0.0 or later.
1609
1610 config OABI_COMPAT
1611         bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
1612         depends on AEABI && !THUMB2_KERNEL
1613         help
1614           This option preserves the old syscall interface along with the
1615           new (ARM EABI) one. It also provides a compatibility layer to
1616           intercept syscalls that have structure arguments which layout
1617           in memory differs between the legacy ABI and the new ARM EABI
1618           (only for non "thumb" binaries). This option adds a tiny
1619           overhead to all syscalls and produces a slightly larger kernel.
1620
1621           The seccomp filter system will not be available when this is
1622           selected, since there is no way yet to sensibly distinguish
1623           between calling conventions during filtering.
1624
1625           If you know you'll be using only pure EABI user space then you
1626           can say N here. If this option is not selected and you attempt
1627           to execute a legacy ABI binary then the result will be
1628           UNPREDICTABLE (in fact it can be predicted that it won't work
1629           at all). If in doubt say N.
1630
1631 config ARCH_HAS_HOLES_MEMORYMODEL
1632         bool
1633
1634 config ARCH_SPARSEMEM_ENABLE
1635         bool
1636
1637 config ARCH_SPARSEMEM_DEFAULT
1638         def_bool ARCH_SPARSEMEM_ENABLE
1639
1640 config ARCH_SELECT_MEMORY_MODEL
1641         def_bool ARCH_SPARSEMEM_ENABLE
1642
1643 config HAVE_ARCH_PFN_VALID
1644         def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
1645
1646 config HAVE_GENERIC_GUP
1647         def_bool y
1648         depends on ARM_LPAE
1649
1650 config HIGHMEM
1651         bool "High Memory Support"
1652         depends on MMU
1653         help
1654           The address space of ARM processors is only 4 Gigabytes large
1655           and it has to accommodate user address space, kernel address
1656           space as well as some memory mapped IO. That means that, if you
1657           have a large amount of physical memory and/or IO, not all of the
1658           memory can be "permanently mapped" by the kernel. The physical
1659           memory that is not permanently mapped is called "high memory".
1660
1661           Depending on the selected kernel/user memory split, minimum
1662           vmalloc space and actual amount of RAM, you may not need this
1663           option which should result in a slightly faster kernel.
1664
1665           If unsure, say n.
1666
1667 config HIGHPTE
1668         bool "Allocate 2nd-level pagetables from highmem" if EXPERT
1669         depends on HIGHMEM
1670         default y
1671         help
1672           The VM uses one page of physical memory for each page table.
1673           For systems with a lot of processes, this can use a lot of
1674           precious low memory, eventually leading to low memory being
1675           consumed by page tables.  Setting this option will allow
1676           user-space 2nd level page tables to reside in high memory.
1677
1678 config CPU_SW_DOMAIN_PAN
1679         bool "Enable use of CPU domains to implement privileged no-access"
1680         depends on MMU && !ARM_LPAE
1681         default y
1682         help
1683           Increase kernel security by ensuring that normal kernel accesses
1684           are unable to access userspace addresses.  This can help prevent
1685           use-after-free bugs becoming an exploitable privilege escalation
1686           by ensuring that magic values (such as LIST_POISON) will always
1687           fault when dereferenced.
1688
1689           CPUs with low-vector mappings use a best-efforts implementation.
1690           Their lower 1MB needs to remain accessible for the vectors, but
1691           the remainder of userspace will become appropriately inaccessible.
1692
1693 config HW_PERF_EVENTS
1694         def_bool y
1695         depends on ARM_PMU
1696
1697 config SYS_SUPPORTS_HUGETLBFS
1698        def_bool y
1699        depends on ARM_LPAE
1700
1701 config HAVE_ARCH_TRANSPARENT_HUGEPAGE
1702        def_bool y
1703        depends on ARM_LPAE
1704
1705 config ARCH_WANT_GENERAL_HUGETLB
1706         def_bool y
1707
1708 config ARM_MODULE_PLTS
1709         bool "Use PLTs to allow module memory to spill over into vmalloc area"
1710         depends on MODULES
1711         help
1712           Allocate PLTs when loading modules so that jumps and calls whose
1713           targets are too far away for their relative offsets to be encoded
1714           in the instructions themselves can be bounced via veneers in the
1715           module's PLT. This allows modules to be allocated in the generic
1716           vmalloc area after the dedicated module memory area has been
1717           exhausted. The modules will use slightly more memory, but after
1718           rounding up to page size, the actual memory footprint is usually
1719           the same.
1720
1721           Say y if you are getting out of memory errors while loading modules
1722
1723 source "mm/Kconfig"
1724
1725 config FORCE_MAX_ZONEORDER
1726         int "Maximum zone order"
1727         default "12" if SOC_AM33XX
1728         default "9" if SA1111 || ARCH_EFM32
1729         default "11"
1730         help
1731           The kernel memory allocator divides physically contiguous memory
1732           blocks into "zones", where each zone is a power of two number of
1733           pages.  This option selects the largest power of two that the kernel
1734           keeps in the memory allocator.  If you need to allocate very large
1735           blocks of physically contiguous memory, then you may need to
1736           increase this value.
1737
1738           This config option is actually maximum order plus one. For example,
1739           a value of 11 means that the largest free memory block is 2^10 pages.
1740
1741 config ALIGNMENT_TRAP
1742         bool
1743         depends on CPU_CP15_MMU
1744         default y if !ARCH_EBSA110
1745         select HAVE_PROC_CPU if PROC_FS
1746         help
1747           ARM processors cannot fetch/store information which is not
1748           naturally aligned on the bus, i.e., a 4 byte fetch must start at an
1749           address divisible by 4. On 32-bit ARM processors, these non-aligned
1750           fetch/store instructions will be emulated in software if you say
1751           here, which has a severe performance impact. This is necessary for
1752           correct operation of some network protocols. With an IP-only
1753           configuration it is safe to say N, otherwise say Y.
1754
1755 config UACCESS_WITH_MEMCPY
1756         bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user()"
1757         depends on MMU
1758         default y if CPU_FEROCEON
1759         help
1760           Implement faster copy_to_user and clear_user methods for CPU
1761           cores where a 8-word STM instruction give significantly higher
1762           memory write throughput than a sequence of individual 32bit stores.
1763
1764           A possible side effect is a slight increase in scheduling latency
1765           between threads sharing the same address space if they invoke
1766           such copy operations with large buffers.
1767
1768           However, if the CPU data cache is using a write-allocate mode,
1769           this option is unlikely to provide any performance gain.
1770
1771 config SECCOMP
1772         bool
1773         prompt "Enable seccomp to safely compute untrusted bytecode"
1774         ---help---
1775           This kernel feature is useful for number crunching applications
1776           that may need to compute untrusted bytecode during their
1777           execution. By using pipes or other transports made available to
1778           the process as file descriptors supporting the read/write
1779           syscalls, it's possible to isolate those applications in
1780           their own address space using seccomp. Once seccomp is
1781           enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
1782           and the task is only allowed to execute a few safe syscalls
1783           defined by each seccomp mode.
1784
1785 config SWIOTLB
1786         def_bool y
1787
1788 config IOMMU_HELPER
1789         def_bool SWIOTLB
1790
1791 config PARAVIRT
1792         bool "Enable paravirtualization code"
1793         help
1794           This changes the kernel so it can modify itself when it is run
1795           under a hypervisor, potentially improving performance significantly
1796           over full virtualization.
1797
1798 config PARAVIRT_TIME_ACCOUNTING
1799         bool "Paravirtual steal time accounting"
1800         select PARAVIRT
1801         default n
1802         help
1803           Select this option to enable fine granularity task steal time
1804           accounting. Time spent executing other tasks in parallel with
1805           the current vCPU is discounted from the vCPU power. To account for
1806           that, there can be a small performance impact.
1807
1808           If in doubt, say N here.
1809
1810 config XEN_DOM0
1811         def_bool y
1812         depends on XEN
1813
1814 config XEN
1815         bool "Xen guest support on ARM"
1816         depends on ARM && AEABI && OF
1817         depends on CPU_V7 && !CPU_V6
1818         depends on !GENERIC_ATOMIC64
1819         depends on MMU
1820         select ARCH_DMA_ADDR_T_64BIT
1821         select ARM_PSCI
1822         select SWIOTLB_XEN
1823         select PARAVIRT
1824         help
1825           Say Y if you want to run Linux in a Virtual Machine on Xen on ARM.
1826
1827 endmenu
1828
1829 menu "Boot options"
1830
1831 config USE_OF
1832         bool "Flattened Device Tree support"
1833         select IRQ_DOMAIN
1834         select OF
1835         help
1836           Include support for flattened device tree machine descriptions.
1837
1838 config ATAGS
1839         bool "Support for the traditional ATAGS boot data passing" if USE_OF
1840         default y
1841         help
1842           This is the traditional way of passing data to the kernel at boot
1843           time. If you are solely relying on the flattened device tree (or
1844           the ARM_ATAG_DTB_COMPAT option) then you may unselect this option
1845           to remove ATAGS support from your kernel binary.  If unsure,
1846           leave this to y.
1847
1848 config DEPRECATED_PARAM_STRUCT
1849         bool "Provide old way to pass kernel parameters"
1850         depends on ATAGS
1851         help
1852           This was deprecated in 2001 and announced to live on for 5 years.
1853           Some old boot loaders still use this way.
1854
1855 # Compressed boot loader in ROM.  Yes, we really want to ask about
1856 # TEXT and BSS so we preserve their values in the config files.
1857 config ZBOOT_ROM_TEXT
1858         hex "Compressed ROM boot loader base address"
1859         default "0"
1860         help
1861           The physical address at which the ROM-able zImage is to be
1862           placed in the target.  Platforms which normally make use of
1863           ROM-able zImage formats normally set this to a suitable
1864           value in their defconfig file.
1865
1866           If ZBOOT_ROM is not enabled, this has no effect.
1867
1868 config ZBOOT_ROM_BSS
1869         hex "Compressed ROM boot loader BSS address"
1870         default "0"
1871         help
1872           The base address of an area of read/write memory in the target
1873           for the ROM-able zImage which must be available while the
1874           decompressor is running. It must be large enough to hold the
1875           entire decompressed kernel plus an additional 128 KiB.
1876           Platforms which normally make use of ROM-able zImage formats
1877           normally set this to a suitable value in their defconfig file.
1878
1879           If ZBOOT_ROM is not enabled, this has no effect.
1880
1881 config ZBOOT_ROM
1882         bool "Compressed boot loader in ROM/flash"
1883         depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS
1884         depends on !ARM_APPENDED_DTB && !XIP_KERNEL && !AUTO_ZRELADDR
1885         help
1886           Say Y here if you intend to execute your compressed kernel image
1887           (zImage) directly from ROM or flash.  If unsure, say N.
1888
1889 config ARM_APPENDED_DTB
1890         bool "Use appended device tree blob to zImage (EXPERIMENTAL)"
1891         depends on OF
1892         help
1893           With this option, the boot code will look for a device tree binary
1894           (DTB) appended to zImage
1895           (e.g. cat zImage <filename>.dtb > zImage_w_dtb).
1896
1897           This is meant as a backward compatibility convenience for those
1898           systems with a bootloader that can't be upgraded to accommodate
1899           the documented boot protocol using a device tree.
1900
1901           Beware that there is very little in terms of protection against
1902           this option being confused by leftover garbage in memory that might
1903           look like a DTB header after a reboot if no actual DTB is appended
1904           to zImage.  Do not leave this option active in a production kernel
1905           if you don't intend to always append a DTB.  Proper passing of the
1906           location into r2 of a bootloader provided DTB is always preferable
1907           to this option.
1908
1909 config ARM_ATAG_DTB_COMPAT
1910         bool "Supplement the appended DTB with traditional ATAG information"
1911         depends on ARM_APPENDED_DTB
1912         help
1913           Some old bootloaders can't be updated to a DTB capable one, yet
1914           they provide ATAGs with memory configuration, the ramdisk address,
1915           the kernel cmdline string, etc.  Such information is dynamically
1916           provided by the bootloader and can't always be stored in a static
1917           DTB.  To allow a device tree enabled kernel to be used with such
1918           bootloaders, this option allows zImage to extract the information
1919           from the ATAG list and store it at run time into the appended DTB.
1920
1921 choice
1922         prompt "Kernel command line type" if ARM_ATAG_DTB_COMPAT
1923         default ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
1924
1925 config ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
1926         bool "Use bootloader kernel arguments if available"
1927         help
1928           Uses the command-line options passed by the boot loader instead of
1929           the device tree bootargs property. If the boot loader doesn't provide
1930           any, the device tree bootargs property will be used.
1931
1932 config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND
1933         bool "Extend with bootloader kernel arguments"
1934         help
1935           The command-line arguments provided by the boot loader will be
1936           appended to the the device tree bootargs property.
1937
1938 endchoice
1939
1940 config CMDLINE
1941         string "Default kernel command string"
1942         default ""
1943         help
1944           On some architectures (EBSA110 and CATS), there is currently no way
1945           for the boot loader to pass arguments to the kernel. For these
1946           architectures, you should supply some command-line options at build
1947           time by entering them here. As a minimum, you should specify the
1948           memory size and the root device (e.g., mem=64M root=/dev/nfs).
1949
1950 choice
1951         prompt "Kernel command line type" if CMDLINE != ""
1952         default CMDLINE_FROM_BOOTLOADER
1953         depends on ATAGS
1954
1955 config CMDLINE_FROM_BOOTLOADER
1956         bool "Use bootloader kernel arguments if available"
1957         help
1958           Uses the command-line options passed by the boot loader. If
1959           the boot loader doesn't provide any, the default kernel command
1960           string provided in CMDLINE will be used.
1961
1962 config CMDLINE_EXTEND
1963         bool "Extend bootloader kernel arguments"
1964         help
1965           The command-line arguments provided by the boot loader will be
1966           appended to the default kernel command string.
1967
1968 config CMDLINE_FORCE
1969         bool "Always use the default kernel command string"
1970         help
1971           Always use the default kernel command string, even if the boot
1972           loader passes other arguments to the kernel.
1973           This is useful if you cannot or don't want to change the
1974           command-line options your boot loader passes to the kernel.
1975 endchoice
1976
1977 config XIP_KERNEL
1978         bool "Kernel Execute-In-Place from ROM"
1979         depends on !ARM_LPAE && !ARCH_MULTIPLATFORM
1980         help
1981           Execute-In-Place allows the kernel to run from non-volatile storage
1982           directly addressable by the CPU, such as NOR flash. This saves RAM
1983           space since the text section of the kernel is not loaded from flash
1984           to RAM.  Read-write sections, such as the data section and stack,
1985           are still copied to RAM.  The XIP kernel is not compressed since
1986           it has to run directly from flash, so it will take more space to
1987           store it.  The flash address used to link the kernel object files,
1988           and for storing it, is configuration dependent. Therefore, if you
1989           say Y here, you must know the proper physical address where to
1990           store the kernel image depending on your own flash memory usage.
1991
1992           Also note that the make target becomes "make xipImage" rather than
1993           "make zImage" or "make Image".  The final kernel binary to put in
1994           ROM memory will be arch/arm/boot/xipImage.
1995
1996           If unsure, say N.
1997
1998 config XIP_PHYS_ADDR
1999         hex "XIP Kernel Physical Location"
2000         depends on XIP_KERNEL
2001         default "0x00080000"
2002         help
2003           This is the physical address in your flash memory the kernel will
2004           be linked for and stored to.  This address is dependent on your
2005           own flash usage.
2006
2007 config KEXEC
2008         bool "Kexec system call (EXPERIMENTAL)"
2009         depends on (!SMP || PM_SLEEP_SMP)
2010         depends on MMU
2011         select KEXEC_CORE
2012         help
2013           kexec is a system call that implements the ability to shutdown your
2014           current kernel, and to start another kernel.  It is like a reboot
2015           but it is independent of the system firmware.   And like a reboot
2016           you can start any kernel with it, not just Linux.
2017
2018           It is an ongoing process to be certain the hardware in a machine
2019           is properly shutdown, so do not be surprised if this code does not
2020           initially work for you.
2021
2022 config ATAGS_PROC
2023         bool "Export atags in procfs"
2024         depends on ATAGS && KEXEC
2025         default y
2026         help
2027           Should the atags used to boot the kernel be exported in an "atags"
2028           file in procfs. Useful with kexec.
2029
2030 config CRASH_DUMP
2031         bool "Build kdump crash kernel (EXPERIMENTAL)"
2032         help
2033           Generate crash dump after being started by kexec. This should
2034           be normally only set in special crash dump kernels which are
2035           loaded in the main kernel with kexec-tools into a specially
2036           reserved region and then later executed after a crash by
2037           kdump/kexec. The crash dump kernel must be compiled to a
2038           memory address not used by the main kernel
2039
2040           For more details see Documentation/kdump/kdump.txt
2041
2042 config AUTO_ZRELADDR
2043         bool "Auto calculation of the decompressed kernel image address"
2044         help
2045           ZRELADDR is the physical address where the decompressed kernel
2046           image will be placed. If AUTO_ZRELADDR is selected, the address
2047           will be determined at run-time by masking the current IP with
2048           0xf8000000. This assumes the zImage being placed in the first 128MB
2049           from start of memory.
2050
2051 config EFI_STUB
2052         bool
2053
2054 config EFI
2055         bool "UEFI runtime support"
2056         depends on OF && !CPU_BIG_ENDIAN && MMU && AUTO_ZRELADDR && !XIP_KERNEL
2057         select UCS2_STRING
2058         select EFI_PARAMS_FROM_FDT
2059         select EFI_STUB
2060         select EFI_ARMSTUB
2061         select EFI_RUNTIME_WRAPPERS
2062         ---help---
2063           This option provides support for runtime services provided
2064           by UEFI firmware (such as non-volatile variables, realtime
2065           clock, and platform reset). A UEFI stub is also provided to
2066           allow the kernel to be booted as an EFI application. This
2067           is only useful for kernels that may run on systems that have
2068           UEFI firmware.
2069
2070 config DMI
2071         bool "Enable support for SMBIOS (DMI) tables"
2072         depends on EFI
2073         default y
2074         help
2075           This enables SMBIOS/DMI feature for systems.
2076
2077           This option is only useful on systems that have UEFI firmware.
2078           However, even with this option, the resultant kernel should
2079           continue to boot on existing non-UEFI platforms.
2080
2081           NOTE: This does *NOT* enable or encourage the use of DMI quirks,
2082           i.e., the the practice of identifying the platform via DMI to
2083           decide whether certain workarounds for buggy hardware and/or
2084           firmware need to be enabled. This would require the DMI subsystem
2085           to be enabled much earlier than we do on ARM, which is non-trivial.
2086
2087 endmenu
2088
2089 menu "CPU Power Management"
2090
2091 source "drivers/cpufreq/Kconfig"
2092
2093 source "drivers/cpuidle/Kconfig"
2094
2095 endmenu
2096
2097 menu "Floating point emulation"
2098
2099 comment "At least one emulation must be selected"
2100
2101 config FPE_NWFPE
2102         bool "NWFPE math emulation"
2103         depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL
2104         ---help---
2105           Say Y to include the NWFPE floating point emulator in the kernel.
2106           This is necessary to run most binaries. Linux does not currently
2107           support floating point hardware so you need to say Y here even if
2108           your machine has an FPA or floating point co-processor podule.
2109
2110           You may say N here if you are going to load the Acorn FPEmulator
2111           early in the bootup.
2112
2113 config FPE_NWFPE_XP
2114         bool "Support extended precision"
2115         depends on FPE_NWFPE
2116         help
2117           Say Y to include 80-bit support in the kernel floating-point
2118           emulator.  Otherwise, only 32 and 64-bit support is compiled in.
2119           Note that gcc does not generate 80-bit operations by default,
2120           so in most cases this option only enlarges the size of the
2121           floating point emulator without any good reason.
2122
2123           You almost surely want to say N here.
2124
2125 config FPE_FASTFPE
2126         bool "FastFPE math emulation (EXPERIMENTAL)"
2127         depends on (!AEABI || OABI_COMPAT) && !CPU_32v3
2128         ---help---
2129           Say Y here to include the FAST floating point emulator in the kernel.
2130           This is an experimental much faster emulator which now also has full
2131           precision for the mantissa.  It does not support any exceptions.
2132           It is very simple, and approximately 3-6 times faster than NWFPE.
2133
2134           It should be sufficient for most programs.  It may be not suitable
2135           for scientific calculations, but you have to check this for yourself.
2136           If you do not feel you need a faster FP emulation you should better
2137           choose NWFPE.
2138
2139 config VFP
2140         bool "VFP-format floating point maths"
2141         depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON
2142         help
2143           Say Y to include VFP support code in the kernel. This is needed
2144           if your hardware includes a VFP unit.
2145
2146           Please see <file:Documentation/arm/VFP/release-notes.txt> for
2147           release notes and additional status information.
2148
2149           Say N if your target does not have VFP hardware.
2150
2151 config VFPv3
2152         bool
2153         depends on VFP
2154         default y if CPU_V7
2155
2156 config NEON
2157         bool "Advanced SIMD (NEON) Extension support"
2158         depends on VFPv3 && CPU_V7
2159         help
2160           Say Y to include support code for NEON, the ARMv7 Advanced SIMD
2161           Extension.
2162
2163 config KERNEL_MODE_NEON
2164         bool "Support for NEON in kernel mode"
2165         depends on NEON && AEABI
2166         help
2167           Say Y to include support for NEON in kernel mode.
2168
2169 endmenu
2170
2171 menu "Userspace binary formats"
2172
2173 source "fs/Kconfig.binfmt"
2174
2175 endmenu
2176
2177 menu "Power management options"
2178
2179 source "kernel/power/Kconfig"
2180
2181 config ARCH_SUSPEND_POSSIBLE
2182         depends on CPU_ARM920T || CPU_ARM926T || CPU_FEROCEON || CPU_SA1100 || \
2183                 CPU_V6 || CPU_V6K || CPU_V7 || CPU_V7M || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK
2184         def_bool y
2185
2186 config ARM_CPU_SUSPEND
2187         def_bool PM_SLEEP || BL_SWITCHER || ARM_PSCI_FW
2188         depends on ARCH_SUSPEND_POSSIBLE
2189
2190 config ARCH_HIBERNATION_POSSIBLE
2191         bool
2192         depends on MMU
2193         default y if ARCH_SUSPEND_POSSIBLE
2194
2195 endmenu
2196
2197 source "net/Kconfig"
2198
2199 source "drivers/Kconfig"
2200
2201 source "drivers/firmware/Kconfig"
2202
2203 source "fs/Kconfig"
2204
2205 source "arch/arm/Kconfig.debug"
2206
2207 source "security/Kconfig"
2208
2209 source "crypto/Kconfig"
2210 if CRYPTO
2211 source "arch/arm/crypto/Kconfig"
2212 endif
2213
2214 source "lib/Kconfig"
2215
2216 source "arch/arm/kvm/Kconfig"