arch/arm/cpu/arm926ejs/at91/at91sam9263_devices.c

   1 /*
   2  * (C) Copyright 2007-2008
   3  * Stelian Pop <stelian.pop@leadtechdesign.com>
   4  * Lead Tech Design <www.leadtechdesign.com>
   5  *
   6  * (C) Copyright 2009
   7  * Daniel Gorsulowski <daniel.gorsulowski@esd.eu>
   8  * esd electronic system design gmbh <www.esd.eu>
   9  *
  10  * See file CREDITS for list of people who contributed to this
  11  * project.
  12  *
  13  * This program is free software; you can redistribute it and/or
  14  * modify it under the terms of the GNU General Public License as
  15  * published by the Free Software Foundation; either version 2 of
  16  * the License, or (at your option) any later version.
  17  *
  18  * This program is distributed in the hope that it will be useful,
  19  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  20  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  21  * GNU General Public License for more details.
  22  *
  23  * You should have received a copy of the GNU General Public License
  24  * along with this program; if not, write to the Free Software
  25  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  26  * MA 02111-1307 USA
  27  */
  28
  29 #include <common.h>
  30 #include <asm/arch/hardware.h>
  31 #include <asm/arch/io.h>
  32 #include <asm/arch/at91_common.h>
  33 #include <asm/arch/at91_pmc.h>
  34 #include <asm/arch/at91_pio.h>
  35
  36 void at91_serial0_hw_init(void)
  37 {
  38         at91_pmc_t      *pmc    = (at91_pmc_t *) AT91_PMC_BASE;
  39
  40         at91_set_a_periph(AT91_PIO_PORTA, 26, 1);               /* TXD0 */
  41         at91_set_a_periph(AT91_PIO_PORTA, 27, 0);               /* RXD0 */
  42         writel(1 << AT91SAM9263_ID_US0, &pmc->pcer);
  43 }
  44
  45 void at91_serial1_hw_init(void)
  46 {
  47         at91_pmc_t      *pmc    = (at91_pmc_t *) AT91_PMC_BASE;
  48
  49         at91_set_a_periph(AT91_PIO_PORTD, 0, 1);                /* TXD1 */
  50         at91_set_a_periph(AT91_PIO_PORTD, 1, 0);                /* RXD1 */
  51         writel(1 << AT91SAM9263_ID_US1, &pmc->pcer);
  52 }
  53
  54 void at91_serial2_hw_init(void)
  55 {
  56         at91_pmc_t      *pmc    = (at91_pmc_t *) AT91_PMC_BASE;
  57
  58         at91_set_a_periph(AT91_PIO_PORTD, 2, 1);                /* TXD2 */
  59         at91_set_a_periph(AT91_PIO_PORTD, 3, 0);                /* RXD2 */
  60         writel(1 << AT91SAM9263_ID_US2, &pmc->pcer);
  61 }
  62
  63 void at91_serial3_hw_init(void)
  64 {
  65         at91_pmc_t      *pmc    = (at91_pmc_t *) AT91_PMC_BASE;
  66
  67         at91_set_a_periph(AT91_PIO_PORTC, 30, 0);               /* DRXD */
  68         at91_set_a_periph(AT91_PIO_PORTC, 31, 1);               /* DTXD */
  69         writel(1 << AT91_ID_SYS, &pmc->pcer);
  70 }
  71
  72 void at91_serial_hw_init(void)
  73 {
  74 #ifdef CONFIG_USART0
  75         at91_serial0_hw_init();
  76 #endif
  77
  78 #ifdef CONFIG_USART1
  79         at91_serial1_hw_init();
  80 #endif
  81
  82 #ifdef CONFIG_USART2
  83         at91_serial2_hw_init();
  84 #endif
  85
  86 #ifdef CONFIG_USART3    /* DBGU */
  87         at91_serial3_hw_init();
  88 #endif
  89 }
  90
  91 #ifdef CONFIG_HAS_DATAFLASH
  92 void at91_spi0_hw_init(unsigned long cs_mask)
  93 {
  94         at91_pmc_t      *pmc    = (at91_pmc_t *) AT91_PMC_BASE;
  95
  96         at91_set_b_periph(AT91_PIO_PORTA, 0, 0);        /* SPI0_MISO */
  97         at91_set_b_periph(AT91_PIO_PORTA, 1, 0);        /* SPI0_MOSI */
  98         at91_set_b_periph(AT91_PIO_PORTA, 2, 0);        /* SPI0_SPCK */
  99
 100         /* Enable clock */
 101         writel(1 << AT91SAM9263_ID_SPI0, &pmc->pcer);
 102
 103         if (cs_mask & (1 << 0)) {
 104                 at91_set_b_periph(AT91_PIO_PORTA, 5, 1);
 105         }
 106         if (cs_mask & (1 << 1)) {
 107                 at91_set_b_periph(AT91_PIO_PORTA, 3, 1);
 108         }
 109         if (cs_mask & (1 << 2)) {
 110                 at91_set_b_periph(AT91_PIO_PORTA, 4, 1);
 111         }
 112         if (cs_mask & (1 << 3)) {
 113                 at91_set_b_periph(AT91_PIO_PORTB, 11, 1);
 114         }
 115         if (cs_mask & (1 << 4)) {
 116                 at91_set_pio_output(AT91_PIO_PORTA, 5, 1);
 117         }
 118         if (cs_mask & (1 << 5)) {
 119                 at91_set_pio_output(AT91_PIO_PORTA, 3, 1);
 120         }
 121         if (cs_mask & (1 << 6)) {
 122                 at91_set_pio_output(AT91_PIO_PORTA, 4, 1);
 123         }
 124         if (cs_mask & (1 << 7)) {
 125                 at91_set_pio_output(AT91_PIO_PORTB, 11, 1);
 126         }
 127 }
 128
 129 void at91_spi1_hw_init(unsigned long cs_mask)
 130 {
 131         at91_pmc_t      *pmc    = (at91_pmc_t *) AT91_PMC_BASE;
 132
 133         at91_set_a_periph(AT91_PIO_PORTB, 12, 0);       /* SPI1_MISO */
 134         at91_set_a_periph(AT91_PIO_PORTB, 13, 0);       /* SPI1_MOSI */
 135         at91_set_a_periph(AT91_PIO_PORTB, 14, 0);       /* SPI1_SPCK */
 136
 137         /* Enable clock */
 138         writel(1 << AT91SAM9263_ID_SPI1, &pmc->pcer);
 139
 140         if (cs_mask & (1 << 0)) {
 141                 at91_set_a_periph(AT91_PIO_PORTB, 15, 1);
 142         }
 143         if (cs_mask & (1 << 1)) {
 144                 at91_set_a_periph(AT91_PIO_PORTB, 16, 1);
 145         }
 146         if (cs_mask & (1 << 2)) {
 147                 at91_set_a_periph(AT91_PIO_PORTB, 17, 1);
 148         }
 149         if (cs_mask & (1 << 3)) {
 150                 at91_set_a_periph(AT91_PIO_PORTB, 18, 1);
 151         }
 152         if (cs_mask & (1 << 4)) {
 153                 at91_set_pio_output(AT91_PIO_PORTB, 15, 1);
 154         }
 155         if (cs_mask & (1 << 5)) {
 156                 at91_set_pio_output(AT91_PIO_PORTB, 16, 1);
 157         }
 158         if (cs_mask & (1 << 6)) {
 159                 at91_set_pio_output(AT91_PIO_PORTB, 17, 1);
 160         }
 161         if (cs_mask & (1 << 7)) {
 162                 at91_set_pio_output(AT91_PIO_PORTB, 18, 1);
 163         }
 164 }
 165 #endif
 166
 167 #ifdef CONFIG_MACB
 168 void at91_macb_hw_init(void)
 169 {
 170         at91_set_a_periph(AT91_PIO_PORTE, 21, 0);       /* ETXCK_EREFCK */
 171         at91_set_b_periph(AT91_PIO_PORTC, 25, 0);       /* ERXDV */
 172         at91_set_a_periph(AT91_PIO_PORTE, 25, 0);       /* ERX0 */
 173         at91_set_a_periph(AT91_PIO_PORTE, 26, 0);       /* ERX1 */
 174         at91_set_a_periph(AT91_PIO_PORTE, 27, 0);       /* ERXER */
 175         at91_set_a_periph(AT91_PIO_PORTE, 28, 0);       /* ETXEN */
 176         at91_set_a_periph(AT91_PIO_PORTE, 23, 0);       /* ETX0 */
 177         at91_set_a_periph(AT91_PIO_PORTE, 24, 0);       /* ETX1 */
 178         at91_set_a_periph(AT91_PIO_PORTE, 30, 0);       /* EMDIO */
 179         at91_set_a_periph(AT91_PIO_PORTE, 29, 0);       /* EMDC */
 180
 181 #ifndef CONFIG_RMII
 182         at91_set_a_periph(AT91_PIO_PORTE, 22, 0);       /* ECRS */
 183         at91_set_b_periph(AT91_PIO_PORTC, 26, 0);       /* ECOL */
 184         at91_set_b_periph(AT91_PIO_PORTC, 22, 0);       /* ERX2 */
 185         at91_set_b_periph(AT91_PIO_PORTC, 23, 0);       /* ERX3 */
 186         at91_set_b_periph(AT91_PIO_PORTC, 27, 0);       /* ERXCK */
 187         at91_set_b_periph(AT91_PIO_PORTC, 20, 0);       /* ETX2 */
 188         at91_set_b_periph(AT91_PIO_PORTC, 21, 0);       /* ETX3 */
 189         at91_set_b_periph(AT91_PIO_PORTC, 24, 0);       /* ETXER */
 190 #endif
 191 }
 192 #endif
 193
 194 #ifdef CONFIG_USB_OHCI_NEW
 195 void at91_uhp_hw_init(void)
 196 {
 197         /* Enable VBus on UHP ports */
 198         at91_set_pio_output(AT91_PIO_PORTA, 21, 0);
 199         at91_set_pio_output(AT91_PIO_PORTA, 24, 0);
 200 }
 201 #endif
 202
 203 #ifdef CONFIG_AT91_CAN
 204 void at91_can_hw_init(void)
 205 {
 206         at91_pmc_t      *pmc    = (at91_pmc_t *) AT91_PMC_BASE;
 207
 208         at91_set_a_periph(AT91_PIO_PORTA, 13, 0);       /* CAN_TX */
 209         at91_set_a_periph(AT91_PIO_PORTA, 14, 1);       /* CAN_RX */
 210
 211         /* Enable clock */
 212         writel(1 << AT91SAM9263_ID_CAN, &pmc->pcer);
 213 }
 214 #endif