2 * SoC-specific lowlevel code for tms320dm365 and similar chips
3 * Actually used for booting from NAND with nand_spl.
6 * Heiko Schocher, DENX Software Engineering, hs@denx.de.
8 * SPDX-License-Identifier: GPL-2.0+
14 #include <asm/arch/dm365_lowlevel.h>
15 #include <asm/arch/hardware.h>
17 void dm365_waitloop(unsigned long loopcnt
)
21 for (i
= 0; i
< loopcnt
; i
++)
25 int dm365_pll1_init(unsigned long pllmult
, unsigned long prediv
)
27 unsigned int clksrc
= 0x0;
29 /* Power up the PLL */
30 clrbits_le32(&dv_pll0_regs
->pllctl
, PLLCTL_PLLPWRDN
);
32 clrbits_le32(&dv_pll0_regs
->pllctl
, PLLCTL_RES_9
);
33 setbits_le32(&dv_pll0_regs
->pllctl
,
34 clksrc
<< PLLCTL_CLOCK_MODE_SHIFT
);
37 * Set PLLENSRC '0', PLL Enable(PLLEN) selection is controlled
40 clrbits_le32(&dv_pll0_regs
->pllctl
, PLLCTL_PLLENSRC
);
42 /* Set PLLEN=0 => PLL BYPASS MODE */
43 clrbits_le32(&dv_pll0_regs
->pllctl
, PLLCTL_PLLEN
);
47 /* PLLRST=1(reset assert) */
48 setbits_le32(&dv_pll0_regs
->pllctl
, PLLCTL_PLLRST
);
52 /*Bring PLL out of Reset*/
53 clrbits_le32(&dv_pll0_regs
->pllctl
, PLLCTL_PLLRST
);
55 /* Program the Multiper and Pre-Divider for PLL1 */
56 writel(pllmult
, &dv_pll0_regs
->pllm
);
57 writel(prediv
, &dv_pll0_regs
->prediv
);
59 /* Assert TENABLE = 1, TENABLEDIV = 1, TINITZ = 1 */
60 writel(PLLSECCTL_STOPMODE
| PLLSECCTL_TENABLEDIV
| PLLSECCTL_TENABLE
|
61 PLLSECCTL_TINITZ
, &dv_pll0_regs
->secctl
);
62 /* Assert TENABLE = 1, TENABLEDIV = 1, TINITZ = 0 */
63 writel(PLLSECCTL_STOPMODE
| PLLSECCTL_TENABLEDIV
| PLLSECCTL_TENABLE
,
64 &dv_pll0_regs
->secctl
);
65 /* Assert TENABLE = 0, TENABLEDIV = 0, TINITZ = 0 */
66 writel(PLLSECCTL_STOPMODE
, &dv_pll0_regs
->secctl
);
67 /* Assert TENABLE = 0, TENABLEDIV = 0, TINITZ = 1 */
68 writel(PLLSECCTL_STOPMODE
| PLLSECCTL_TINITZ
, &dv_pll0_regs
->secctl
);
70 /* Program the PostDiv for PLL1 */
71 writel(PLL_POSTDEN
, &dv_pll0_regs
->postdiv
);
73 /* Post divider setting for PLL1 */
74 writel(CONFIG_SYS_DM36x_PLL1_PLLDIV1
, &dv_pll0_regs
->plldiv1
);
75 writel(CONFIG_SYS_DM36x_PLL1_PLLDIV2
, &dv_pll0_regs
->plldiv2
);
76 writel(CONFIG_SYS_DM36x_PLL1_PLLDIV3
, &dv_pll0_regs
->plldiv3
);
77 writel(CONFIG_SYS_DM36x_PLL1_PLLDIV4
, &dv_pll0_regs
->plldiv4
);
78 writel(CONFIG_SYS_DM36x_PLL1_PLLDIV5
, &dv_pll0_regs
->plldiv5
);
79 writel(CONFIG_SYS_DM36x_PLL1_PLLDIV6
, &dv_pll0_regs
->plldiv6
);
80 writel(CONFIG_SYS_DM36x_PLL1_PLLDIV7
, &dv_pll0_regs
->plldiv7
);
81 writel(CONFIG_SYS_DM36x_PLL1_PLLDIV8
, &dv_pll0_regs
->plldiv8
);
82 writel(CONFIG_SYS_DM36x_PLL1_PLLDIV9
, &dv_pll0_regs
->plldiv9
);
86 /* Set the GOSET bit */
87 writel(PLLCMD_GOSET
, &dv_pll0_regs
->pllcmd
); /* Go */
91 /* Wait for PLL to LOCK */
92 while (!((readl(&dv_sys_module_regs
->pll0_config
) & PLL0_LOCK
)
96 /* Enable the PLL Bit of PLLCTL*/
97 setbits_le32(&dv_pll0_regs
->pllctl
, PLLCTL_PLLEN
);
102 int dm365_pll2_init(unsigned long pllm
, unsigned long prediv
)
104 unsigned int clksrc
= 0x0;
106 /* Power up the PLL*/
107 clrbits_le32(&dv_pll1_regs
->pllctl
, PLLCTL_PLLPWRDN
);
110 * Select the Clock Mode as Onchip Oscilator or External Clock on
112 * VDB has input on MXI pin
114 clrbits_le32(&dv_pll1_regs
->pllctl
, PLLCTL_RES_9
);
115 setbits_le32(&dv_pll1_regs
->pllctl
,
116 clksrc
<< PLLCTL_CLOCK_MODE_SHIFT
);
119 * Set PLLENSRC '0', PLL Enable(PLLEN) selection is controlled
122 clrbits_le32(&dv_pll1_regs
->pllctl
, PLLCTL_PLLENSRC
);
124 /* Set PLLEN=0 => PLL BYPASS MODE */
125 clrbits_le32(&dv_pll1_regs
->pllctl
, PLLCTL_PLLEN
);
129 /* PLLRST=1(reset assert) */
130 setbits_le32(&dv_pll1_regs
->pllctl
, PLLCTL_PLLRST
);
134 /* Bring PLL out of Reset */
135 clrbits_le32(&dv_pll1_regs
->pllctl
, PLLCTL_PLLRST
);
137 /* Program the Multiper and Pre-Divider for PLL2 */
138 writel(pllm
, &dv_pll1_regs
->pllm
);
139 writel(prediv
, &dv_pll1_regs
->prediv
);
141 writel(PLL_POSTDEN
, &dv_pll1_regs
->postdiv
);
143 /* Assert TENABLE = 1, TENABLEDIV = 1, TINITZ = 1 */
144 writel(PLLSECCTL_STOPMODE
| PLLSECCTL_TENABLEDIV
| PLLSECCTL_TENABLE
|
145 PLLSECCTL_TINITZ
, &dv_pll1_regs
->secctl
);
146 /* Assert TENABLE = 1, TENABLEDIV = 1, TINITZ = 0 */
147 writel(PLLSECCTL_STOPMODE
| PLLSECCTL_TENABLEDIV
| PLLSECCTL_TENABLE
,
148 &dv_pll1_regs
->secctl
);
149 /* Assert TENABLE = 0, TENABLEDIV = 0, TINITZ = 0 */
150 writel(PLLSECCTL_STOPMODE
, &dv_pll1_regs
->secctl
);
151 /* Assert TENABLE = 0, TENABLEDIV = 0, TINITZ = 1 */
152 writel(PLLSECCTL_STOPMODE
| PLLSECCTL_TINITZ
, &dv_pll1_regs
->secctl
);
154 /* Post divider setting for PLL2 */
155 writel(CONFIG_SYS_DM36x_PLL2_PLLDIV1
, &dv_pll1_regs
->plldiv1
);
156 writel(CONFIG_SYS_DM36x_PLL2_PLLDIV2
, &dv_pll1_regs
->plldiv2
);
157 writel(CONFIG_SYS_DM36x_PLL2_PLLDIV3
, &dv_pll1_regs
->plldiv3
);
158 writel(CONFIG_SYS_DM36x_PLL2_PLLDIV4
, &dv_pll1_regs
->plldiv4
);
159 writel(CONFIG_SYS_DM36x_PLL2_PLLDIV5
, &dv_pll1_regs
->plldiv5
);
161 /* GoCmd for PostDivider to take effect */
162 writel(PLLCMD_GOSET
, &dv_pll1_regs
->pllcmd
);
166 /* Wait for PLL to LOCK */
167 while (!((readl(&dv_sys_module_regs
->pll1_config
) & PLL1_LOCK
)
171 dm365_waitloop(4100);
173 /* Enable the PLL2 */
174 setbits_le32(&dv_pll1_regs
->pllctl
, PLLCTL_PLLEN
);
176 /* do this after PLL's have been set up */
177 writel(CONFIG_SYS_DM36x_PERI_CLK_CTRL
,
178 &dv_sys_module_regs
->peri_clkctl
);
183 int dm365_ddr_setup(void)
185 lpsc_on(DAVINCI_LPSC_DDR_EMIF
);
186 clrbits_le32(&dv_sys_module_regs
->vtpiocr
,
187 VPTIO_IOPWRDN
| VPTIO_CLRZ
| VPTIO_LOCK
| VPTIO_PWRDN
);
189 /* Set bit CLRZ (bit 13) */
190 setbits_le32(&dv_sys_module_regs
->vtpiocr
, VPTIO_CLRZ
);
192 /* Check VTP READY Status */
193 while (!(readl(&dv_sys_module_regs
->vtpiocr
) & VPTIO_RDY
))
196 /* Set bit VTP_IOPWRDWN bit 14 for DDR input buffers) */
197 setbits_le32(&dv_sys_module_regs
->vtpiocr
, VPTIO_IOPWRDN
);
199 /* Set bit LOCK(bit7) */
200 setbits_le32(&dv_sys_module_regs
->vtpiocr
, VPTIO_LOCK
);
203 * Powerdown VTP as it is locked (bit 6)
204 * Set bit VTP_IOPWRDWN bit 14 for DDR input buffers)
206 setbits_le32(&dv_sys_module_regs
->vtpiocr
,
207 VPTIO_IOPWRDN
| VPTIO_PWRDN
);
209 /* Wait for calibration to complete */
212 /* Set the DDR2 to synreset, then enable it again */
213 lpsc_syncreset(DAVINCI_LPSC_DDR_EMIF
);
214 lpsc_on(DAVINCI_LPSC_DDR_EMIF
);
216 writel(CONFIG_SYS_DM36x_DDR2_DDRPHYCR
, &dv_ddr2_regs_ctrl
->ddrphycr
);
218 /* Program SDRAM Bank Config Register */
219 writel((CONFIG_SYS_DM36x_DDR2_SDBCR
| DV_DDR_BOOTUNLOCK
),
220 &dv_ddr2_regs_ctrl
->sdbcr
);
221 writel((CONFIG_SYS_DM36x_DDR2_SDBCR
| DV_DDR_TIMUNLOCK
),
222 &dv_ddr2_regs_ctrl
->sdbcr
);
224 /* Program SDRAM Timing Control Register1 */
225 writel(CONFIG_SYS_DM36x_DDR2_SDTIMR
, &dv_ddr2_regs_ctrl
->sdtimr
);
226 /* Program SDRAM Timing Control Register2 */
227 writel(CONFIG_SYS_DM36x_DDR2_SDTIMR2
, &dv_ddr2_regs_ctrl
->sdtimr2
);
229 writel(CONFIG_SYS_DM36x_DDR2_PBBPR
, &dv_ddr2_regs_ctrl
->pbbpr
);
231 writel(CONFIG_SYS_DM36x_DDR2_SDBCR
, &dv_ddr2_regs_ctrl
->sdbcr
);
233 /* Program SDRAM Refresh Control Register */
234 writel(CONFIG_SYS_DM36x_DDR2_SDRCR
, &dv_ddr2_regs_ctrl
->sdrcr
);
236 lpsc_syncreset(DAVINCI_LPSC_DDR_EMIF
);
237 lpsc_on(DAVINCI_LPSC_DDR_EMIF
);
242 static void dm365_vpss_sync_reset(void)
244 unsigned int PdNum
= 0;
247 setbits_le32(&dv_sys_module_regs
->vpss_clkctl
,
248 VPSS_CLK_CTL_VPSS_CLKMD
);
250 /* LPSC SyncReset DDR Clock Enable */
251 writel(((readl(&dv_psc_regs
->mdctl
[DAVINCI_LPSC_VPSSMASTER
]) &
252 ~PSC_MD_STATE_MSK
) | PSC_SYNCRESET
),
253 &dv_psc_regs
->mdctl
[DAVINCI_LPSC_VPSSMASTER
]);
255 writel((1 << PdNum
), &dv_psc_regs
->ptcmd
);
257 while (!(((readl(&dv_psc_regs
->ptstat
) >> PdNum
) & PSC_GOSTAT
) == 0))
259 while (!((readl(&dv_psc_regs
->mdstat
[DAVINCI_LPSC_VPSSMASTER
]) &
260 PSC_MD_STATE_MSK
) == PSC_SYNCRESET
))
264 static void dm365_por_reset(void)
266 struct davinci_timer
*wdog
=
267 (struct davinci_timer
*)DAVINCI_WDOG_BASE
;
269 if (readl(&dv_pll0_regs
->rstype
) &
270 (PLL_RSTYPE_POR
| PLL_RSTYPE_XWRST
)) {
271 dm365_vpss_sync_reset();
273 writel(DV_TMPBUF_VAL
, TMPBUF
);
274 setbits_le32(TMPSTATUS
, FLAG_PORRST
);
275 writel(DV_WDT_ENABLE_SYS_RESET
, &wdog
->na1
);
276 writel(DV_WDT_TRIGGER_SYS_RESET
, &wdog
->na2
);
282 static void dm365_wdt_reset(void)
284 struct davinci_timer
*wdog
=
285 (struct davinci_timer
*)DAVINCI_WDOG_BASE
;
287 if (readl(TMPBUF
) != DV_TMPBUF_VAL
) {
288 writel(DV_TMPBUF_VAL
, TMPBUF
);
289 setbits_le32(TMPSTATUS
, FLAG_PORRST
);
290 setbits_le32(TMPSTATUS
, FLAG_FLGOFF
);
294 dm365_vpss_sync_reset();
296 writel(DV_WDT_ENABLE_SYS_RESET
, &wdog
->na1
);
297 writel(DV_WDT_TRIGGER_SYS_RESET
, &wdog
->na2
);
303 static void dm365_wdt_flag_on(void)
306 clrbits_le32(&dv_sys_module_regs
->vpss_clkctl
,
307 VPSS_CLK_CTL_VPSS_CLKMD
);
309 setbits_le32(TMPSTATUS
, FLAG_FLGON
);
312 void dm365_psc_init(void)
315 unsigned char lpsc_start
;
316 unsigned char lpsc_end
, lpscgroup
, lpscmin
, lpscmax
;
317 unsigned int PdNum
= 0;
322 for (lpscgroup
= lpscmin
; lpscgroup
<= lpscmax
; lpscgroup
++) {
323 if (lpscgroup
== 0) {
324 /* Enabling LPSC 3 to 28 SCR first */
325 lpsc_start
= DAVINCI_LPSC_VPSSMSTR
;
326 lpsc_end
= DAVINCI_LPSC_TIMER1
;
327 } else if (lpscgroup
== 1) { /* Skip locked LPSCs [29-37] */
328 lpsc_start
= DAVINCI_LPSC_CFG5
;
329 lpsc_end
= DAVINCI_LPSC_VPSSMASTER
;
331 lpsc_start
= DAVINCI_LPSC_MJCP
;
332 lpsc_end
= DAVINCI_LPSC_HDVICP
;
335 /* NEXT=0x3, Enable LPSC's */
336 for (i
= lpsc_start
; i
<= lpsc_end
; i
++)
337 setbits_le32(&dv_psc_regs
->mdctl
[i
], PSC_ENABLE
);
340 * Program goctl to start transition sequence for LPSCs
341 * CSL_PSC_0_REGS->PTCMD = (1<<PdNum); Kick off Power
344 writel((1 << PdNum
), &dv_psc_regs
->ptcmd
);
347 * Wait for GOSTAT = NO TRANSITION from PSC for Powerdomain 0
349 while (!(((readl(&dv_psc_regs
->ptstat
) >> PdNum
) & PSC_GOSTAT
)
353 /* Wait for MODSTAT = ENABLE from LPSC's */
354 for (i
= lpsc_start
; i
<= lpsc_end
; i
++)
355 while (!((readl(&dv_psc_regs
->mdstat
[i
]) &
356 PSC_MD_STATE_MSK
) == PSC_ENABLE
))
361 static void dm365_emif_init(void)
363 writel(CONFIG_SYS_DM36x_AWCCR
, &davinci_emif_regs
->awccr
);
364 writel(CONFIG_SYS_DM36x_AB1CR
, &davinci_emif_regs
->ab1cr
);
366 setbits_le32(&davinci_emif_regs
->nandfcr
, DAVINCI_NANDFCR_CS2NAND
);
368 writel(CONFIG_SYS_DM36x_AB2CR
, &davinci_emif_regs
->ab2cr
);
373 void dm365_pinmux_ctl(unsigned long offset
, unsigned long mask
,
376 clrbits_le32(&dv_sys_module_regs
->pinmux
[offset
], mask
);
377 setbits_le32(&dv_sys_module_regs
->pinmux
[offset
], (mask
& value
));
380 __attribute__((weak
))
381 void board_gpio_init(void)
386 #if defined(CONFIG_POST)
387 int post_log(char *format
, ...)
393 void dm36x_lowlevel_init(ulong bootflag
)
395 struct davinci_uart_ctrl_regs
*davinci_uart_ctrl_regs
=
396 (struct davinci_uart_ctrl_regs
*)(CONFIG_SYS_NS16550_COM1
+
397 DAVINCI_UART_CTRL_BASE
);
399 /* Mask all interrupts */
400 writel(DV_AINTC_INTCTL_IDMODE
, &dv_aintc_regs
->intctl
);
401 writel(0x0, &dv_aintc_regs
->eabase
);
402 writel(0x0, &dv_aintc_regs
->eint0
);
403 writel(0x0, &dv_aintc_regs
->eint1
);
405 /* Clear all interrupts */
406 writel(0xffffffff, &dv_aintc_regs
->fiq0
);
407 writel(0xffffffff, &dv_aintc_regs
->fiq1
);
408 writel(0xffffffff, &dv_aintc_regs
->irq0
);
409 writel(0xffffffff, &dv_aintc_regs
->irq1
);
414 /* System PSC setup - enable all */
418 dm365_pinmux_ctl(0, 0xFFFFFFFF, CONFIG_SYS_DM36x_PINMUX0
);
419 dm365_pinmux_ctl(1, 0xFFFFFFFF, CONFIG_SYS_DM36x_PINMUX1
);
420 dm365_pinmux_ctl(2, 0xFFFFFFFF, CONFIG_SYS_DM36x_PINMUX2
);
421 dm365_pinmux_ctl(3, 0xFFFFFFFF, CONFIG_SYS_DM36x_PINMUX3
);
422 dm365_pinmux_ctl(4, 0xFFFFFFFF, CONFIG_SYS_DM36x_PINMUX4
);
425 dm365_pll1_init(CONFIG_SYS_DM36x_PLL1_PLLM
,
426 CONFIG_SYS_DM36x_PLL1_PREDIV
);
427 dm365_pll2_init(CONFIG_SYS_DM36x_PLL2_PLLM
,
428 CONFIG_SYS_DM36x_PLL2_PREDIV
);
433 NS16550_init((NS16550_t
)(CONFIG_SYS_NS16550_COM1
),
434 CONFIG_SYS_NS16550_CLK
/ 16 / CONFIG_BAUDRATE
);
437 * Fix Power and Emulation Management Register
438 * see sprufh2.pdf page 38 Table 22
440 writel((DAVINCI_UART_PWREMU_MGMT_FREE
| DAVINCI_UART_PWREMU_MGMT_URRST
|
441 DAVINCI_UART_PWREMU_MGMT_UTRST
),
442 &davinci_uart_ctrl_regs
->pwremu_mgmt
);
452 #if defined(CONFIG_POST)
454 * Do memory tests, calls arch_memory_failure_handle()