arch/arm/cpu/arm926ejs/kirkwood/timer.c

   1 /*
   2  * Copyright (C) Marvell International Ltd. and its affiliates
   3  * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 #include <common.h>
   9 #include <asm/io.h>
  10 #include <asm/arch/kirkwood.h>
  11
  12 #define UBOOT_CNTR      0       /* counter to use for uboot timer */
  13
  14 /* Timer reload and current value registers */
  15 struct kwtmr_val {
  16         u32 reload;     /* Timer reload reg */
  17         u32 val;        /* Timer value reg */
  18 };
  19
  20 /* Timer registers */
  21 struct kwtmr_registers {
  22         u32 ctrl;       /* Timer control reg */
  23         u32 pad[3];
  24         struct kwtmr_val tmr[2];
  25         u32 wdt_reload;
  26         u32 wdt_val;
  27 };
  28
  29 struct kwtmr_registers *kwtmr_regs = (struct kwtmr_registers *)KW_TIMER_BASE;
  30
  31 /*
  32  * ARM Timers Registers Map
  33  */
  34 #define CNTMR_CTRL_REG                  &kwtmr_regs->ctrl
  35 #define CNTMR_RELOAD_REG(tmrnum)        &kwtmr_regs->tmr[tmrnum].reload
  36 #define CNTMR_VAL_REG(tmrnum)           &kwtmr_regs->tmr[tmrnum].val
  37
  38 /*
  39  * ARM Timers Control Register
  40  * CPU_TIMERS_CTRL_REG (CTCR)
  41  */
  42 #define CTCR_ARM_TIMER_EN_OFFS(cntr)    (cntr * 2)
  43 #define CTCR_ARM_TIMER_EN_MASK(cntr)    (1 << CTCR_ARM_TIMER_EN_OFFS)
  44 #define CTCR_ARM_TIMER_EN(cntr)         (1 << CTCR_ARM_TIMER_EN_OFFS(cntr))
  45 #define CTCR_ARM_TIMER_DIS(cntr)        (0 << CTCR_ARM_TIMER_EN_OFFS(cntr))
  46
  47 #define CTCR_ARM_TIMER_AUTO_OFFS(cntr)  ((cntr * 2) + 1)
  48 #define CTCR_ARM_TIMER_AUTO_MASK(cntr)  (1 << 1)
  49 #define CTCR_ARM_TIMER_AUTO_EN(cntr)    (1 << CTCR_ARM_TIMER_AUTO_OFFS(cntr))
  50 #define CTCR_ARM_TIMER_AUTO_DIS(cntr)   (0 << CTCR_ARM_TIMER_AUTO_OFFS(cntr))
  51
  52 /*
  53  * ARM Timer\Watchdog Reload Register
  54  * CNTMR_RELOAD_REG (TRR)
  55  */
  56 #define TRG_ARM_TIMER_REL_OFFS          0
  57 #define TRG_ARM_TIMER_REL_MASK          0xffffffff
  58
  59 /*
  60  * ARM Timer\Watchdog Register
  61  * CNTMR_VAL_REG (TVRG)
  62  */
  63 #define TVR_ARM_TIMER_OFFS              0
  64 #define TVR_ARM_TIMER_MASK              0xffffffff
  65 #define TVR_ARM_TIMER_MAX               0xffffffff
  66 #define TIMER_LOAD_VAL                  0xffffffff
  67
  68 #define READ_TIMER                      (readl(CNTMR_VAL_REG(UBOOT_CNTR)) /     \
  69                                          (CONFIG_SYS_TCLK / 1000))
  70
  71 DECLARE_GLOBAL_DATA_PTR;
  72
  73 #define timestamp gd->arch.tbl
  74 #define lastdec gd->arch.lastinc
  75
  76 ulong get_timer_masked(void)
  77 {
  78         ulong now = READ_TIMER;
  79
  80         if (lastdec >= now) {
  81                 /* normal mode */
  82                 timestamp += lastdec - now;
  83         } else {
  84                 /* we have an overflow ... */
  85                 timestamp += lastdec +
  86                         (TIMER_LOAD_VAL / (CONFIG_SYS_TCLK / 1000)) - now;
  87         }
  88         lastdec = now;
  89
  90         return timestamp;
  91 }
  92
  93 ulong get_timer(ulong base)
  94 {
  95         return get_timer_masked() - base;
  96 }
  97
  98 void __udelay(unsigned long usec)
  99 {
 100         uint current;
 101         ulong delayticks;
 102
 103         current = readl(CNTMR_VAL_REG(UBOOT_CNTR));
 104         delayticks = (usec * (CONFIG_SYS_TCLK / 1000000));
 105
 106         if (current < delayticks) {
 107                 delayticks -= current;
 108                 while (readl(CNTMR_VAL_REG(UBOOT_CNTR)) < current) ;
 109                 while ((TIMER_LOAD_VAL - delayticks) <
 110                         readl(CNTMR_VAL_REG(UBOOT_CNTR))) ;
 111         } else {
 112                 while (readl(CNTMR_VAL_REG(UBOOT_CNTR)) >
 113                         (current - delayticks)) ;
 114         }
 115 }
 116
 117 /*
 118  * init the counter
 119  */
 120 int timer_init(void)
 121 {
 122         unsigned int cntmrctrl;
 123
 124         /* load value into timer */
 125         writel(TIMER_LOAD_VAL, CNTMR_RELOAD_REG(UBOOT_CNTR));
 126         writel(TIMER_LOAD_VAL, CNTMR_VAL_REG(UBOOT_CNTR));
 127
 128         /* enable timer in auto reload mode */
 129         cntmrctrl = readl(CNTMR_CTRL_REG);
 130         cntmrctrl |= CTCR_ARM_TIMER_EN(UBOOT_CNTR);
 131         cntmrctrl |= CTCR_ARM_TIMER_AUTO_EN(UBOOT_CNTR);
 132         writel(cntmrctrl, CNTMR_CTRL_REG);
 133
 134         /* init the timestamp and lastdec value */
 135         lastdec = READ_TIMER;
 136         timestamp = 0;
 137
 138         return 0;
 139 }
 140
 141 /*
 142  * This function is derived from PowerPC code (read timebase as long long).
 143  * On ARM it just returns the timer value.
 144  */
 145 unsigned long long get_ticks(void)
 146 {
 147         return get_timer(0);
 148 }
 149
 150 /*
 151  * This function is derived from PowerPC code (timebase clock frequency).
 152  * On ARM it returns the number of timer ticks per second.
 153  */
 154 ulong get_tbclk (void)
 155 {
 156         return (ulong)CONFIG_SYS_HZ;
 157 }