2 * Freescale i.MX23/i.MX28 common code
4 * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
5 * on behalf of DENX Software Engineering GmbH
7 * Based on code from LTIB:
8 * Copyright (C) 2010 Freescale Semiconductor, Inc.
10 * SPDX-License-Identifier: GPL-2.0+
14 #include <asm/errno.h>
16 #include <asm/arch/clock.h>
17 #include <asm/imx-common/dma.h>
18 #include <asm/arch/gpio.h>
19 #include <asm/arch/iomux.h>
20 #include <asm/arch/imx-regs.h>
21 #include <asm/arch/sys_proto.h>
22 #include <linux/compiler.h>
24 DECLARE_GLOBAL_DATA_PTR
;
26 /* Lowlevel init isn't used on i.MX28, so just have a dummy here */
27 void lowlevel_init(void) {}
29 void reset_cpu(ulong ignored
) __attribute__((noreturn
));
31 void reset_cpu(ulong ignored
)
33 struct mxs_rtc_regs
*rtc_regs
=
34 (struct mxs_rtc_regs
*)MXS_RTC_BASE
;
35 struct mxs_lcdif_regs
*lcdif_regs
=
36 (struct mxs_lcdif_regs
*)MXS_LCDIF_BASE
;
39 * Shut down the LCD controller as it interferes with BootROM boot mode
42 writel(LCDIF_CTRL_RUN
, &lcdif_regs
->hw_lcdif_ctrl_clr
);
44 /* Wait 1 uS before doing the actual watchdog reset */
45 writel(1, &rtc_regs
->hw_rtc_watchdog
);
46 writel(RTC_CTRL_WATCHDOGEN
, &rtc_regs
->hw_rtc_ctrl_set
);
48 /* Endless loop, reset will exit from here */
53 void enable_caches(void)
55 #ifndef CONFIG_SYS_ICACHE_OFF
58 #ifndef CONFIG_SYS_DCACHE_OFF
64 * This function will craft a jumptable at 0x0 which will redirect interrupt
65 * vectoring to proper location of U-Boot in RAM.
67 * The structure of the jumptable will be as follows:
68 * ldr pc, [pc, #0x18] ..... for each vector, thus repeated 8 times
69 * <destination address> ... for each previous ldr, thus also repeated 8 times
71 * The "ldr pc, [pc, #0x18]" instruction above loads address from memory at
72 * offset 0x18 from current value of PC register. Note that PC is already
73 * incremented by 4 when computing the offset, so the effective offset is
74 * actually 0x20, this the associated <destination address>. Loading the PC
75 * register with an address performs a jump to that address.
77 void mx28_fixup_vt(uint32_t start_addr
)
79 /* ldr pc, [pc, #0x18] */
80 const uint32_t ldr_pc
= 0xe59ff018;
81 /* Jumptable location is 0x0 */
82 uint32_t *vt
= (uint32_t *)0x0;
85 for (i
= 0; i
< 8; i
++) {
86 /* cppcheck-suppress nullPointer */
88 /* cppcheck-suppress nullPointer */
89 vt
[i
+ 8] = start_addr
+ (4 * i
);
93 #ifdef CONFIG_ARCH_MISC_INIT
94 int arch_misc_init(void)
96 mx28_fixup_vt(gd
->relocaddr
);
101 int arch_cpu_init(void)
103 struct mxs_clkctrl_regs
*clkctrl_regs
=
104 (struct mxs_clkctrl_regs
*)MXS_CLKCTRL_BASE
;
105 extern uint32_t _start
;
107 mx28_fixup_vt((uint32_t)&_start
);
112 /* Clear bypass bit */
113 writel(CLKCTRL_CLKSEQ_BYPASS_GPMI
,
114 &clkctrl_regs
->hw_clkctrl_clkseq_set
);
116 /* Set GPMI clock to ref_gpmi / 12 */
117 clrsetbits_le32(&clkctrl_regs
->hw_clkctrl_gpmi
,
118 CLKCTRL_GPMI_CLKGATE
| CLKCTRL_GPMI_DIV_MASK
, 1);
123 * Configure GPIO unit
127 #ifdef CONFIG_APBH_DMA
135 u32
get_cpu_rev(void)
137 struct mxs_digctl_regs
*digctl_regs
=
138 (struct mxs_digctl_regs
*)MXS_DIGCTL_BASE
;
139 uint8_t rev
= readl(&digctl_regs
->hw_digctl_chipid
) & 0x000000FF;
141 switch (readl(&digctl_regs
->hw_digctl_chipid
) & HW_DIGCTL_CHIPID_MASK
) {
142 case HW_DIGCTL_CHIPID_MX23
:
149 return (MXC_CPU_MX23
<< 12) | (rev
+ 0x10);
153 case HW_DIGCTL_CHIPID_MX28
:
156 return (MXC_CPU_MX28
<< 12) | 0x12;
165 #if defined(CONFIG_DISPLAY_CPUINFO)
166 const char *get_imx_type(u32 imxtype
)
170 return "23"; /* Quad-Plus version of the mx6 */
172 return "28"; /* Dual-Plus version of the mx6 */
178 int print_cpuinfo(void)
181 struct mxs_spl_data
*data
= (struct mxs_spl_data
*)
182 ((CONFIG_SYS_TEXT_BASE
- sizeof(struct mxs_spl_data
)) & ~0xf);
184 cpurev
= get_cpu_rev();
185 printf("CPU: Freescale i.MX%s rev%d.%d at %d MHz\n",
186 get_imx_type((cpurev
& 0xFF000) >> 12),
187 (cpurev
& 0x000F0) >> 4,
188 (cpurev
& 0x0000F) >> 0,
189 mxc_get_clock(MXC_ARM_CLK
) / 1000000);
190 printf("BOOT: %s\n", mxs_boot_modes
[data
->boot_mode_idx
].mode
);
195 int do_mx28_showclocks(cmd_tbl_t
*cmdtp
, int flag
, int argc
, char *const argv
[])
197 printf("CPU: %3d MHz\n", mxc_get_clock(MXC_ARM_CLK
) / 1000000);
198 printf("BUS: %3d MHz\n", mxc_get_clock(MXC_AHB_CLK
) / 1000000);
199 printf("EMI: %3d MHz\n", mxc_get_clock(MXC_EMI_CLK
));
200 printf("GPMI: %3d MHz\n", mxc_get_clock(MXC_GPMI_CLK
) / 1000000);
205 * Initializes on-chip ethernet controllers.
207 #if defined(CONFIG_MX28) && defined(CONFIG_CMD_NET)
208 int cpu_eth_init(bd_t
*bis
)
210 struct mxs_clkctrl_regs
*clkctrl_regs
=
211 (struct mxs_clkctrl_regs
*)MXS_CLKCTRL_BASE
;
213 /* Turn on ENET clocks */
214 clrbits_le32(&clkctrl_regs
->hw_clkctrl_enet
,
215 CLKCTRL_ENET_SLEEP
| CLKCTRL_ENET_DISABLE
);
217 /* Set up ENET PLL for 50 MHz */
218 /* Power on ENET PLL */
219 writel(CLKCTRL_PLL2CTRL0_POWER
,
220 &clkctrl_regs
->hw_clkctrl_pll2ctrl0_set
);
224 /* Gate on ENET PLL */
225 writel(CLKCTRL_PLL2CTRL0_CLKGATE
,
226 &clkctrl_regs
->hw_clkctrl_pll2ctrl0_clr
);
228 /* Enable pad output */
229 setbits_le32(&clkctrl_regs
->hw_clkctrl_enet
, CLKCTRL_ENET_CLK_OUT_EN
);
235 __weak
void mx28_adjust_mac(int dev_id
, unsigned char *mac
)
238 mac
[1] = 0x04; /* Use FSL vendor MAC address by default */
240 if (dev_id
== 1) /* Let MAC1 be MAC0 + 1 by default */
244 #ifdef CONFIG_MX28_FEC_MAC_IN_OCOTP
246 #define MXS_OCOTP_MAX_TIMEOUT 1000000
247 void imx_get_mac_from_fuse(int dev_id
, unsigned char *mac
)
249 struct mxs_ocotp_regs
*ocotp_regs
=
250 (struct mxs_ocotp_regs
*)MXS_OCOTP_BASE
;
255 writel(OCOTP_CTRL_RD_BANK_OPEN
, &ocotp_regs
->hw_ocotp_ctrl_set
);
257 if (mxs_wait_mask_clr(&ocotp_regs
->hw_ocotp_ctrl_reg
, OCOTP_CTRL_BUSY
,
258 MXS_OCOTP_MAX_TIMEOUT
)) {
259 printf("MXS FEC: Can't get MAC from OCOTP\n");
263 data
= readl(&ocotp_regs
->hw_ocotp_cust0
);
265 mac
[2] = (data
>> 24) & 0xff;
266 mac
[3] = (data
>> 16) & 0xff;
267 mac
[4] = (data
>> 8) & 0xff;
268 mac
[5] = data
& 0xff;
269 mx28_adjust_mac(dev_id
, mac
);
272 void imx_get_mac_from_fuse(int dev_id
, unsigned char *mac
)
278 int mxs_dram_init(void)
280 struct mxs_spl_data
*data
= (struct mxs_spl_data
*)
281 ((CONFIG_SYS_TEXT_BASE
- sizeof(struct mxs_spl_data
)) & ~0xf);
283 if (data
->mem_dram_size
== 0) {
285 "Error, the RAM size passed up from SPL is 0!\n");
289 gd
->ram_size
= data
->mem_dram_size
;
294 clocks
, CONFIG_SYS_MAXARGS
, 1, do_mx28_showclocks
,