arch/arm/cpu/arm926ejs/mxs/spl_lradc_init.c

   1 /*
   2  * Freescale i.MX28 Battery measurement init
   3  *
   4  * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
   5  * on behalf of DENX Software Engineering GmbH
   6  *
   7  * See file CREDITS for list of people who contributed to this
   8  * project.
   9  *
  10  * This program is free software; you can redistribute it and/or
  11  * modify it under the terms of the GNU General Public License as
  12  * published by the Free Software Foundation; either version 2 of
  13  * the License, or (at your option) any later version.
  14  *
  15  * This program is distributed in the hope that it will be useful,
  16  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18  * GNU General Public License for more details.
  19  *
  20  * You should have received a copy of the GNU General Public License
  21  * along with this program; if not, write to the Free Software
  22  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  23  * MA 02111-1307 USA
  24  */
  25
  26 #include <common.h>
  27 #include <config.h>
  28 #include <asm/io.h>
  29 #include <asm/arch/imx-regs.h>
  30
  31 #include "mx28_init.h"
  32
  33 void mx28_lradc_init(void)
  34 {
  35         struct mxs_lradc_regs *regs = (struct mxs_lradc_regs *)MXS_LRADC_BASE;
  36
  37         writel(LRADC_CTRL0_SFTRST, &regs->hw_lradc_ctrl0_clr);
  38         writel(LRADC_CTRL0_CLKGATE, &regs->hw_lradc_ctrl0_clr);
  39         writel(LRADC_CTRL0_ONCHIP_GROUNDREF, &regs->hw_lradc_ctrl0_clr);
  40
  41         clrsetbits_le32(&regs->hw_lradc_ctrl3,
  42                         LRADC_CTRL3_CYCLE_TIME_MASK,
  43                         LRADC_CTRL3_CYCLE_TIME_6MHZ);
  44
  45         clrsetbits_le32(&regs->hw_lradc_ctrl4,
  46                         LRADC_CTRL4_LRADC7SELECT_MASK |
  47                         LRADC_CTRL4_LRADC6SELECT_MASK,
  48                         LRADC_CTRL4_LRADC7SELECT_CHANNEL7 |
  49                         LRADC_CTRL4_LRADC6SELECT_CHANNEL10);
  50 }
  51
  52 void mx28_lradc_enable_batt_measurement(void)
  53 {
  54         struct mxs_lradc_regs *regs = (struct mxs_lradc_regs *)MXS_LRADC_BASE;
  55
  56         /* Check if the channel is present at all. */
  57         if (!(readl(&regs->hw_lradc_status) & LRADC_STATUS_CHANNEL7_PRESENT))
  58                 return;
  59
  60         writel(LRADC_CTRL1_LRADC7_IRQ_EN, &regs->hw_lradc_ctrl1_clr);
  61         writel(LRADC_CTRL1_LRADC7_IRQ, &regs->hw_lradc_ctrl1_clr);
  62
  63         clrsetbits_le32(&regs->hw_lradc_conversion,
  64                         LRADC_CONVERSION_SCALE_FACTOR_MASK,
  65                         LRADC_CONVERSION_SCALE_FACTOR_LI_ION);
  66         writel(LRADC_CONVERSION_AUTOMATIC, &regs->hw_lradc_conversion_set);
  67
  68         /* Configure the channel. */
  69         writel((1 << 7) << LRADC_CTRL2_DIVIDE_BY_TWO_OFFSET,
  70                 &regs->hw_lradc_ctrl2_clr);
  71         writel(0xffffffff, &regs->hw_lradc_ch7_clr);
  72         clrbits_le32(&regs->hw_lradc_ch7, LRADC_CH_NUM_SAMPLES_MASK);
  73         writel(LRADC_CH_ACCUMULATE, &regs->hw_lradc_ch7_clr);
  74
  75         /* Schedule the channel. */
  76         writel(1 << 7, &regs->hw_lradc_ctrl0_set);
  77
  78         /* Start the channel sampling. */
  79         writel(((1 << 7) << LRADC_DELAY_TRIGGER_LRADCS_OFFSET) |
  80                 ((1 << 3) << LRADC_DELAY_TRIGGER_DELAYS_OFFSET) |
  81                 100, &regs->hw_lradc_delay3);
  82
  83         writel(0xffffffff, &regs->hw_lradc_ch7_clr);
  84
  85         writel(LRADC_DELAY_KICK, &regs->hw_lradc_delay3_set);
  86 }