arch/arm/cpu/arm926ejs/orion5x/cpu.c

   1 /*
   2  * Copyright (C) 2010 Albert ARIBAUD <albert.aribaud@free.fr>
   3  *
   4  * Based on original Kirkwood support which is
   5  * (C) Copyright 2009
   6  * Marvell Semiconductor <www.marvell.com>
   7  * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
   8  *
   9  * See file CREDITS for list of people who contributed to this
  10  * project.
  11  *
  12  * This program is free software; you can redistribute it and/or
  13  * modify it under the terms of the GNU General Public License as
  14  * published by the Free Software Foundation; either version 2 of
  15  * the License, or (at your option) any later version.
  16  *
  17  * This program is distributed in the hope that it will be useful,
  18  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  19  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  20  * GNU General Public License for more details.
  21  *
  22  * You should have received a copy of the GNU General Public License
  23  * along with this program; if not, write to the Free Software
  24  * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
  25  * MA 02110-1301 USA
  26  */
  27
  28 #include <common.h>
  29 #include <netdev.h>
  30 #include <asm/cache.h>
  31 #include <u-boot/md5.h>
  32 #include <asm/arch/orion5x.h>
  33 #include <hush.h>
  34
  35 #define BUFLEN  16
  36
  37 void reset_cpu(unsigned long ignored)
  38 {
  39         struct orion5x_cpu_registers *cpureg =
  40             (struct orion5x_cpu_registers *)ORION5X_CPU_REG_BASE;
  41
  42         writel(readl(&cpureg->rstoutn_mask) | (1 << 2),
  43                 &cpureg->rstoutn_mask);
  44         writel(readl(&cpureg->sys_soft_rst) | 1,
  45                 &cpureg->sys_soft_rst);
  46         while (1)
  47                 ;
  48 }
  49
  50 /*
  51  * Window Size
  52  * Used with the Base register to set the address window size and location.
  53  * Must be programmed from LSB to MSB as sequence of ones followed by
  54  * sequence of zeros. The number of ones specifies the size of the window in
  55  * 64 KByte granularity (e.g., a value of 0x00FF specifies 256 = 16 MByte).
  56  * NOTE: A value of 0x0 specifies 64-KByte size.
  57  */
  58 unsigned int orion5x_winctrl_calcsize(unsigned int sizeval)
  59 {
  60         int i;
  61         unsigned int j = 0;
  62         u32 val = sizeval >> 1;
  63
  64         for (i = 0; val >= 0x10000; i++) {
  65                 j |= (1 << i);
  66                 val = val >> 1;
  67         }
  68         return 0x0000ffff & j;
  69 }
  70
  71 /*
  72  * orion5x_config_adr_windows - Configure address Windows
  73  *
  74  * There are 8 address windows supported by Orion5x Soc to addess different
  75  * devices. Each window can be configured for size, BAR and remap addr
  76  * Below configuration is standard for most of the cases
  77  *
  78  * If remap function not used, remap_lo must be set as base
  79  *
  80  * NOTES:
  81  *
  82  * 1) in order to avoid windows with inconsistent control and base values
  83  *    (which could prevent access to BOOTCS and hence execution from FLASH)
  84  *    always disable window before writing the base value then reenable it
  85  *    by writing the control value.
  86  *
  87  * 2) in order to avoid losing access to BOOTCS when disabling window 7,
  88  *    first configure window 6 for BOOTCS, then configure window 7 for BOOTCS,
  89  *    then configure windows 6 for its own target.
  90  *
  91  * Reference Documentation:
  92  * Mbus-L to Mbus Bridge Registers Configuration.
  93  * (Sec 25.1 and 25.3 of Datasheet)
  94  */
  95 int orion5x_config_adr_windows(void)
  96 {
  97         struct orion5x_win_registers *winregs =
  98                 (struct orion5x_win_registers *)ORION5X_CPU_WIN_BASE;
  99
 100 /* Disable window 0, configure it for its intended target, enable it. */
 101         writel(0, &winregs[0].ctrl);
 102         writel(ORION5X_ADR_PCIE_MEM, &winregs[0].base);
 103         writel(ORION5X_ADR_PCIE_MEM_REMAP_LO, &winregs[0].remap_lo);
 104         writel(ORION5X_ADR_PCIE_MEM_REMAP_HI, &winregs[0].remap_hi);
 105         writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_SZ_PCIE_MEM,
 106                 ORION5X_TARGET_PCIE, ORION5X_ATTR_PCIE_MEM,
 107                 ORION5X_WIN_ENABLE), &winregs[0].ctrl);
 108 /* Disable window 1, configure it for its intended target, enable it. */
 109         writel(0, &winregs[1].ctrl);
 110         writel(ORION5X_ADR_PCIE_IO, &winregs[1].base);
 111         writel(ORION5X_ADR_PCIE_IO_REMAP_LO, &winregs[1].remap_lo);
 112         writel(ORION5X_ADR_PCIE_IO_REMAP_HI, &winregs[1].remap_hi);
 113         writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_SZ_PCIE_IO,
 114                 ORION5X_TARGET_PCIE, ORION5X_ATTR_PCIE_IO,
 115                 ORION5X_WIN_ENABLE), &winregs[1].ctrl);
 116 /* Disable window 2, configure it for its intended target, enable it. */
 117         writel(0, &winregs[2].ctrl);
 118         writel(ORION5X_ADR_PCI_MEM, &winregs[2].base);
 119         writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_SZ_PCI_MEM,
 120                 ORION5X_TARGET_PCI, ORION5X_ATTR_PCI_MEM,
 121                 ORION5X_WIN_ENABLE), &winregs[2].ctrl);
 122 /* Disable window 3, configure it for its intended target, enable it. */
 123         writel(0, &winregs[3].ctrl);
 124         writel(ORION5X_ADR_PCI_IO, &winregs[3].base);
 125         writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_SZ_PCI_IO,
 126                 ORION5X_TARGET_PCI, ORION5X_ATTR_PCI_IO,
 127                 ORION5X_WIN_ENABLE), &winregs[3].ctrl);
 128 /* Disable window 4, configure it for its intended target, enable it. */
 129         writel(0, &winregs[4].ctrl);
 130         writel(ORION5X_ADR_DEV_CS0, &winregs[4].base);
 131         writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_SZ_DEV_CS0,
 132                 ORION5X_TARGET_DEVICE, ORION5X_ATTR_DEV_CS0,
 133                 ORION5X_WIN_ENABLE), &winregs[4].ctrl);
 134 /* Disable window 5, configure it for its intended target, enable it. */
 135         writel(0, &winregs[5].ctrl);
 136         writel(ORION5X_ADR_DEV_CS1, &winregs[5].base);
 137         writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_SZ_DEV_CS1,
 138                 ORION5X_TARGET_DEVICE, ORION5X_ATTR_DEV_CS1,
 139                 ORION5X_WIN_ENABLE), &winregs[5].ctrl);
 140 /* Disable window 6, configure it for FLASH, enable it. */
 141         writel(0, &winregs[6].ctrl);
 142         writel(ORION5X_ADR_BOOTROM, &winregs[6].base);
 143         writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_SZ_BOOTROM,
 144                 ORION5X_TARGET_DEVICE, ORION5X_ATTR_BOOTROM,
 145                 ORION5X_WIN_ENABLE), &winregs[6].ctrl);
 146 /* Disable window 7, configure it for FLASH, enable it. */
 147         writel(0, &winregs[7].ctrl);
 148         writel(ORION5X_ADR_BOOTROM, &winregs[7].base);
 149         writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_SZ_BOOTROM,
 150                 ORION5X_TARGET_DEVICE, ORION5X_ATTR_BOOTROM,
 151                 ORION5X_WIN_ENABLE), &winregs[7].ctrl);
 152 /* Disable window 6, configure it for its intended target, enable it. */
 153         writel(0, &winregs[6].ctrl);
 154         writel(ORION5X_ADR_DEV_CS2, &winregs[6].base);
 155         writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_SZ_DEV_CS2,
 156                 ORION5X_TARGET_DEVICE, ORION5X_ATTR_DEV_CS2,
 157                 ORION5X_WIN_ENABLE), &winregs[6].ctrl);
 158
 159         return 0;
 160 }
 161
 162 /*
 163  * Orion5x identification is done through PCIE space.
 164  */
 165
 166 u32 orion5x_device_id(void)
 167 {
 168         return readl(PCIE_DEV_ID_OFF) >> 16;
 169 }
 170
 171 u32 orion5x_device_rev(void)
 172 {
 173         return readl(PCIE_DEV_REV_OFF) & 0xff;
 174 }
 175
 176 #if defined(CONFIG_DISPLAY_CPUINFO)
 177
 178 /* Display device and revision IDs.
 179  * This function must cover all known device/revision
 180  * combinations, not only the one for which u-boot is
 181  * compiled; this way, one can identify actual HW in
 182  * case of a mismatch.
 183  */
 184 int print_cpuinfo(void)
 185 {
 186         char dev_str[] = "0x0000";
 187         char rev_str[] = "0x00";
 188         char *dev_name = NULL;
 189         char *rev_name = NULL;
 190
 191         u32 dev = orion5x_device_id();
 192         u32 rev = orion5x_device_rev();
 193
 194         if (dev == MV88F5181_DEV_ID) {
 195                 dev_name = "MV88F5181";
 196                 if (rev == MV88F5181_REV_B1)
 197                         rev_name = "B1";
 198                 else if (rev == MV88F5181L_REV_A1) {
 199                         dev_name = "MV88F5181L";
 200                         rev_name = "A1";
 201                 } else if (rev == MV88F5181L_REV_A0) {
 202                         dev_name = "MV88F5181L";
 203                         rev_name = "A0";
 204                 }
 205         } else if (dev == MV88F5182_DEV_ID) {
 206                 dev_name = "MV88F5182";
 207                 if (rev == MV88F5182_REV_A2)
 208                         rev_name = "A2";
 209         } else if (dev == MV88F5281_DEV_ID) {
 210                 dev_name = "MV88F5281";
 211                 if (rev == MV88F5281_REV_D2)
 212                         rev_name = "D2";
 213                 else if (rev == MV88F5281_REV_D1)
 214                         rev_name = "D1";
 215                 else if (rev == MV88F5281_REV_D0)
 216                         rev_name = "D0";
 217         } else if (dev == MV88F6183_DEV_ID) {
 218                 dev_name = "MV88F6183";
 219                 if (rev == MV88F6183_REV_B0)
 220                         rev_name = "B0";
 221         }
 222         if (dev_name == NULL) {
 223                 sprintf(dev_str, "0x%04x", dev);
 224                 dev_name = dev_str;
 225         }
 226         if (rev_name == NULL) {
 227                 sprintf(rev_str, "0x%02x", rev);
 228                 rev_name = rev_str;
 229         }
 230
 231         printf("SoC:   Orion5x %s-%s\n", dev_name, rev_name);
 232
 233         return 0;
 234 }
 235 #endif /* CONFIG_DISPLAY_CPUINFO */
 236
 237 #ifdef CONFIG_ARCH_CPU_INIT
 238 int arch_cpu_init(void)
 239 {
 240         /* Enable and invalidate L2 cache in write through mode */
 241         invalidate_l2_cache();
 242
 243         orion5x_config_adr_windows();
 244
 245         return 0;
 246 }
 247 #endif /* CONFIG_ARCH_CPU_INIT */
 248
 249 /*
 250  * SOC specific misc init
 251  */
 252 #if defined(CONFIG_ARCH_MISC_INIT)
 253 int arch_misc_init(void)
 254 {
 255         u32 temp;
 256
 257         /*CPU streaming & write allocate */
 258         temp = readfr_extra_feature_reg();
 259         temp &= ~(1 << 28);     /* disable wr alloc */
 260         writefr_extra_feature_reg(temp);
 261
 262         temp = readfr_extra_feature_reg();
 263         temp &= ~(1 << 29);     /* streaming disabled */
 264         writefr_extra_feature_reg(temp);
 265
 266         /* L2Cache settings */
 267         temp = readfr_extra_feature_reg();
 268         /* Disable L2C pre fetch - Set bit 24 */
 269         temp |= (1 << 24);
 270         /* enable L2C - Set bit 22 */
 271         temp |= (1 << 22);
 272         writefr_extra_feature_reg(temp);
 273
 274         icache_enable();
 275         /* Change reset vector to address 0x0 */
 276         temp = get_cr();
 277         set_cr(temp & ~CR_V);
 278
 279         /* Set CPIOs and MPPs - values provided by board
 280            include file */
 281         writel(ORION5X_MPP0_7, ORION5X_MPP_BASE+0x00);
 282         writel(ORION5X_MPP8_15, ORION5X_MPP_BASE+0x04);
 283         writel(ORION5X_MPP16_23, ORION5X_MPP_BASE+0x50);
 284         writel(ORION5X_GPIO_OUT_ENABLE, ORION5X_GPIO_BASE+0x04);
 285
 286         /* initialize timer */
 287         timer_init_r();
 288         return 0;
 289 }
 290 #endif /* CONFIG_ARCH_MISC_INIT */
 291
 292 #ifdef CONFIG_MVGBE
 293 int cpu_eth_init(bd_t *bis)
 294 {
 295         mvgbe_initialize(bis);
 296         return 0;
 297 }
 298 #endif