arch/arm/cpu/arm_cortexa8/mx51/clock.c

   1 /*
   2  * (C) Copyright 2007
   3  * Sascha Hauer, Pengutronix
   4  *
   5  * (C) Copyright 2009 Freescale Semiconductor, Inc.
   6  *
   7  * See file CREDITS for list of people who contributed to this
   8  * project.
   9  *
  10  * This program is free software; you can redistribute it and/or
  11  * modify it under the terms of the GNU General Public License as
  12  * published by the Free Software Foundation; either version 2 of
  13  * the License, or (at your option) any later version.
  14  *
  15  * This program is distributed in the hope that it will be useful,
  16  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18  * GNU General Public License for more details.
  19  *
  20  * You should have received a copy of the GNU General Public License
  21  * along with this program; if not, write to the Free Software
  22  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  23  * MA 02111-1307 USA
  24  */
  25
  26 #include <common.h>
  27 #include <asm/io.h>
  28 #include <asm/errno.h>
  29 #include <asm/arch/imx-regs.h>
  30 #include <asm/arch/crm_regs.h>
  31 #include <asm/arch/clock.h>
  32
  33 enum pll_clocks {
  34         PLL1_CLOCK = 0,
  35         PLL2_CLOCK,
  36         PLL3_CLOCK,
  37         PLL_CLOCKS,
  38 };
  39
  40 struct mxc_pll_reg *mxc_plls[PLL_CLOCKS] = {
  41         [PLL1_CLOCK] = (struct mxc_pll_reg *)PLL1_BASE_ADDR,
  42         [PLL2_CLOCK] = (struct mxc_pll_reg *)PLL2_BASE_ADDR,
  43         [PLL3_CLOCK] = (struct mxc_pll_reg *)PLL3_BASE_ADDR,
  44 };
  45
  46 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)MXC_CCM_BASE;
  47
  48 /*
  49  * Calculate the frequency of this pll.
  50  */
  51 static u32 decode_pll(struct mxc_pll_reg *pll, u32 infreq)
  52 {
  53         u32 mfi, mfn, mfd, pd;
  54
  55         mfn = __raw_readl(&pll->mfn);
  56         mfd = __raw_readl(&pll->mfd) + 1;
  57         mfi = __raw_readl(&pll->op);
  58         pd = (mfi  & 0xF) + 1;
  59         mfi = (mfi >> 4) & 0xF;
  60         mfi = (mfi >= 5) ? mfi : 5;
  61
  62         return ((4 * (infreq / 1000) * (mfi * mfd + mfn)) / (mfd * pd)) * 1000;
  63 }
  64
  65 /*
  66  * Get mcu main rate
  67  */
  68 u32 get_mcu_main_clk(void)
  69 {
  70         u32 reg, freq;
  71
  72         reg = (__raw_readl(&mxc_ccm->cacrr) & MXC_CCM_CACRR_ARM_PODF_MASK) >>
  73                 MXC_CCM_CACRR_ARM_PODF_OFFSET;
  74         freq = decode_pll(mxc_plls[PLL1_CLOCK], CONFIG_MX51_HCLK_FREQ);
  75         return freq / (reg + 1);
  76 }
  77
  78 /*
  79  * Get the rate of peripheral's root clock.
  80  */
  81 static u32 get_periph_clk(void)
  82 {
  83         u32 reg;
  84
  85         reg = __raw_readl(&mxc_ccm->cbcdr);
  86         if (!(reg & MXC_CCM_CBCDR_PERIPH_CLK_SEL))
  87                 return decode_pll(mxc_plls[PLL2_CLOCK], CONFIG_MX51_HCLK_FREQ);
  88         reg = __raw_readl(&mxc_ccm->cbcmr);
  89         switch ((reg & MXC_CCM_CBCMR_PERIPH_CLK_SEL_MASK) >>
  90                 MXC_CCM_CBCMR_PERIPH_CLK_SEL_OFFSET) {
  91         case 0:
  92                 return decode_pll(mxc_plls[PLL1_CLOCK], CONFIG_MX51_HCLK_FREQ);
  93         case 1:
  94                 return decode_pll(mxc_plls[PLL3_CLOCK], CONFIG_MX51_HCLK_FREQ);
  95         default:
  96                 return 0;
  97         }
  98         /* NOTREACHED */
  99 }
 100
 101 /*
 102  * Get the rate of ipg clock.
 103  */
 104 static u32 get_ipg_clk(void)
 105 {
 106         u32 ahb_podf, ipg_podf;
 107
 108         ahb_podf = __raw_readl(&mxc_ccm->cbcdr);
 109         ipg_podf = (ahb_podf & MXC_CCM_CBCDR_IPG_PODF_MASK) >>
 110                         MXC_CCM_CBCDR_IPG_PODF_OFFSET;
 111         ahb_podf = (ahb_podf & MXC_CCM_CBCDR_AHB_PODF_MASK) >>
 112                         MXC_CCM_CBCDR_AHB_PODF_OFFSET;
 113         return get_periph_clk() / ((ahb_podf + 1) * (ipg_podf + 1));
 114 }
 115
 116 /*
 117  * Get the rate of ipg_per clock.
 118  */
 119 static u32 get_ipg_per_clk(void)
 120 {
 121         u32 pred1, pred2, podf;
 122
 123         if (__raw_readl(&mxc_ccm->cbcmr) & MXC_CCM_CBCMR_PERCLK_IPG_CLK_SEL)
 124                 return get_ipg_clk();
 125         /* Fixme: not handle what about lpm*/
 126         podf = __raw_readl(&mxc_ccm->cbcdr);
 127         pred1 = (podf & MXC_CCM_CBCDR_PERCLK_PRED1_MASK) >>
 128                 MXC_CCM_CBCDR_PERCLK_PRED1_OFFSET;
 129         pred2 = (podf & MXC_CCM_CBCDR_PERCLK_PRED2_MASK) >>
 130                 MXC_CCM_CBCDR_PERCLK_PRED2_OFFSET;
 131         podf = (podf & MXC_CCM_CBCDR_PERCLK_PODF_MASK) >>
 132                 MXC_CCM_CBCDR_PERCLK_PODF_OFFSET;
 133
 134         return get_periph_clk() / ((pred1 + 1) * (pred2 + 1) * (podf + 1));
 135 }
 136
 137 /*
 138  * Get the rate of uart clk.
 139  */
 140 static u32 get_uart_clk(void)
 141 {
 142         unsigned int freq, reg, pred, podf;
 143
 144         reg = __raw_readl(&mxc_ccm->cscmr1);
 145         switch ((reg & MXC_CCM_CSCMR1_UART_CLK_SEL_MASK) >>
 146                 MXC_CCM_CSCMR1_UART_CLK_SEL_OFFSET) {
 147         case 0x0:
 148                 freq = decode_pll(mxc_plls[PLL1_CLOCK],
 149                                     CONFIG_MX51_HCLK_FREQ);
 150                 break;
 151         case 0x1:
 152                 freq = decode_pll(mxc_plls[PLL2_CLOCK],
 153                                     CONFIG_MX51_HCLK_FREQ);
 154                 break;
 155         case 0x2:
 156                 freq = decode_pll(mxc_plls[PLL3_CLOCK],
 157                                     CONFIG_MX51_HCLK_FREQ);
 158                 break;
 159         default:
 160                 return 66500000;
 161         }
 162
 163         reg = __raw_readl(&mxc_ccm->cscdr1);
 164
 165         pred = (reg & MXC_CCM_CSCDR1_UART_CLK_PRED_MASK) >>
 166                 MXC_CCM_CSCDR1_UART_CLK_PRED_OFFSET;
 167
 168         podf = (reg & MXC_CCM_CSCDR1_UART_CLK_PODF_MASK) >>
 169                 MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET;
 170         freq /= (pred + 1) * (podf + 1);
 171
 172         return freq;
 173 }
 174
 175 /*
 176  * This function returns the low power audio clock.
 177  */
 178 u32 get_lp_apm(void)
 179 {
 180         u32 ret_val = 0;
 181         u32 ccsr = __raw_readl(&mxc_ccm->ccsr);
 182
 183         if (((ccsr >> 9) & 1) == 0)
 184                 ret_val = CONFIG_MX51_HCLK_FREQ;
 185         else
 186                 ret_val = ((32768 * 1024));
 187
 188         return ret_val;
 189 }
 190
 191 /*
 192  * get cspi clock rate.
 193  */
 194 u32 imx_get_cspiclk(void)
 195 {
 196         u32 ret_val = 0, pdf, pre_pdf, clk_sel;
 197         u32 cscmr1 = __raw_readl(&mxc_ccm->cscmr1);
 198         u32 cscdr2 = __raw_readl(&mxc_ccm->cscdr2);
 199
 200         pre_pdf = (cscdr2 & MXC_CCM_CSCDR2_CSPI_CLK_PRED_MASK) \
 201                         >> MXC_CCM_CSCDR2_CSPI_CLK_PRED_OFFSET;
 202         pdf = (cscdr2 & MXC_CCM_CSCDR2_CSPI_CLK_PODF_MASK) \
 203                         >> MXC_CCM_CSCDR2_CSPI_CLK_PODF_OFFSET;
 204         clk_sel = (cscmr1 & MXC_CCM_CSCMR1_CSPI_CLK_SEL_MASK) \
 205                         >> MXC_CCM_CSCMR1_CSPI_CLK_SEL_OFFSET;
 206
 207         switch (clk_sel) {
 208         case 0:
 209                 ret_val = decode_pll(mxc_plls[PLL1_CLOCK],
 210                                         CONFIG_MX51_HCLK_FREQ) /
 211                                         ((pre_pdf + 1) * (pdf + 1));
 212                 break;
 213         case 1:
 214                 ret_val = decode_pll(mxc_plls[PLL2_CLOCK],
 215                                         CONFIG_MX51_HCLK_FREQ) /
 216                                         ((pre_pdf + 1) * (pdf + 1));
 217                 break;
 218         case 2:
 219                 ret_val = decode_pll(mxc_plls[PLL3_CLOCK],
 220                                         CONFIG_MX51_HCLK_FREQ) /
 221                                         ((pre_pdf + 1) * (pdf + 1));
 222                 break;
 223         default:
 224                 ret_val = get_lp_apm() / ((pre_pdf + 1) * (pdf + 1));
 225                 break;
 226         }
 227
 228         return ret_val;
 229 }
 230
 231 /*
 232  * The API of get mxc clockes.
 233  */
 234 unsigned int mxc_get_clock(enum mxc_clock clk)
 235 {
 236         switch (clk) {
 237         case MXC_ARM_CLK:
 238                 return get_mcu_main_clk();
 239         case MXC_AHB_CLK:
 240                 break;
 241         case MXC_IPG_CLK:
 242                 return get_ipg_clk();
 243         case MXC_IPG_PERCLK:
 244                 return get_ipg_per_clk();
 245         case MXC_UART_CLK:
 246                 return get_uart_clk();
 247         case MXC_CSPI_CLK:
 248                 return imx_get_cspiclk();
 249         case MXC_FEC_CLK:
 250                 return decode_pll(mxc_plls[PLL1_CLOCK],
 251                                     CONFIG_MX51_HCLK_FREQ);
 252         default:
 253                 break;
 254         }
 255         return -1;
 256 }
 257
 258 u32 imx_get_uartclk(void)
 259 {
 260         return get_uart_clk();
 261 }
 262
 263
 264 u32 imx_get_fecclk(void)
 265 {
 266         return mxc_get_clock(MXC_IPG_CLK);
 267 }
 268
 269 /*
 270  * Dump some core clockes.
 271  */
 272 int do_mx51_showclocks(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 273 {
 274         u32 freq;
 275
 276         freq = decode_pll(mxc_plls[PLL1_CLOCK], CONFIG_MX51_HCLK_FREQ);
 277         printf("mx51 pll1: %dMHz\n", freq / 1000000);
 278         freq = decode_pll(mxc_plls[PLL2_CLOCK], CONFIG_MX51_HCLK_FREQ);
 279         printf("mx51 pll2: %dMHz\n", freq / 1000000);
 280         freq = decode_pll(mxc_plls[PLL3_CLOCK], CONFIG_MX51_HCLK_FREQ);
 281         printf("mx51 pll3: %dMHz\n", freq / 1000000);
 282         printf("ipg clock     : %dHz\n", mxc_get_clock(MXC_IPG_CLK));
 283         printf("ipg per clock : %dHz\n", mxc_get_clock(MXC_IPG_PERCLK));
 284
 285         return 0;
 286 }
 287
 288 /***************************************************/
 289
 290 U_BOOT_CMD(
 291         clockinfo,      CONFIG_SYS_MAXARGS,     1,      do_mx51_showclocks,
 292         "display mx51 clocks\n",
 293         ""
 294 );