arch/arm/cpu/arm_cortexa8/omap3/mem.c

   1 /*
   2  * (C) Copyright 2008
   3  * Texas Instruments, <www.ti.com>
   4  *
   5  * Author :
   6  *     Manikandan Pillai <mani.pillai@ti.com>
   7  *
   8  * Initial Code from:
   9  *     Richard Woodruff <r-woodruff2@ti.com>
  10  *     Syed Mohammed Khasim <khasim@ti.com>
  11  *
  12  * This program is free software; you can redistribute it and/or
  13  * modify it under the terms of the GNU General Public License as
  14  * published by the Free Software Foundation; either version 2 of
  15  * the License, or (at your option) any later version.
  16  *
  17  * This program is distributed in the hope that it will be useful,
  18  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  19  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  20  * GNU General Public License for more details.
  21  *
  22  * You should have received a copy of the GNU General Public License
  23  * along with this program; if not, write to the Free Software
  24  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  25  * MA 02111-1307 USA
  26  */
  27
  28 #include <common.h>
  29 #include <asm/io.h>
  30 #include <asm/arch/mem.h>
  31 #include <asm/arch/sys_proto.h>
  32 #include <command.h>
  33
  34 /*
  35  * Only One NAND allowed on board at a time.
  36  * The GPMC CS Base for the same
  37  */
  38 unsigned int boot_flash_base;
  39 unsigned int boot_flash_off;
  40 unsigned int boot_flash_sec;
  41 unsigned int boot_flash_type;
  42 volatile unsigned int boot_flash_env_addr;
  43
  44 struct gpmc *gpmc_cfg;
  45
  46 #if defined(CONFIG_CMD_NAND)
  47 static const u32 gpmc_m_nand[GPMC_MAX_REG] = {
  48         M_NAND_GPMC_CONFIG1,
  49         M_NAND_GPMC_CONFIG2,
  50         M_NAND_GPMC_CONFIG3,
  51         M_NAND_GPMC_CONFIG4,
  52         M_NAND_GPMC_CONFIG5,
  53         M_NAND_GPMC_CONFIG6, 0
  54 };
  55
  56 #if defined(CONFIG_ENV_IS_IN_NAND)
  57 #define GPMC_CS 0
  58 #else
  59 #define GPMC_CS 1
  60 #endif
  61
  62 #endif
  63
  64 #if defined(CONFIG_CMD_ONENAND)
  65 static const u32 gpmc_onenand[GPMC_MAX_REG] = {
  66         ONENAND_GPMC_CONFIG1,
  67         ONENAND_GPMC_CONFIG2,
  68         ONENAND_GPMC_CONFIG3,
  69         ONENAND_GPMC_CONFIG4,
  70         ONENAND_GPMC_CONFIG5,
  71         ONENAND_GPMC_CONFIG6, 0
  72 };
  73
  74 #if defined(CONFIG_ENV_IS_IN_ONENAND)
  75 #define GPMC_CS 0
  76 #else
  77 #define GPMC_CS 1
  78 #endif
  79
  80 #endif
  81
  82 static struct sdrc *sdrc_base = (struct sdrc *)OMAP34XX_SDRC_BASE;
  83
  84 /**************************************************************************
  85  * make_cs1_contiguous() - for es2 and above remap cs1 behind cs0 to allow
  86  *  command line mem=xyz use all memory with out discontinuous support
  87  *  compiled in.  Could do it at the ATAG, but there really is two banks...
  88  * Called as part of 2nd phase DDR init.
  89  **************************************************************************/
  90 void make_cs1_contiguous(void)
  91 {
  92         u32 size, a_add_low, a_add_high;
  93
  94         size = get_sdr_cs_size(CS0);
  95         size >>= 25;    /* divide by 32 MiB to find size to offset CS1 */
  96         a_add_high = (size & 3) << 8;   /* set up low field */
  97         a_add_low = (size & 0x3C) >> 2; /* set up high field */
  98         writel((a_add_high | a_add_low), &sdrc_base->cs_cfg);
  99
 100 }
 101
 102 /********************************************************
 103  *  mem_ok() - test used to see if timings are correct
 104  *             for a part. Helps in guessing which part
 105  *             we are currently using.
 106  *******************************************************/
 107 u32 mem_ok(u32 cs)
 108 {
 109         u32 val1, val2, addr;
 110         u32 pattern = 0x12345678;
 111
 112         addr = OMAP34XX_SDRC_CS0 + get_sdr_cs_offset(cs);
 113
 114         writel(0x0, addr + 0x400);      /* clear pos A */
 115         writel(pattern, addr);          /* pattern to pos B */
 116         writel(0x0, addr + 4);          /* remove pattern off the bus */
 117         val1 = readl(addr + 0x400);     /* get pos A value */
 118         val2 = readl(addr);             /* get val2 */
 119
 120         if ((val1 != 0) || (val2 != pattern))   /* see if pos A val changed */
 121                 return 0;
 122         else
 123                 return 1;
 124 }
 125
 126 /********************************************************
 127  *  sdrc_init() - init the sdrc chip selects CS0 and CS1
 128  *  - early init routines, called from flash or
 129  *  SRAM.
 130  *******************************************************/
 131 void sdrc_init(void)
 132 {
 133         /* only init up first bank here */
 134         do_sdrc_init(CS0, EARLY_INIT);
 135 }
 136
 137 /*************************************************************************
 138  * do_sdrc_init(): initialize the SDRAM for use.
 139  *  -code sets up SDRAM basic SDRC timings for CS0
 140  *  -optimal settings can be placed here, or redone after i2c
 141  *      inspection of board info
 142  *
 143  *  - code called once in C-Stack only context for CS0 and a possible 2nd
 144  *      time depending on memory configuration from stack+global context
 145  **************************************************************************/
 146
 147 void do_sdrc_init(u32 cs, u32 early)
 148 {
 149         struct sdrc_actim *sdrc_actim_base;
 150
 151         if(cs)
 152                 sdrc_actim_base = (struct sdrc_actim *)SDRC_ACTIM_CTRL1_BASE;
 153         else
 154                 sdrc_actim_base = (struct sdrc_actim *)SDRC_ACTIM_CTRL0_BASE;
 155
 156         if (early) {
 157                 /* reset sdrc controller */
 158                 writel(SOFTRESET, &sdrc_base->sysconfig);
 159                 wait_on_value(RESETDONE, RESETDONE, &sdrc_base->status,
 160                               12000000);
 161                 writel(0, &sdrc_base->sysconfig);
 162
 163                 /* setup sdrc to ball mux */
 164                 writel(SDRC_SHARING, &sdrc_base->sharing);
 165
 166                 /* Disable Power Down of CKE cuz of 1 CKE on combo part */
 167                 writel(WAKEUPPROC | PWDNEN | SRFRONRESET | PAGEPOLICY_HIGH,
 168                                 &sdrc_base->power);
 169
 170                 writel(ENADLL | DLLPHASE_90, &sdrc_base->dlla_ctrl);
 171                 sdelay(0x20000);
 172         }
 173
 174         writel(RASWIDTH_13BITS | CASWIDTH_10BITS | ADDRMUXLEGACY |
 175                 RAMSIZE_128 | BANKALLOCATION | B32NOT16 | B32NOT16 |
 176                 DEEPPD | DDR_SDRAM, &sdrc_base->cs[cs].mcfg);
 177         writel(ARCV | ARE_ARCV_1, &sdrc_base->cs[cs].rfr_ctrl);
 178         writel(V_ACTIMA_165, &sdrc_actim_base->ctrla);
 179         writel(V_ACTIMB_165, &sdrc_actim_base->ctrlb);
 180
 181         writel(CMD_NOP, &sdrc_base ->cs[cs].manual);
 182         writel(CMD_PRECHARGE, &sdrc_base->cs[cs].manual);
 183         writel(CMD_AUTOREFRESH, &sdrc_base->cs[cs].manual);
 184         writel(CMD_AUTOREFRESH, &sdrc_base->cs[cs].manual);
 185
 186         /*
 187          * CAS latency 3, Write Burst = Read Burst, Serial Mode,
 188          * Burst length = 4
 189          */
 190         writel(CASL3 | BURSTLENGTH4, &sdrc_base->cs[cs].mr);
 191
 192         if (!mem_ok(cs))
 193                 writel(0, &sdrc_base->cs[cs].mcfg);
 194 }
 195
 196 void enable_gpmc_cs_config(const u32 *gpmc_config, struct gpmc_cs *cs, u32 base,
 197                         u32 size)
 198 {
 199         writel(0, &cs->config7);
 200         sdelay(1000);
 201         /* Delay for settling */
 202         writel(gpmc_config[0], &cs->config1);
 203         writel(gpmc_config[1], &cs->config2);
 204         writel(gpmc_config[2], &cs->config3);
 205         writel(gpmc_config[3], &cs->config4);
 206         writel(gpmc_config[4], &cs->config5);
 207         writel(gpmc_config[5], &cs->config6);
 208         /* Enable the config */
 209         writel((((size & 0xF) << 8) | ((base >> 24) & 0x3F) |
 210                 (1 << 6)), &cs->config7);
 211         sdelay(2000);
 212 }
 213
 214 /*****************************************************
 215  * gpmc_init(): init gpmc bus
 216  * Init GPMC for x16, MuxMode (SDRAM in x32).
 217  * This code can only be executed from SRAM or SDRAM.
 218  *****************************************************/
 219 void gpmc_init(void)
 220 {
 221         /* putting a blanket check on GPMC based on ZeBu for now */
 222         gpmc_cfg = (struct gpmc *)GPMC_BASE;
 223 #if defined(CONFIG_CMD_NAND) || defined(CONFIG_CMD_ONENAND)
 224         const u32 *gpmc_config = NULL;
 225         u32 base = 0;
 226         u32 size = 0;
 227 #if defined(CONFIG_ENV_IS_IN_NAND) || defined(CONFIG_ENV_IS_IN_ONENAND)
 228         u32 f_off = CONFIG_SYS_MONITOR_LEN;
 229         u32 f_sec = 0;
 230 #endif
 231 #endif
 232         u32 config = 0;
 233
 234         /* global settings */
 235         writel(0, &gpmc_cfg->irqenable); /* isr's sources masked */
 236         writel(0, &gpmc_cfg->timeout_control);/* timeout disable */
 237
 238         config = readl(&gpmc_cfg->config);
 239         config &= (~0xf00);
 240         writel(config, &gpmc_cfg->config);
 241
 242         /*
 243          * Disable the GPMC0 config set by ROM code
 244          * It conflicts with our MPDB (both at 0x08000000)
 245          */
 246         writel(0, &gpmc_cfg->cs[0].config7);
 247         sdelay(1000);
 248
 249 #if defined(CONFIG_CMD_NAND)    /* CS 0 */
 250         gpmc_config = gpmc_m_nand;
 251
 252         base = PISMO1_NAND_BASE;
 253         size = PISMO1_NAND_SIZE;
 254         enable_gpmc_cs_config(gpmc_config, &gpmc_cfg->cs[0], base, size);
 255 #if defined(CONFIG_ENV_IS_IN_NAND)
 256         f_off = SMNAND_ENV_OFFSET;
 257         f_sec = (128 << 10);    /* 128 KiB */
 258         /* env setup */
 259         boot_flash_base = base;
 260         boot_flash_off = f_off;
 261         boot_flash_sec = f_sec;
 262         boot_flash_env_addr = f_off;
 263 #endif
 264 #endif
 265
 266 #if defined(CONFIG_CMD_ONENAND)
 267         gpmc_config = gpmc_onenand;
 268         base = PISMO1_ONEN_BASE;
 269         size = PISMO1_ONEN_SIZE;
 270         enable_gpmc_cs_config(gpmc_config, &gpmc_cfg->cs[0], base, size);
 271 #if defined(CONFIG_ENV_IS_IN_ONENAND)
 272         f_off = ONENAND_ENV_OFFSET;
 273         f_sec = (128 << 10);    /* 128 KiB */
 274         /* env setup */
 275         boot_flash_base = base;
 276         boot_flash_off = f_off;
 277         boot_flash_sec = f_sec;
 278         boot_flash_env_addr = f_off;
 279 #endif
 280 #endif
 281 }