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1 /*
2 * DDR Configuration for AM33xx devices.
3 *
4 * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
5 *
6 * SPDX-License-Identifier: GPL-2.0+
7 */
8
9 #include <asm/arch/cpu.h>
10 #include <asm/arch/ddr_defs.h>
11 #include <asm/arch/sys_proto.h>
12 #include <asm/io.h>
13 #include <asm/emif.h>
14
15 /**
16 * Base address for EMIF instances
17 */
18 static struct emif_reg_struct *emif_reg[2] = {
19 (struct emif_reg_struct *)EMIF4_0_CFG_BASE,
20 (struct emif_reg_struct *)EMIF4_1_CFG_BASE};
21
22 /**
23 * Base addresses for DDR PHY cmd/data regs
24 */
25 static struct ddr_cmd_regs *ddr_cmd_reg[2] = {
26 (struct ddr_cmd_regs *)DDR_PHY_CMD_ADDR,
27 (struct ddr_cmd_regs *)DDR_PHY_CMD_ADDR2};
28
29 static struct ddr_data_regs *ddr_data_reg[2] = {
30 (struct ddr_data_regs *)DDR_PHY_DATA_ADDR,
31 (struct ddr_data_regs *)DDR_PHY_DATA_ADDR2};
32
33 /**
34 * Base address for ddr io control instances
35 */
36 static struct ddr_cmdtctrl *ioctrl_reg = {
37 (struct ddr_cmdtctrl *)DDR_CONTROL_BASE_ADDR};
38
39 static inline u32 get_mr(int nr, u32 cs, u32 mr_addr)
40 {
41 u32 mr;
42
43 mr_addr |= cs << EMIF_REG_CS_SHIFT;
44 writel(mr_addr, &emif_reg[nr]->emif_lpddr2_mode_reg_cfg);
45
46 mr = readl(&emif_reg[nr]->emif_lpddr2_mode_reg_data);
47 debug("get_mr: EMIF1 cs %d mr %08x val 0x%x\n", cs, mr_addr, mr);
48 if (((mr & 0x0000ff00) >> 8) == (mr & 0xff) &&
49 ((mr & 0x00ff0000) >> 16) == (mr & 0xff) &&
50 ((mr & 0xff000000) >> 24) == (mr & 0xff))
51 return mr & 0xff;
52 else
53 return mr;
54 }
55
56 static inline void set_mr(int nr, u32 cs, u32 mr_addr, u32 mr_val)
57 {
58 mr_addr |= cs << EMIF_REG_CS_SHIFT;
59 writel(mr_addr, &emif_reg[nr]->emif_lpddr2_mode_reg_cfg);
60 writel(mr_val, &emif_reg[nr]->emif_lpddr2_mode_reg_data);
61 }
62
63 static void configure_mr(int nr, u32 cs)
64 {
65 u32 mr_addr;
66
67 while (get_mr(nr, cs, LPDDR2_MR0) & LPDDR2_MR0_DAI_MASK)
68 ;
69 set_mr(nr, cs, LPDDR2_MR10, 0x56);
70
71 set_mr(nr, cs, LPDDR2_MR1, 0x43);
72 set_mr(nr, cs, LPDDR2_MR2, 0x2);
73
74 mr_addr = LPDDR2_MR2 | EMIF_REG_REFRESH_EN_MASK;
75 set_mr(nr, cs, mr_addr, 0x2);
76 }
77
78 /*
79 * Configure EMIF4D5 registers and MR registers
80 */
81 void config_sdram_emif4d5(const struct emif_regs *regs, int nr)
82 {
83 writel(0xA0, &emif_reg[nr]->emif_pwr_mgmt_ctrl);
84 writel(0xA0, &emif_reg[nr]->emif_pwr_mgmt_ctrl_shdw);
85 writel(0x1, &emif_reg[nr]->emif_iodft_tlgc);
86 writel(regs->zq_config, &emif_reg[nr]->emif_zq_config);
87
88 writel(regs->temp_alert_config, &emif_reg[nr]->emif_temp_alert_config);
89 writel(regs->emif_rd_wr_lvl_rmp_win,
90 &emif_reg[nr]->emif_rd_wr_lvl_rmp_win);
91 writel(regs->emif_rd_wr_lvl_rmp_ctl,
92 &emif_reg[nr]->emif_rd_wr_lvl_rmp_ctl);
93 writel(regs->emif_rd_wr_lvl_ctl, &emif_reg[nr]->emif_rd_wr_lvl_ctl);
94 writel(regs->emif_rd_wr_exec_thresh,
95 &emif_reg[nr]->emif_rd_wr_exec_thresh);
96
97 writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl);
98 writel(regs->sdram_config, &emif_reg[nr]->emif_sdram_config);
99 writel(regs->sdram_config, &cstat->secure_emif_sdram_config);
100
101 if (emif_sdram_type() == EMIF_SDRAM_TYPE_LPDDR2) {
102 configure_mr(nr, 0);
103 configure_mr(nr, 1);
104 }
105 }
106
107 /**
108 * Configure SDRAM
109 */
110 void config_sdram(const struct emif_regs *regs, int nr)
111 {
112 if (regs->zq_config) {
113 /*
114 * A value of 0x2800 for the REF CTRL will give us
115 * about 570us for a delay, which will be long enough
116 * to configure things.
117 */
118 writel(0x2800, &emif_reg[nr]->emif_sdram_ref_ctrl);
119 writel(regs->zq_config, &emif_reg[nr]->emif_zq_config);
120 writel(regs->sdram_config, &cstat->secure_emif_sdram_config);
121 writel(regs->sdram_config, &emif_reg[nr]->emif_sdram_config);
122 writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl);
123 writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl_shdw);
124 }
125 writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl);
126 writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl_shdw);
127 writel(regs->sdram_config, &emif_reg[nr]->emif_sdram_config);
128 }
129
130 /**
131 * Set SDRAM timings
132 */
133 void set_sdram_timings(const struct emif_regs *regs, int nr)
134 {
135 writel(regs->sdram_tim1, &emif_reg[nr]->emif_sdram_tim_1);
136 writel(regs->sdram_tim1, &emif_reg[nr]->emif_sdram_tim_1_shdw);
137 writel(regs->sdram_tim2, &emif_reg[nr]->emif_sdram_tim_2);
138 writel(regs->sdram_tim2, &emif_reg[nr]->emif_sdram_tim_2_shdw);
139 writel(regs->sdram_tim3, &emif_reg[nr]->emif_sdram_tim_3);
140 writel(regs->sdram_tim3, &emif_reg[nr]->emif_sdram_tim_3_shdw);
141 }
142
143 void __weak emif_get_ext_phy_ctrl_const_regs(const u32 **regs, u32 *size)
144 {
145 }
146
147 /*
148 * Configure EXT PHY registers
149 */
150 static void ext_phy_settings(const struct emif_regs *regs, int nr)
151 {
152 u32 *ext_phy_ctrl_base = 0;
153 u32 *emif_ext_phy_ctrl_base = 0;
154 const u32 *ext_phy_ctrl_const_regs;
155 u32 i = 0;
156 u32 size;
157
158 ext_phy_ctrl_base = (u32 *)&(regs->emif_ddr_ext_phy_ctrl_1);
159 emif_ext_phy_ctrl_base =
160 (u32 *)&(emif_reg[nr]->emif_ddr_ext_phy_ctrl_1);
161
162 /* Configure external phy control timing registers */
163 for (i = 0; i < EMIF_EXT_PHY_CTRL_TIMING_REG; i++) {
164 writel(*ext_phy_ctrl_base, emif_ext_phy_ctrl_base++);
165 /* Update shadow registers */
166 writel(*ext_phy_ctrl_base++, emif_ext_phy_ctrl_base++);
167 }
168
169 /*
170 * external phy 6-24 registers do not change with
171 * ddr frequency
172 */
173 emif_get_ext_phy_ctrl_const_regs(&ext_phy_ctrl_const_regs, &size);
174
175 if (!size)
176 return;
177
178 for (i = 0; i < size; i++) {
179 writel(ext_phy_ctrl_const_regs[i], emif_ext_phy_ctrl_base++);
180 /* Update shadow registers */
181 writel(ext_phy_ctrl_const_regs[i], emif_ext_phy_ctrl_base++);
182 }
183 }
184
185 /**
186 * Configure DDR PHY
187 */
188 void config_ddr_phy(const struct emif_regs *regs, int nr)
189 {
190 /*
191 * disable initialization and refreshes for now until we
192 * finish programming EMIF regs.
193 */
194 setbits_le32(&emif_reg[nr]->emif_sdram_ref_ctrl,
195 EMIF_REG_INITREF_DIS_MASK);
196
197 writel(regs->emif_ddr_phy_ctlr_1,
198 &emif_reg[nr]->emif_ddr_phy_ctrl_1);
199 writel(regs->emif_ddr_phy_ctlr_1,
200 &emif_reg[nr]->emif_ddr_phy_ctrl_1_shdw);
201
202 if (get_emif_rev((u32)emif_reg[nr]) == EMIF_4D5)
203 ext_phy_settings(regs, nr);
204 }
205
206 /**
207 * Configure DDR CMD control registers
208 */
209 void config_cmd_ctrl(const struct cmd_control *cmd, int nr)
210 {
211 if (!cmd)
212 return;
213
214 writel(cmd->cmd0csratio, &ddr_cmd_reg[nr]->cm0csratio);
215 writel(cmd->cmd0iclkout, &ddr_cmd_reg[nr]->cm0iclkout);
216
217 writel(cmd->cmd1csratio, &ddr_cmd_reg[nr]->cm1csratio);
218 writel(cmd->cmd1iclkout, &ddr_cmd_reg[nr]->cm1iclkout);
219
220 writel(cmd->cmd2csratio, &ddr_cmd_reg[nr]->cm2csratio);
221 writel(cmd->cmd2iclkout, &ddr_cmd_reg[nr]->cm2iclkout);
222 }
223
224 /**
225 * Configure DDR DATA registers
226 */
227 void config_ddr_data(const struct ddr_data *data, int nr)
228 {
229 int i;
230
231 if (!data)
232 return;
233
234 for (i = 0; i < DDR_DATA_REGS_NR; i++) {
235 writel(data->datardsratio0,
236 &(ddr_data_reg[nr]+i)->dt0rdsratio0);
237 writel(data->datawdsratio0,
238 &(ddr_data_reg[nr]+i)->dt0wdsratio0);
239 writel(data->datawiratio0,
240 &(ddr_data_reg[nr]+i)->dt0wiratio0);
241 writel(data->datagiratio0,
242 &(ddr_data_reg[nr]+i)->dt0giratio0);
243 writel(data->datafwsratio0,
244 &(ddr_data_reg[nr]+i)->dt0fwsratio0);
245 writel(data->datawrsratio0,
246 &(ddr_data_reg[nr]+i)->dt0wrsratio0);
247 }
248 }
249
250 void config_io_ctrl(const struct ctrl_ioregs *ioregs)
251 {
252 if (!ioregs)
253 return;
254
255 writel(ioregs->cm0ioctl, &ioctrl_reg->cm0ioctl);
256 writel(ioregs->cm1ioctl, &ioctrl_reg->cm1ioctl);
257 writel(ioregs->cm2ioctl, &ioctrl_reg->cm2ioctl);
258 writel(ioregs->dt0ioctl, &ioctrl_reg->dt0ioctl);
259 writel(ioregs->dt1ioctl, &ioctrl_reg->dt1ioctl);
260 #ifdef CONFIG_AM43XX
261 writel(ioregs->dt2ioctrl, &ioctrl_reg->dt2ioctrl);
262 writel(ioregs->dt3ioctrl, &ioctrl_reg->dt3ioctrl);
263 writel(ioregs->emif_sdram_config_ext,
264 &ioctrl_reg->emif_sdram_config_ext);
265 #endif
266 }