2 * Clock setup for SMDK5250 board based on EXYNOS5
4 * Copyright (C) 2012 Samsung Electronics
6 * SPDX-License-Identifier: GPL-2.0+
12 #include <asm/arch/clk.h>
13 #include <asm/arch/clock.h>
14 #include <asm/arch/spl.h>
15 #include <asm/arch/dwmmc.h>
17 #include "clock_init.h"
18 #include "common_setup.h"
19 #include "exynos5_setup.h"
21 #define FSYS1_MMC0_DIV_MASK 0xff0f
22 #define FSYS1_MMC0_DIV_VAL 0x0701
24 DECLARE_GLOBAL_DATA_PTR
;
26 struct arm_clk_ratios arm_clk_ratios
[] = {
36 .pclk_dbg_ratio
= 0x1,
51 .pclk_dbg_ratio
= 0x1,
66 .pclk_dbg_ratio
= 0x1,
81 .pclk_dbg_ratio
= 0x1,
96 .pclk_dbg_ratio
= 0x1,
103 .arm_freq_mhz
= 1700,
111 .pclk_dbg_ratio
= 0x1,
119 struct mem_timings mem_timings
[] = {
121 .mem_manuf
= MEM_MANUF_ELPIDA
,
122 .mem_type
= DDR_MODE_DDR3
,
123 .frequency_mhz
= 800,
143 .pclk_cdrex_ratio
= 0x5,
145 0x00020018, 0x00030000, 0x00010042, 0x00000d70
147 .timing_ref
= 0x000000bb,
148 .timing_row
= 0x8c36650e,
149 .timing_data
= 0x3630580b,
150 .timing_power
= 0x41000a44,
151 .phy0_dqs
= 0x08080808,
152 .phy1_dqs
= 0x08080808,
153 .phy0_dq
= 0x08080808,
154 .phy1_dq
= 0x08080808,
157 .phy0_pulld_dqs
= 0xf,
158 .phy1_pulld_dqs
= 0xf,
160 .lpddr3_ctrl_phy_reset
= 0x1,
161 .ctrl_start_point
= 0x10,
183 * Dynamic Clock: Always Running
184 * Memory Burst length: 8
186 * Memory Bus width: 32 bit
188 * Additional Latancy for PLL: 0 Cycle
190 .memcontrol
= DMC_MEMCONTROL_CLK_STOP_DISABLE
|
191 DMC_MEMCONTROL_DPWRDN_DISABLE
|
192 DMC_MEMCONTROL_DPWRDN_ACTIVE_PRECHARGE
|
193 DMC_MEMCONTROL_TP_DISABLE
|
194 DMC_MEMCONTROL_DSREF_ENABLE
|
195 DMC_MEMCONTROL_ADD_LAT_PALL_CYCLE(0) |
196 DMC_MEMCONTROL_MEM_TYPE_DDR3
|
197 DMC_MEMCONTROL_MEM_WIDTH_32BIT
|
198 DMC_MEMCONTROL_NUM_CHIP_1
|
199 DMC_MEMCONTROL_BL_8
|
200 DMC_MEMCONTROL_PZQ_DISABLE
|
201 DMC_MEMCONTROL_MRR_BYTE_7_0
,
202 .memconfig
= DMC_MEMCONFIGX_CHIP_MAP_INTERLEAVED
|
203 DMC_MEMCONFIGX_CHIP_COL_10
|
204 DMC_MEMCONFIGX_CHIP_ROW_15
|
205 DMC_MEMCONFIGX_CHIP_BANK_8
,
206 .membaseconfig0
= DMC_MEMBASECONFIG_VAL(0x40),
207 .membaseconfig1
= DMC_MEMBASECONFIG_VAL(0x80),
208 .prechconfig_tp_cnt
= 0xff,
211 .concontrol
= DMC_CONCONTROL_DFI_INIT_START_DISABLE
|
212 DMC_CONCONTROL_TIMEOUT_LEVEL0
|
213 DMC_CONCONTROL_RD_FETCH_DISABLE
|
214 DMC_CONCONTROL_EMPTY_DISABLE
|
215 DMC_CONCONTROL_AREF_EN_DISABLE
|
216 DMC_CONCONTROL_IO_PD_CON_DISABLE
,
218 .chips_per_channel
= 2,
219 .chips_to_configure
= 1,
221 .impedance
= IMP_OUTPUT_DRV_30_OHM
,
222 .gate_leveling_enable
= 0,
224 .mem_manuf
= MEM_MANUF_SAMSUNG
,
225 .mem_type
= DDR_MODE_DDR3
,
226 .frequency_mhz
= 800,
246 .pclk_cdrex_ratio
= 0x5,
248 0x00020018, 0x00030000, 0x00010000, 0x00000d70
250 .timing_ref
= 0x000000bb,
251 .timing_row
= 0x8c36650e,
252 .timing_data
= 0x3630580b,
253 .timing_power
= 0x41000a44,
254 .phy0_dqs
= 0x08080808,
255 .phy1_dqs
= 0x08080808,
256 .phy0_dq
= 0x08080808,
257 .phy1_dq
= 0x08080808,
260 .phy0_pulld_dqs
= 0xf,
261 .phy1_pulld_dqs
= 0xf,
263 .lpddr3_ctrl_phy_reset
= 0x1,
264 .ctrl_start_point
= 0x10,
286 * Dynamic Clock: Always Running
287 * Memory Burst length: 8
289 * Memory Bus width: 32 bit
291 * Additional Latancy for PLL: 0 Cycle
293 .memcontrol
= DMC_MEMCONTROL_CLK_STOP_DISABLE
|
294 DMC_MEMCONTROL_DPWRDN_DISABLE
|
295 DMC_MEMCONTROL_DPWRDN_ACTIVE_PRECHARGE
|
296 DMC_MEMCONTROL_TP_DISABLE
|
297 DMC_MEMCONTROL_DSREF_ENABLE
|
298 DMC_MEMCONTROL_ADD_LAT_PALL_CYCLE(0) |
299 DMC_MEMCONTROL_MEM_TYPE_DDR3
|
300 DMC_MEMCONTROL_MEM_WIDTH_32BIT
|
301 DMC_MEMCONTROL_NUM_CHIP_1
|
302 DMC_MEMCONTROL_BL_8
|
303 DMC_MEMCONTROL_PZQ_DISABLE
|
304 DMC_MEMCONTROL_MRR_BYTE_7_0
,
305 .memconfig
= DMC_MEMCONFIGX_CHIP_MAP_INTERLEAVED
|
306 DMC_MEMCONFIGX_CHIP_COL_10
|
307 DMC_MEMCONFIGX_CHIP_ROW_15
|
308 DMC_MEMCONFIGX_CHIP_BANK_8
,
309 .membaseconfig0
= DMC_MEMBASECONFIG_VAL(0x40),
310 .membaseconfig1
= DMC_MEMBASECONFIG_VAL(0x80),
311 .prechconfig_tp_cnt
= 0xff,
314 .concontrol
= DMC_CONCONTROL_DFI_INIT_START_DISABLE
|
315 DMC_CONCONTROL_TIMEOUT_LEVEL0
|
316 DMC_CONCONTROL_RD_FETCH_DISABLE
|
317 DMC_CONCONTROL_EMPTY_DISABLE
|
318 DMC_CONCONTROL_AREF_EN_DISABLE
|
319 DMC_CONCONTROL_IO_PD_CON_DISABLE
,
321 .chips_per_channel
= 2,
322 .chips_to_configure
= 1,
324 .impedance
= IMP_OUTPUT_DRV_40_OHM
,
325 .gate_leveling_enable
= 1,
330 * Get the required memory type and speed (SPL version).
332 * In SPL we have no device tree, so we use the machine parameters
334 * @param mem_type Returns memory type
335 * @param frequency_mhz Returns memory speed in MHz
336 * @param arm_freq Returns ARM clock speed in MHz
337 * @param mem_manuf Return Memory Manufacturer name
339 static void clock_get_mem_selection(enum ddr_mode
*mem_type
,
340 unsigned *frequency_mhz
, unsigned *arm_freq
,
341 enum mem_manuf
*mem_manuf
)
343 struct spl_machine_param
*params
;
345 params
= spl_get_machine_params();
346 *mem_type
= params
->mem_type
;
347 *frequency_mhz
= params
->frequency_mhz
;
348 *arm_freq
= params
->arm_freq_mhz
;
349 *mem_manuf
= params
->mem_manuf
;
352 /* Get the ratios for setting ARM clock */
353 struct arm_clk_ratios
*get_arm_ratios(void)
355 struct arm_clk_ratios
*arm_ratio
;
356 enum ddr_mode mem_type
;
357 enum mem_manuf mem_manuf
;
358 unsigned frequency_mhz
, arm_freq
;
361 clock_get_mem_selection(&mem_type
, &frequency_mhz
,
362 &arm_freq
, &mem_manuf
);
364 for (i
= 0, arm_ratio
= arm_clk_ratios
; i
< ARRAY_SIZE(arm_clk_ratios
);
366 if (arm_ratio
->arm_freq_mhz
== arm_freq
)
370 /* will hang if failed to find clock ratio */
377 struct mem_timings
*clock_get_mem_timings(void)
379 struct mem_timings
*mem
;
380 enum ddr_mode mem_type
;
381 enum mem_manuf mem_manuf
;
382 unsigned frequency_mhz
, arm_freq
;
385 clock_get_mem_selection(&mem_type
, &frequency_mhz
,
386 &arm_freq
, &mem_manuf
);
387 for (i
= 0, mem
= mem_timings
; i
< ARRAY_SIZE(mem_timings
);
389 if (mem
->mem_type
== mem_type
&&
390 mem
->frequency_mhz
== frequency_mhz
&&
391 mem
->mem_manuf
== mem_manuf
)
395 /* will hang if failed to find memory timings */
402 void system_clock_init()
404 struct exynos5_clock
*clk
=
405 (struct exynos5_clock
*)samsung_get_base_clock();
406 struct mem_timings
*mem
;
407 struct arm_clk_ratios
*arm_clk_ratio
;
410 mem
= clock_get_mem_timings();
411 arm_clk_ratio
= get_arm_ratios();
413 clrbits_le32(&clk
->src_cpu
, MUX_APLL_SEL_MASK
);
415 val
= readl(&clk
->mux_stat_cpu
);
416 } while ((val
| MUX_APLL_SEL_MASK
) != val
);
418 clrbits_le32(&clk
->src_core1
, MUX_MPLL_SEL_MASK
);
420 val
= readl(&clk
->mux_stat_core1
);
421 } while ((val
| MUX_MPLL_SEL_MASK
) != val
);
423 clrbits_le32(&clk
->src_top2
, MUX_CPLL_SEL_MASK
);
424 clrbits_le32(&clk
->src_top2
, MUX_EPLL_SEL_MASK
);
425 clrbits_le32(&clk
->src_top2
, MUX_VPLL_SEL_MASK
);
426 clrbits_le32(&clk
->src_top2
, MUX_GPLL_SEL_MASK
);
427 tmp
= MUX_CPLL_SEL_MASK
| MUX_EPLL_SEL_MASK
| MUX_VPLL_SEL_MASK
430 val
= readl(&clk
->mux_stat_top2
);
431 } while ((val
| tmp
) != val
);
433 clrbits_le32(&clk
->src_cdrex
, MUX_BPLL_SEL_MASK
);
435 val
= readl(&clk
->mux_stat_cdrex
);
436 } while ((val
| MUX_BPLL_SEL_MASK
) != val
);
439 writel(APLL_LOCK_VAL
, &clk
->apll_lock
);
441 writel(MPLL_LOCK_VAL
, &clk
->mpll_lock
);
443 writel(BPLL_LOCK_VAL
, &clk
->bpll_lock
);
445 writel(CPLL_LOCK_VAL
, &clk
->cpll_lock
);
447 writel(GPLL_LOCK_VAL
, &clk
->gpll_lock
);
449 writel(EPLL_LOCK_VAL
, &clk
->epll_lock
);
451 writel(VPLL_LOCK_VAL
, &clk
->vpll_lock
);
453 writel(CLK_REG_DISABLE
, &clk
->pll_div2_sel
);
455 writel(MUX_HPM_SEL_MASK
, &clk
->src_cpu
);
457 val
= readl(&clk
->mux_stat_cpu
);
458 } while ((val
| HPM_SEL_SCLK_MPLL
) != val
);
460 val
= arm_clk_ratio
->arm2_ratio
<< 28
461 | arm_clk_ratio
->apll_ratio
<< 24
462 | arm_clk_ratio
->pclk_dbg_ratio
<< 20
463 | arm_clk_ratio
->atb_ratio
<< 16
464 | arm_clk_ratio
->periph_ratio
<< 12
465 | arm_clk_ratio
->acp_ratio
<< 8
466 | arm_clk_ratio
->cpud_ratio
<< 4
467 | arm_clk_ratio
->arm_ratio
;
468 writel(val
, &clk
->div_cpu0
);
470 val
= readl(&clk
->div_stat_cpu0
);
473 writel(CLK_DIV_CPU1_VAL
, &clk
->div_cpu1
);
475 val
= readl(&clk
->div_stat_cpu1
);
479 writel(APLL_CON1_VAL
, &clk
->apll_con1
);
480 val
= set_pll(arm_clk_ratio
->apll_mdiv
, arm_clk_ratio
->apll_pdiv
,
481 arm_clk_ratio
->apll_sdiv
);
482 writel(val
, &clk
->apll_con0
);
483 while ((readl(&clk
->apll_con0
) & APLL_CON0_LOCKED
) == 0)
487 writel(MPLL_CON1_VAL
, &clk
->mpll_con1
);
488 val
= set_pll(mem
->mpll_mdiv
, mem
->mpll_pdiv
, mem
->mpll_sdiv
);
489 writel(val
, &clk
->mpll_con0
);
490 while ((readl(&clk
->mpll_con0
) & MPLL_CON0_LOCKED
) == 0)
494 writel(BPLL_CON1_VAL
, &clk
->bpll_con1
);
495 val
= set_pll(mem
->bpll_mdiv
, mem
->bpll_pdiv
, mem
->bpll_sdiv
);
496 writel(val
, &clk
->bpll_con0
);
497 while ((readl(&clk
->bpll_con0
) & BPLL_CON0_LOCKED
) == 0)
501 writel(CPLL_CON1_VAL
, &clk
->cpll_con1
);
502 val
= set_pll(mem
->cpll_mdiv
, mem
->cpll_pdiv
, mem
->cpll_sdiv
);
503 writel(val
, &clk
->cpll_con0
);
504 while ((readl(&clk
->cpll_con0
) & CPLL_CON0_LOCKED
) == 0)
508 writel(GPLL_CON1_VAL
, &clk
->gpll_con1
);
509 val
= set_pll(mem
->gpll_mdiv
, mem
->gpll_pdiv
, mem
->gpll_sdiv
);
510 writel(val
, &clk
->gpll_con0
);
511 while ((readl(&clk
->gpll_con0
) & GPLL_CON0_LOCKED
) == 0)
515 writel(EPLL_CON2_VAL
, &clk
->epll_con2
);
516 writel(EPLL_CON1_VAL
, &clk
->epll_con1
);
517 val
= set_pll(mem
->epll_mdiv
, mem
->epll_pdiv
, mem
->epll_sdiv
);
518 writel(val
, &clk
->epll_con0
);
519 while ((readl(&clk
->epll_con0
) & EPLL_CON0_LOCKED
) == 0)
523 writel(VPLL_CON2_VAL
, &clk
->vpll_con2
);
524 writel(VPLL_CON1_VAL
, &clk
->vpll_con1
);
525 val
= set_pll(mem
->vpll_mdiv
, mem
->vpll_pdiv
, mem
->vpll_sdiv
);
526 writel(val
, &clk
->vpll_con0
);
527 while ((readl(&clk
->vpll_con0
) & VPLL_CON0_LOCKED
) == 0)
530 writel(CLK_SRC_CORE0_VAL
, &clk
->src_core0
);
531 writel(CLK_DIV_CORE0_VAL
, &clk
->div_core0
);
532 while (readl(&clk
->div_stat_core0
) != 0)
535 writel(CLK_DIV_CORE1_VAL
, &clk
->div_core1
);
536 while (readl(&clk
->div_stat_core1
) != 0)
539 writel(CLK_DIV_SYSRGT_VAL
, &clk
->div_sysrgt
);
540 while (readl(&clk
->div_stat_sysrgt
) != 0)
543 writel(CLK_DIV_ACP_VAL
, &clk
->div_acp
);
544 while (readl(&clk
->div_stat_acp
) != 0)
547 writel(CLK_DIV_SYSLFT_VAL
, &clk
->div_syslft
);
548 while (readl(&clk
->div_stat_syslft
) != 0)
551 writel(CLK_SRC_TOP0_VAL
, &clk
->src_top0
);
552 writel(CLK_SRC_TOP1_VAL
, &clk
->src_top1
);
553 writel(TOP2_VAL
, &clk
->src_top2
);
554 writel(CLK_SRC_TOP3_VAL
, &clk
->src_top3
);
556 writel(CLK_DIV_TOP0_VAL
, &clk
->div_top0
);
557 while (readl(&clk
->div_stat_top0
))
560 writel(CLK_DIV_TOP1_VAL
, &clk
->div_top1
);
561 while (readl(&clk
->div_stat_top1
))
564 writel(CLK_SRC_LEX_VAL
, &clk
->src_lex
);
566 val
= readl(&clk
->mux_stat_lex
);
567 if (val
== (val
| 1))
571 writel(CLK_DIV_LEX_VAL
, &clk
->div_lex
);
572 while (readl(&clk
->div_stat_lex
))
575 writel(CLK_DIV_R0X_VAL
, &clk
->div_r0x
);
576 while (readl(&clk
->div_stat_r0x
))
579 writel(CLK_DIV_R0X_VAL
, &clk
->div_r0x
);
580 while (readl(&clk
->div_stat_r0x
))
583 writel(CLK_DIV_R1X_VAL
, &clk
->div_r1x
);
584 while (readl(&clk
->div_stat_r1x
))
587 writel(CLK_REG_DISABLE
, &clk
->src_cdrex
);
589 writel(CLK_DIV_CDREX_VAL
, &clk
->div_cdrex
);
590 while (readl(&clk
->div_stat_cdrex
))
593 val
= readl(&clk
->src_cpu
);
594 val
|= CLK_SRC_CPU_VAL
;
595 writel(val
, &clk
->src_cpu
);
597 val
= readl(&clk
->src_top2
);
598 val
|= CLK_SRC_TOP2_VAL
;
599 writel(val
, &clk
->src_top2
);
601 val
= readl(&clk
->src_core1
);
602 val
|= CLK_SRC_CORE1_VAL
;
603 writel(val
, &clk
->src_core1
);
605 writel(CLK_SRC_FSYS0_VAL
, &clk
->src_fsys
);
606 writel(CLK_DIV_FSYS0_VAL
, &clk
->div_fsys0
);
607 while (readl(&clk
->div_stat_fsys0
))
610 writel(CLK_REG_DISABLE
, &clk
->clkout_cmu_cpu
);
611 writel(CLK_REG_DISABLE
, &clk
->clkout_cmu_core
);
612 writel(CLK_REG_DISABLE
, &clk
->clkout_cmu_acp
);
613 writel(CLK_REG_DISABLE
, &clk
->clkout_cmu_top
);
614 writel(CLK_REG_DISABLE
, &clk
->clkout_cmu_lex
);
615 writel(CLK_REG_DISABLE
, &clk
->clkout_cmu_r0x
);
616 writel(CLK_REG_DISABLE
, &clk
->clkout_cmu_r1x
);
617 writel(CLK_REG_DISABLE
, &clk
->clkout_cmu_cdrex
);
619 writel(CLK_SRC_PERIC0_VAL
, &clk
->src_peric0
);
620 writel(CLK_DIV_PERIC0_VAL
, &clk
->div_peric0
);
622 writel(CLK_SRC_PERIC1_VAL
, &clk
->src_peric1
);
623 writel(CLK_DIV_PERIC1_VAL
, &clk
->div_peric1
);
624 writel(CLK_DIV_PERIC2_VAL
, &clk
->div_peric2
);
625 writel(CLK_DIV_PERIC3_VAL
, &clk
->div_peric3
);
627 writel(SCLK_SRC_ISP_VAL
, &clk
->sclk_src_isp
);
628 writel(SCLK_DIV_ISP_VAL
, &clk
->sclk_div_isp
);
629 writel(CLK_DIV_ISP0_VAL
, &clk
->div_isp0
);
630 writel(CLK_DIV_ISP1_VAL
, &clk
->div_isp1
);
631 writel(CLK_DIV_ISP2_VAL
, &clk
->div_isp2
);
633 /* FIMD1 SRC CLK SELECTION */
634 writel(CLK_SRC_DISP1_0_VAL
, &clk
->src_disp1_0
);
636 val
= MMC2_PRE_RATIO_VAL
<< MMC2_PRE_RATIO_OFFSET
637 | MMC2_RATIO_VAL
<< MMC2_RATIO_OFFSET
638 | MMC3_PRE_RATIO_VAL
<< MMC3_PRE_RATIO_OFFSET
639 | MMC3_RATIO_VAL
<< MMC3_RATIO_OFFSET
;
640 writel(val
, &clk
->div_fsys2
);
643 void clock_init_dp_clock(void)
645 struct exynos5_clock
*clk
=
646 (struct exynos5_clock
*)samsung_get_base_clock();
648 /* DP clock enable */
649 setbits_le32(&clk
->gate_ip_disp1
, CLK_GATE_DP1_ALLOW
);
651 /* We run DP at 267 Mhz */
652 setbits_le32(&clk
->div_disp1_0
, CLK_DIV_DISP1_0_FIMD1
);
656 * Set clock divisor value for booting from EMMC.
657 * Set DWMMC channel-0 clk div to operate mmc0 device at 50MHz.
659 void emmc_boot_clk_div_set(void)
661 struct exynos5_clock
*clk
=
662 (struct exynos5_clock
*)samsung_get_base_clock();
663 unsigned int div_mmc
;
665 div_mmc
= readl((unsigned int) &clk
->div_fsys1
) & ~FSYS1_MMC0_DIV_MASK
;
666 div_mmc
|= FSYS1_MMC0_DIV_VAL
;
667 writel(div_mmc
, (unsigned int) &clk
->div_fsys1
);