arch/arm/cpu/armv7/ls102xa/Kconfig

   1 config ARCH_LS1021A
   2         bool
   3         select SYS_FSL_ERRATUM_A008378
   4         select SYS_FSL_ERRATUM_A008407
   5         select SYS_FSL_ERRATUM_A008997
   6         select SYS_FSL_ERRATUM_A009007
   7         select SYS_FSL_ERRATUM_A009008
   8         select SYS_FSL_ERRATUM_A009663
   9         select SYS_FSL_ERRATUM_A009798
  10         select SYS_FSL_ERRATUM_A009942
  11         select SYS_FSL_ERRATUM_A010315
  12         select SYS_FSL_HAS_CCI400
  13         select SYS_FSL_SRDS_1
  14         select SYS_HAS_SERDES
  15         select SYS_FSL_DDR_BE if SYS_FSL_DDR
  16         select SYS_FSL_DDR_VER_50 if SYS_FSL_DDR
  17         select SYS_FSL_HAS_DDR3 if SYS_FSL_DDR
  18         select SYS_FSL_HAS_DDR4 if SYS_FSL_DDR
  19         select SYS_FSL_HAS_SEC
  20         select SYS_FSL_SEC_COMPAT_5
  21         select SYS_FSL_SEC_LE
  22         imply SCSI
  23         imply CMD_PCI
  24
  25 menu "LS102xA architecture"
  26         depends on ARCH_LS1021A
  27
  28 config FSL_PCIE_COMPAT
  29         string "PCIe compatible of Kernel DT"
  30         depends on PCIE_LAYERSCAPE
  31         default "fsl,ls1021a-pcie" if ARCH_LS1021A
  32         help
  33           This compatible is used to find pci controller node in Kernel DT
  34           to complete fixup.
  35
  36 config LS1_DEEP_SLEEP
  37         bool "Deep sleep"
  38         depends on ARCH_LS1021A
  39
  40 config MAX_CPUS
  41         int "Maximum number of CPUs permitted for LS102xA"
  42         depends on ARCH_LS1021A
  43         default 2
  44         help
  45           Set this number to the maximum number of possible CPUs in the SoC.
  46           SoCs may have multiple clusters with each cluster may have multiple
  47           ports. If some ports are reserved but higher ports are used for
  48           cores, count the reserved ports. This will allocate enough memory
  49           in spin table to properly handle all cores.
  50
  51 config SECURE_BOOT
  52         bool    "Secure Boot"
  53         help
  54                 Enable Freescale Secure Boot feature. Normally selected
  55                 by defconfig. If unsure, do not change.
  56
  57 config SYS_CCI400_OFFSET
  58         hex "Offset for CCI400 base"
  59         depends on SYS_FSL_HAS_CCI400
  60         default 0x180000
  61         help
  62           Offset for CCI400 base.
  63           CCI400 base addr = CCSRBAR + CCI400_OFFSET
  64
  65 config SYS_FSL_ERRATUM_A008997
  66         bool
  67         help
  68           Workaround for USB PHY erratum A008997
  69
  70 config SYS_FSL_ERRATUM_A009007
  71         bool
  72         help
  73           Workaround for USB PHY erratum A009007
  74
  75 config SYS_FSL_ERRATUM_A009008
  76         bool
  77         help
  78           Workaround for USB PHY erratum A009008
  79
  80 config SYS_FSL_ERRATUM_A009798
  81         bool
  82         help
  83           Workaround for USB PHY erratum A009798
  84
  85 config SYS_FSL_ERRATUM_A010315
  86         bool "Workaround for PCIe erratum A010315"
  87
  88 config SYS_FSL_HAS_CCI400
  89         bool
  90
  91 config SYS_FSL_SRDS_1
  92         bool
  93
  94 config SYS_FSL_SRDS_2
  95         bool
  96
  97 config SYS_HAS_SERDES
  98         bool
  99
 100 config SYS_FSL_IFC_BANK_COUNT
 101         int "Maximum banks of Integrated flash controller"
 102         depends on ARCH_LS1021A
 103         default 8
 104
 105 config SYS_FSL_ERRATUM_A008407
 106         bool
 107
 108 endmenu