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Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx
[people/ms/u-boot.git] / arch / arm / cpu / armv7 / mx6 / clock.c
1 /*
2 * Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
3 *
4 * SPDX-License-Identifier: GPL-2.0+
5 */
6
7 #include <common.h>
8 #include <div64.h>
9 #include <asm/io.h>
10 #include <asm/errno.h>
11 #include <asm/arch/imx-regs.h>
12 #include <asm/arch/crm_regs.h>
13 #include <asm/arch/clock.h>
14 #include <asm/arch/sys_proto.h>
15
16 enum pll_clocks {
17 PLL_SYS, /* System PLL */
18 PLL_BUS, /* System Bus PLL*/
19 PLL_USBOTG, /* OTG USB PLL */
20 PLL_ENET, /* ENET PLL */
21 };
22
23 struct mxc_ccm_reg *imx_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
24
25 #ifdef CONFIG_MXC_OCOTP
26 void enable_ocotp_clk(unsigned char enable)
27 {
28 u32 reg;
29
30 reg = __raw_readl(&imx_ccm->CCGR2);
31 if (enable)
32 reg |= MXC_CCM_CCGR2_OCOTP_CTRL_MASK;
33 else
34 reg &= ~MXC_CCM_CCGR2_OCOTP_CTRL_MASK;
35 __raw_writel(reg, &imx_ccm->CCGR2);
36 }
37 #endif
38
39 #ifdef CONFIG_NAND_MXS
40 void setup_gpmi_io_clk(u32 cfg)
41 {
42 /* Disable clocks per ERR007177 from MX6 errata */
43 clrbits_le32(&imx_ccm->CCGR4,
44 MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK |
45 MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK |
46 MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK |
47 MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK |
48 MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_MASK);
49
50 clrbits_le32(&imx_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK);
51
52 clrsetbits_le32(&imx_ccm->cs2cdr,
53 MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK |
54 MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK |
55 MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK,
56 cfg);
57
58 setbits_le32(&imx_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK);
59 setbits_le32(&imx_ccm->CCGR4,
60 MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK |
61 MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK |
62 MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK |
63 MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK |
64 MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_MASK);
65 }
66 #endif
67
68 void enable_usboh3_clk(unsigned char enable)
69 {
70 u32 reg;
71
72 reg = __raw_readl(&imx_ccm->CCGR6);
73 if (enable)
74 reg |= MXC_CCM_CCGR6_USBOH3_MASK;
75 else
76 reg &= ~(MXC_CCM_CCGR6_USBOH3_MASK);
77 __raw_writel(reg, &imx_ccm->CCGR6);
78
79 }
80
81 #if defined(CONFIG_FEC_MXC) && !defined(CONFIG_MX6SX)
82 void enable_enet_clk(unsigned char enable)
83 {
84 u32 mask, *addr;
85
86 if (is_cpu_type(MXC_CPU_MX6UL)) {
87 mask = MXC_CCM_CCGR3_ENET_MASK;
88 addr = &imx_ccm->CCGR3;
89 } else {
90 mask = MXC_CCM_CCGR1_ENET_MASK;
91 addr = &imx_ccm->CCGR1;
92 }
93
94 if (enable)
95 setbits_le32(addr, mask);
96 else
97 clrbits_le32(addr, mask);
98 }
99 #endif
100
101 #ifdef CONFIG_MXC_UART
102 void enable_uart_clk(unsigned char enable)
103 {
104 u32 mask;
105
106 if (is_cpu_type(MXC_CPU_MX6UL))
107 mask = MXC_CCM_CCGR5_UART_MASK;
108 else
109 mask = MXC_CCM_CCGR5_UART_MASK | MXC_CCM_CCGR5_UART_SERIAL_MASK;
110
111 if (enable)
112 setbits_le32(&imx_ccm->CCGR5, mask);
113 else
114 clrbits_le32(&imx_ccm->CCGR5, mask);
115 }
116 #endif
117
118 #ifdef CONFIG_MMC
119 int enable_usdhc_clk(unsigned char enable, unsigned bus_num)
120 {
121 u32 mask;
122
123 if (bus_num > 3)
124 return -EINVAL;
125
126 mask = MXC_CCM_CCGR_CG_MASK << (bus_num * 2 + 2);
127 if (enable)
128 setbits_le32(&imx_ccm->CCGR6, mask);
129 else
130 clrbits_le32(&imx_ccm->CCGR6, mask);
131
132 return 0;
133 }
134 #endif
135
136 #ifdef CONFIG_SYS_I2C_MXC
137 /* i2c_num can be from 0 - 3 */
138 int enable_i2c_clk(unsigned char enable, unsigned i2c_num)
139 {
140 u32 reg;
141 u32 mask;
142 u32 *addr;
143
144 if (i2c_num > 3)
145 return -EINVAL;
146 if (i2c_num < 3) {
147 mask = MXC_CCM_CCGR_CG_MASK
148 << (MXC_CCM_CCGR2_I2C1_SERIAL_OFFSET
149 + (i2c_num << 1));
150 reg = __raw_readl(&imx_ccm->CCGR2);
151 if (enable)
152 reg |= mask;
153 else
154 reg &= ~mask;
155 __raw_writel(reg, &imx_ccm->CCGR2);
156 } else {
157 if (is_cpu_type(MXC_CPU_MX6SX) || is_cpu_type(MXC_CPU_MX6UL)) {
158 mask = MXC_CCM_CCGR6_I2C4_MASK;
159 addr = &imx_ccm->CCGR6;
160 } else {
161 mask = MXC_CCM_CCGR1_I2C4_SERIAL_MASK;
162 addr = &imx_ccm->CCGR1;
163 }
164 reg = __raw_readl(addr);
165 if (enable)
166 reg |= mask;
167 else
168 reg &= ~mask;
169 __raw_writel(reg, addr);
170 }
171 return 0;
172 }
173 #endif
174
175 /* spi_num can be from 0 - SPI_MAX_NUM */
176 int enable_spi_clk(unsigned char enable, unsigned spi_num)
177 {
178 u32 reg;
179 u32 mask;
180
181 if (spi_num > SPI_MAX_NUM)
182 return -EINVAL;
183
184 mask = MXC_CCM_CCGR_CG_MASK << (spi_num << 1);
185 reg = __raw_readl(&imx_ccm->CCGR1);
186 if (enable)
187 reg |= mask;
188 else
189 reg &= ~mask;
190 __raw_writel(reg, &imx_ccm->CCGR1);
191 return 0;
192 }
193 static u32 decode_pll(enum pll_clocks pll, u32 infreq)
194 {
195 u32 div;
196
197 switch (pll) {
198 case PLL_SYS:
199 div = __raw_readl(&imx_ccm->analog_pll_sys);
200 div &= BM_ANADIG_PLL_SYS_DIV_SELECT;
201
202 return (infreq * div) >> 1;
203 case PLL_BUS:
204 div = __raw_readl(&imx_ccm->analog_pll_528);
205 div &= BM_ANADIG_PLL_528_DIV_SELECT;
206
207 return infreq * (20 + (div << 1));
208 case PLL_USBOTG:
209 div = __raw_readl(&imx_ccm->analog_usb1_pll_480_ctrl);
210 div &= BM_ANADIG_USB1_PLL_480_CTRL_DIV_SELECT;
211
212 return infreq * (20 + (div << 1));
213 case PLL_ENET:
214 div = __raw_readl(&imx_ccm->analog_pll_enet);
215 div &= BM_ANADIG_PLL_ENET_DIV_SELECT;
216
217 return 25000000 * (div + (div >> 1) + 1);
218 default:
219 return 0;
220 }
221 /* NOTREACHED */
222 }
223 static u32 mxc_get_pll_pfd(enum pll_clocks pll, int pfd_num)
224 {
225 u32 div;
226 u64 freq;
227
228 switch (pll) {
229 case PLL_BUS:
230 if (!is_cpu_type(MXC_CPU_MX6UL)) {
231 if (pfd_num == 3) {
232 /* No PFD3 on PPL2 */
233 return 0;
234 }
235 }
236 div = __raw_readl(&imx_ccm->analog_pfd_528);
237 freq = (u64)decode_pll(PLL_BUS, MXC_HCLK);
238 break;
239 case PLL_USBOTG:
240 div = __raw_readl(&imx_ccm->analog_pfd_480);
241 freq = (u64)decode_pll(PLL_USBOTG, MXC_HCLK);
242 break;
243 default:
244 /* No PFD on other PLL */
245 return 0;
246 }
247
248 return lldiv(freq * 18, (div & ANATOP_PFD_FRAC_MASK(pfd_num)) >>
249 ANATOP_PFD_FRAC_SHIFT(pfd_num));
250 }
251
252 static u32 get_mcu_main_clk(void)
253 {
254 u32 reg, freq;
255
256 reg = __raw_readl(&imx_ccm->cacrr);
257 reg &= MXC_CCM_CACRR_ARM_PODF_MASK;
258 reg >>= MXC_CCM_CACRR_ARM_PODF_OFFSET;
259 freq = decode_pll(PLL_SYS, MXC_HCLK);
260
261 return freq / (reg + 1);
262 }
263
264 u32 get_periph_clk(void)
265 {
266 u32 reg, div = 0, freq = 0;
267
268 reg = __raw_readl(&imx_ccm->cbcdr);
269 if (reg & MXC_CCM_CBCDR_PERIPH_CLK_SEL) {
270 div = (reg & MXC_CCM_CBCDR_PERIPH_CLK2_PODF_MASK) >>
271 MXC_CCM_CBCDR_PERIPH_CLK2_PODF_OFFSET;
272 reg = __raw_readl(&imx_ccm->cbcmr);
273 reg &= MXC_CCM_CBCMR_PERIPH_CLK2_SEL_MASK;
274 reg >>= MXC_CCM_CBCMR_PERIPH_CLK2_SEL_OFFSET;
275
276 switch (reg) {
277 case 0:
278 freq = decode_pll(PLL_USBOTG, MXC_HCLK);
279 break;
280 case 1:
281 case 2:
282 freq = MXC_HCLK;
283 break;
284 default:
285 break;
286 }
287 } else {
288 reg = __raw_readl(&imx_ccm->cbcmr);
289 reg &= MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK;
290 reg >>= MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_OFFSET;
291
292 switch (reg) {
293 case 0:
294 freq = decode_pll(PLL_BUS, MXC_HCLK);
295 break;
296 case 1:
297 freq = mxc_get_pll_pfd(PLL_BUS, 2);
298 break;
299 case 2:
300 freq = mxc_get_pll_pfd(PLL_BUS, 0);
301 break;
302 case 3:
303 /* static / 2 divider */
304 freq = mxc_get_pll_pfd(PLL_BUS, 2) / 2;
305 break;
306 default:
307 break;
308 }
309 }
310
311 return freq / (div + 1);
312 }
313
314 static u32 get_ipg_clk(void)
315 {
316 u32 reg, ipg_podf;
317
318 reg = __raw_readl(&imx_ccm->cbcdr);
319 reg &= MXC_CCM_CBCDR_IPG_PODF_MASK;
320 ipg_podf = reg >> MXC_CCM_CBCDR_IPG_PODF_OFFSET;
321
322 return get_ahb_clk() / (ipg_podf + 1);
323 }
324
325 static u32 get_ipg_per_clk(void)
326 {
327 u32 reg, perclk_podf;
328
329 reg = __raw_readl(&imx_ccm->cscmr1);
330 if (is_cpu_type(MXC_CPU_MX6SL) || is_cpu_type(MXC_CPU_MX6SX) ||
331 is_mx6dqp() || is_cpu_type(MXC_CPU_MX6UL)) {
332 if (reg & MXC_CCM_CSCMR1_PER_CLK_SEL_MASK)
333 return MXC_HCLK; /* OSC 24Mhz */
334 }
335
336 perclk_podf = reg & MXC_CCM_CSCMR1_PERCLK_PODF_MASK;
337
338 return get_ipg_clk() / (perclk_podf + 1);
339 }
340
341 static u32 get_uart_clk(void)
342 {
343 u32 reg, uart_podf;
344 u32 freq = decode_pll(PLL_USBOTG, MXC_HCLK) / 6; /* static divider */
345 reg = __raw_readl(&imx_ccm->cscdr1);
346
347 if (is_cpu_type(MXC_CPU_MX6SL) || is_cpu_type(MXC_CPU_MX6SX) ||
348 is_mx6dqp() || is_cpu_type(MXC_CPU_MX6UL)) {
349 if (reg & MXC_CCM_CSCDR1_UART_CLK_SEL)
350 freq = MXC_HCLK;
351 }
352
353 reg &= MXC_CCM_CSCDR1_UART_CLK_PODF_MASK;
354 uart_podf = reg >> MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET;
355
356 return freq / (uart_podf + 1);
357 }
358
359 static u32 get_cspi_clk(void)
360 {
361 u32 reg, cspi_podf;
362
363 reg = __raw_readl(&imx_ccm->cscdr2);
364 cspi_podf = (reg & MXC_CCM_CSCDR2_ECSPI_CLK_PODF_MASK) >>
365 MXC_CCM_CSCDR2_ECSPI_CLK_PODF_OFFSET;
366
367 if (is_mx6dqp() || is_cpu_type(MXC_CPU_MX6SL) ||
368 is_cpu_type(MXC_CPU_MX6SX) || is_cpu_type(MXC_CPU_MX6UL)) {
369 if (reg & MXC_CCM_CSCDR2_ECSPI_CLK_SEL_MASK)
370 return MXC_HCLK / (cspi_podf + 1);
371 }
372
373 return decode_pll(PLL_USBOTG, MXC_HCLK) / (8 * (cspi_podf + 1));
374 }
375
376 static u32 get_axi_clk(void)
377 {
378 u32 root_freq, axi_podf;
379 u32 cbcdr = __raw_readl(&imx_ccm->cbcdr);
380
381 axi_podf = cbcdr & MXC_CCM_CBCDR_AXI_PODF_MASK;
382 axi_podf >>= MXC_CCM_CBCDR_AXI_PODF_OFFSET;
383
384 if (cbcdr & MXC_CCM_CBCDR_AXI_SEL) {
385 if (cbcdr & MXC_CCM_CBCDR_AXI_ALT_SEL)
386 root_freq = mxc_get_pll_pfd(PLL_BUS, 2);
387 else
388 root_freq = mxc_get_pll_pfd(PLL_USBOTG, 1);
389 } else
390 root_freq = get_periph_clk();
391
392 return root_freq / (axi_podf + 1);
393 }
394
395 static u32 get_emi_slow_clk(void)
396 {
397 u32 emi_clk_sel, emi_slow_podf, cscmr1, root_freq = 0;
398
399 cscmr1 = __raw_readl(&imx_ccm->cscmr1);
400 emi_clk_sel = cscmr1 & MXC_CCM_CSCMR1_ACLK_EMI_SLOW_MASK;
401 emi_clk_sel >>= MXC_CCM_CSCMR1_ACLK_EMI_SLOW_OFFSET;
402 emi_slow_podf = cscmr1 & MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_MASK;
403 emi_slow_podf >>= MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_OFFSET;
404
405 switch (emi_clk_sel) {
406 case 0:
407 root_freq = get_axi_clk();
408 break;
409 case 1:
410 root_freq = decode_pll(PLL_USBOTG, MXC_HCLK);
411 break;
412 case 2:
413 root_freq = mxc_get_pll_pfd(PLL_BUS, 2);
414 break;
415 case 3:
416 root_freq = mxc_get_pll_pfd(PLL_BUS, 0);
417 break;
418 }
419
420 return root_freq / (emi_slow_podf + 1);
421 }
422
423 static u32 get_mmdc_ch0_clk(void)
424 {
425 u32 cbcmr = __raw_readl(&imx_ccm->cbcmr);
426 u32 cbcdr = __raw_readl(&imx_ccm->cbcdr);
427
428 u32 freq, podf, per2_clk2_podf;
429
430 if (is_cpu_type(MXC_CPU_MX6SX) || is_cpu_type(MXC_CPU_MX6UL) ||
431 is_cpu_type(MXC_CPU_MX6SL)) {
432 podf = (cbcdr & MXC_CCM_CBCDR_MMDC_CH1_PODF_MASK) >>
433 MXC_CCM_CBCDR_MMDC_CH1_PODF_OFFSET;
434 if (cbcdr & MXC_CCM_CBCDR_PERIPH2_CLK_SEL) {
435 per2_clk2_podf = (cbcdr & MXC_CCM_CBCDR_PERIPH2_CLK2_PODF_MASK) >>
436 MXC_CCM_CBCDR_PERIPH2_CLK2_PODF_OFFSET;
437 if (is_cpu_type(MXC_CPU_MX6SL)) {
438 if (cbcmr & MXC_CCM_CBCMR_PERIPH2_CLK2_SEL)
439 freq = MXC_HCLK;
440 else
441 freq = decode_pll(PLL_USBOTG, MXC_HCLK);
442 } else {
443 if (cbcmr & MXC_CCM_CBCMR_PERIPH2_CLK2_SEL)
444 freq = decode_pll(PLL_BUS, MXC_HCLK);
445 else
446 freq = decode_pll(PLL_USBOTG, MXC_HCLK);
447 }
448 } else {
449 per2_clk2_podf = 0;
450 switch ((cbcmr &
451 MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_MASK) >>
452 MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_OFFSET) {
453 case 0:
454 freq = decode_pll(PLL_BUS, MXC_HCLK);
455 break;
456 case 1:
457 freq = mxc_get_pll_pfd(PLL_BUS, 2);
458 break;
459 case 2:
460 freq = mxc_get_pll_pfd(PLL_BUS, 0);
461 break;
462 case 3:
463 /* static / 2 divider */
464 freq = mxc_get_pll_pfd(PLL_BUS, 2) / 2;
465 break;
466 }
467 }
468 return freq / (podf + 1) / (per2_clk2_podf + 1);
469 } else {
470 podf = (cbcdr & MXC_CCM_CBCDR_MMDC_CH0_PODF_MASK) >>
471 MXC_CCM_CBCDR_MMDC_CH0_PODF_OFFSET;
472 return get_periph_clk() / (podf + 1);
473 }
474 }
475
476 #ifdef CONFIG_FSL_QSPI
477 /* qspi_num can be from 0 - 1 */
478 void enable_qspi_clk(int qspi_num)
479 {
480 u32 reg = 0;
481 /* Enable QuadSPI clock */
482 switch (qspi_num) {
483 case 0:
484 /* disable the clock gate */
485 clrbits_le32(&imx_ccm->CCGR3, MXC_CCM_CCGR3_QSPI1_MASK);
486
487 /* set 50M : (50 = 396 / 2 / 4) */
488 reg = readl(&imx_ccm->cscmr1);
489 reg &= ~(MXC_CCM_CSCMR1_QSPI1_PODF_MASK |
490 MXC_CCM_CSCMR1_QSPI1_CLK_SEL_MASK);
491 reg |= ((1 << MXC_CCM_CSCMR1_QSPI1_PODF_OFFSET) |
492 (2 << MXC_CCM_CSCMR1_QSPI1_CLK_SEL_OFFSET));
493 writel(reg, &imx_ccm->cscmr1);
494
495 /* enable the clock gate */
496 setbits_le32(&imx_ccm->CCGR3, MXC_CCM_CCGR3_QSPI1_MASK);
497 break;
498 case 1:
499 /*
500 * disable the clock gate
501 * QSPI2 and GPMI_BCH_INPUT_GPMI_IO share the same clock gate,
502 * disable both of them.
503 */
504 clrbits_le32(&imx_ccm->CCGR4, MXC_CCM_CCGR4_QSPI2_ENFC_MASK |
505 MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK);
506
507 /* set 50M : (50 = 396 / 2 / 4) */
508 reg = readl(&imx_ccm->cs2cdr);
509 reg &= ~(MXC_CCM_CS2CDR_QSPI2_CLK_PODF_MASK |
510 MXC_CCM_CS2CDR_QSPI2_CLK_PRED_MASK |
511 MXC_CCM_CS2CDR_QSPI2_CLK_SEL_MASK);
512 reg |= (MXC_CCM_CS2CDR_QSPI2_CLK_PRED(0x1) |
513 MXC_CCM_CS2CDR_QSPI2_CLK_SEL(0x3));
514 writel(reg, &imx_ccm->cs2cdr);
515
516 /*enable the clock gate*/
517 setbits_le32(&imx_ccm->CCGR4, MXC_CCM_CCGR4_QSPI2_ENFC_MASK |
518 MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK);
519 break;
520 default:
521 break;
522 }
523 }
524 #endif
525
526 #ifdef CONFIG_FEC_MXC
527 int enable_fec_anatop_clock(int fec_id, enum enet_freq freq)
528 {
529 u32 reg = 0;
530 s32 timeout = 100000;
531
532 struct anatop_regs __iomem *anatop =
533 (struct anatop_regs __iomem *)ANATOP_BASE_ADDR;
534
535 if (freq < ENET_25MHZ || freq > ENET_125MHZ)
536 return -EINVAL;
537
538 if (fec_id == 0) {
539 reg &= ~BM_ANADIG_PLL_ENET_DIV_SELECT;
540 reg |= BF_ANADIG_PLL_ENET_DIV_SELECT(freq);
541 } else if (fec_id == 1) {
542 /* Only i.MX6SX/UL support ENET2 */
543 if (!(is_cpu_type(MXC_CPU_MX6SX) ||
544 is_cpu_type(MXC_CPU_MX6UL)))
545 return -EINVAL;
546 reg &= ~BM_ANADIG_PLL_ENET2_DIV_SELECT;
547 reg |= BF_ANADIG_PLL_ENET2_DIV_SELECT(freq);
548 } else {
549 return -EINVAL;
550 }
551
552 if ((reg & BM_ANADIG_PLL_ENET_POWERDOWN) ||
553 (!(reg & BM_ANADIG_PLL_ENET_LOCK))) {
554 reg &= ~BM_ANADIG_PLL_ENET_POWERDOWN;
555 writel(reg, &anatop->pll_enet);
556 while (timeout--) {
557 if (readl(&anatop->pll_enet) & BM_ANADIG_PLL_ENET_LOCK)
558 break;
559 }
560 if (timeout < 0)
561 return -ETIMEDOUT;
562 }
563
564 /* Enable FEC clock */
565 if (fec_id == 0)
566 reg |= BM_ANADIG_PLL_ENET_ENABLE;
567 else
568 reg |= BM_ANADIG_PLL_ENET2_ENABLE;
569 reg &= ~BM_ANADIG_PLL_ENET_BYPASS;
570 writel(reg, &anatop->pll_enet);
571
572 #ifdef CONFIG_MX6SX
573 /*
574 * Set enet ahb clock to 200MHz
575 * pll2_pfd2_396m-> ENET_PODF-> ENET_AHB
576 */
577 reg = readl(&imx_ccm->chsccdr);
578 reg &= ~(MXC_CCM_CHSCCDR_ENET_PRE_CLK_SEL_MASK
579 | MXC_CCM_CHSCCDR_ENET_PODF_MASK
580 | MXC_CCM_CHSCCDR_ENET_CLK_SEL_MASK);
581 /* PLL2 PFD2 */
582 reg |= (4 << MXC_CCM_CHSCCDR_ENET_PRE_CLK_SEL_OFFSET);
583 /* Div = 2*/
584 reg |= (1 << MXC_CCM_CHSCCDR_ENET_PODF_OFFSET);
585 reg |= (0 << MXC_CCM_CHSCCDR_ENET_CLK_SEL_OFFSET);
586 writel(reg, &imx_ccm->chsccdr);
587
588 /* Enable enet system clock */
589 reg = readl(&imx_ccm->CCGR3);
590 reg |= MXC_CCM_CCGR3_ENET_MASK;
591 writel(reg, &imx_ccm->CCGR3);
592 #endif
593 return 0;
594 }
595 #endif
596
597 static u32 get_usdhc_clk(u32 port)
598 {
599 u32 root_freq = 0, usdhc_podf = 0, clk_sel = 0;
600 u32 cscmr1 = __raw_readl(&imx_ccm->cscmr1);
601 u32 cscdr1 = __raw_readl(&imx_ccm->cscdr1);
602
603 switch (port) {
604 case 0:
605 usdhc_podf = (cscdr1 & MXC_CCM_CSCDR1_USDHC1_PODF_MASK) >>
606 MXC_CCM_CSCDR1_USDHC1_PODF_OFFSET;
607 clk_sel = cscmr1 & MXC_CCM_CSCMR1_USDHC1_CLK_SEL;
608
609 break;
610 case 1:
611 usdhc_podf = (cscdr1 & MXC_CCM_CSCDR1_USDHC2_PODF_MASK) >>
612 MXC_CCM_CSCDR1_USDHC2_PODF_OFFSET;
613 clk_sel = cscmr1 & MXC_CCM_CSCMR1_USDHC2_CLK_SEL;
614
615 break;
616 case 2:
617 usdhc_podf = (cscdr1 & MXC_CCM_CSCDR1_USDHC3_PODF_MASK) >>
618 MXC_CCM_CSCDR1_USDHC3_PODF_OFFSET;
619 clk_sel = cscmr1 & MXC_CCM_CSCMR1_USDHC3_CLK_SEL;
620
621 break;
622 case 3:
623 usdhc_podf = (cscdr1 & MXC_CCM_CSCDR1_USDHC4_PODF_MASK) >>
624 MXC_CCM_CSCDR1_USDHC4_PODF_OFFSET;
625 clk_sel = cscmr1 & MXC_CCM_CSCMR1_USDHC4_CLK_SEL;
626
627 break;
628 default:
629 break;
630 }
631
632 if (clk_sel)
633 root_freq = mxc_get_pll_pfd(PLL_BUS, 0);
634 else
635 root_freq = mxc_get_pll_pfd(PLL_BUS, 2);
636
637 return root_freq / (usdhc_podf + 1);
638 }
639
640 u32 imx_get_uartclk(void)
641 {
642 return get_uart_clk();
643 }
644
645 u32 imx_get_fecclk(void)
646 {
647 return mxc_get_clock(MXC_IPG_CLK);
648 }
649
650 #if defined(CONFIG_CMD_SATA) || defined(CONFIG_PCIE_IMX)
651 static int enable_enet_pll(uint32_t en)
652 {
653 struct mxc_ccm_reg *const imx_ccm
654 = (struct mxc_ccm_reg *) CCM_BASE_ADDR;
655 s32 timeout = 100000;
656 u32 reg = 0;
657
658 /* Enable PLLs */
659 reg = readl(&imx_ccm->analog_pll_enet);
660 reg &= ~BM_ANADIG_PLL_SYS_POWERDOWN;
661 writel(reg, &imx_ccm->analog_pll_enet);
662 reg |= BM_ANADIG_PLL_SYS_ENABLE;
663 while (timeout--) {
664 if (readl(&imx_ccm->analog_pll_enet) & BM_ANADIG_PLL_SYS_LOCK)
665 break;
666 }
667 if (timeout <= 0)
668 return -EIO;
669 reg &= ~BM_ANADIG_PLL_SYS_BYPASS;
670 writel(reg, &imx_ccm->analog_pll_enet);
671 reg |= en;
672 writel(reg, &imx_ccm->analog_pll_enet);
673 return 0;
674 }
675 #endif
676
677 #ifdef CONFIG_CMD_SATA
678 static void ungate_sata_clock(void)
679 {
680 struct mxc_ccm_reg *const imx_ccm =
681 (struct mxc_ccm_reg *)CCM_BASE_ADDR;
682
683 /* Enable SATA clock. */
684 setbits_le32(&imx_ccm->CCGR5, MXC_CCM_CCGR5_SATA_MASK);
685 }
686
687 int enable_sata_clock(void)
688 {
689 ungate_sata_clock();
690 return enable_enet_pll(BM_ANADIG_PLL_ENET_ENABLE_SATA);
691 }
692
693 void disable_sata_clock(void)
694 {
695 struct mxc_ccm_reg *const imx_ccm =
696 (struct mxc_ccm_reg *)CCM_BASE_ADDR;
697
698 clrbits_le32(&imx_ccm->CCGR5, MXC_CCM_CCGR5_SATA_MASK);
699 }
700 #endif
701
702 #ifdef CONFIG_PCIE_IMX
703 static void ungate_pcie_clock(void)
704 {
705 struct mxc_ccm_reg *const imx_ccm =
706 (struct mxc_ccm_reg *)CCM_BASE_ADDR;
707
708 /* Enable PCIe clock. */
709 setbits_le32(&imx_ccm->CCGR4, MXC_CCM_CCGR4_PCIE_MASK);
710 }
711
712 int enable_pcie_clock(void)
713 {
714 struct anatop_regs *anatop_regs =
715 (struct anatop_regs *)ANATOP_BASE_ADDR;
716 struct mxc_ccm_reg *ccm_regs = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
717 u32 lvds1_clk_sel;
718
719 /*
720 * Here be dragons!
721 *
722 * The register ANATOP_MISC1 is not documented in the Freescale
723 * MX6RM. The register that is mapped in the ANATOP space and
724 * marked as ANATOP_MISC1 is actually documented in the PMU section
725 * of the datasheet as PMU_MISC1.
726 *
727 * Switch LVDS clock source to SATA (0xb) on mx6q/dl or PCI (0xa) on
728 * mx6sx, disable clock INPUT and enable clock OUTPUT. This is important
729 * for PCI express link that is clocked from the i.MX6.
730 */
731 #define ANADIG_ANA_MISC1_LVDSCLK1_IBEN (1 << 12)
732 #define ANADIG_ANA_MISC1_LVDSCLK1_OBEN (1 << 10)
733 #define ANADIG_ANA_MISC1_LVDS1_CLK_SEL_MASK 0x0000001F
734 #define ANADIG_ANA_MISC1_LVDS1_CLK_SEL_PCIE_REF 0xa
735 #define ANADIG_ANA_MISC1_LVDS1_CLK_SEL_SATA_REF 0xb
736
737 if (is_cpu_type(MXC_CPU_MX6SX))
738 lvds1_clk_sel = ANADIG_ANA_MISC1_LVDS1_CLK_SEL_PCIE_REF;
739 else
740 lvds1_clk_sel = ANADIG_ANA_MISC1_LVDS1_CLK_SEL_SATA_REF;
741
742 clrsetbits_le32(&anatop_regs->ana_misc1,
743 ANADIG_ANA_MISC1_LVDSCLK1_IBEN |
744 ANADIG_ANA_MISC1_LVDS1_CLK_SEL_MASK,
745 ANADIG_ANA_MISC1_LVDSCLK1_OBEN | lvds1_clk_sel);
746
747 /* PCIe reference clock sourced from AXI. */
748 clrbits_le32(&ccm_regs->cbcmr, MXC_CCM_CBCMR_PCIE_AXI_CLK_SEL);
749
750 /* Party time! Ungate the clock to the PCIe. */
751 #ifdef CONFIG_CMD_SATA
752 ungate_sata_clock();
753 #endif
754 ungate_pcie_clock();
755
756 return enable_enet_pll(BM_ANADIG_PLL_ENET_ENABLE_SATA |
757 BM_ANADIG_PLL_ENET_ENABLE_PCIE);
758 }
759 #endif
760
761 #ifdef CONFIG_SECURE_BOOT
762 void hab_caam_clock_enable(unsigned char enable)
763 {
764 u32 reg;
765
766 /* CG4 ~ CG6, CAAM clocks */
767 reg = __raw_readl(&imx_ccm->CCGR0);
768 if (enable)
769 reg |= (MXC_CCM_CCGR0_CAAM_WRAPPER_IPG_MASK |
770 MXC_CCM_CCGR0_CAAM_WRAPPER_ACLK_MASK |
771 MXC_CCM_CCGR0_CAAM_SECURE_MEM_MASK);
772 else
773 reg &= ~(MXC_CCM_CCGR0_CAAM_WRAPPER_IPG_MASK |
774 MXC_CCM_CCGR0_CAAM_WRAPPER_ACLK_MASK |
775 MXC_CCM_CCGR0_CAAM_SECURE_MEM_MASK);
776 __raw_writel(reg, &imx_ccm->CCGR0);
777
778 /* EMI slow clk */
779 reg = __raw_readl(&imx_ccm->CCGR6);
780 if (enable)
781 reg |= MXC_CCM_CCGR6_EMI_SLOW_MASK;
782 else
783 reg &= ~MXC_CCM_CCGR6_EMI_SLOW_MASK;
784 __raw_writel(reg, &imx_ccm->CCGR6);
785 }
786 #endif
787
788 static void enable_pll3(void)
789 {
790 struct anatop_regs __iomem *anatop =
791 (struct anatop_regs __iomem *)ANATOP_BASE_ADDR;
792
793 /* make sure pll3 is enabled */
794 if ((readl(&anatop->usb1_pll_480_ctrl) &
795 BM_ANADIG_USB1_PLL_480_CTRL_LOCK) == 0) {
796 /* enable pll's power */
797 writel(BM_ANADIG_USB1_PLL_480_CTRL_POWER,
798 &anatop->usb1_pll_480_ctrl_set);
799 writel(0x80, &anatop->ana_misc2_clr);
800 /* wait for pll lock */
801 while ((readl(&anatop->usb1_pll_480_ctrl) &
802 BM_ANADIG_USB1_PLL_480_CTRL_LOCK) == 0)
803 ;
804 /* disable bypass */
805 writel(BM_ANADIG_USB1_PLL_480_CTRL_BYPASS,
806 &anatop->usb1_pll_480_ctrl_clr);
807 /* enable pll output */
808 writel(BM_ANADIG_USB1_PLL_480_CTRL_ENABLE,
809 &anatop->usb1_pll_480_ctrl_set);
810 }
811 }
812
813 void enable_thermal_clk(void)
814 {
815 enable_pll3();
816 }
817
818 unsigned int mxc_get_clock(enum mxc_clock clk)
819 {
820 switch (clk) {
821 case MXC_ARM_CLK:
822 return get_mcu_main_clk();
823 case MXC_PER_CLK:
824 return get_periph_clk();
825 case MXC_AHB_CLK:
826 return get_ahb_clk();
827 case MXC_IPG_CLK:
828 return get_ipg_clk();
829 case MXC_IPG_PERCLK:
830 case MXC_I2C_CLK:
831 return get_ipg_per_clk();
832 case MXC_UART_CLK:
833 return get_uart_clk();
834 case MXC_CSPI_CLK:
835 return get_cspi_clk();
836 case MXC_AXI_CLK:
837 return get_axi_clk();
838 case MXC_EMI_SLOW_CLK:
839 return get_emi_slow_clk();
840 case MXC_DDR_CLK:
841 return get_mmdc_ch0_clk();
842 case MXC_ESDHC_CLK:
843 return get_usdhc_clk(0);
844 case MXC_ESDHC2_CLK:
845 return get_usdhc_clk(1);
846 case MXC_ESDHC3_CLK:
847 return get_usdhc_clk(2);
848 case MXC_ESDHC4_CLK:
849 return get_usdhc_clk(3);
850 case MXC_SATA_CLK:
851 return get_ahb_clk();
852 default:
853 printf("Unsupported MXC CLK: %d\n", clk);
854 break;
855 }
856
857 return 0;
858 }
859
860 /*
861 * Dump some core clockes.
862 */
863 int do_mx6_showclocks(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
864 {
865 u32 freq;
866 freq = decode_pll(PLL_SYS, MXC_HCLK);
867 printf("PLL_SYS %8d MHz\n", freq / 1000000);
868 freq = decode_pll(PLL_BUS, MXC_HCLK);
869 printf("PLL_BUS %8d MHz\n", freq / 1000000);
870 freq = decode_pll(PLL_USBOTG, MXC_HCLK);
871 printf("PLL_OTG %8d MHz\n", freq / 1000000);
872 freq = decode_pll(PLL_ENET, MXC_HCLK);
873 printf("PLL_NET %8d MHz\n", freq / 1000000);
874
875 printf("\n");
876 printf("IPG %8d kHz\n", mxc_get_clock(MXC_IPG_CLK) / 1000);
877 printf("UART %8d kHz\n", mxc_get_clock(MXC_UART_CLK) / 1000);
878 #ifdef CONFIG_MXC_SPI
879 printf("CSPI %8d kHz\n", mxc_get_clock(MXC_CSPI_CLK) / 1000);
880 #endif
881 printf("AHB %8d kHz\n", mxc_get_clock(MXC_AHB_CLK) / 1000);
882 printf("AXI %8d kHz\n", mxc_get_clock(MXC_AXI_CLK) / 1000);
883 printf("DDR %8d kHz\n", mxc_get_clock(MXC_DDR_CLK) / 1000);
884 printf("USDHC1 %8d kHz\n", mxc_get_clock(MXC_ESDHC_CLK) / 1000);
885 printf("USDHC2 %8d kHz\n", mxc_get_clock(MXC_ESDHC2_CLK) / 1000);
886 printf("USDHC3 %8d kHz\n", mxc_get_clock(MXC_ESDHC3_CLK) / 1000);
887 printf("USDHC4 %8d kHz\n", mxc_get_clock(MXC_ESDHC4_CLK) / 1000);
888 printf("EMI SLOW %8d kHz\n", mxc_get_clock(MXC_EMI_SLOW_CLK) / 1000);
889 printf("IPG PERCLK %8d kHz\n", mxc_get_clock(MXC_IPG_PERCLK) / 1000);
890
891 return 0;
892 }
893
894 #ifndef CONFIG_MX6SX
895 void enable_ipu_clock(void)
896 {
897 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
898 int reg;
899 reg = readl(&mxc_ccm->CCGR3);
900 reg |= MXC_CCM_CCGR3_IPU1_IPU_MASK;
901 writel(reg, &mxc_ccm->CCGR3);
902
903 if (is_mx6dqp()) {
904 setbits_le32(&mxc_ccm->CCGR6, MXC_CCM_CCGR6_PRG_CLK0_MASK);
905 setbits_le32(&mxc_ccm->CCGR3, MXC_CCM_CCGR3_IPU2_IPU_MASK);
906 }
907 }
908 #endif
909 /***************************************************/
910
911 U_BOOT_CMD(
912 clocks, CONFIG_SYS_MAXARGS, 1, do_mx6_showclocks,
913 "display clocks",
914 ""
915 );
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