2 * Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
4 * SPDX-License-Identifier: GPL-2.0+
10 #include <asm/errno.h>
11 #include <asm/arch/imx-regs.h>
12 #include <asm/arch/crm_regs.h>
13 #include <asm/arch/clock.h>
14 #include <asm/arch/sys_proto.h>
17 PLL_SYS
, /* System PLL */
18 PLL_BUS
, /* System Bus PLL*/
19 PLL_USBOTG
, /* OTG USB PLL */
20 PLL_ENET
, /* ENET PLL */
21 PLL_AUDIO
, /* AUDIO PLL */
22 PLL_VIDEO
, /* AUDIO PLL */
25 struct mxc_ccm_reg
*imx_ccm
= (struct mxc_ccm_reg
*)CCM_BASE_ADDR
;
27 #ifdef CONFIG_MXC_OCOTP
28 void enable_ocotp_clk(unsigned char enable
)
32 reg
= __raw_readl(&imx_ccm
->CCGR2
);
34 reg
|= MXC_CCM_CCGR2_OCOTP_CTRL_MASK
;
36 reg
&= ~MXC_CCM_CCGR2_OCOTP_CTRL_MASK
;
37 __raw_writel(reg
, &imx_ccm
->CCGR2
);
41 #ifdef CONFIG_NAND_MXS
42 void setup_gpmi_io_clk(u32 cfg
)
44 /* Disable clocks per ERR007177 from MX6 errata */
45 clrbits_le32(&imx_ccm
->CCGR4
,
46 MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK
|
47 MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK
|
48 MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK
|
49 MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK
|
50 MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_MASK
);
52 #if defined(CONFIG_MX6SX)
53 clrbits_le32(&imx_ccm
->CCGR4
, MXC_CCM_CCGR4_QSPI2_ENFC_MASK
);
55 clrsetbits_le32(&imx_ccm
->cs2cdr
,
56 MXC_CCM_CS2CDR_QSPI2_CLK_PODF_MASK
|
57 MXC_CCM_CS2CDR_QSPI2_CLK_PRED_MASK
|
58 MXC_CCM_CS2CDR_QSPI2_CLK_SEL_MASK
,
61 setbits_le32(&imx_ccm
->CCGR4
, MXC_CCM_CCGR4_QSPI2_ENFC_MASK
);
63 clrbits_le32(&imx_ccm
->CCGR2
, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK
);
65 clrsetbits_le32(&imx_ccm
->cs2cdr
,
66 MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK
|
67 MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK
|
68 MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK
,
71 setbits_le32(&imx_ccm
->CCGR2
, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK
);
73 setbits_le32(&imx_ccm
->CCGR4
,
74 MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK
|
75 MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK
|
76 MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK
|
77 MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK
|
78 MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_MASK
);
82 void enable_usboh3_clk(unsigned char enable
)
86 reg
= __raw_readl(&imx_ccm
->CCGR6
);
88 reg
|= MXC_CCM_CCGR6_USBOH3_MASK
;
90 reg
&= ~(MXC_CCM_CCGR6_USBOH3_MASK
);
91 __raw_writel(reg
, &imx_ccm
->CCGR6
);
95 #if defined(CONFIG_FEC_MXC) && !defined(CONFIG_MX6SX)
96 void enable_enet_clk(unsigned char enable
)
100 if (is_cpu_type(MXC_CPU_MX6UL
)) {
101 mask
= MXC_CCM_CCGR3_ENET_MASK
;
102 addr
= &imx_ccm
->CCGR3
;
104 mask
= MXC_CCM_CCGR1_ENET_MASK
;
105 addr
= &imx_ccm
->CCGR1
;
109 setbits_le32(addr
, mask
);
111 clrbits_le32(addr
, mask
);
115 #ifdef CONFIG_MXC_UART
116 void enable_uart_clk(unsigned char enable
)
120 if (is_cpu_type(MXC_CPU_MX6UL
))
121 mask
= MXC_CCM_CCGR5_UART_MASK
;
123 mask
= MXC_CCM_CCGR5_UART_MASK
| MXC_CCM_CCGR5_UART_SERIAL_MASK
;
126 setbits_le32(&imx_ccm
->CCGR5
, mask
);
128 clrbits_le32(&imx_ccm
->CCGR5
, mask
);
133 int enable_usdhc_clk(unsigned char enable
, unsigned bus_num
)
140 mask
= MXC_CCM_CCGR_CG_MASK
<< (bus_num
* 2 + 2);
142 setbits_le32(&imx_ccm
->CCGR6
, mask
);
144 clrbits_le32(&imx_ccm
->CCGR6
, mask
);
150 #ifdef CONFIG_SYS_I2C_MXC
151 /* i2c_num can be from 0 - 3 */
152 int enable_i2c_clk(unsigned char enable
, unsigned i2c_num
)
161 mask
= MXC_CCM_CCGR_CG_MASK
162 << (MXC_CCM_CCGR2_I2C1_SERIAL_OFFSET
164 reg
= __raw_readl(&imx_ccm
->CCGR2
);
169 __raw_writel(reg
, &imx_ccm
->CCGR2
);
171 if (is_cpu_type(MXC_CPU_MX6SX
) || is_cpu_type(MXC_CPU_MX6UL
)) {
172 mask
= MXC_CCM_CCGR6_I2C4_MASK
;
173 addr
= &imx_ccm
->CCGR6
;
175 mask
= MXC_CCM_CCGR1_I2C4_SERIAL_MASK
;
176 addr
= &imx_ccm
->CCGR1
;
178 reg
= __raw_readl(addr
);
183 __raw_writel(reg
, addr
);
189 /* spi_num can be from 0 - SPI_MAX_NUM */
190 int enable_spi_clk(unsigned char enable
, unsigned spi_num
)
195 if (spi_num
> SPI_MAX_NUM
)
198 mask
= MXC_CCM_CCGR_CG_MASK
<< (spi_num
<< 1);
199 reg
= __raw_readl(&imx_ccm
->CCGR1
);
204 __raw_writel(reg
, &imx_ccm
->CCGR1
);
207 static u32
decode_pll(enum pll_clocks pll
, u32 infreq
)
209 u32 div
, test_div
, pll_num
, pll_denom
;
213 div
= __raw_readl(&imx_ccm
->analog_pll_sys
);
214 div
&= BM_ANADIG_PLL_SYS_DIV_SELECT
;
216 return (infreq
* div
) >> 1;
218 div
= __raw_readl(&imx_ccm
->analog_pll_528
);
219 div
&= BM_ANADIG_PLL_528_DIV_SELECT
;
221 return infreq
* (20 + (div
<< 1));
223 div
= __raw_readl(&imx_ccm
->analog_usb1_pll_480_ctrl
);
224 div
&= BM_ANADIG_USB1_PLL_480_CTRL_DIV_SELECT
;
226 return infreq
* (20 + (div
<< 1));
228 div
= __raw_readl(&imx_ccm
->analog_pll_enet
);
229 div
&= BM_ANADIG_PLL_ENET_DIV_SELECT
;
231 return 25000000 * (div
+ (div
>> 1) + 1);
233 div
= __raw_readl(&imx_ccm
->analog_pll_audio
);
234 if (!(div
& BM_ANADIG_PLL_AUDIO_ENABLE
))
236 /* BM_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC is ignored */
237 if (div
& BM_ANADIG_PLL_AUDIO_BYPASS
)
239 pll_num
= __raw_readl(&imx_ccm
->analog_pll_audio_num
);
240 pll_denom
= __raw_readl(&imx_ccm
->analog_pll_audio_denom
);
241 test_div
= (div
& BM_ANADIG_PLL_AUDIO_TEST_DIV_SELECT
) >>
242 BP_ANADIG_PLL_AUDIO_TEST_DIV_SELECT
;
243 div
&= BM_ANADIG_PLL_AUDIO_DIV_SELECT
;
245 debug("Error test_div\n");
248 test_div
= 1 << (2 - test_div
);
250 return infreq
* (div
+ pll_num
/ pll_denom
) / test_div
;
252 div
= __raw_readl(&imx_ccm
->analog_pll_video
);
253 if (!(div
& BM_ANADIG_PLL_VIDEO_ENABLE
))
255 /* BM_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC is ignored */
256 if (div
& BM_ANADIG_PLL_VIDEO_BYPASS
)
258 pll_num
= __raw_readl(&imx_ccm
->analog_pll_video_num
);
259 pll_denom
= __raw_readl(&imx_ccm
->analog_pll_video_denom
);
260 test_div
= (div
& BM_ANADIG_PLL_VIDEO_POST_DIV_SELECT
) >>
261 BP_ANADIG_PLL_VIDEO_POST_DIV_SELECT
;
262 div
&= BM_ANADIG_PLL_VIDEO_DIV_SELECT
;
264 debug("Error test_div\n");
267 test_div
= 1 << (2 - test_div
);
269 return infreq
* (div
+ pll_num
/ pll_denom
) / test_div
;
275 static u32
mxc_get_pll_pfd(enum pll_clocks pll
, int pfd_num
)
282 if (!is_cpu_type(MXC_CPU_MX6UL
)) {
284 /* No PFD3 on PPL2 */
288 div
= __raw_readl(&imx_ccm
->analog_pfd_528
);
289 freq
= (u64
)decode_pll(PLL_BUS
, MXC_HCLK
);
292 div
= __raw_readl(&imx_ccm
->analog_pfd_480
);
293 freq
= (u64
)decode_pll(PLL_USBOTG
, MXC_HCLK
);
296 /* No PFD on other PLL */
300 return lldiv(freq
* 18, (div
& ANATOP_PFD_FRAC_MASK(pfd_num
)) >>
301 ANATOP_PFD_FRAC_SHIFT(pfd_num
));
304 static u32
get_mcu_main_clk(void)
308 reg
= __raw_readl(&imx_ccm
->cacrr
);
309 reg
&= MXC_CCM_CACRR_ARM_PODF_MASK
;
310 reg
>>= MXC_CCM_CACRR_ARM_PODF_OFFSET
;
311 freq
= decode_pll(PLL_SYS
, MXC_HCLK
);
313 return freq
/ (reg
+ 1);
316 u32
get_periph_clk(void)
318 u32 reg
, div
= 0, freq
= 0;
320 reg
= __raw_readl(&imx_ccm
->cbcdr
);
321 if (reg
& MXC_CCM_CBCDR_PERIPH_CLK_SEL
) {
322 div
= (reg
& MXC_CCM_CBCDR_PERIPH_CLK2_PODF_MASK
) >>
323 MXC_CCM_CBCDR_PERIPH_CLK2_PODF_OFFSET
;
324 reg
= __raw_readl(&imx_ccm
->cbcmr
);
325 reg
&= MXC_CCM_CBCMR_PERIPH_CLK2_SEL_MASK
;
326 reg
>>= MXC_CCM_CBCMR_PERIPH_CLK2_SEL_OFFSET
;
330 freq
= decode_pll(PLL_USBOTG
, MXC_HCLK
);
340 reg
= __raw_readl(&imx_ccm
->cbcmr
);
341 reg
&= MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK
;
342 reg
>>= MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_OFFSET
;
346 freq
= decode_pll(PLL_BUS
, MXC_HCLK
);
349 freq
= mxc_get_pll_pfd(PLL_BUS
, 2);
352 freq
= mxc_get_pll_pfd(PLL_BUS
, 0);
355 /* static / 2 divider */
356 freq
= mxc_get_pll_pfd(PLL_BUS
, 2) / 2;
363 return freq
/ (div
+ 1);
366 static u32
get_ipg_clk(void)
370 reg
= __raw_readl(&imx_ccm
->cbcdr
);
371 reg
&= MXC_CCM_CBCDR_IPG_PODF_MASK
;
372 ipg_podf
= reg
>> MXC_CCM_CBCDR_IPG_PODF_OFFSET
;
374 return get_ahb_clk() / (ipg_podf
+ 1);
377 static u32
get_ipg_per_clk(void)
379 u32 reg
, perclk_podf
;
381 reg
= __raw_readl(&imx_ccm
->cscmr1
);
382 if (is_cpu_type(MXC_CPU_MX6SL
) || is_cpu_type(MXC_CPU_MX6SX
) ||
383 is_mx6dqp() || is_cpu_type(MXC_CPU_MX6UL
)) {
384 if (reg
& MXC_CCM_CSCMR1_PER_CLK_SEL_MASK
)
385 return MXC_HCLK
; /* OSC 24Mhz */
388 perclk_podf
= reg
& MXC_CCM_CSCMR1_PERCLK_PODF_MASK
;
390 return get_ipg_clk() / (perclk_podf
+ 1);
393 static u32
get_uart_clk(void)
396 u32 freq
= decode_pll(PLL_USBOTG
, MXC_HCLK
) / 6; /* static divider */
397 reg
= __raw_readl(&imx_ccm
->cscdr1
);
399 if (is_cpu_type(MXC_CPU_MX6SL
) || is_cpu_type(MXC_CPU_MX6SX
) ||
400 is_mx6dqp() || is_cpu_type(MXC_CPU_MX6UL
)) {
401 if (reg
& MXC_CCM_CSCDR1_UART_CLK_SEL
)
405 reg
&= MXC_CCM_CSCDR1_UART_CLK_PODF_MASK
;
406 uart_podf
= reg
>> MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET
;
408 return freq
/ (uart_podf
+ 1);
411 static u32
get_cspi_clk(void)
415 reg
= __raw_readl(&imx_ccm
->cscdr2
);
416 cspi_podf
= (reg
& MXC_CCM_CSCDR2_ECSPI_CLK_PODF_MASK
) >>
417 MXC_CCM_CSCDR2_ECSPI_CLK_PODF_OFFSET
;
419 if (is_mx6dqp() || is_cpu_type(MXC_CPU_MX6SL
) ||
420 is_cpu_type(MXC_CPU_MX6SX
) || is_cpu_type(MXC_CPU_MX6UL
)) {
421 if (reg
& MXC_CCM_CSCDR2_ECSPI_CLK_SEL_MASK
)
422 return MXC_HCLK
/ (cspi_podf
+ 1);
425 return decode_pll(PLL_USBOTG
, MXC_HCLK
) / (8 * (cspi_podf
+ 1));
428 static u32
get_axi_clk(void)
430 u32 root_freq
, axi_podf
;
431 u32 cbcdr
= __raw_readl(&imx_ccm
->cbcdr
);
433 axi_podf
= cbcdr
& MXC_CCM_CBCDR_AXI_PODF_MASK
;
434 axi_podf
>>= MXC_CCM_CBCDR_AXI_PODF_OFFSET
;
436 if (cbcdr
& MXC_CCM_CBCDR_AXI_SEL
) {
437 if (cbcdr
& MXC_CCM_CBCDR_AXI_ALT_SEL
)
438 root_freq
= mxc_get_pll_pfd(PLL_BUS
, 2);
440 root_freq
= mxc_get_pll_pfd(PLL_USBOTG
, 1);
442 root_freq
= get_periph_clk();
444 return root_freq
/ (axi_podf
+ 1);
447 static u32
get_emi_slow_clk(void)
449 u32 emi_clk_sel
, emi_slow_podf
, cscmr1
, root_freq
= 0;
451 cscmr1
= __raw_readl(&imx_ccm
->cscmr1
);
452 emi_clk_sel
= cscmr1
& MXC_CCM_CSCMR1_ACLK_EMI_SLOW_MASK
;
453 emi_clk_sel
>>= MXC_CCM_CSCMR1_ACLK_EMI_SLOW_OFFSET
;
454 emi_slow_podf
= cscmr1
& MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_MASK
;
455 emi_slow_podf
>>= MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_OFFSET
;
457 switch (emi_clk_sel
) {
459 root_freq
= get_axi_clk();
462 root_freq
= decode_pll(PLL_USBOTG
, MXC_HCLK
);
465 root_freq
= mxc_get_pll_pfd(PLL_BUS
, 2);
468 root_freq
= mxc_get_pll_pfd(PLL_BUS
, 0);
472 return root_freq
/ (emi_slow_podf
+ 1);
475 static u32
get_mmdc_ch0_clk(void)
477 u32 cbcmr
= __raw_readl(&imx_ccm
->cbcmr
);
478 u32 cbcdr
= __raw_readl(&imx_ccm
->cbcdr
);
480 u32 freq
, podf
, per2_clk2_podf
, pmu_misc2_audio_div
;
482 if (is_cpu_type(MXC_CPU_MX6SX
) || is_cpu_type(MXC_CPU_MX6UL
) ||
483 is_cpu_type(MXC_CPU_MX6SL
)) {
484 podf
= (cbcdr
& MXC_CCM_CBCDR_MMDC_CH1_PODF_MASK
) >>
485 MXC_CCM_CBCDR_MMDC_CH1_PODF_OFFSET
;
486 if (cbcdr
& MXC_CCM_CBCDR_PERIPH2_CLK_SEL
) {
487 per2_clk2_podf
= (cbcdr
& MXC_CCM_CBCDR_PERIPH2_CLK2_PODF_MASK
) >>
488 MXC_CCM_CBCDR_PERIPH2_CLK2_PODF_OFFSET
;
489 if (is_cpu_type(MXC_CPU_MX6SL
)) {
490 if (cbcmr
& MXC_CCM_CBCMR_PERIPH2_CLK2_SEL
)
493 freq
= decode_pll(PLL_USBOTG
, MXC_HCLK
);
495 if (cbcmr
& MXC_CCM_CBCMR_PERIPH2_CLK2_SEL
)
496 freq
= decode_pll(PLL_BUS
, MXC_HCLK
);
498 freq
= decode_pll(PLL_USBOTG
, MXC_HCLK
);
503 MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_MASK
) >>
504 MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_OFFSET
) {
506 freq
= decode_pll(PLL_BUS
, MXC_HCLK
);
509 freq
= mxc_get_pll_pfd(PLL_BUS
, 2);
512 freq
= mxc_get_pll_pfd(PLL_BUS
, 0);
515 pmu_misc2_audio_div
= PMU_MISC2_AUDIO_DIV(__raw_readl(&imx_ccm
->pmu_misc2
));
516 switch (pmu_misc2_audio_div
) {
519 pmu_misc2_audio_div
= 1;
522 pmu_misc2_audio_div
= 2;
525 pmu_misc2_audio_div
= 4;
528 freq
= decode_pll(PLL_AUDIO
, MXC_HCLK
) /
533 return freq
/ (podf
+ 1) / (per2_clk2_podf
+ 1);
535 podf
= (cbcdr
& MXC_CCM_CBCDR_MMDC_CH0_PODF_MASK
) >>
536 MXC_CCM_CBCDR_MMDC_CH0_PODF_OFFSET
;
537 return get_periph_clk() / (podf
+ 1);
541 #if defined(CONFIG_VIDEO_MXS)
542 static int enable_pll_video(u32 pll_div
, u32 pll_num
, u32 pll_denom
,
548 debug("pll5 div = %d, num = %d, denom = %d\n",
549 pll_div
, pll_num
, pll_denom
);
551 /* Power up PLL5 video */
552 writel(BM_ANADIG_PLL_VIDEO_POWERDOWN
|
553 BM_ANADIG_PLL_VIDEO_BYPASS
|
554 BM_ANADIG_PLL_VIDEO_DIV_SELECT
|
555 BM_ANADIG_PLL_VIDEO_POST_DIV_SELECT
,
556 &imx_ccm
->analog_pll_video_clr
);
558 /* Set div, num and denom */
561 writel(BF_ANADIG_PLL_VIDEO_DIV_SELECT(pll_div
) |
562 BF_ANADIG_PLL_VIDEO_POST_DIV_SELECT(0x2),
563 &imx_ccm
->analog_pll_video_set
);
566 writel(BF_ANADIG_PLL_VIDEO_DIV_SELECT(pll_div
) |
567 BF_ANADIG_PLL_VIDEO_POST_DIV_SELECT(0x1),
568 &imx_ccm
->analog_pll_video_set
);
571 writel(BF_ANADIG_PLL_VIDEO_DIV_SELECT(pll_div
) |
572 BF_ANADIG_PLL_VIDEO_POST_DIV_SELECT(0x0),
573 &imx_ccm
->analog_pll_video_set
);
576 puts("Wrong test_div!\n");
580 writel(BF_ANADIG_PLL_VIDEO_NUM_A(pll_num
),
581 &imx_ccm
->analog_pll_video_num
);
582 writel(BF_ANADIG_PLL_VIDEO_DENOM_B(pll_denom
),
583 &imx_ccm
->analog_pll_video_denom
);
586 start
= get_timer(0); /* Get current timestamp */
589 reg
= readl(&imx_ccm
->analog_pll_video
);
590 if (reg
& BM_ANADIG_PLL_VIDEO_LOCK
) {
592 writel(BM_ANADIG_PLL_VIDEO_ENABLE
,
593 &imx_ccm
->analog_pll_video_set
);
596 } while (get_timer(0) < (start
+ 10)); /* Wait 10ms */
598 puts("Lock PLL5 timeout\n");
604 * 24M--> PLL_VIDEO -> LCDIFx_PRED -> LCDIFx_PODF -> LCD
606 * 'freq' using KHz as unit, see driver/video/mxsfb.c.
608 void mxs_set_lcdclk(u32 base_addr
, u32 freq
)
611 u32 hck
= MXC_HCLK
/ 1000;
612 /* DIV_SELECT ranges from 27 to 54 */
616 u32 i
, j
, max_pred
= 8, max_postd
= 8, pred
= 1, postd
= 1;
617 u32 pll_div
, pll_num
, pll_denom
, post_div
= 1;
619 debug("mxs_set_lcdclk, freq = %dKHz\n", freq
);
621 if ((!is_cpu_type(MXC_CPU_MX6SX
)) && !is_cpu_type(MXC_CPU_MX6UL
)) {
622 debug("This chip not support lcd!\n");
626 if (base_addr
== LCDIF1_BASE_ADDR
) {
627 reg
= readl(&imx_ccm
->cscdr2
);
628 /* Can't change clocks when clock not from pre-mux */
629 if ((reg
& MXC_CCM_CSCDR2_LCDIF1_CLK_SEL_MASK
) != 0)
633 if (is_cpu_type(MXC_CPU_MX6SX
)) {
634 reg
= readl(&imx_ccm
->cscdr2
);
635 /* Can't change clocks when clock not from pre-mux */
636 if ((reg
& MXC_CCM_CSCDR2_LCDIF2_CLK_SEL_MASK
) != 0)
640 temp
= freq
* max_pred
* max_postd
;
643 * Register: PLL_VIDEO
644 * Bit Field: POST_DIV_SELECT
645 * 00 — Divide by 4.
646 * 01 — Divide by 2.
647 * 10 — Divide by 1.
649 * No need to check post_div(1)
651 for (post_div
= 2; post_div
<= 4; post_div
<<= 1) {
652 if ((temp
* post_div
) > min
) {
659 printf("Fail to set rate to %dkhz", freq
);
664 /* Choose the best pred and postd to match freq for lcd */
665 for (i
= 1; i
<= max_pred
; i
++) {
666 for (j
= 1; j
<= max_postd
; j
++) {
668 if (temp
> max
|| temp
< min
)
670 if (best
== 0 || temp
< best
) {
679 printf("Fail to set rate to %dKHz", freq
);
683 debug("best %d, pred = %d, postd = %d\n", best
, pred
, postd
);
685 pll_div
= best
/ hck
;
687 pll_num
= (best
- hck
* pll_div
) * pll_denom
/ hck
;
691 * (24MHz * (pll_div + --------- ))
693 *freq KHz = --------------------------------
694 * post_div * pred * postd * 1000
697 if (base_addr
== LCDIF1_BASE_ADDR
) {
698 if (enable_pll_video(pll_div
, pll_num
, pll_denom
, post_div
))
701 /* Select pre-lcd clock to PLL5 and set pre divider */
702 clrsetbits_le32(&imx_ccm
->cscdr2
,
703 MXC_CCM_CSCDR2_LCDIF1_PRED_SEL_MASK
|
704 MXC_CCM_CSCDR2_LCDIF1_PRE_DIV_MASK
,
705 (0x2 << MXC_CCM_CSCDR2_LCDIF1_PRED_SEL_OFFSET
) |
707 MXC_CCM_CSCDR2_LCDIF1_PRE_DIV_OFFSET
));
709 /* Set the post divider */
710 clrsetbits_le32(&imx_ccm
->cbcmr
,
711 MXC_CCM_CBCMR_LCDIF1_PODF_MASK
,
713 MXC_CCM_CBCMR_LCDIF1_PODF_OFFSET
));
714 } else if (is_cpu_type(MXC_CPU_MX6SX
)) {
715 /* Setting LCDIF2 for i.MX6SX */
716 if (enable_pll_video(pll_div
, pll_num
, pll_denom
, post_div
))
719 /* Select pre-lcd clock to PLL5 and set pre divider */
720 clrsetbits_le32(&imx_ccm
->cscdr2
,
721 MXC_CCM_CSCDR2_LCDIF2_PRED_SEL_MASK
|
722 MXC_CCM_CSCDR2_LCDIF2_PRE_DIV_MASK
,
723 (0x2 << MXC_CCM_CSCDR2_LCDIF2_PRED_SEL_OFFSET
) |
725 MXC_CCM_CSCDR2_LCDIF2_PRE_DIV_OFFSET
));
727 /* Set the post divider */
728 clrsetbits_le32(&imx_ccm
->cscmr1
,
729 MXC_CCM_CSCMR1_LCDIF2_PODF_MASK
,
731 MXC_CCM_CSCMR1_LCDIF2_PODF_OFFSET
));
735 int enable_lcdif_clock(u32 base_addr
)
738 u32 lcdif_clk_sel_mask
, lcdif_ccgr3_mask
;
740 if (is_cpu_type(MXC_CPU_MX6SX
)) {
741 if ((base_addr
!= LCDIF1_BASE_ADDR
) &&
742 (base_addr
!= LCDIF2_BASE_ADDR
)) {
743 puts("Wrong LCD interface!\n");
746 /* Set to pre-mux clock at default */
747 lcdif_clk_sel_mask
= (base_addr
== LCDIF2_BASE_ADDR
) ?
748 MXC_CCM_CSCDR2_LCDIF2_CLK_SEL_MASK
:
749 MXC_CCM_CSCDR2_LCDIF1_CLK_SEL_MASK
;
750 lcdif_ccgr3_mask
= (base_addr
== LCDIF2_BASE_ADDR
) ?
751 (MXC_CCM_CCGR3_LCDIF2_PIX_MASK
|
752 MXC_CCM_CCGR3_DISP_AXI_MASK
) :
753 (MXC_CCM_CCGR3_LCDIF1_PIX_MASK
|
754 MXC_CCM_CCGR3_DISP_AXI_MASK
);
755 } else if (is_cpu_type(MXC_CPU_MX6UL
)) {
756 if (base_addr
!= LCDIF1_BASE_ADDR
) {
757 puts("Wrong LCD interface!\n");
760 /* Set to pre-mux clock at default */
761 lcdif_clk_sel_mask
= MXC_CCM_CSCDR2_LCDIF1_CLK_SEL_MASK
;
762 lcdif_ccgr3_mask
= MXC_CCM_CCGR3_LCDIF1_PIX_MASK
;
767 reg
= readl(&imx_ccm
->cscdr2
);
768 reg
&= ~lcdif_clk_sel_mask
;
769 writel(reg
, &imx_ccm
->cscdr2
);
771 /* Enable the LCDIF pix clock */
772 reg
= readl(&imx_ccm
->CCGR3
);
773 reg
|= lcdif_ccgr3_mask
;
774 writel(reg
, &imx_ccm
->CCGR3
);
776 reg
= readl(&imx_ccm
->CCGR2
);
777 reg
|= MXC_CCM_CCGR2_LCD_MASK
;
778 writel(reg
, &imx_ccm
->CCGR2
);
784 #ifdef CONFIG_FSL_QSPI
785 /* qspi_num can be from 0 - 1 */
786 void enable_qspi_clk(int qspi_num
)
789 /* Enable QuadSPI clock */
792 /* disable the clock gate */
793 clrbits_le32(&imx_ccm
->CCGR3
, MXC_CCM_CCGR3_QSPI1_MASK
);
795 /* set 50M : (50 = 396 / 2 / 4) */
796 reg
= readl(&imx_ccm
->cscmr1
);
797 reg
&= ~(MXC_CCM_CSCMR1_QSPI1_PODF_MASK
|
798 MXC_CCM_CSCMR1_QSPI1_CLK_SEL_MASK
);
799 reg
|= ((1 << MXC_CCM_CSCMR1_QSPI1_PODF_OFFSET
) |
800 (2 << MXC_CCM_CSCMR1_QSPI1_CLK_SEL_OFFSET
));
801 writel(reg
, &imx_ccm
->cscmr1
);
803 /* enable the clock gate */
804 setbits_le32(&imx_ccm
->CCGR3
, MXC_CCM_CCGR3_QSPI1_MASK
);
808 * disable the clock gate
809 * QSPI2 and GPMI_BCH_INPUT_GPMI_IO share the same clock gate,
810 * disable both of them.
812 clrbits_le32(&imx_ccm
->CCGR4
, MXC_CCM_CCGR4_QSPI2_ENFC_MASK
|
813 MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK
);
815 /* set 50M : (50 = 396 / 2 / 4) */
816 reg
= readl(&imx_ccm
->cs2cdr
);
817 reg
&= ~(MXC_CCM_CS2CDR_QSPI2_CLK_PODF_MASK
|
818 MXC_CCM_CS2CDR_QSPI2_CLK_PRED_MASK
|
819 MXC_CCM_CS2CDR_QSPI2_CLK_SEL_MASK
);
820 reg
|= (MXC_CCM_CS2CDR_QSPI2_CLK_PRED(0x1) |
821 MXC_CCM_CS2CDR_QSPI2_CLK_SEL(0x3));
822 writel(reg
, &imx_ccm
->cs2cdr
);
824 /*enable the clock gate*/
825 setbits_le32(&imx_ccm
->CCGR4
, MXC_CCM_CCGR4_QSPI2_ENFC_MASK
|
826 MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK
);
834 #ifdef CONFIG_FEC_MXC
835 int enable_fec_anatop_clock(int fec_id
, enum enet_freq freq
)
838 s32 timeout
= 100000;
840 struct anatop_regs __iomem
*anatop
=
841 (struct anatop_regs __iomem
*)ANATOP_BASE_ADDR
;
843 if (freq
< ENET_25MHZ
|| freq
> ENET_125MHZ
)
846 reg
= readl(&anatop
->pll_enet
);
849 reg
&= ~BM_ANADIG_PLL_ENET_DIV_SELECT
;
850 reg
|= BF_ANADIG_PLL_ENET_DIV_SELECT(freq
);
851 } else if (fec_id
== 1) {
852 /* Only i.MX6SX/UL support ENET2 */
853 if (!(is_cpu_type(MXC_CPU_MX6SX
) ||
854 is_cpu_type(MXC_CPU_MX6UL
)))
856 reg
&= ~BM_ANADIG_PLL_ENET2_DIV_SELECT
;
857 reg
|= BF_ANADIG_PLL_ENET2_DIV_SELECT(freq
);
862 if ((reg
& BM_ANADIG_PLL_ENET_POWERDOWN
) ||
863 (!(reg
& BM_ANADIG_PLL_ENET_LOCK
))) {
864 reg
&= ~BM_ANADIG_PLL_ENET_POWERDOWN
;
865 writel(reg
, &anatop
->pll_enet
);
867 if (readl(&anatop
->pll_enet
) & BM_ANADIG_PLL_ENET_LOCK
)
874 /* Enable FEC clock */
876 reg
|= BM_ANADIG_PLL_ENET_ENABLE
;
878 reg
|= BM_ANADIG_PLL_ENET2_ENABLE
;
879 reg
&= ~BM_ANADIG_PLL_ENET_BYPASS
;
880 writel(reg
, &anatop
->pll_enet
);
884 * Set enet ahb clock to 200MHz
885 * pll2_pfd2_396m-> ENET_PODF-> ENET_AHB
887 reg
= readl(&imx_ccm
->chsccdr
);
888 reg
&= ~(MXC_CCM_CHSCCDR_ENET_PRE_CLK_SEL_MASK
889 | MXC_CCM_CHSCCDR_ENET_PODF_MASK
890 | MXC_CCM_CHSCCDR_ENET_CLK_SEL_MASK
);
892 reg
|= (4 << MXC_CCM_CHSCCDR_ENET_PRE_CLK_SEL_OFFSET
);
894 reg
|= (1 << MXC_CCM_CHSCCDR_ENET_PODF_OFFSET
);
895 reg
|= (0 << MXC_CCM_CHSCCDR_ENET_CLK_SEL_OFFSET
);
896 writel(reg
, &imx_ccm
->chsccdr
);
898 /* Enable enet system clock */
899 reg
= readl(&imx_ccm
->CCGR3
);
900 reg
|= MXC_CCM_CCGR3_ENET_MASK
;
901 writel(reg
, &imx_ccm
->CCGR3
);
907 static u32
get_usdhc_clk(u32 port
)
909 u32 root_freq
= 0, usdhc_podf
= 0, clk_sel
= 0;
910 u32 cscmr1
= __raw_readl(&imx_ccm
->cscmr1
);
911 u32 cscdr1
= __raw_readl(&imx_ccm
->cscdr1
);
915 usdhc_podf
= (cscdr1
& MXC_CCM_CSCDR1_USDHC1_PODF_MASK
) >>
916 MXC_CCM_CSCDR1_USDHC1_PODF_OFFSET
;
917 clk_sel
= cscmr1
& MXC_CCM_CSCMR1_USDHC1_CLK_SEL
;
921 usdhc_podf
= (cscdr1
& MXC_CCM_CSCDR1_USDHC2_PODF_MASK
) >>
922 MXC_CCM_CSCDR1_USDHC2_PODF_OFFSET
;
923 clk_sel
= cscmr1
& MXC_CCM_CSCMR1_USDHC2_CLK_SEL
;
927 usdhc_podf
= (cscdr1
& MXC_CCM_CSCDR1_USDHC3_PODF_MASK
) >>
928 MXC_CCM_CSCDR1_USDHC3_PODF_OFFSET
;
929 clk_sel
= cscmr1
& MXC_CCM_CSCMR1_USDHC3_CLK_SEL
;
933 usdhc_podf
= (cscdr1
& MXC_CCM_CSCDR1_USDHC4_PODF_MASK
) >>
934 MXC_CCM_CSCDR1_USDHC4_PODF_OFFSET
;
935 clk_sel
= cscmr1
& MXC_CCM_CSCMR1_USDHC4_CLK_SEL
;
943 root_freq
= mxc_get_pll_pfd(PLL_BUS
, 0);
945 root_freq
= mxc_get_pll_pfd(PLL_BUS
, 2);
947 return root_freq
/ (usdhc_podf
+ 1);
950 u32
imx_get_uartclk(void)
952 return get_uart_clk();
955 u32
imx_get_fecclk(void)
957 return mxc_get_clock(MXC_IPG_CLK
);
960 #if defined(CONFIG_CMD_SATA) || defined(CONFIG_PCIE_IMX)
961 static int enable_enet_pll(uint32_t en
)
963 struct mxc_ccm_reg
*const imx_ccm
964 = (struct mxc_ccm_reg
*) CCM_BASE_ADDR
;
965 s32 timeout
= 100000;
969 reg
= readl(&imx_ccm
->analog_pll_enet
);
970 reg
&= ~BM_ANADIG_PLL_SYS_POWERDOWN
;
971 writel(reg
, &imx_ccm
->analog_pll_enet
);
972 reg
|= BM_ANADIG_PLL_SYS_ENABLE
;
974 if (readl(&imx_ccm
->analog_pll_enet
) & BM_ANADIG_PLL_SYS_LOCK
)
979 reg
&= ~BM_ANADIG_PLL_SYS_BYPASS
;
980 writel(reg
, &imx_ccm
->analog_pll_enet
);
982 writel(reg
, &imx_ccm
->analog_pll_enet
);
987 #ifdef CONFIG_CMD_SATA
988 static void ungate_sata_clock(void)
990 struct mxc_ccm_reg
*const imx_ccm
=
991 (struct mxc_ccm_reg
*)CCM_BASE_ADDR
;
993 /* Enable SATA clock. */
994 setbits_le32(&imx_ccm
->CCGR5
, MXC_CCM_CCGR5_SATA_MASK
);
997 int enable_sata_clock(void)
1000 return enable_enet_pll(BM_ANADIG_PLL_ENET_ENABLE_SATA
);
1003 void disable_sata_clock(void)
1005 struct mxc_ccm_reg
*const imx_ccm
=
1006 (struct mxc_ccm_reg
*)CCM_BASE_ADDR
;
1008 clrbits_le32(&imx_ccm
->CCGR5
, MXC_CCM_CCGR5_SATA_MASK
);
1012 #ifdef CONFIG_PCIE_IMX
1013 static void ungate_pcie_clock(void)
1015 struct mxc_ccm_reg
*const imx_ccm
=
1016 (struct mxc_ccm_reg
*)CCM_BASE_ADDR
;
1018 /* Enable PCIe clock. */
1019 setbits_le32(&imx_ccm
->CCGR4
, MXC_CCM_CCGR4_PCIE_MASK
);
1022 int enable_pcie_clock(void)
1024 struct anatop_regs
*anatop_regs
=
1025 (struct anatop_regs
*)ANATOP_BASE_ADDR
;
1026 struct mxc_ccm_reg
*ccm_regs
= (struct mxc_ccm_reg
*)CCM_BASE_ADDR
;
1032 * The register ANATOP_MISC1 is not documented in the Freescale
1033 * MX6RM. The register that is mapped in the ANATOP space and
1034 * marked as ANATOP_MISC1 is actually documented in the PMU section
1035 * of the datasheet as PMU_MISC1.
1037 * Switch LVDS clock source to SATA (0xb) on mx6q/dl or PCI (0xa) on
1038 * mx6sx, disable clock INPUT and enable clock OUTPUT. This is important
1039 * for PCI express link that is clocked from the i.MX6.
1041 #define ANADIG_ANA_MISC1_LVDSCLK1_IBEN (1 << 12)
1042 #define ANADIG_ANA_MISC1_LVDSCLK1_OBEN (1 << 10)
1043 #define ANADIG_ANA_MISC1_LVDS1_CLK_SEL_MASK 0x0000001F
1044 #define ANADIG_ANA_MISC1_LVDS1_CLK_SEL_PCIE_REF 0xa
1045 #define ANADIG_ANA_MISC1_LVDS1_CLK_SEL_SATA_REF 0xb
1047 if (is_cpu_type(MXC_CPU_MX6SX
))
1048 lvds1_clk_sel
= ANADIG_ANA_MISC1_LVDS1_CLK_SEL_PCIE_REF
;
1050 lvds1_clk_sel
= ANADIG_ANA_MISC1_LVDS1_CLK_SEL_SATA_REF
;
1052 clrsetbits_le32(&anatop_regs
->ana_misc1
,
1053 ANADIG_ANA_MISC1_LVDSCLK1_IBEN
|
1054 ANADIG_ANA_MISC1_LVDS1_CLK_SEL_MASK
,
1055 ANADIG_ANA_MISC1_LVDSCLK1_OBEN
| lvds1_clk_sel
);
1057 /* PCIe reference clock sourced from AXI. */
1058 clrbits_le32(&ccm_regs
->cbcmr
, MXC_CCM_CBCMR_PCIE_AXI_CLK_SEL
);
1060 /* Party time! Ungate the clock to the PCIe. */
1061 #ifdef CONFIG_CMD_SATA
1062 ungate_sata_clock();
1064 ungate_pcie_clock();
1066 return enable_enet_pll(BM_ANADIG_PLL_ENET_ENABLE_SATA
|
1067 BM_ANADIG_PLL_ENET_ENABLE_PCIE
);
1071 #ifdef CONFIG_SECURE_BOOT
1072 void hab_caam_clock_enable(unsigned char enable
)
1076 /* CG4 ~ CG6, CAAM clocks */
1077 reg
= __raw_readl(&imx_ccm
->CCGR0
);
1079 reg
|= (MXC_CCM_CCGR0_CAAM_WRAPPER_IPG_MASK
|
1080 MXC_CCM_CCGR0_CAAM_WRAPPER_ACLK_MASK
|
1081 MXC_CCM_CCGR0_CAAM_SECURE_MEM_MASK
);
1083 reg
&= ~(MXC_CCM_CCGR0_CAAM_WRAPPER_IPG_MASK
|
1084 MXC_CCM_CCGR0_CAAM_WRAPPER_ACLK_MASK
|
1085 MXC_CCM_CCGR0_CAAM_SECURE_MEM_MASK
);
1086 __raw_writel(reg
, &imx_ccm
->CCGR0
);
1089 reg
= __raw_readl(&imx_ccm
->CCGR6
);
1091 reg
|= MXC_CCM_CCGR6_EMI_SLOW_MASK
;
1093 reg
&= ~MXC_CCM_CCGR6_EMI_SLOW_MASK
;
1094 __raw_writel(reg
, &imx_ccm
->CCGR6
);
1098 static void enable_pll3(void)
1100 struct anatop_regs __iomem
*anatop
=
1101 (struct anatop_regs __iomem
*)ANATOP_BASE_ADDR
;
1103 /* make sure pll3 is enabled */
1104 if ((readl(&anatop
->usb1_pll_480_ctrl
) &
1105 BM_ANADIG_USB1_PLL_480_CTRL_LOCK
) == 0) {
1106 /* enable pll's power */
1107 writel(BM_ANADIG_USB1_PLL_480_CTRL_POWER
,
1108 &anatop
->usb1_pll_480_ctrl_set
);
1109 writel(0x80, &anatop
->ana_misc2_clr
);
1110 /* wait for pll lock */
1111 while ((readl(&anatop
->usb1_pll_480_ctrl
) &
1112 BM_ANADIG_USB1_PLL_480_CTRL_LOCK
) == 0)
1114 /* disable bypass */
1115 writel(BM_ANADIG_USB1_PLL_480_CTRL_BYPASS
,
1116 &anatop
->usb1_pll_480_ctrl_clr
);
1117 /* enable pll output */
1118 writel(BM_ANADIG_USB1_PLL_480_CTRL_ENABLE
,
1119 &anatop
->usb1_pll_480_ctrl_set
);
1123 void enable_thermal_clk(void)
1128 unsigned int mxc_get_clock(enum mxc_clock clk
)
1132 return get_mcu_main_clk();
1134 return get_periph_clk();
1136 return get_ahb_clk();
1138 return get_ipg_clk();
1139 case MXC_IPG_PERCLK
:
1141 return get_ipg_per_clk();
1143 return get_uart_clk();
1145 return get_cspi_clk();
1147 return get_axi_clk();
1148 case MXC_EMI_SLOW_CLK
:
1149 return get_emi_slow_clk();
1151 return get_mmdc_ch0_clk();
1153 return get_usdhc_clk(0);
1154 case MXC_ESDHC2_CLK
:
1155 return get_usdhc_clk(1);
1156 case MXC_ESDHC3_CLK
:
1157 return get_usdhc_clk(2);
1158 case MXC_ESDHC4_CLK
:
1159 return get_usdhc_clk(3);
1161 return get_ahb_clk();
1163 printf("Unsupported MXC CLK: %d\n", clk
);
1171 * Dump some core clockes.
1173 int do_mx6_showclocks(cmd_tbl_t
*cmdtp
, int flag
, int argc
, char * const argv
[])
1176 freq
= decode_pll(PLL_SYS
, MXC_HCLK
);
1177 printf("PLL_SYS %8d MHz\n", freq
/ 1000000);
1178 freq
= decode_pll(PLL_BUS
, MXC_HCLK
);
1179 printf("PLL_BUS %8d MHz\n", freq
/ 1000000);
1180 freq
= decode_pll(PLL_USBOTG
, MXC_HCLK
);
1181 printf("PLL_OTG %8d MHz\n", freq
/ 1000000);
1182 freq
= decode_pll(PLL_ENET
, MXC_HCLK
);
1183 printf("PLL_NET %8d MHz\n", freq
/ 1000000);
1186 printf("ARM %8d kHz\n", mxc_get_clock(MXC_ARM_CLK
) / 1000);
1187 printf("IPG %8d kHz\n", mxc_get_clock(MXC_IPG_CLK
) / 1000);
1188 printf("UART %8d kHz\n", mxc_get_clock(MXC_UART_CLK
) / 1000);
1189 #ifdef CONFIG_MXC_SPI
1190 printf("CSPI %8d kHz\n", mxc_get_clock(MXC_CSPI_CLK
) / 1000);
1192 printf("AHB %8d kHz\n", mxc_get_clock(MXC_AHB_CLK
) / 1000);
1193 printf("AXI %8d kHz\n", mxc_get_clock(MXC_AXI_CLK
) / 1000);
1194 printf("DDR %8d kHz\n", mxc_get_clock(MXC_DDR_CLK
) / 1000);
1195 printf("USDHC1 %8d kHz\n", mxc_get_clock(MXC_ESDHC_CLK
) / 1000);
1196 printf("USDHC2 %8d kHz\n", mxc_get_clock(MXC_ESDHC2_CLK
) / 1000);
1197 printf("USDHC3 %8d kHz\n", mxc_get_clock(MXC_ESDHC3_CLK
) / 1000);
1198 printf("USDHC4 %8d kHz\n", mxc_get_clock(MXC_ESDHC4_CLK
) / 1000);
1199 printf("EMI SLOW %8d kHz\n", mxc_get_clock(MXC_EMI_SLOW_CLK
) / 1000);
1200 printf("IPG PERCLK %8d kHz\n", mxc_get_clock(MXC_IPG_PERCLK
) / 1000);
1205 #ifndef CONFIG_MX6SX
1206 void enable_ipu_clock(void)
1208 struct mxc_ccm_reg
*mxc_ccm
= (struct mxc_ccm_reg
*)CCM_BASE_ADDR
;
1210 reg
= readl(&mxc_ccm
->CCGR3
);
1211 reg
|= MXC_CCM_CCGR3_IPU1_IPU_MASK
;
1212 writel(reg
, &mxc_ccm
->CCGR3
);
1215 setbits_le32(&mxc_ccm
->CCGR6
, MXC_CCM_CCGR6_PRG_CLK0_MASK
);
1216 setbits_le32(&mxc_ccm
->CCGR3
, MXC_CCM_CCGR3_IPU2_IPU_MASK
);
1221 #if defined(CONFIG_MX6Q) || defined(CONFIG_MX6D) || defined(CONFIG_MX6DL) || \
1222 defined(CONFIG_MX6S)
1223 static void disable_ldb_di_clock_sources(void)
1225 struct mxc_ccm_reg
*mxc_ccm
= (struct mxc_ccm_reg
*)CCM_BASE_ADDR
;
1228 /* Make sure PFDs are disabled at boot. */
1229 reg
= readl(&mxc_ccm
->analog_pfd_528
);
1230 /* Cannot disable pll2_pfd2_396M, as it is the MMDC clock in iMX6DL */
1231 if (is_cpu_type(MXC_CPU_MX6DL
))
1235 writel(reg
, &mxc_ccm
->analog_pfd_528
);
1237 /* Disable PLL3 PFDs */
1238 reg
= readl(&mxc_ccm
->analog_pfd_480
);
1240 writel(reg
, &mxc_ccm
->analog_pfd_480
);
1243 reg
= readl(&mxc_ccm
->analog_pll_video
);
1245 writel(reg
, &mxc_ccm
->analog_pll_video
);
1248 static void enable_ldb_di_clock_sources(void)
1250 struct mxc_ccm_reg
*mxc_ccm
= (struct mxc_ccm_reg
*)CCM_BASE_ADDR
;
1253 reg
= readl(&mxc_ccm
->analog_pfd_528
);
1254 if (is_cpu_type(MXC_CPU_MX6DL
))
1255 reg
&= ~(0x80008080);
1257 reg
&= ~(0x80808080);
1258 writel(reg
, &mxc_ccm
->analog_pfd_528
);
1260 reg
= readl(&mxc_ccm
->analog_pfd_480
);
1261 reg
&= ~(0x80808080);
1262 writel(reg
, &mxc_ccm
->analog_pfd_480
);
1266 * Try call this function as early in the boot process as possible since the
1267 * function temporarily disables PLL2 PFD's, PLL3 PFD's and PLL5.
1269 void select_ldb_di_clock_source(enum ldb_di_clock clk
)
1271 struct mxc_ccm_reg
*mxc_ccm
= (struct mxc_ccm_reg
*)CCM_BASE_ADDR
;
1275 * Need to follow a strict procedure when changing the LDB
1276 * clock, else we can introduce a glitch. Things to keep in
1278 * 1. The current and new parent clocks must be disabled.
1279 * 2. The default clock for ldb_dio_clk is mmdc_ch1 which has
1281 * 3. In the RTL implementation of the LDB_DI_CLK_SEL mux
1282 * the top four options are in one mux and the PLL3 option along
1283 * with another option is in the second mux. There is third mux
1284 * used to decide between the first and second mux.
1285 * The code below switches the parent to the bottom mux first
1286 * and then manipulates the top mux. This ensures that no glitch
1287 * will enter the divider.
1289 * Need to disable MMDC_CH1 clock manually as there is no CG bit
1290 * for this clock. The only way to disable this clock is to move
1291 * it to pll3_sw_clk and then to disable pll3_sw_clk
1292 * Make sure periph2_clk2_sel is set to pll3_sw_clk
1295 /* Disable all ldb_di clock parents */
1296 disable_ldb_di_clock_sources();
1298 /* Set MMDC_CH1 mask bit */
1299 reg
= readl(&mxc_ccm
->ccdr
);
1300 reg
|= MXC_CCM_CCDR_MMDC_CH1_HS_MASK
;
1301 writel(reg
, &mxc_ccm
->ccdr
);
1303 /* Set periph2_clk2_sel to be sourced from PLL3_sw_clk */
1304 reg
= readl(&mxc_ccm
->cbcmr
);
1305 reg
&= ~MXC_CCM_CBCMR_PERIPH2_CLK2_SEL
;
1306 writel(reg
, &mxc_ccm
->cbcmr
);
1309 * Set the periph2_clk_sel to the top mux so that
1310 * mmdc_ch1 is from pll3_sw_clk.
1312 reg
= readl(&mxc_ccm
->cbcdr
);
1313 reg
|= MXC_CCM_CBCDR_PERIPH2_CLK_SEL
;
1314 writel(reg
, &mxc_ccm
->cbcdr
);
1316 /* Wait for the clock switch */
1317 while (readl(&mxc_ccm
->cdhipr
))
1319 /* Disable pll3_sw_clk by selecting bypass clock source */
1320 reg
= readl(&mxc_ccm
->ccsr
);
1321 reg
|= MXC_CCM_CCSR_PLL3_SW_CLK_SEL
;
1322 writel(reg
, &mxc_ccm
->ccsr
);
1324 /* Set the ldb_di0_clk and ldb_di1_clk to 111b */
1325 reg
= readl(&mxc_ccm
->cs2cdr
);
1326 reg
|= ((7 << MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET
)
1327 | (7 << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET
));
1328 writel(reg
, &mxc_ccm
->cs2cdr
);
1330 /* Set the ldb_di0_clk and ldb_di1_clk to 100b */
1331 reg
= readl(&mxc_ccm
->cs2cdr
);
1332 reg
&= ~(MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK
1333 | MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK
);
1334 reg
|= ((4 << MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET
)
1335 | (4 << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET
));
1336 writel(reg
, &mxc_ccm
->cs2cdr
);
1338 /* Set the ldb_di0_clk and ldb_di1_clk to desired source */
1339 reg
= readl(&mxc_ccm
->cs2cdr
);
1340 reg
&= ~(MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK
1341 | MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK
);
1342 reg
|= ((clk
<< MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET
)
1343 | (clk
<< MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET
));
1344 writel(reg
, &mxc_ccm
->cs2cdr
);
1346 /* Unbypass pll3_sw_clk */
1347 reg
= readl(&mxc_ccm
->ccsr
);
1348 reg
&= ~MXC_CCM_CCSR_PLL3_SW_CLK_SEL
;
1349 writel(reg
, &mxc_ccm
->ccsr
);
1352 * Set the periph2_clk_sel back to the bottom mux so that
1353 * mmdc_ch1 is from its original parent.
1355 reg
= readl(&mxc_ccm
->cbcdr
);
1356 reg
&= ~MXC_CCM_CBCDR_PERIPH2_CLK_SEL
;
1357 writel(reg
, &mxc_ccm
->cbcdr
);
1359 /* Wait for the clock switch */
1360 while (readl(&mxc_ccm
->cdhipr
))
1362 /* Clear MMDC_CH1 mask bit */
1363 reg
= readl(&mxc_ccm
->ccdr
);
1364 reg
&= ~MXC_CCM_CCDR_MMDC_CH1_HS_MASK
;
1365 writel(reg
, &mxc_ccm
->ccdr
);
1367 enable_ldb_di_clock_sources();
1371 /***************************************************/
1374 clocks
, CONFIG_SYS_MAXARGS
, 1, do_mx6_showclocks
,